1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
15 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
17 #include "MCTargetDesc/X86BaseInfo.h"
18 #include "X86RegisterInfo.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/Target/TargetInstrInfo.h"
22 #define GET_INSTRINFO_HEADER
23 #include "X86GenInstrInfo.inc"
26 class X86RegisterInfo;
30 // X86 specific condition code. These correspond to X86_*_COND in
31 // X86InstrInfo.td. They must be kept in synch.
49 LAST_VALID_COND = COND_S,
51 // Artificial condition codes. These are used by AnalyzeBranch
52 // to indicate a block terminated with two conditional branches to
53 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
54 // which can't be represented on x86 with a single condition. These
55 // are never used in MachineInstrs.
62 // Turn condition code into conditional branch opcode.
63 unsigned GetCondBranchFromCond(CondCode CC);
65 /// \brief Return a set opcode for the given condition and whether it has
67 unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false);
69 /// \brief Return a cmov opcode for the given condition, register size in
70 /// bytes, and operand type.
71 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
72 bool HasMemoryOperand = false);
74 // Turn CMov opcode into condition code.
75 CondCode getCondFromCMovOpc(unsigned Opc);
77 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
78 /// e.g. turning COND_E to COND_NE.
79 CondCode GetOppositeBranchCondition(CondCode CC);
80 } // end namespace X86;
83 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
84 /// a reference to a stub for a global, not the global itself.
85 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
87 case X86II::MO_DLLIMPORT: // dllimport stub.
88 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
89 case X86II::MO_GOT: // normal GOT reference.
90 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
91 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
92 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
99 /// isGlobalRelativeToPICBase - Return true if the specified global value
100 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
101 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
102 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
103 switch (TargetFlag) {
104 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
105 case X86II::MO_GOT: // isPICStyleGOT: other global.
106 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
107 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
108 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
109 case X86II::MO_TLVP: // ??? Pretty sure..
116 inline static bool isScale(const MachineOperand &MO) {
118 (MO.getImm() == 1 || MO.getImm() == 2 ||
119 MO.getImm() == 4 || MO.getImm() == 8);
122 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
123 if (MI->getOperand(Op).isFI()) return true;
124 return Op+X86::AddrSegmentReg <= MI->getNumOperands() &&
125 MI->getOperand(Op+X86::AddrBaseReg).isReg() &&
126 isScale(MI->getOperand(Op+X86::AddrScaleAmt)) &&
127 MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
128 (MI->getOperand(Op+X86::AddrDisp).isImm() ||
129 MI->getOperand(Op+X86::AddrDisp).isGlobal() ||
130 MI->getOperand(Op+X86::AddrDisp).isCPI() ||
131 MI->getOperand(Op+X86::AddrDisp).isJTI());
134 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
135 if (MI->getOperand(Op).isFI()) return true;
136 return Op+X86::AddrNumOperands <= MI->getNumOperands() &&
137 MI->getOperand(Op+X86::AddrSegmentReg).isReg() &&
141 class X86InstrInfo final : public X86GenInstrInfo {
142 X86Subtarget &Subtarget;
143 const X86RegisterInfo RI;
145 /// RegOp2MemOpTable3Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
146 /// RegOp2MemOpTable2, RegOp2MemOpTable3 - Load / store folding opcode maps.
148 typedef DenseMap<unsigned,
149 std::pair<unsigned, unsigned> > RegOp2MemOpTableType;
150 RegOp2MemOpTableType RegOp2MemOpTable2Addr;
151 RegOp2MemOpTableType RegOp2MemOpTable0;
152 RegOp2MemOpTableType RegOp2MemOpTable1;
153 RegOp2MemOpTableType RegOp2MemOpTable2;
154 RegOp2MemOpTableType RegOp2MemOpTable3;
155 RegOp2MemOpTableType RegOp2MemOpTable4;
157 /// MemOp2RegOpTable - Load / store unfolding opcode map.
159 typedef DenseMap<unsigned,
160 std::pair<unsigned, unsigned> > MemOp2RegOpTableType;
161 MemOp2RegOpTableType MemOp2RegOpTable;
163 static void AddTableEntry(RegOp2MemOpTableType &R2MTable,
164 MemOp2RegOpTableType &M2RTable,
165 unsigned RegOp, unsigned MemOp, unsigned Flags);
167 virtual void anchor();
169 bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
170 MachineBasicBlock *&FBB,
171 SmallVectorImpl<MachineOperand> &Cond,
172 SmallVectorImpl<MachineInstr *> &CondBranches,
173 bool AllowModify) const;
176 explicit X86InstrInfo(X86Subtarget &STI);
178 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
179 /// such, whenever a client has an instance of instruction info, it should
180 /// always be able to get register info as well (through this method).
182 const X86RegisterInfo &getRegisterInfo() const { return RI; }
184 /// getSPAdjust - This returns the stack pointer adjustment made by
185 /// this instruction. For x86, we need to handle more complex call
186 /// sequences involving PUSHes.
187 int getSPAdjust(const MachineInstr *MI) const override;
189 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
190 /// extension instruction. That is, it's like a copy where it's legal for the
191 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
192 /// true, then it's expected the pre-extension value is available as a subreg
193 /// of the result register. This also returns the sub-register index in
195 bool isCoalescableExtInstr(const MachineInstr &MI,
196 unsigned &SrcReg, unsigned &DstReg,
197 unsigned &SubIdx) const override;
199 unsigned isLoadFromStackSlot(const MachineInstr *MI,
200 int &FrameIndex) const override;
201 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
202 /// stack locations as well. This uses a heuristic so it isn't
203 /// reliable for correctness.
204 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
205 int &FrameIndex) const override;
207 unsigned isStoreToStackSlot(const MachineInstr *MI,
208 int &FrameIndex) const override;
209 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
210 /// stack locations as well. This uses a heuristic so it isn't
211 /// reliable for correctness.
212 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
213 int &FrameIndex) const override;
215 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
216 AliasAnalysis *AA) const override;
217 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
218 unsigned DestReg, unsigned SubIdx,
219 const MachineInstr *Orig,
220 const TargetRegisterInfo &TRI) const override;
222 /// Given an operand within a MachineInstr, insert preceding code to put it
223 /// into the right format for a particular kind of LEA instruction. This may
224 /// involve using an appropriate super-register instead (with an implicit use
225 /// of the original) or creating a new virtual register and inserting COPY
226 /// instructions to get the data into the right class.
228 /// Reference parameters are set to indicate how caller should add this
229 /// operand to the LEA instruction.
230 bool classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
231 unsigned LEAOpcode, bool AllowSP,
232 unsigned &NewSrc, bool &isKill,
233 bool &isUndef, MachineOperand &ImplicitOp) const;
235 /// convertToThreeAddress - This method must be implemented by targets that
236 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
237 /// may be able to convert a two-address instruction into a true
238 /// three-address instruction on demand. This allows the X86 target (for
239 /// example) to convert ADD and SHL instructions into LEA instructions if they
240 /// would require register copies due to two-addressness.
242 /// This method returns a null pointer if the transformation cannot be
243 /// performed, otherwise it returns the new instruction.
245 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
246 MachineBasicBlock::iterator &MBBI,
247 LiveVariables *LV) const override;
249 /// commuteInstruction - We have a few instructions that must be hacked on to
252 MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const override;
254 bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
255 unsigned &SrcOpIdx2) const override;
258 bool isUnpredicatedTerminator(const MachineInstr* MI) const override;
259 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
260 MachineBasicBlock *&FBB,
261 SmallVectorImpl<MachineOperand> &Cond,
262 bool AllowModify) const override;
264 bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
266 const TargetRegisterInfo *TRI) const override;
267 bool AnalyzeBranchPredicate(MachineBasicBlock &MBB,
268 TargetInstrInfo::MachineBranchPredicate &MBP,
269 bool AllowModify = false) const override;
271 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
272 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
273 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
274 DebugLoc DL) const override;
275 bool canInsertSelect(const MachineBasicBlock&, ArrayRef<MachineOperand> Cond,
276 unsigned, unsigned, int&, int&, int&) const override;
277 void insertSelect(MachineBasicBlock &MBB,
278 MachineBasicBlock::iterator MI, DebugLoc DL,
279 unsigned DstReg, ArrayRef<MachineOperand> Cond,
280 unsigned TrueReg, unsigned FalseReg) const override;
281 void copyPhysReg(MachineBasicBlock &MBB,
282 MachineBasicBlock::iterator MI, DebugLoc DL,
283 unsigned DestReg, unsigned SrcReg,
284 bool KillSrc) const override;
285 void storeRegToStackSlot(MachineBasicBlock &MBB,
286 MachineBasicBlock::iterator MI,
287 unsigned SrcReg, bool isKill, int FrameIndex,
288 const TargetRegisterClass *RC,
289 const TargetRegisterInfo *TRI) const override;
291 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
292 SmallVectorImpl<MachineOperand> &Addr,
293 const TargetRegisterClass *RC,
294 MachineInstr::mmo_iterator MMOBegin,
295 MachineInstr::mmo_iterator MMOEnd,
296 SmallVectorImpl<MachineInstr*> &NewMIs) const;
298 void loadRegFromStackSlot(MachineBasicBlock &MBB,
299 MachineBasicBlock::iterator MI,
300 unsigned DestReg, int FrameIndex,
301 const TargetRegisterClass *RC,
302 const TargetRegisterInfo *TRI) const override;
304 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
305 SmallVectorImpl<MachineOperand> &Addr,
306 const TargetRegisterClass *RC,
307 MachineInstr::mmo_iterator MMOBegin,
308 MachineInstr::mmo_iterator MMOEnd,
309 SmallVectorImpl<MachineInstr*> &NewMIs) const;
311 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
313 /// foldMemoryOperand - If this target supports it, fold a load or store of
314 /// the specified stack slot into the specified machine instruction for the
315 /// specified operand(s). If this is possible, the target should perform the
316 /// folding and return true, otherwise it should return false. If it folds
317 /// the instruction, it is likely that the MachineInstruction the iterator
318 /// references has been changed.
319 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
320 ArrayRef<unsigned> Ops,
321 MachineBasicBlock::iterator InsertPt,
322 int FrameIndex) const override;
324 /// foldMemoryOperand - Same as the previous version except it allows folding
325 /// of any load and store from / to any address, not just from a specific
327 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
328 ArrayRef<unsigned> Ops,
329 MachineBasicBlock::iterator InsertPt,
330 MachineInstr *LoadMI) const override;
332 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
333 /// a store or a load and a store into two or more instruction. If this is
334 /// possible, returns true as well as the new instructions by reference.
335 bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
336 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
337 SmallVectorImpl<MachineInstr*> &NewMIs) const override;
339 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
340 SmallVectorImpl<SDNode*> &NewNodes) const override;
342 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
343 /// instruction after load / store are unfolded from an instruction of the
344 /// specified opcode. It returns zero if the specified unfolding is not
345 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
346 /// index of the operand which will hold the register holding the loaded
348 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
349 bool UnfoldLoad, bool UnfoldStore,
350 unsigned *LoadRegIndex = nullptr) const override;
352 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
353 /// to determine if two loads are loading from the same base address. It
354 /// should only return true if the base pointers are the same and the
355 /// only differences between the two addresses are the offset. It also returns
356 /// the offsets by reference.
357 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
358 int64_t &Offset2) const override;
360 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
361 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
362 /// be scheduled togther. On some targets if two loads are loading from
363 /// addresses in the same cache line, it's better if they are scheduled
364 /// together. This function takes two integers that represent the load offsets
365 /// from the common base address. It returns true if it decides it's desirable
366 /// to schedule the two loads together. "NumLoads" is the number of loads that
367 /// have already been scheduled after Load1.
368 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
369 int64_t Offset1, int64_t Offset2,
370 unsigned NumLoads) const override;
372 bool shouldScheduleAdjacent(MachineInstr* First,
373 MachineInstr *Second) const override;
375 void getNoopForMachoTarget(MCInst &NopInst) const override;
378 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
380 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
381 /// instruction that defines the specified register class.
382 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
384 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha
385 /// would clobber the EFLAGS condition register. Note the result may be
386 /// conservative. If it cannot definitely determine the safety after visiting
387 /// a few instructions in each direction it assumes it's not safe.
388 bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
389 MachineBasicBlock::iterator I) const;
391 /// True if MI has a condition code def, e.g. EFLAGS, that is
393 bool hasLiveCondCodeDef(MachineInstr *MI) const;
395 static bool isX86_64ExtendedReg(const MachineOperand &MO) {
396 if (!MO.isReg()) return false;
397 return X86II::isX86_64ExtendedReg(MO.getReg());
400 /// getGlobalBaseReg - Return a virtual register initialized with the
401 /// the global base register value. Output instructions required to
402 /// initialize the register in the function entry block, if necessary.
404 unsigned getGlobalBaseReg(MachineFunction *MF) const;
406 std::pair<uint16_t, uint16_t>
407 getExecutionDomain(const MachineInstr *MI) const override;
409 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override;
412 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
413 const TargetRegisterInfo *TRI) const override;
414 unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
415 const TargetRegisterInfo *TRI) const override;
416 void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
417 const TargetRegisterInfo *TRI) const override;
419 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
421 ArrayRef<MachineOperand> MOs,
422 MachineBasicBlock::iterator InsertPt,
423 unsigned Size, unsigned Alignment,
424 bool AllowCommute) const;
427 getUnconditionalBranch(MCInst &Branch,
428 const MCSymbolRefExpr *BranchTarget) const override;
430 void getTrap(MCInst &MI) const override;
432 unsigned getJumpInstrTableEntryBound() const override;
434 bool isHighLatencyDef(int opc) const override;
436 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
437 const MachineRegisterInfo *MRI,
438 const MachineInstr *DefMI, unsigned DefIdx,
439 const MachineInstr *UseMI,
440 unsigned UseIdx) const override;
442 bool useMachineCombiner() const override {
446 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
448 bool hasReassociableOperands(const MachineInstr &Inst,
449 const MachineBasicBlock *MBB) const override;
451 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
452 MachineInstr &NewMI1,
453 MachineInstr &NewMI2) const override;
455 /// analyzeCompare - For a comparison instruction, return the source registers
456 /// in SrcReg and SrcReg2 if having two register operands, and the value it
457 /// compares against in CmpValue. Return true if the comparison instruction
459 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
460 unsigned &SrcReg2, int &CmpMask,
461 int &CmpValue) const override;
463 /// optimizeCompareInstr - Check if there exists an earlier instruction that
464 /// operates on the same source operands and sets flags in the same way as
465 /// Compare; remove Compare if possible.
466 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
467 unsigned SrcReg2, int CmpMask, int CmpValue,
468 const MachineRegisterInfo *MRI) const override;
470 /// optimizeLoadInstr - Try to remove the load by folding it to a register
471 /// operand at the use. We fold the load instructions if and only if the
472 /// def and use are in the same BB. We only look at one load and see
473 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
474 /// defined by the load we are trying to fold. DefMI returns the machine
475 /// instruction that defines FoldAsLoadDefReg, and the function returns
476 /// the machine instruction generated due to folding.
477 MachineInstr* optimizeLoadInstr(MachineInstr *MI,
478 const MachineRegisterInfo *MRI,
479 unsigned &FoldAsLoadDefReg,
480 MachineInstr *&DefMI) const override;
482 std::pair<unsigned, unsigned>
483 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
485 ArrayRef<std::pair<unsigned, const char *>>
486 getSerializableDirectMachineOperandTargetFlags() const override;
489 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
490 MachineFunction::iterator &MFI,
491 MachineBasicBlock::iterator &MBBI,
492 LiveVariables *LV) const;
494 /// isFrameOperand - Return true and the FrameIndex if the specified
495 /// operand and follow operands form a reference to the stack frame.
496 bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
497 int &FrameIndex) const;
500 } // End llvm namespace