1 //===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86INSTRUCTIONINFO_H
15 #define X86INSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/Target/TargetRegisterInfo.h"
24 class X86RegisterInfo;
25 class X86TargetMachine;
28 // X86 specific condition code. These correspond to X86_*_COND in
29 // X86InstrInfo.td. They must be kept in synch.
48 // Artificial condition codes. These are used by AnalyzeBranch
49 // to indicate a block terminated with two conditional branches to
50 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
51 // which can't be represented on x86 with a single condition. These
52 // are never used in MachineInstrs.
59 // Turn condition code into conditional branch opcode.
60 unsigned GetCondBranchFromCond(CondCode CC);
62 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
63 /// e.g. turning COND_E to COND_NE.
64 CondCode GetOppositeBranchCondition(X86::CondCode CC);
68 /// X86II - This namespace holds all of the target specific flags that
69 /// instruction info tracks.
73 //===------------------------------------------------------------------===//
74 // X86 Specific MachineOperand flags.
78 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
80 /// SYMBOL_LABEL + [. - PICBASELABEL]
81 MO_GOT_ABSOLUTE_ADDRESS = 1,
83 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
84 /// immediate should get the value of the symbol minus the PIC base label:
85 /// SYMBOL_LABEL - PICBASELABEL
86 MO_PIC_BASE_OFFSET = 2,
88 /// MO_GOT - On a symbol operand this indicates that the immediate is the
89 /// offset to the GOT entry for the symbol name from the base of the GOT.
91 /// See the X86-64 ELF ABI supplement for more details.
95 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
96 /// the offset to the location of the symbol name from the base of the GOT.
98 /// See the X86-64 ELF ABI supplement for more details.
99 /// SYMBOL_LABEL @GOTOFF
102 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
103 /// offset to the GOT entry for the symbol name from the current code
106 /// See the X86-64 ELF ABI supplement for more details.
107 /// SYMBOL_LABEL @GOTPCREL
110 /// MO_PLT - On a symbol operand this indicates that the immediate is
111 /// offset to the PLT entry of symbol name from the current code location.
113 /// See the X86-64 ELF ABI supplement for more details.
114 /// SYMBOL_LABEL @PLT
117 /// MO_TLSGD - On a symbol operand this indicates that the immediate is
120 /// See 'ELF Handling for Thread-Local Storage' for more details.
121 /// SYMBOL_LABEL @TLSGD
124 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
127 /// See 'ELF Handling for Thread-Local Storage' for more details.
128 /// SYMBOL_LABEL @GOTTPOFF
131 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
134 /// See 'ELF Handling for Thread-Local Storage' for more details.
135 /// SYMBOL_LABEL @INDNTPOFF
138 /// MO_TPOFF - On a symbol operand this indicates that the immediate is
141 /// See 'ELF Handling for Thread-Local Storage' for more details.
142 /// SYMBOL_LABEL @TPOFF
145 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
148 /// See 'ELF Handling for Thread-Local Storage' for more details.
149 /// SYMBOL_LABEL @NTPOFF
152 //===------------------------------------------------------------------===//
153 // Instruction encodings. These are the standard/most common forms for X86
157 // PseudoFrm - This represents an instruction that is a pseudo instruction
158 // or one that has not been implemented yet. It is illegal to code generate
159 // it, but tolerated for intermediate implementation stages.
162 /// Raw - This form is for instructions that don't have any operands, so
163 /// they are just a fixed opcode value, like 'leave'.
166 /// AddRegFrm - This form is used for instructions like 'push r32' that have
167 /// their one register operand added to their opcode.
170 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
171 /// to specify a destination, which in this case is a register.
175 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
176 /// to specify a destination, which in this case is memory.
180 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
181 /// to specify a source, which in this case is a register.
185 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
186 /// to specify a source, which in this case is memory.
190 /// MRM[0-7][rm] - These forms are used to represent instructions that use
191 /// a Mod/RM byte, and use the middle field to hold extended opcode
192 /// information. In the intel manual these are represented as /0, /1, ...
195 // First, instructions that operate on a register r/m operand...
196 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3
197 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7
199 // Next, instructions that operate on a memory r/m operand...
200 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3
201 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7
203 // MRMInitReg - This form is used for instructions whose source and
204 // destinations are the same register.
209 //===------------------------------------------------------------------===//
212 // OpSize - Set if this instruction requires an operand size prefix (0x66),
213 // which most often indicates that the instruction operates on 16 bit data
214 // instead of 32 bit data.
217 // AsSize - Set if this instruction requires an operand size prefix (0x67),
218 // which most often indicates that the instruction address 16 bit address
219 // instead of 32 bit address (or 32 bit address in 64 bit mode).
222 //===------------------------------------------------------------------===//
223 // Op0Mask - There are several prefix bytes that are used to form two byte
224 // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is
225 // used to obtain the setting of this field. If no bits in this field is
226 // set, there is no prefix byte for obtaining a multibyte opcode.
229 Op0Mask = 0xF << Op0Shift,
231 // TB - TwoByte - Set if this instruction has a two byte opcode, which
232 // starts with a 0x0F byte before the real opcode.
235 // REP - The 0xF3 prefix byte indicating repetition of the following
239 // D8-DF - These escape opcodes are used by the floating point unit. These
240 // values must remain sequential.
241 D8 = 3 << Op0Shift, D9 = 4 << Op0Shift,
242 DA = 5 << Op0Shift, DB = 6 << Op0Shift,
243 DC = 7 << Op0Shift, DD = 8 << Op0Shift,
244 DE = 9 << Op0Shift, DF = 10 << Op0Shift,
246 // XS, XD - These prefix codes are for single and double precision scalar
247 // floating point operations performed in the SSE registers.
248 XD = 11 << Op0Shift, XS = 12 << Op0Shift,
250 // T8, TA - Prefix after the 0x0F prefix.
251 T8 = 13 << Op0Shift, TA = 14 << Op0Shift,
253 //===------------------------------------------------------------------===//
254 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
255 // They are used to specify GPRs and SSE registers, 64-bit operand size,
256 // etc. We only cares about REX.W and REX.R bits and only the former is
257 // statically determined.
260 REX_W = 1 << REXShift,
262 //===------------------------------------------------------------------===//
263 // This three-bit field describes the size of an immediate operand. Zero is
264 // unused so that we can tell if we forgot to set a value.
266 ImmMask = 7 << ImmShift,
267 Imm8 = 1 << ImmShift,
268 Imm16 = 2 << ImmShift,
269 Imm32 = 3 << ImmShift,
270 Imm64 = 4 << ImmShift,
272 //===------------------------------------------------------------------===//
273 // FP Instruction Classification... Zero is non-fp instruction.
275 // FPTypeMask - Mask for all of the FP types...
277 FPTypeMask = 7 << FPTypeShift,
279 // NotFP - The default, set for instructions that do not use FP registers.
280 NotFP = 0 << FPTypeShift,
282 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
283 ZeroArgFP = 1 << FPTypeShift,
285 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
286 OneArgFP = 2 << FPTypeShift,
288 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
289 // result back to ST(0). For example, fcos, fsqrt, etc.
291 OneArgFPRW = 3 << FPTypeShift,
293 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
294 // explicit argument, storing the result to either ST(0) or the implicit
295 // argument. For example: fadd, fsub, fmul, etc...
296 TwoArgFP = 4 << FPTypeShift,
298 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
299 // explicit argument, but have no destination. Example: fucom, fucomi, ...
300 CompareFP = 5 << FPTypeShift,
302 // CondMovFP - "2 operand" floating point conditional move instructions.
303 CondMovFP = 6 << FPTypeShift,
305 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
306 SpecialFP = 7 << FPTypeShift,
310 LOCK = 1 << LOCKShift,
312 // Segment override prefixes. Currently we just need ability to address
313 // stuff in gs and fs segments.
315 SegOvrMask = 3 << SegOvrShift,
316 FS = 1 << SegOvrShift,
317 GS = 2 << SegOvrShift,
319 // Bits 22 -> 23 are unused
321 OpcodeMask = 0xFF << OpcodeShift
325 const int X86AddrNumOperands = 5;
327 inline static bool isScale(const MachineOperand &MO) {
329 (MO.getImm() == 1 || MO.getImm() == 2 ||
330 MO.getImm() == 4 || MO.getImm() == 8);
333 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
334 if (MI->getOperand(Op).isFI()) return true;
335 return Op+4 <= MI->getNumOperands() &&
336 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
337 MI->getOperand(Op+2).isReg() &&
338 (MI->getOperand(Op+3).isImm() ||
339 MI->getOperand(Op+3).isGlobal() ||
340 MI->getOperand(Op+3).isCPI() ||
341 MI->getOperand(Op+3).isJTI());
344 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
345 if (MI->getOperand(Op).isFI()) return true;
346 return Op+5 <= MI->getNumOperands() &&
347 MI->getOperand(Op+4).isReg() &&
351 class X86InstrInfo : public TargetInstrInfoImpl {
352 X86TargetMachine &TM;
353 const X86RegisterInfo RI;
355 /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
356 /// RegOp2MemOpTable2 - Load / store folding opcode maps.
358 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr;
359 DenseMap<unsigned*, unsigned> RegOp2MemOpTable0;
360 DenseMap<unsigned*, unsigned> RegOp2MemOpTable1;
361 DenseMap<unsigned*, unsigned> RegOp2MemOpTable2;
363 /// MemOp2RegOpTable - Load / store unfolding opcode map.
365 DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
368 explicit X86InstrInfo(X86TargetMachine &tm);
370 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
371 /// such, whenever a client has an instance of instruction info, it should
372 /// always be able to get register info as well (through this method).
374 virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
376 /// Return true if the instruction is a register to register move and return
377 /// the source and dest operands and their sub-register indices by reference.
378 virtual bool isMoveInstr(const MachineInstr &MI,
379 unsigned &SrcReg, unsigned &DstReg,
380 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
382 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
383 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
385 bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const;
386 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
387 unsigned DestReg, const MachineInstr *Orig) const;
389 bool isInvariantLoad(const MachineInstr *MI) const;
391 /// convertToThreeAddress - This method must be implemented by targets that
392 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
393 /// may be able to convert a two-address instruction into a true
394 /// three-address instruction on demand. This allows the X86 target (for
395 /// example) to convert ADD and SHL instructions into LEA instructions if they
396 /// would require register copies due to two-addressness.
398 /// This method returns a null pointer if the transformation cannot be
399 /// performed, otherwise it returns the new instruction.
401 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
402 MachineBasicBlock::iterator &MBBI,
403 LiveVariables *LV) const;
405 /// commuteInstruction - We have a few instructions that must be hacked on to
408 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
411 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
412 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
413 MachineBasicBlock *&FBB,
414 SmallVectorImpl<MachineOperand> &Cond,
415 bool AllowModify) const;
416 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
417 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
418 MachineBasicBlock *FBB,
419 const SmallVectorImpl<MachineOperand> &Cond) const;
420 virtual bool copyRegToReg(MachineBasicBlock &MBB,
421 MachineBasicBlock::iterator MI,
422 unsigned DestReg, unsigned SrcReg,
423 const TargetRegisterClass *DestRC,
424 const TargetRegisterClass *SrcRC) const;
425 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
426 MachineBasicBlock::iterator MI,
427 unsigned SrcReg, bool isKill, int FrameIndex,
428 const TargetRegisterClass *RC) const;
430 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
431 SmallVectorImpl<MachineOperand> &Addr,
432 const TargetRegisterClass *RC,
433 SmallVectorImpl<MachineInstr*> &NewMIs) const;
435 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
436 MachineBasicBlock::iterator MI,
437 unsigned DestReg, int FrameIndex,
438 const TargetRegisterClass *RC) const;
440 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
441 SmallVectorImpl<MachineOperand> &Addr,
442 const TargetRegisterClass *RC,
443 SmallVectorImpl<MachineInstr*> &NewMIs) const;
445 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
446 MachineBasicBlock::iterator MI,
447 const std::vector<CalleeSavedInfo> &CSI) const;
449 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
450 MachineBasicBlock::iterator MI,
451 const std::vector<CalleeSavedInfo> &CSI) const;
453 /// foldMemoryOperand - If this target supports it, fold a load or store of
454 /// the specified stack slot into the specified machine instruction for the
455 /// specified operand(s). If this is possible, the target should perform the
456 /// folding and return true, otherwise it should return false. If it folds
457 /// the instruction, it is likely that the MachineInstruction the iterator
458 /// references has been changed.
459 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
461 const SmallVectorImpl<unsigned> &Ops,
462 int FrameIndex) const;
464 /// foldMemoryOperand - Same as the previous version except it allows folding
465 /// of any load and store from / to any address, not just from a specific
467 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
469 const SmallVectorImpl<unsigned> &Ops,
470 MachineInstr* LoadMI) const;
472 /// canFoldMemoryOperand - Returns true if the specified load / store is
473 /// folding is possible.
474 virtual bool canFoldMemoryOperand(const MachineInstr*,
475 const SmallVectorImpl<unsigned> &) const;
477 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
478 /// a store or a load and a store into two or more instruction. If this is
479 /// possible, returns true as well as the new instructions by reference.
480 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
481 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
482 SmallVectorImpl<MachineInstr*> &NewMIs) const;
484 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
485 SmallVectorImpl<SDNode*> &NewNodes) const;
487 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
488 /// instruction after load / store are unfolded from an instruction of the
489 /// specified opcode. It returns zero if the specified unfolding is not
491 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
492 bool UnfoldLoad, bool UnfoldStore) const;
494 virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
496 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
498 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
499 /// instruction that defines the specified register class.
500 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
502 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
503 // specified machine instruction.
505 unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const {
506 return TID->TSFlags >> X86II::OpcodeShift;
508 unsigned char getBaseOpcodeFor(unsigned Opcode) const {
509 return getBaseOpcodeFor(&get(Opcode));
512 static bool isX86_64NonExtLowByteReg(unsigned reg) {
513 return (reg == X86::SPL || reg == X86::BPL ||
514 reg == X86::SIL || reg == X86::DIL);
517 static unsigned sizeOfImm(const TargetInstrDesc *Desc);
518 static bool isX86_64ExtendedReg(const MachineOperand &MO);
519 static unsigned determineREX(const MachineInstr &MI);
521 /// GetInstSize - Returns the size of the specified MachineInstr.
523 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
525 /// getGlobalBaseReg - Return a virtual register initialized with the
526 /// the global base register value. Output instructions required to
527 /// initialize the register in the function entry block, if necessary.
529 unsigned getGlobalBaseReg(MachineFunction *MF) const;
532 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
535 const SmallVectorImpl<MachineOperand> &MOs) const;
538 } // End llvm namespace