1 //===-- X86InstructionInfo.def - X86 Instruction Information ----*- C++ -*-===//
3 // This file describes all of the instructions that the X86 backend uses. It
4 // relys on an external 'I' macro being defined that takes the arguments
5 // specified below, and is used to make all of the information relevant to an
6 // instruction be in one place.
8 // Note that X86 Instructions always have the destination register listed as
9 // operand 0, unless it does not produce a value (in which case the TSFlags will
10 // include X86II::Void).
12 //===----------------------------------------------------------------------===//
14 // NOTE: No include guards desired
17 #errror "Must define I macro before including X86/X86InstructionInfo.def!"
20 // Arguments to be passed into the I macro
21 // #1: Enum name - This ends up being the opcode symbol in the X86 namespace
22 // #2: Opcode name, as used by the gnu assembler
23 // #3: Instruction Flags - This should be a field or'd together that contains
24 // constants from the MachineInstrInfo.h file.
25 // #4: Target Specific Flags - Another bitfield containing X86 specific flags
26 // that we are interested in for each instruction. These should be flags
27 // defined in X86InstrInfo.h in the X86II namespace.
30 // The first instruction must always be the PHI instruction: (FIXME, not yet)
33 // The second instruction must always be the noop instruction: (FIXME, not yet)
34 I(NOOP , "nop", 0, X86II::Void) // nop 90
36 // Flow control instructions
37 I(RET , "ret", M_RET_FLAG, X86II::Void) // ret CB
38 I(JMP , "jmp", M_BRANCH_FLAG, X86II::Void) // jmp foo EB|E9 cb|w
41 I(MOVrr8 , "movb", 0, 0) // R8 = R8 88/r
42 I(MOVrr16 , "movw", 0, 0) // R16 = R16 89/r
43 I(MOVrr32 , "movl", 0, 0) // R32 = R32 89/r
44 I(MOVir8 , "movb", 0, 0) // R8 = imm8 B0+ rb
45 I(MOVir16 , "movw", 0, 0) // R16 = imm16 B8+ rw
46 I(MOVir32 , "movl", 0, 0) // R32 = imm32 B8+ rd
48 // Arithmetic instructions
49 I(ADDrr8 , "addb", 0, 0) // R8 += R8 00/r
50 I(ADDrr16 , "addw", 0, 0) // R16 += R16 01/r
51 I(ADDrr32 , "addl", 0, 0) // R32 += R32 01/r
52 I(SUBrr8 , "subb", 0, 0) // R8 -= R8 2A/r
53 I(SUBrr16 , "subw", 0, 0) // R16 -= R16 2B/r
54 I(SUBrr32 , "subl", 0, 0) // R32 -= R32 2B/r
55 I(MULrr8 , "mulb", 0, 0) // AX = AL*R8 F6/4
56 I(MULrr16 , "mulw", 0, 0) // DX:AX= AX*R16 F7/4
57 I(MULrr32 , "mull", 0, 0) // ED:EA= EA*R32 F7/4
61 I(ANDrr8 , "andb", 0, 0) // R8 &= R8 20/r
62 I(ANDrr16 , "andw", 0, 0) // R16 &= R16 21/r
63 I(ANDrr32 , "andl", 0, 0) // R32 &= R32 21/r
64 I(ORrr8 , "orb", 0, 0) // R8 |= R8 08/r
65 I(ORrr16 , "orw", 0, 0) // R16 |= R16 09/r
66 I(ORrr32 , "orl", 0, 0) // R32 |= R32 09/r
67 I(XORrr8 , "xorb", 0, 0) // R8 ^= R8 30/r
68 I(XORrr16 , "xorw", 0, 0) // R16 ^= R16 31/r
69 I(XORrr32 , "xorl", 0, 0) // R32 ^= R32 31/r
72 I(SHLrr8 , "shlb", 0, 0) // R8 <<= cl D2/4
73 I(SHLir8 , "shlb", 0, 0) // R8 <<= imm8 C0/4 ib
74 I(SHLrr16 , "shlw", 0, 0) // R16 <<= cl D3/4
75 I(SHLir16 , "shlw", 0, 0) // R16 <<= imm8 C1/4 ib
76 I(SHLrr32 , "shll", 0, 0) // R32 <<= cl D3/4
77 I(SHLir32 , "shll", 0, 0) // R32 <<= imm8 C1/4 ib
78 I(SHRrr8 , "shrb", 0, 0) // R8 >>>= cl D2/5
79 I(SHRir8 , "shrb", 0, 0) // R8 >>>= imm8 C0/5 ib
80 I(SHRrr16 , "shrw", 0, 0) // R16 >>>= cl D3/5
81 I(SHRir16 , "shrw", 0, 0) // R16 >>>= imm8 C1/5 ib
82 I(SHRrr32 , "shrl", 0, 0) // R32 >>>= cl D3/5
83 I(SHRir32 , "shrl", 0, 0) // R32 >>>= imm8 C1/5 ib
84 I(SARrr8 , "sarb", 0, 0) // R8 >>= cl D2/7
85 I(SARir8 , "sarb", 0, 0) // R8 >>= imm8 C0/7 ib
86 I(SARrr16 , "sarw", 0, 0) // R16 >>= cl D3/7
87 I(SARir16 , "sarw", 0, 0) // R16 >>= imm8 C1/7 ib
88 I(SARrr32 , "sarl", 0, 0) // R32 >>= cl D3/7
89 I(SARir32 , "sarl", 0, 0) // R32 >>= imm8 C1/7 ib
91 // At this point, I is dead, so undefine the macro