1 //===-- X86InstructionInfo.def - X86 Instruction Information ----*- C++ -*-===//
3 // This file describes all of the instructions that the X86 backend uses. It
4 // relys on an external 'I' macro being defined that takes the arguments
5 // specified below, and is used to make all of the information relevant to an
6 // instruction be in one place.
8 // Note that X86 Instructions always have the destination register listed as
9 // operand 0, unless it does not produce a value (in which case the TSFlags will
10 // include X86II::Void).
12 //===----------------------------------------------------------------------===//
14 // NOTE: No include guards desired
17 #errror "Must define I macro before including X86/X86InstructionInfo.def!"
20 // Arguments to be passed into the I macro
21 // #1: Enum name - This ends up being the opcode symbol in the X86 namespace
22 // #2: Opcode name, as used by the gnu assembler
23 // #3: Instruction Flags - This should be a field or'd together that contains
24 // constants from the MachineInstrInfo.h file.
25 // #4: Target Specific Flags - Another bitfield containing X86 specific flags
26 // that we are interested in for each instruction. These should be flags
27 // defined in X86InstrInfo.h in the X86II namespace.
30 // The first instruction must always be the PHI instruction: (FIXME, not yet)
33 // The second instruction must always be the noop instruction: (FIXME, not yet)
34 I(NOOP , "nop", 0, X86II::Void) // nop 90
36 // Flow control instructions
37 I(RET , "ret", M_RET_FLAG, X86II::Void) // ret CB
38 I(JMP , "jmp", M_BRANCH_FLAG, X86II::Void) // jmp foo EB|E9 cb|w
41 I(MOVrr8 , "movb", 0, 0) // R8 = R8 88/r
42 I(MOVrr16 , "movw", 0, 0) // R16 = R16 89/r
43 I(MOVrr32 , "movl", 0, 0) // R32 = R32 89/r
44 I(MOVir8 , "movb", 0, 0) // R8 = imm8 B0+ rb
45 I(MOVir16 , "movw", 0, 0) // R16 = imm16 B8+ rw
46 I(MOVir32 , "movl", 0, 0) // R32 = imm32 B8+ rd
47 I(LEAVE , "leave", 0, 0) // leave C9
49 // Arithmetic instructions
50 I(ADDrr8 , "addb", 0, 0) // R8 += R8 00/r
51 I(ADDrr16 , "addw", 0, 0) // R16 += R16 01/r
52 I(ADDrr32 , "addl", 0, 0) // R32 += R32 01/r
53 I(SUBrr8 , "subb", 0, 0) // R8 -= R8 2A/r
54 I(SUBrr16 , "subw", 0, 0) // R16 -= R16 2B/r
55 I(SUBrr32 , "subl", 0, 0) // R32 -= R32 2B/r
56 I(MULrr8 , "mulb", 0, 0) // AX = AL*R8 F6/4
57 I(MULrr16 , "mulw", 0, 0) // DX:AX= AX*R16 F7/4
58 I(MULrr32 , "mull", 0, 0) // ED:EA= EA*R32 F7/4
60 // unsigned division/remainder
61 I(DIVrr8 , "divb", 0, 0) // AX/r8= AL&AH F6/6
62 I(DIVrr16 , "divw", 0, 0) // DA/r16=AX&DX F7/6
63 I(DIVrr32 , "divl", 0, 0) // DA/r32=EAX&DX F7/6
65 // signed division/remainder
66 I(IDIVrr8 , "idivb", 0, 0) // AX/r8= AL&AH F6/6
67 I(IDIVrr16 , "idivw", 0, 0) // DA/r16=AX&DX F7/6
68 I(IDIVrr32 , "idivl", 0, 0) // DA/r32=EAX&DX F7/6
71 I(ANDrr8 , "andb", 0, 0) // R8 &= R8 20/r
72 I(ANDrr16 , "andw", 0, 0) // R16 &= R16 21/r
73 I(ANDrr32 , "andl", 0, 0) // R32 &= R32 21/r
74 I(ORrr8 , "orb", 0, 0) // R8 |= R8 08/r
75 I(ORrr16 , "orw", 0, 0) // R16 |= R16 09/r
76 I(ORrr32 , "orl", 0, 0) // R32 |= R32 09/r
77 I(XORrr8 , "xorb", 0, 0) // R8 ^= R8 30/r
78 I(XORrr16 , "xorw", 0, 0) // R16 ^= R16 31/r
79 I(XORrr32 , "xorl", 0, 0) // R32 ^= R32 31/r
82 I(SHLrr8 , "shlb", 0, 0) // R8 <<= cl D2/4
83 I(SHLir8 , "shlb", 0, 0) // R8 <<= imm8 C0/4 ib
84 I(SHLrr16 , "shlw", 0, 0) // R16 <<= cl D3/4
85 I(SHLir16 , "shlw", 0, 0) // R16 <<= imm8 C1/4 ib
86 I(SHLrr32 , "shll", 0, 0) // R32 <<= cl D3/4
87 I(SHLir32 , "shll", 0, 0) // R32 <<= imm8 C1/4 ib
88 I(SHRrr8 , "shrb", 0, 0) // R8 >>>= cl D2/5
89 I(SHRir8 , "shrb", 0, 0) // R8 >>>= imm8 C0/5 ib
90 I(SHRrr16 , "shrw", 0, 0) // R16 >>>= cl D3/5
91 I(SHRir16 , "shrw", 0, 0) // R16 >>>= imm8 C1/5 ib
92 I(SHRrr32 , "shrl", 0, 0) // R32 >>>= cl D3/5
93 I(SHRir32 , "shrl", 0, 0) // R32 >>>= imm8 C1/5 ib
94 I(SARrr8 , "sarb", 0, 0) // R8 >>= cl D2/7
95 I(SARir8 , "sarb", 0, 0) // R8 >>= imm8 C0/7 ib
96 I(SARrr16 , "sarw", 0, 0) // R16 >>= cl D3/7
97 I(SARir16 , "sarw", 0, 0) // R16 >>= imm8 C1/7 ib
98 I(SARrr32 , "sarl", 0, 0) // R32 >>= cl D3/7
99 I(SARir32 , "sarl", 0, 0) // R32 >>= imm8 C1/7 ib
101 // Floating point loads
102 I(FLDr4 , "flds", 0, 0) // push float D9/0
103 I(FLDr8 , "fldl ", 0, 0) // push double DD/0
105 // Floating point compares
106 I(FUCOMPP , "fucompp", 0, 0) // compare+pop2x DA E9
108 // Floating point flag ops
109 I(FNSTSWr8 , "fnstsw", 0, 0) // AX = fp flags DF E0
111 // Condition code ops, incl. set if equal/not equal/...
112 I(SAHF , "sahf", 0, 0) // flags = AH 9E
113 I(SETA , "seta", 0, 0) // R8 = > unsign 0F 97
114 I(SETAE , "setae", 0, 0) // R8 = >=unsign 0F 93
115 I(SETB , "setb", 0, 0) // R8 = < unsign 0F 92
116 I(SETBE , "setbe", 0, 0) // R8 = <=unsign 0F 96
117 I(SETE , "sete", 0, 0) // R8 = == 0F 94
118 I(SETG , "setg", 0, 0) // R8 = > signed 0F 9F
119 I(SETGE , "setge", 0, 0) // R8 = >=signed 0F 9D
120 I(SETL , "setl", 0, 0) // R8 = < signed 0F 9C
121 I(SETLE , "setle", 0, 0) // R8 = <=signed 0F 9E
122 I(SETNE , "setne", 0, 0) // R8 = != 0F 95
124 // Integer comparisons
125 I(CMPrr8 , "cmpb", 0, 0) // compare R8,R8 38/r
126 I(CMPrr16 , "cmpw", 0, 0) // compare R16,R16 39/r
127 I(CMPrr32 , "cmpl", 0, 0) // compare R32,R32 39/r
130 I(CBW , "cbw", 0, 0) // AH = signext(AL) 98
131 I(CWD , "cwd", 0, 0) // DX = signext(AX) 99
132 I(CWQ , "cwq", 0, 0) // EDX= signext(EAX) 99
133 I(CWDE , "cwde", 0, 0) // EAX = extend AX 98
135 // At this point, I is dead, so undefine the macro