1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/LLVMContext.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/LiveVariables.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCInst.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetOptions.h"
37 #define GET_INSTRINFO_CTOR
38 #include "X86GenInstrInfo.inc"
43 NoFusing("disable-spill-fusing",
44 cl::desc("Disable fusing of spill code into instructions"));
46 PrintFailedFusing("print-failed-fuse-candidates",
47 cl::desc("Print instructions that the allocator wants to"
48 " fuse, but the X86 backend currently can't"),
51 ReMatPICStubLoad("remat-pic-stub-load",
52 cl::desc("Re-materialize load from stub in PIC mode"),
53 cl::init(false), cl::Hidden);
56 // Select which memory operand is being unfolded.
57 // (stored in bits 0 - 7)
64 // Minimum alignment required for load/store.
65 // Used for RegOp->MemOp conversion.
66 // (stored in bits 8 - 15)
68 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
69 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
70 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
71 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT,
73 // Do not insert the reverse map (MemOp -> RegOp) into the table.
74 // This may be needed because there is a many -> one mapping.
75 TB_NO_REVERSE = 1 << 16,
77 // Do not insert the forward map (RegOp -> MemOp) into the table.
78 // This is needed for Native Client, which prohibits branch
79 // instructions from using a memory operand.
80 TB_NO_FORWARD = 1 << 17,
82 TB_FOLDED_LOAD = 1 << 18,
83 TB_FOLDED_STORE = 1 << 19
86 struct X86OpTblEntry {
92 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
93 : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
94 ? X86::ADJCALLSTACKDOWN64
95 : X86::ADJCALLSTACKDOWN32),
96 (tm.getSubtarget<X86Subtarget>().is64Bit()
97 ? X86::ADJCALLSTACKUP64
98 : X86::ADJCALLSTACKUP32)),
99 TM(tm), RI(tm, *this) {
101 static const X86OpTblEntry OpTbl2Addr[] = {
102 { X86::ADC32ri, X86::ADC32mi, 0 },
103 { X86::ADC32ri8, X86::ADC32mi8, 0 },
104 { X86::ADC32rr, X86::ADC32mr, 0 },
105 { X86::ADC64ri32, X86::ADC64mi32, 0 },
106 { X86::ADC64ri8, X86::ADC64mi8, 0 },
107 { X86::ADC64rr, X86::ADC64mr, 0 },
108 { X86::ADD16ri, X86::ADD16mi, 0 },
109 { X86::ADD16ri8, X86::ADD16mi8, 0 },
110 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
111 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
112 { X86::ADD16rr, X86::ADD16mr, 0 },
113 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
114 { X86::ADD32ri, X86::ADD32mi, 0 },
115 { X86::ADD32ri8, X86::ADD32mi8, 0 },
116 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
117 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
118 { X86::ADD32rr, X86::ADD32mr, 0 },
119 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
120 { X86::ADD64ri32, X86::ADD64mi32, 0 },
121 { X86::ADD64ri8, X86::ADD64mi8, 0 },
122 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
123 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
124 { X86::ADD64rr, X86::ADD64mr, 0 },
125 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
126 { X86::ADD8ri, X86::ADD8mi, 0 },
127 { X86::ADD8rr, X86::ADD8mr, 0 },
128 { X86::AND16ri, X86::AND16mi, 0 },
129 { X86::AND16ri8, X86::AND16mi8, 0 },
130 { X86::AND16rr, X86::AND16mr, 0 },
131 { X86::AND32ri, X86::AND32mi, 0 },
132 { X86::AND32ri8, X86::AND32mi8, 0 },
133 { X86::AND32rr, X86::AND32mr, 0 },
134 { X86::AND64ri32, X86::AND64mi32, 0 },
135 { X86::AND64ri8, X86::AND64mi8, 0 },
136 { X86::AND64rr, X86::AND64mr, 0 },
137 { X86::AND8ri, X86::AND8mi, 0 },
138 { X86::AND8rr, X86::AND8mr, 0 },
139 { X86::DEC16r, X86::DEC16m, 0 },
140 { X86::DEC32r, X86::DEC32m, 0 },
141 { X86::DEC64_16r, X86::DEC64_16m, 0 },
142 { X86::DEC64_32r, X86::DEC64_32m, 0 },
143 { X86::DEC64r, X86::DEC64m, 0 },
144 { X86::DEC8r, X86::DEC8m, 0 },
145 { X86::INC16r, X86::INC16m, 0 },
146 { X86::INC32r, X86::INC32m, 0 },
147 { X86::INC64_16r, X86::INC64_16m, 0 },
148 { X86::INC64_32r, X86::INC64_32m, 0 },
149 { X86::INC64r, X86::INC64m, 0 },
150 { X86::INC8r, X86::INC8m, 0 },
151 { X86::NEG16r, X86::NEG16m, 0 },
152 { X86::NEG32r, X86::NEG32m, 0 },
153 { X86::NEG64r, X86::NEG64m, 0 },
154 { X86::NEG8r, X86::NEG8m, 0 },
155 { X86::NOT16r, X86::NOT16m, 0 },
156 { X86::NOT32r, X86::NOT32m, 0 },
157 { X86::NOT64r, X86::NOT64m, 0 },
158 { X86::NOT8r, X86::NOT8m, 0 },
159 { X86::OR16ri, X86::OR16mi, 0 },
160 { X86::OR16ri8, X86::OR16mi8, 0 },
161 { X86::OR16rr, X86::OR16mr, 0 },
162 { X86::OR32ri, X86::OR32mi, 0 },
163 { X86::OR32ri8, X86::OR32mi8, 0 },
164 { X86::OR32rr, X86::OR32mr, 0 },
165 { X86::OR64ri32, X86::OR64mi32, 0 },
166 { X86::OR64ri8, X86::OR64mi8, 0 },
167 { X86::OR64rr, X86::OR64mr, 0 },
168 { X86::OR8ri, X86::OR8mi, 0 },
169 { X86::OR8rr, X86::OR8mr, 0 },
170 { X86::ROL16r1, X86::ROL16m1, 0 },
171 { X86::ROL16rCL, X86::ROL16mCL, 0 },
172 { X86::ROL16ri, X86::ROL16mi, 0 },
173 { X86::ROL32r1, X86::ROL32m1, 0 },
174 { X86::ROL32rCL, X86::ROL32mCL, 0 },
175 { X86::ROL32ri, X86::ROL32mi, 0 },
176 { X86::ROL64r1, X86::ROL64m1, 0 },
177 { X86::ROL64rCL, X86::ROL64mCL, 0 },
178 { X86::ROL64ri, X86::ROL64mi, 0 },
179 { X86::ROL8r1, X86::ROL8m1, 0 },
180 { X86::ROL8rCL, X86::ROL8mCL, 0 },
181 { X86::ROL8ri, X86::ROL8mi, 0 },
182 { X86::ROR16r1, X86::ROR16m1, 0 },
183 { X86::ROR16rCL, X86::ROR16mCL, 0 },
184 { X86::ROR16ri, X86::ROR16mi, 0 },
185 { X86::ROR32r1, X86::ROR32m1, 0 },
186 { X86::ROR32rCL, X86::ROR32mCL, 0 },
187 { X86::ROR32ri, X86::ROR32mi, 0 },
188 { X86::ROR64r1, X86::ROR64m1, 0 },
189 { X86::ROR64rCL, X86::ROR64mCL, 0 },
190 { X86::ROR64ri, X86::ROR64mi, 0 },
191 { X86::ROR8r1, X86::ROR8m1, 0 },
192 { X86::ROR8rCL, X86::ROR8mCL, 0 },
193 { X86::ROR8ri, X86::ROR8mi, 0 },
194 { X86::SAR16r1, X86::SAR16m1, 0 },
195 { X86::SAR16rCL, X86::SAR16mCL, 0 },
196 { X86::SAR16ri, X86::SAR16mi, 0 },
197 { X86::SAR32r1, X86::SAR32m1, 0 },
198 { X86::SAR32rCL, X86::SAR32mCL, 0 },
199 { X86::SAR32ri, X86::SAR32mi, 0 },
200 { X86::SAR64r1, X86::SAR64m1, 0 },
201 { X86::SAR64rCL, X86::SAR64mCL, 0 },
202 { X86::SAR64ri, X86::SAR64mi, 0 },
203 { X86::SAR8r1, X86::SAR8m1, 0 },
204 { X86::SAR8rCL, X86::SAR8mCL, 0 },
205 { X86::SAR8ri, X86::SAR8mi, 0 },
206 { X86::SBB32ri, X86::SBB32mi, 0 },
207 { X86::SBB32ri8, X86::SBB32mi8, 0 },
208 { X86::SBB32rr, X86::SBB32mr, 0 },
209 { X86::SBB64ri32, X86::SBB64mi32, 0 },
210 { X86::SBB64ri8, X86::SBB64mi8, 0 },
211 { X86::SBB64rr, X86::SBB64mr, 0 },
212 { X86::SHL16rCL, X86::SHL16mCL, 0 },
213 { X86::SHL16ri, X86::SHL16mi, 0 },
214 { X86::SHL32rCL, X86::SHL32mCL, 0 },
215 { X86::SHL32ri, X86::SHL32mi, 0 },
216 { X86::SHL64rCL, X86::SHL64mCL, 0 },
217 { X86::SHL64ri, X86::SHL64mi, 0 },
218 { X86::SHL8rCL, X86::SHL8mCL, 0 },
219 { X86::SHL8ri, X86::SHL8mi, 0 },
220 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
221 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
222 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
223 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
224 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
225 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
226 { X86::SHR16r1, X86::SHR16m1, 0 },
227 { X86::SHR16rCL, X86::SHR16mCL, 0 },
228 { X86::SHR16ri, X86::SHR16mi, 0 },
229 { X86::SHR32r1, X86::SHR32m1, 0 },
230 { X86::SHR32rCL, X86::SHR32mCL, 0 },
231 { X86::SHR32ri, X86::SHR32mi, 0 },
232 { X86::SHR64r1, X86::SHR64m1, 0 },
233 { X86::SHR64rCL, X86::SHR64mCL, 0 },
234 { X86::SHR64ri, X86::SHR64mi, 0 },
235 { X86::SHR8r1, X86::SHR8m1, 0 },
236 { X86::SHR8rCL, X86::SHR8mCL, 0 },
237 { X86::SHR8ri, X86::SHR8mi, 0 },
238 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
239 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
240 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
241 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
242 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
243 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
244 { X86::SUB16ri, X86::SUB16mi, 0 },
245 { X86::SUB16ri8, X86::SUB16mi8, 0 },
246 { X86::SUB16rr, X86::SUB16mr, 0 },
247 { X86::SUB32ri, X86::SUB32mi, 0 },
248 { X86::SUB32ri8, X86::SUB32mi8, 0 },
249 { X86::SUB32rr, X86::SUB32mr, 0 },
250 { X86::SUB64ri32, X86::SUB64mi32, 0 },
251 { X86::SUB64ri8, X86::SUB64mi8, 0 },
252 { X86::SUB64rr, X86::SUB64mr, 0 },
253 { X86::SUB8ri, X86::SUB8mi, 0 },
254 { X86::SUB8rr, X86::SUB8mr, 0 },
255 { X86::XOR16ri, X86::XOR16mi, 0 },
256 { X86::XOR16ri8, X86::XOR16mi8, 0 },
257 { X86::XOR16rr, X86::XOR16mr, 0 },
258 { X86::XOR32ri, X86::XOR32mi, 0 },
259 { X86::XOR32ri8, X86::XOR32mi8, 0 },
260 { X86::XOR32rr, X86::XOR32mr, 0 },
261 { X86::XOR64ri32, X86::XOR64mi32, 0 },
262 { X86::XOR64ri8, X86::XOR64mi8, 0 },
263 { X86::XOR64rr, X86::XOR64mr, 0 },
264 { X86::XOR8ri, X86::XOR8mi, 0 },
265 { X86::XOR8rr, X86::XOR8mr, 0 }
268 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
269 unsigned RegOp = OpTbl2Addr[i].RegOp;
270 unsigned MemOp = OpTbl2Addr[i].MemOp;
271 unsigned Flags = OpTbl2Addr[i].Flags;
272 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
274 // Index 0, folded load and store, no alignment requirement.
275 Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
278 static const X86OpTblEntry OpTbl0[] = {
279 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
280 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
281 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
282 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
283 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
284 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
285 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
286 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
287 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
288 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
289 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
290 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
291 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
292 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
293 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
294 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
295 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
296 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
297 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
298 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
299 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
300 { X86::FsMOVAPDrr, X86::MOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE },
301 { X86::FsMOVAPSrr, X86::MOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE },
302 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
303 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
304 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
305 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
306 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
307 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
308 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
309 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
310 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
311 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
312 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
313 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
314 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
315 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
316 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
317 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
318 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
319 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
320 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
321 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
322 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
323 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
324 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
325 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
326 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
327 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
328 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
329 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
330 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
331 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
332 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
333 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
334 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
335 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
336 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
337 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
338 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
339 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
340 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
341 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
342 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
343 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
344 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
345 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
346 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
347 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
348 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
349 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
350 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
351 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
352 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
353 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
354 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
355 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
356 // AVX 128-bit versions of foldable instructions
357 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
358 { X86::FsVMOVAPDrr, X86::VMOVSDmr, TB_FOLDED_STORE | TB_NO_REVERSE },
359 { X86::FsVMOVAPSrr, X86::VMOVSSmr, TB_FOLDED_STORE | TB_NO_REVERSE },
360 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
361 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
362 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
363 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
364 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
365 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
366 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
367 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
368 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
369 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
370 // AVX 256-bit foldable instructions
371 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
372 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
373 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
374 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
375 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
376 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE }
379 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
380 unsigned RegOp = OpTbl0[i].RegOp;
381 unsigned MemOp = OpTbl0[i].MemOp;
382 unsigned Flags = OpTbl0[i].Flags;
383 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
384 RegOp, MemOp, TB_INDEX_0 | Flags);
387 static const X86OpTblEntry OpTbl1[] = {
388 { X86::CMP16rr, X86::CMP16rm, 0 },
389 { X86::CMP32rr, X86::CMP32rm, 0 },
390 { X86::CMP64rr, X86::CMP64rm, 0 },
391 { X86::CMP8rr, X86::CMP8rm, 0 },
392 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
393 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
394 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
395 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
396 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
397 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
398 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
399 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
400 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
401 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
402 { X86::FsMOVAPDrr, X86::MOVSDrm, TB_NO_REVERSE },
403 { X86::FsMOVAPSrr, X86::MOVSSrm, TB_NO_REVERSE },
404 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
405 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
406 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
407 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
408 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
409 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
410 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
411 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
412 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, TB_ALIGN_16 },
413 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, TB_ALIGN_16 },
414 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, TB_ALIGN_16 },
415 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, TB_ALIGN_16 },
416 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, TB_ALIGN_16 },
417 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
418 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
419 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
420 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
421 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
422 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
423 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
424 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
425 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
426 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
427 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
428 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
429 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
430 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
431 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
432 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
433 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
434 { X86::MOV16rr, X86::MOV16rm, 0 },
435 { X86::MOV32rr, X86::MOV32rm, 0 },
436 { X86::MOV64rr, X86::MOV64rm, 0 },
437 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
438 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
439 { X86::MOV8rr, X86::MOV8rm, 0 },
440 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
441 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
442 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
443 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
444 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
445 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
446 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
447 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
448 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
449 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
450 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
451 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
452 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
453 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
454 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
455 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
456 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
457 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
458 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
459 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
460 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
461 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
462 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
463 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
464 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
465 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
466 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
467 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
468 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
469 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
470 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
471 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
472 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
473 { X86::RCPPSr_Int, X86::RCPPSm_Int, TB_ALIGN_16 },
474 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
475 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, TB_ALIGN_16 },
476 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
477 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
478 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
479 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, TB_ALIGN_16 },
480 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
481 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, TB_ALIGN_16 },
482 { X86::SQRTSDr, X86::SQRTSDm, 0 },
483 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
484 { X86::SQRTSSr, X86::SQRTSSm, 0 },
485 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
486 { X86::TEST16rr, X86::TEST16rm, 0 },
487 { X86::TEST32rr, X86::TEST32rm, 0 },
488 { X86::TEST64rr, X86::TEST64rm, 0 },
489 { X86::TEST8rr, X86::TEST8rm, 0 },
490 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
491 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
492 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
493 // AVX 128-bit versions of foldable instructions
494 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
495 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
496 { X86::Int_VCVTDQ2PDrr, X86::Int_VCVTDQ2PDrm, TB_ALIGN_16 },
497 { X86::Int_VCVTDQ2PSrr, X86::Int_VCVTDQ2PSrm, TB_ALIGN_16 },
498 { X86::Int_VCVTPD2DQrr, X86::Int_VCVTPD2DQrm, TB_ALIGN_16 },
499 { X86::Int_VCVTPD2PSrr, X86::Int_VCVTPD2PSrm, TB_ALIGN_16 },
500 { X86::Int_VCVTPS2DQrr, X86::Int_VCVTPS2DQrm, TB_ALIGN_16 },
501 { X86::Int_VCVTPS2PDrr, X86::Int_VCVTPS2PDrm, 0 },
502 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
503 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
504 { X86::FsVMOVAPDrr, X86::VMOVSDrm, TB_NO_REVERSE },
505 { X86::FsVMOVAPSrr, X86::VMOVSSrm, TB_NO_REVERSE },
506 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
507 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
508 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
509 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
510 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
511 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
512 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
513 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
514 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, TB_ALIGN_16 },
515 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, TB_ALIGN_16 },
516 { X86::VMOVUPDrr, X86::VMOVUPDrm, TB_ALIGN_16 },
517 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
518 { X86::VMOVZDI2PDIrr, X86::VMOVZDI2PDIrm, 0 },
519 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 },
520 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
521 { X86::VPABSBrr128, X86::VPABSBrm128, TB_ALIGN_16 },
522 { X86::VPABSDrr128, X86::VPABSDrm128, TB_ALIGN_16 },
523 { X86::VPABSWrr128, X86::VPABSWrm128, TB_ALIGN_16 },
524 { X86::VPERMILPDri, X86::VPERMILPDmi, TB_ALIGN_16 },
525 { X86::VPERMILPSri, X86::VPERMILPSmi, TB_ALIGN_16 },
526 { X86::VPSHUFDri, X86::VPSHUFDmi, TB_ALIGN_16 },
527 { X86::VPSHUFHWri, X86::VPSHUFHWmi, TB_ALIGN_16 },
528 { X86::VPSHUFLWri, X86::VPSHUFLWmi, TB_ALIGN_16 },
529 { X86::VRCPPSr, X86::VRCPPSm, TB_ALIGN_16 },
530 { X86::VRCPPSr_Int, X86::VRCPPSm_Int, TB_ALIGN_16 },
531 { X86::VRSQRTPSr, X86::VRSQRTPSm, TB_ALIGN_16 },
532 { X86::VRSQRTPSr_Int, X86::VRSQRTPSm_Int, TB_ALIGN_16 },
533 { X86::VSQRTPDr, X86::VSQRTPDm, TB_ALIGN_16 },
534 { X86::VSQRTPDr_Int, X86::VSQRTPDm_Int, TB_ALIGN_16 },
535 { X86::VSQRTPSr, X86::VSQRTPSm, TB_ALIGN_16 },
536 { X86::VSQRTPSr_Int, X86::VSQRTPSm_Int, TB_ALIGN_16 },
537 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
538 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
539 // AVX 256-bit foldable instructions
540 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
541 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
542 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
543 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
544 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
545 { X86::VPERMILPDYri, X86::VPERMILPDYmi, TB_ALIGN_32 },
546 { X86::VPERMILPSYri, X86::VPERMILPSYmi, TB_ALIGN_32 },
547 // AVX2 foldable instructions
548 { X86::VPABSBrr256, X86::VPABSBrm256, TB_ALIGN_32 },
549 { X86::VPABSDrr256, X86::VPABSDrm256, TB_ALIGN_32 },
550 { X86::VPABSWrr256, X86::VPABSWrm256, TB_ALIGN_32 },
551 { X86::VPSHUFDYri, X86::VPSHUFDYmi, TB_ALIGN_32 },
552 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, TB_ALIGN_32 },
553 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, TB_ALIGN_32 },
554 { X86::VRCPPSYr, X86::VRCPPSYm, TB_ALIGN_32 },
555 { X86::VRCPPSYr_Int, X86::VRCPPSYm_Int, TB_ALIGN_32 },
556 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, TB_ALIGN_32 },
557 { X86::VRSQRTPSYr_Int, X86::VRSQRTPSYm_Int, TB_ALIGN_32 },
558 { X86::VSQRTPDYr, X86::VSQRTPDYm, TB_ALIGN_32 },
559 { X86::VSQRTPDYr_Int, X86::VSQRTPDYm_Int, TB_ALIGN_32 },
560 { X86::VSQRTPSYr, X86::VSQRTPSYm, TB_ALIGN_32 },
561 { X86::VSQRTPSYr_Int, X86::VSQRTPSYm_Int, TB_ALIGN_32 },
564 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
565 unsigned RegOp = OpTbl1[i].RegOp;
566 unsigned MemOp = OpTbl1[i].MemOp;
567 unsigned Flags = OpTbl1[i].Flags;
568 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
570 // Index 1, folded load
571 Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
574 static const X86OpTblEntry OpTbl2[] = {
575 { X86::ADC32rr, X86::ADC32rm, 0 },
576 { X86::ADC64rr, X86::ADC64rm, 0 },
577 { X86::ADD16rr, X86::ADD16rm, 0 },
578 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
579 { X86::ADD32rr, X86::ADD32rm, 0 },
580 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
581 { X86::ADD64rr, X86::ADD64rm, 0 },
582 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
583 { X86::ADD8rr, X86::ADD8rm, 0 },
584 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
585 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
586 { X86::ADDSDrr, X86::ADDSDrm, 0 },
587 { X86::ADDSSrr, X86::ADDSSrm, 0 },
588 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
589 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
590 { X86::AND16rr, X86::AND16rm, 0 },
591 { X86::AND32rr, X86::AND32rm, 0 },
592 { X86::AND64rr, X86::AND64rm, 0 },
593 { X86::AND8rr, X86::AND8rm, 0 },
594 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
595 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
596 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
597 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
598 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
599 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
600 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
601 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
602 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
603 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
604 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
605 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
606 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
607 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
608 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
609 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
610 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
611 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
612 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
613 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
614 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
615 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
616 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
617 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
618 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
619 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
620 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
621 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
622 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
623 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
624 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
625 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
626 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
627 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
628 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
629 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
630 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
631 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
632 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
633 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
634 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
635 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
636 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
637 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
638 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
639 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
640 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
641 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
642 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
643 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
644 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
645 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
646 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
647 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
648 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
649 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
650 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
651 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
652 { X86::CMPSDrr, X86::CMPSDrm, 0 },
653 { X86::CMPSSrr, X86::CMPSSrm, 0 },
654 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
655 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
656 { X86::DIVSDrr, X86::DIVSDrm, 0 },
657 { X86::DIVSSrr, X86::DIVSSrm, 0 },
658 { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 },
659 { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 },
660 { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 },
661 { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 },
662 { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 },
663 { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 },
664 { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 },
665 { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 },
666 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
667 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
668 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
669 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
670 { X86::IMUL16rr, X86::IMUL16rm, 0 },
671 { X86::IMUL32rr, X86::IMUL32rm, 0 },
672 { X86::IMUL64rr, X86::IMUL64rm, 0 },
673 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
674 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
675 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
676 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, TB_ALIGN_16 },
677 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
678 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, TB_ALIGN_16 },
679 { X86::MAXSDrr, X86::MAXSDrm, 0 },
680 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
681 { X86::MAXSSrr, X86::MAXSSrm, 0 },
682 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
683 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
684 { X86::MINPDrr_Int, X86::MINPDrm_Int, TB_ALIGN_16 },
685 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
686 { X86::MINPSrr_Int, X86::MINPSrm_Int, TB_ALIGN_16 },
687 { X86::MINSDrr, X86::MINSDrm, 0 },
688 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
689 { X86::MINSSrr, X86::MINSSrm, 0 },
690 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
691 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
692 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
693 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
694 { X86::MULSDrr, X86::MULSDrm, 0 },
695 { X86::MULSSrr, X86::MULSSrm, 0 },
696 { X86::OR16rr, X86::OR16rm, 0 },
697 { X86::OR32rr, X86::OR32rm, 0 },
698 { X86::OR64rr, X86::OR64rm, 0 },
699 { X86::OR8rr, X86::OR8rm, 0 },
700 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
701 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
702 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
703 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
704 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
705 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
706 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
707 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
708 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
709 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
710 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
711 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
712 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
713 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
714 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 },
715 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
716 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
717 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
718 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
719 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
720 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
721 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
722 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
723 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
724 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
725 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
726 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
727 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
728 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
729 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
730 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
731 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
732 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
733 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
734 { X86::PINSRWrri, X86::PINSRWrmi, TB_ALIGN_16 },
735 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
736 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
737 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
738 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
739 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
740 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
741 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
742 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
743 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
744 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
745 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
746 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
747 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
748 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
749 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
750 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
751 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 },
752 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 },
753 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 },
754 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
755 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
756 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
757 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
758 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
759 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
760 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
761 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
762 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
763 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
764 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
765 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
766 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
767 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
768 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
769 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
770 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
771 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
772 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
773 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
774 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
775 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
776 { X86::SBB32rr, X86::SBB32rm, 0 },
777 { X86::SBB64rr, X86::SBB64rm, 0 },
778 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
779 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
780 { X86::SUB16rr, X86::SUB16rm, 0 },
781 { X86::SUB32rr, X86::SUB32rm, 0 },
782 { X86::SUB64rr, X86::SUB64rm, 0 },
783 { X86::SUB8rr, X86::SUB8rm, 0 },
784 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
785 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
786 { X86::SUBSDrr, X86::SUBSDrm, 0 },
787 { X86::SUBSSrr, X86::SUBSSrm, 0 },
788 // FIXME: TEST*rr -> swapped operand of TEST*mr.
789 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
790 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
791 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
792 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
793 { X86::XOR16rr, X86::XOR16rm, 0 },
794 { X86::XOR32rr, X86::XOR32rm, 0 },
795 { X86::XOR64rr, X86::XOR64rm, 0 },
796 { X86::XOR8rr, X86::XOR8rm, 0 },
797 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
798 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
799 // AVX 128-bit versions of foldable instructions
800 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
801 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
802 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
803 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
804 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
805 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
806 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
807 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
808 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
809 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
810 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
811 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
812 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
813 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm, 0 },
814 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
815 { X86::Int_VCVTTSD2SIrr, X86::Int_VCVTTSD2SIrm, 0 },
816 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
817 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm, 0 },
818 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
819 { X86::Int_VCVTTSS2SIrr, X86::Int_VCVTTSS2SIrm, 0 },
820 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
821 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
822 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQrm, TB_ALIGN_16 },
823 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, TB_ALIGN_16 },
824 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
825 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
826 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
827 { X86::VADDPDrr, X86::VADDPDrm, TB_ALIGN_16 },
828 { X86::VADDPSrr, X86::VADDPSrm, TB_ALIGN_16 },
829 { X86::VADDSDrr, X86::VADDSDrm, 0 },
830 { X86::VADDSSrr, X86::VADDSSrm, 0 },
831 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, TB_ALIGN_16 },
832 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, TB_ALIGN_16 },
833 { X86::VANDNPDrr, X86::VANDNPDrm, TB_ALIGN_16 },
834 { X86::VANDNPSrr, X86::VANDNPSrm, TB_ALIGN_16 },
835 { X86::VANDPDrr, X86::VANDPDrm, TB_ALIGN_16 },
836 { X86::VANDPSrr, X86::VANDPSrm, TB_ALIGN_16 },
837 { X86::VBLENDPDrri, X86::VBLENDPDrmi, TB_ALIGN_16 },
838 { X86::VBLENDPSrri, X86::VBLENDPSrmi, TB_ALIGN_16 },
839 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, TB_ALIGN_16 },
840 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, TB_ALIGN_16 },
841 { X86::VCMPPDrri, X86::VCMPPDrmi, TB_ALIGN_16 },
842 { X86::VCMPPSrri, X86::VCMPPSrmi, TB_ALIGN_16 },
843 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
844 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
845 { X86::VDIVPDrr, X86::VDIVPDrm, TB_ALIGN_16 },
846 { X86::VDIVPSrr, X86::VDIVPSrm, TB_ALIGN_16 },
847 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
848 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
849 { X86::VFsANDNPDrr, X86::VFsANDNPDrm, TB_ALIGN_16 },
850 { X86::VFsANDNPSrr, X86::VFsANDNPSrm, TB_ALIGN_16 },
851 { X86::VFsANDPDrr, X86::VFsANDPDrm, TB_ALIGN_16 },
852 { X86::VFsANDPSrr, X86::VFsANDPSrm, TB_ALIGN_16 },
853 { X86::VFsORPDrr, X86::VFsORPDrm, TB_ALIGN_16 },
854 { X86::VFsORPSrr, X86::VFsORPSrm, TB_ALIGN_16 },
855 { X86::VFsXORPDrr, X86::VFsXORPDrm, TB_ALIGN_16 },
856 { X86::VFsXORPSrr, X86::VFsXORPSrm, TB_ALIGN_16 },
857 { X86::VHADDPDrr, X86::VHADDPDrm, TB_ALIGN_16 },
858 { X86::VHADDPSrr, X86::VHADDPSrm, TB_ALIGN_16 },
859 { X86::VHSUBPDrr, X86::VHSUBPDrm, TB_ALIGN_16 },
860 { X86::VHSUBPSrr, X86::VHSUBPSrm, TB_ALIGN_16 },
861 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
862 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
863 { X86::VMAXPDrr, X86::VMAXPDrm, TB_ALIGN_16 },
864 { X86::VMAXPDrr_Int, X86::VMAXPDrm_Int, TB_ALIGN_16 },
865 { X86::VMAXPSrr, X86::VMAXPSrm, TB_ALIGN_16 },
866 { X86::VMAXPSrr_Int, X86::VMAXPSrm_Int, TB_ALIGN_16 },
867 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
868 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
869 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
870 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
871 { X86::VMINPDrr, X86::VMINPDrm, TB_ALIGN_16 },
872 { X86::VMINPDrr_Int, X86::VMINPDrm_Int, TB_ALIGN_16 },
873 { X86::VMINPSrr, X86::VMINPSrm, TB_ALIGN_16 },
874 { X86::VMINPSrr_Int, X86::VMINPSrm_Int, TB_ALIGN_16 },
875 { X86::VMINSDrr, X86::VMINSDrm, 0 },
876 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
877 { X86::VMINSSrr, X86::VMINSSrm, 0 },
878 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
879 { X86::VMPSADBWrri, X86::VMPSADBWrmi, TB_ALIGN_16 },
880 { X86::VMULPDrr, X86::VMULPDrm, TB_ALIGN_16 },
881 { X86::VMULPSrr, X86::VMULPSrm, TB_ALIGN_16 },
882 { X86::VMULSDrr, X86::VMULSDrm, 0 },
883 { X86::VMULSSrr, X86::VMULSSrm, 0 },
884 { X86::VORPDrr, X86::VORPDrm, TB_ALIGN_16 },
885 { X86::VORPSrr, X86::VORPSrm, TB_ALIGN_16 },
886 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, TB_ALIGN_16 },
887 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, TB_ALIGN_16 },
888 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, TB_ALIGN_16 },
889 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, TB_ALIGN_16 },
890 { X86::VPADDBrr, X86::VPADDBrm, TB_ALIGN_16 },
891 { X86::VPADDDrr, X86::VPADDDrm, TB_ALIGN_16 },
892 { X86::VPADDQrr, X86::VPADDQrm, TB_ALIGN_16 },
893 { X86::VPADDSBrr, X86::VPADDSBrm, TB_ALIGN_16 },
894 { X86::VPADDSWrr, X86::VPADDSWrm, TB_ALIGN_16 },
895 { X86::VPADDUSBrr, X86::VPADDUSBrm, TB_ALIGN_16 },
896 { X86::VPADDUSWrr, X86::VPADDUSWrm, TB_ALIGN_16 },
897 { X86::VPADDWrr, X86::VPADDWrm, TB_ALIGN_16 },
898 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, TB_ALIGN_16 },
899 { X86::VPANDNrr, X86::VPANDNrm, TB_ALIGN_16 },
900 { X86::VPANDrr, X86::VPANDrm, TB_ALIGN_16 },
901 { X86::VPAVGBrr, X86::VPAVGBrm, TB_ALIGN_16 },
902 { X86::VPAVGWrr, X86::VPAVGWrm, TB_ALIGN_16 },
903 { X86::VPBLENDWrri, X86::VPBLENDWrmi, TB_ALIGN_16 },
904 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, TB_ALIGN_16 },
905 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, TB_ALIGN_16 },
906 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, TB_ALIGN_16 },
907 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, TB_ALIGN_16 },
908 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, TB_ALIGN_16 },
909 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, TB_ALIGN_16 },
910 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, TB_ALIGN_16 },
911 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, TB_ALIGN_16 },
912 { X86::VPHADDDrr, X86::VPHADDDrm, TB_ALIGN_16 },
913 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, TB_ALIGN_16 },
914 { X86::VPHADDWrr, X86::VPHADDWrm, TB_ALIGN_16 },
915 { X86::VPHSUBDrr, X86::VPHSUBDrm, TB_ALIGN_16 },
916 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, TB_ALIGN_16 },
917 { X86::VPHSUBWrr, X86::VPHSUBWrm, TB_ALIGN_16 },
918 { X86::VPERMILPDrr, X86::VPERMILPDrm, TB_ALIGN_16 },
919 { X86::VPERMILPSrr, X86::VPERMILPSrm, TB_ALIGN_16 },
920 { X86::VPINSRWrri, X86::VPINSRWrmi, TB_ALIGN_16 },
921 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, TB_ALIGN_16 },
922 { X86::VPMADDWDrr, X86::VPMADDWDrm, TB_ALIGN_16 },
923 { X86::VPMAXSWrr, X86::VPMAXSWrm, TB_ALIGN_16 },
924 { X86::VPMAXUBrr, X86::VPMAXUBrm, TB_ALIGN_16 },
925 { X86::VPMINSWrr, X86::VPMINSWrm, TB_ALIGN_16 },
926 { X86::VPMINUBrr, X86::VPMINUBrm, TB_ALIGN_16 },
927 { X86::VPMULDQrr, X86::VPMULDQrm, TB_ALIGN_16 },
928 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, TB_ALIGN_16 },
929 { X86::VPMULHUWrr, X86::VPMULHUWrm, TB_ALIGN_16 },
930 { X86::VPMULHWrr, X86::VPMULHWrm, TB_ALIGN_16 },
931 { X86::VPMULLDrr, X86::VPMULLDrm, TB_ALIGN_16 },
932 { X86::VPMULLWrr, X86::VPMULLWrm, TB_ALIGN_16 },
933 { X86::VPMULUDQrr, X86::VPMULUDQrm, TB_ALIGN_16 },
934 { X86::VPORrr, X86::VPORrm, TB_ALIGN_16 },
935 { X86::VPSADBWrr, X86::VPSADBWrm, TB_ALIGN_16 },
936 { X86::VPSHUFBrr, X86::VPSHUFBrm, TB_ALIGN_16 },
937 { X86::VPSIGNBrr, X86::VPSIGNBrm, TB_ALIGN_16 },
938 { X86::VPSIGNWrr, X86::VPSIGNWrm, TB_ALIGN_16 },
939 { X86::VPSIGNDrr, X86::VPSIGNDrm, TB_ALIGN_16 },
940 { X86::VPSLLDrr, X86::VPSLLDrm, TB_ALIGN_16 },
941 { X86::VPSLLQrr, X86::VPSLLQrm, TB_ALIGN_16 },
942 { X86::VPSLLWrr, X86::VPSLLWrm, TB_ALIGN_16 },
943 { X86::VPSRADrr, X86::VPSRADrm, TB_ALIGN_16 },
944 { X86::VPSRAWrr, X86::VPSRAWrm, TB_ALIGN_16 },
945 { X86::VPSRLDrr, X86::VPSRLDrm, TB_ALIGN_16 },
946 { X86::VPSRLQrr, X86::VPSRLQrm, TB_ALIGN_16 },
947 { X86::VPSRLWrr, X86::VPSRLWrm, TB_ALIGN_16 },
948 { X86::VPSUBBrr, X86::VPSUBBrm, TB_ALIGN_16 },
949 { X86::VPSUBDrr, X86::VPSUBDrm, TB_ALIGN_16 },
950 { X86::VPSUBSBrr, X86::VPSUBSBrm, TB_ALIGN_16 },
951 { X86::VPSUBSWrr, X86::VPSUBSWrm, TB_ALIGN_16 },
952 { X86::VPSUBWrr, X86::VPSUBWrm, TB_ALIGN_16 },
953 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, TB_ALIGN_16 },
954 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, TB_ALIGN_16 },
955 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, TB_ALIGN_16 },
956 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, TB_ALIGN_16 },
957 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, TB_ALIGN_16 },
958 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, TB_ALIGN_16 },
959 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, TB_ALIGN_16 },
960 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, TB_ALIGN_16 },
961 { X86::VPXORrr, X86::VPXORrm, TB_ALIGN_16 },
962 { X86::VSHUFPDrri, X86::VSHUFPDrmi, TB_ALIGN_16 },
963 { X86::VSHUFPSrri, X86::VSHUFPSrmi, TB_ALIGN_16 },
964 { X86::VSUBPDrr, X86::VSUBPDrm, TB_ALIGN_16 },
965 { X86::VSUBPSrr, X86::VSUBPSrm, TB_ALIGN_16 },
966 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
967 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
968 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, TB_ALIGN_16 },
969 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, TB_ALIGN_16 },
970 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, TB_ALIGN_16 },
971 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, TB_ALIGN_16 },
972 { X86::VXORPDrr, X86::VXORPDrm, TB_ALIGN_16 },
973 { X86::VXORPSrr, X86::VXORPSrm, TB_ALIGN_16 },
974 // AVX 256-bit foldable instructions
975 { X86::VADDPDYrr, X86::VADDPDYrm, TB_ALIGN_32 },
976 { X86::VADDPSYrr, X86::VADDPSYrm, TB_ALIGN_32 },
977 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, TB_ALIGN_32 },
978 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, TB_ALIGN_32 },
979 { X86::VANDNPDYrr, X86::VANDNPDYrm, TB_ALIGN_32 },
980 { X86::VANDNPSYrr, X86::VANDNPSYrm, TB_ALIGN_32 },
981 { X86::VANDPDYrr, X86::VANDPDYrm, TB_ALIGN_32 },
982 { X86::VANDPSYrr, X86::VANDPSYrm, TB_ALIGN_32 },
983 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, TB_ALIGN_32 },
984 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, TB_ALIGN_32 },
985 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, TB_ALIGN_32 },
986 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, TB_ALIGN_32 },
987 { X86::VCMPPDYrri, X86::VCMPPDYrmi, TB_ALIGN_32 },
988 { X86::VCMPPSYrri, X86::VCMPPSYrmi, TB_ALIGN_32 },
989 { X86::VDIVPDYrr, X86::VDIVPDYrm, TB_ALIGN_32 },
990 { X86::VDIVPSYrr, X86::VDIVPSYrm, TB_ALIGN_32 },
991 { X86::VHADDPDYrr, X86::VHADDPDYrm, TB_ALIGN_32 },
992 { X86::VHADDPSYrr, X86::VHADDPSYrm, TB_ALIGN_32 },
993 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, TB_ALIGN_32 },
994 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, TB_ALIGN_32 },
995 { X86::VINSERTF128rr, X86::VINSERTF128rm, TB_ALIGN_32 },
996 { X86::VMAXPDYrr, X86::VMAXPDYrm, TB_ALIGN_32 },
997 { X86::VMAXPDYrr_Int, X86::VMAXPDYrm_Int, TB_ALIGN_32 },
998 { X86::VMAXPSYrr, X86::VMAXPSYrm, TB_ALIGN_32 },
999 { X86::VMAXPSYrr_Int, X86::VMAXPSYrm_Int, TB_ALIGN_32 },
1000 { X86::VMINPDYrr, X86::VMINPDYrm, TB_ALIGN_32 },
1001 { X86::VMINPDYrr_Int, X86::VMINPDYrm_Int, TB_ALIGN_32 },
1002 { X86::VMINPSYrr, X86::VMINPSYrm, TB_ALIGN_32 },
1003 { X86::VMINPSYrr_Int, X86::VMINPSYrm_Int, TB_ALIGN_32 },
1004 { X86::VMULPDYrr, X86::VMULPDYrm, TB_ALIGN_32 },
1005 { X86::VMULPSYrr, X86::VMULPSYrm, TB_ALIGN_32 },
1006 { X86::VORPDYrr, X86::VORPDYrm, TB_ALIGN_32 },
1007 { X86::VORPSYrr, X86::VORPSYrm, TB_ALIGN_32 },
1008 { X86::VPERM2F128rr, X86::VPERM2F128rm, TB_ALIGN_32 },
1009 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, TB_ALIGN_32 },
1010 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, TB_ALIGN_32 },
1011 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, TB_ALIGN_32 },
1012 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, TB_ALIGN_32 },
1013 { X86::VSUBPDYrr, X86::VSUBPDYrm, TB_ALIGN_32 },
1014 { X86::VSUBPSYrr, X86::VSUBPSYrm, TB_ALIGN_32 },
1015 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, TB_ALIGN_32 },
1016 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, TB_ALIGN_32 },
1017 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, TB_ALIGN_32 },
1018 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, TB_ALIGN_32 },
1019 { X86::VXORPDYrr, X86::VXORPDYrm, TB_ALIGN_32 },
1020 { X86::VXORPSYrr, X86::VXORPSYrm, TB_ALIGN_32 },
1021 // AVX2 foldable instructions
1022 { X86::VINSERTI128rr, X86::VINSERTI128rm, TB_ALIGN_16 },
1023 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, TB_ALIGN_32 },
1024 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, TB_ALIGN_32 },
1025 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, TB_ALIGN_32 },
1026 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, TB_ALIGN_32 },
1027 { X86::VPADDBYrr, X86::VPADDBYrm, TB_ALIGN_32 },
1028 { X86::VPADDDYrr, X86::VPADDDYrm, TB_ALIGN_32 },
1029 { X86::VPADDQYrr, X86::VPADDQYrm, TB_ALIGN_32 },
1030 { X86::VPADDSBYrr, X86::VPADDSBYrm, TB_ALIGN_32 },
1031 { X86::VPADDSWYrr, X86::VPADDSWYrm, TB_ALIGN_32 },
1032 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, TB_ALIGN_32 },
1033 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, TB_ALIGN_32 },
1034 { X86::VPADDWYrr, X86::VPADDWYrm, TB_ALIGN_32 },
1035 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, TB_ALIGN_32 },
1036 { X86::VPANDNYrr, X86::VPANDNYrm, TB_ALIGN_32 },
1037 { X86::VPANDYrr, X86::VPANDYrm, TB_ALIGN_32 },
1038 { X86::VPAVGBYrr, X86::VPAVGBYrm, TB_ALIGN_32 },
1039 { X86::VPAVGWYrr, X86::VPAVGWYrm, TB_ALIGN_32 },
1040 { X86::VPBLENDDrri, X86::VPBLENDDrmi, TB_ALIGN_32 },
1041 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, TB_ALIGN_32 },
1042 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, TB_ALIGN_32 },
1043 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, TB_ALIGN_32 },
1044 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, TB_ALIGN_32 },
1045 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, TB_ALIGN_32 },
1046 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, TB_ALIGN_32 },
1047 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, TB_ALIGN_32 },
1048 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, TB_ALIGN_32 },
1049 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, TB_ALIGN_32 },
1050 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, TB_ALIGN_32 },
1051 { X86::VPERM2I128rr, X86::VPERM2I128rm, TB_ALIGN_32 },
1052 { X86::VPERMDYrr, X86::VPERMDYrm, TB_ALIGN_32 },
1053 { X86::VPERMPDYri, X86::VPERMPDYmi, TB_ALIGN_32 },
1054 { X86::VPERMPSYrr, X86::VPERMPSYrm, TB_ALIGN_32 },
1055 { X86::VPERMQYri, X86::VPERMQYmi, TB_ALIGN_32 },
1056 { X86::VPHADDDYrr, X86::VPHADDDYrm, TB_ALIGN_32 },
1057 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, TB_ALIGN_32 },
1058 { X86::VPHADDWYrr, X86::VPHADDWYrm, TB_ALIGN_32 },
1059 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, TB_ALIGN_32 },
1060 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, TB_ALIGN_32 },
1061 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, TB_ALIGN_32 },
1062 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, TB_ALIGN_32 },
1063 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, TB_ALIGN_32 },
1064 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, TB_ALIGN_32 },
1065 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, TB_ALIGN_32 },
1066 { X86::VPMINSWYrr, X86::VPMINSWYrm, TB_ALIGN_32 },
1067 { X86::VPMINUBYrr, X86::VPMINUBYrm, TB_ALIGN_32 },
1068 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, TB_ALIGN_32 },
1069 { X86::VPMULDQYrr, X86::VPMULDQYrm, TB_ALIGN_32 },
1070 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, TB_ALIGN_32 },
1071 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, TB_ALIGN_32 },
1072 { X86::VPMULHWYrr, X86::VPMULHWYrm, TB_ALIGN_32 },
1073 { X86::VPMULLDYrr, X86::VPMULLDYrm, TB_ALIGN_32 },
1074 { X86::VPMULLWYrr, X86::VPMULLWYrm, TB_ALIGN_32 },
1075 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, TB_ALIGN_32 },
1076 { X86::VPORYrr, X86::VPORYrm, TB_ALIGN_32 },
1077 { X86::VPSADBWYrr, X86::VPSADBWYrm, TB_ALIGN_32 },
1078 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, TB_ALIGN_32 },
1079 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, TB_ALIGN_32 },
1080 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, TB_ALIGN_32 },
1081 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, TB_ALIGN_32 },
1082 { X86::VPSLLDYrr, X86::VPSLLDYrm, TB_ALIGN_16 },
1083 { X86::VPSLLQYrr, X86::VPSLLQYrm, TB_ALIGN_16 },
1084 { X86::VPSLLWYrr, X86::VPSLLWYrm, TB_ALIGN_16 },
1085 { X86::VPSLLVDrr, X86::VPSLLVDrm, TB_ALIGN_16 },
1086 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, TB_ALIGN_32 },
1087 { X86::VPSLLVQrr, X86::VPSLLVQrm, TB_ALIGN_16 },
1088 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, TB_ALIGN_32 },
1089 { X86::VPSRADYrr, X86::VPSRADYrm, TB_ALIGN_16 },
1090 { X86::VPSRAWYrr, X86::VPSRAWYrm, TB_ALIGN_16 },
1091 { X86::VPSRAVDrr, X86::VPSRAVDrm, TB_ALIGN_16 },
1092 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, TB_ALIGN_32 },
1093 { X86::VPSRLDYrr, X86::VPSRLDYrm, TB_ALIGN_16 },
1094 { X86::VPSRLQYrr, X86::VPSRLQYrm, TB_ALIGN_16 },
1095 { X86::VPSRLWYrr, X86::VPSRLWYrm, TB_ALIGN_16 },
1096 { X86::VPSRLVDrr, X86::VPSRLVDrm, TB_ALIGN_16 },
1097 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, TB_ALIGN_32 },
1098 { X86::VPSRLVQrr, X86::VPSRLVQrm, TB_ALIGN_16 },
1099 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, TB_ALIGN_32 },
1100 { X86::VPSUBBYrr, X86::VPSUBBYrm, TB_ALIGN_32 },
1101 { X86::VPSUBDYrr, X86::VPSUBDYrm, TB_ALIGN_32 },
1102 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, TB_ALIGN_32 },
1103 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, TB_ALIGN_32 },
1104 { X86::VPSUBWYrr, X86::VPSUBWYrm, TB_ALIGN_32 },
1105 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, TB_ALIGN_32 },
1106 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, TB_ALIGN_32 },
1107 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, TB_ALIGN_16 },
1108 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, TB_ALIGN_32 },
1109 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, TB_ALIGN_32 },
1110 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, TB_ALIGN_32 },
1111 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, TB_ALIGN_32 },
1112 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, TB_ALIGN_32 },
1113 { X86::VPXORYrr, X86::VPXORYrm, TB_ALIGN_32 },
1114 // FIXME: add AVX 256-bit foldable instructions
1117 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
1118 unsigned RegOp = OpTbl2[i].RegOp;
1119 unsigned MemOp = OpTbl2[i].MemOp;
1120 unsigned Flags = OpTbl2[i].Flags;
1121 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1123 // Index 2, folded load
1124 Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1127 static const X86OpTblEntry OpTbl3[] = {
1128 // FMA foldable instructions
1129 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, 0 },
1130 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, 0 },
1131 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, 0 },
1132 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, 0 },
1134 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_16 },
1135 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_16 },
1136 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_16 },
1137 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_16 },
1138 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_16 },
1139 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_16 },
1140 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_32 },
1141 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_32 },
1142 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_32 },
1143 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_32 },
1144 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_32 },
1145 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_32 },
1147 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, 0 },
1148 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, 0 },
1149 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, 0 },
1150 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, 0 },
1152 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_16 },
1153 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_16 },
1154 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_16 },
1155 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_16 },
1156 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_16 },
1157 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_16 },
1158 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_32 },
1159 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_32 },
1160 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_32 },
1161 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_32 },
1162 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_32 },
1163 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_32 },
1165 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, 0 },
1166 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, 0 },
1167 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, 0 },
1168 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, 0 },
1170 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_16 },
1171 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_16 },
1172 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_16 },
1173 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_16 },
1174 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_16 },
1175 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_16 },
1176 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_32 },
1177 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_32 },
1178 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_32 },
1179 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_32 },
1180 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_32 },
1181 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_32 },
1185 for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1186 unsigned RegOp = OpTbl3[i].RegOp;
1187 unsigned MemOp = OpTbl3[i].MemOp;
1188 unsigned Flags = OpTbl3[i].Flags;
1189 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1191 // Index 3, folded load
1192 Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1198 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1199 MemOp2RegOpTableType &M2RTable,
1200 unsigned RegOp, unsigned MemOp, unsigned Flags) {
1201 if ((Flags & TB_NO_FORWARD) == 0) {
1202 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1203 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1205 if ((Flags & TB_NO_REVERSE) == 0) {
1206 assert(!M2RTable.count(MemOp) &&
1207 "Duplicated entries in unfolding maps?");
1208 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1213 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1214 unsigned &SrcReg, unsigned &DstReg,
1215 unsigned &SubIdx) const {
1216 switch (MI.getOpcode()) {
1218 case X86::MOVSX16rr8:
1219 case X86::MOVZX16rr8:
1220 case X86::MOVSX32rr8:
1221 case X86::MOVZX32rr8:
1222 case X86::MOVSX64rr8:
1223 case X86::MOVZX64rr8:
1224 if (!TM.getSubtarget<X86Subtarget>().is64Bit())
1225 // It's not always legal to reference the low 8-bit of the larger
1226 // register in 32-bit mode.
1228 case X86::MOVSX32rr16:
1229 case X86::MOVZX32rr16:
1230 case X86::MOVSX64rr16:
1231 case X86::MOVZX64rr16:
1232 case X86::MOVSX64rr32:
1233 case X86::MOVZX64rr32: {
1234 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1237 SrcReg = MI.getOperand(1).getReg();
1238 DstReg = MI.getOperand(0).getReg();
1239 switch (MI.getOpcode()) {
1241 llvm_unreachable(0);
1242 case X86::MOVSX16rr8:
1243 case X86::MOVZX16rr8:
1244 case X86::MOVSX32rr8:
1245 case X86::MOVZX32rr8:
1246 case X86::MOVSX64rr8:
1247 case X86::MOVZX64rr8:
1248 SubIdx = X86::sub_8bit;
1250 case X86::MOVSX32rr16:
1251 case X86::MOVZX32rr16:
1252 case X86::MOVSX64rr16:
1253 case X86::MOVZX64rr16:
1254 SubIdx = X86::sub_16bit;
1256 case X86::MOVSX64rr32:
1257 case X86::MOVZX64rr32:
1258 SubIdx = X86::sub_32bit;
1267 /// isFrameOperand - Return true and the FrameIndex if the specified
1268 /// operand and follow operands form a reference to the stack frame.
1269 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1270 int &FrameIndex) const {
1271 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
1272 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
1273 MI->getOperand(Op+1).getImm() == 1 &&
1274 MI->getOperand(Op+2).getReg() == 0 &&
1275 MI->getOperand(Op+3).getImm() == 0) {
1276 FrameIndex = MI->getOperand(Op).getIndex();
1282 static bool isFrameLoadOpcode(int Opcode) {
1298 case X86::VMOVAPSrm:
1299 case X86::VMOVAPDrm:
1300 case X86::VMOVDQArm:
1301 case X86::VMOVAPSYrm:
1302 case X86::VMOVAPDYrm:
1303 case X86::VMOVDQAYrm:
1304 case X86::MMX_MOVD64rm:
1305 case X86::MMX_MOVQ64rm:
1310 static bool isFrameStoreOpcode(int Opcode) {
1317 case X86::ST_FpP64m:
1325 case X86::VMOVAPSmr:
1326 case X86::VMOVAPDmr:
1327 case X86::VMOVDQAmr:
1328 case X86::VMOVAPSYmr:
1329 case X86::VMOVAPDYmr:
1330 case X86::VMOVDQAYmr:
1331 case X86::MMX_MOVD64mr:
1332 case X86::MMX_MOVQ64mr:
1333 case X86::MMX_MOVNTQmr:
1339 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1340 int &FrameIndex) const {
1341 if (isFrameLoadOpcode(MI->getOpcode()))
1342 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1343 return MI->getOperand(0).getReg();
1347 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1348 int &FrameIndex) const {
1349 if (isFrameLoadOpcode(MI->getOpcode())) {
1351 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1353 // Check for post-frame index elimination operations
1354 const MachineMemOperand *Dummy;
1355 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1360 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1361 int &FrameIndex) const {
1362 if (isFrameStoreOpcode(MI->getOpcode()))
1363 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1364 isFrameOperand(MI, 0, FrameIndex))
1365 return MI->getOperand(X86::AddrNumOperands).getReg();
1369 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1370 int &FrameIndex) const {
1371 if (isFrameStoreOpcode(MI->getOpcode())) {
1373 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1375 // Check for post-frame index elimination operations
1376 const MachineMemOperand *Dummy;
1377 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1382 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1384 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
1385 bool isPICBase = false;
1386 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1387 E = MRI.def_end(); I != E; ++I) {
1388 MachineInstr *DefMI = I.getOperand().getParent();
1389 if (DefMI->getOpcode() != X86::MOVPC32r)
1391 assert(!isPICBase && "More than one PIC base?");
1398 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1399 AliasAnalysis *AA) const {
1400 switch (MI->getOpcode()) {
1415 case X86::VMOVAPSrm:
1416 case X86::VMOVUPSrm:
1417 case X86::VMOVAPDrm:
1418 case X86::VMOVDQArm:
1419 case X86::VMOVAPSYrm:
1420 case X86::VMOVUPSYrm:
1421 case X86::VMOVAPDYrm:
1422 case X86::VMOVDQAYrm:
1423 case X86::MMX_MOVD64rm:
1424 case X86::MMX_MOVQ64rm:
1425 case X86::FsVMOVAPSrm:
1426 case X86::FsVMOVAPDrm:
1427 case X86::FsMOVAPSrm:
1428 case X86::FsMOVAPDrm: {
1429 // Loads from constant pools are trivially rematerializable.
1430 if (MI->getOperand(1).isReg() &&
1431 MI->getOperand(2).isImm() &&
1432 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1433 MI->isInvariantLoad(AA)) {
1434 unsigned BaseReg = MI->getOperand(1).getReg();
1435 if (BaseReg == 0 || BaseReg == X86::RIP)
1437 // Allow re-materialization of PIC load.
1438 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
1440 const MachineFunction &MF = *MI->getParent()->getParent();
1441 const MachineRegisterInfo &MRI = MF.getRegInfo();
1442 bool isPICBase = false;
1443 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1444 E = MRI.def_end(); I != E; ++I) {
1445 MachineInstr *DefMI = I.getOperand().getParent();
1446 if (DefMI->getOpcode() != X86::MOVPC32r)
1448 assert(!isPICBase && "More than one PIC base?");
1458 if (MI->getOperand(2).isImm() &&
1459 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1460 !MI->getOperand(4).isReg()) {
1461 // lea fi#, lea GV, etc. are all rematerializable.
1462 if (!MI->getOperand(1).isReg())
1464 unsigned BaseReg = MI->getOperand(1).getReg();
1467 // Allow re-materialization of lea PICBase + x.
1468 const MachineFunction &MF = *MI->getParent()->getParent();
1469 const MachineRegisterInfo &MRI = MF.getRegInfo();
1470 return regIsPICBase(BaseReg, MRI);
1476 // All other instructions marked M_REMATERIALIZABLE are always trivially
1477 // rematerializable.
1481 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
1482 /// would clobber the EFLAGS condition register. Note the result may be
1483 /// conservative. If it cannot definitely determine the safety after visiting
1484 /// a few instructions in each direction it assumes it's not safe.
1485 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1486 MachineBasicBlock::iterator I) {
1487 MachineBasicBlock::iterator E = MBB.end();
1489 // For compile time consideration, if we are not able to determine the
1490 // safety after visiting 4 instructions in each direction, we will assume
1492 MachineBasicBlock::iterator Iter = I;
1493 for (unsigned i = 0; Iter != E && i < 4; ++i) {
1494 bool SeenDef = false;
1495 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1496 MachineOperand &MO = Iter->getOperand(j);
1497 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1501 if (MO.getReg() == X86::EFLAGS) {
1509 // This instruction defines EFLAGS, no need to look any further.
1512 // Skip over DBG_VALUE.
1513 while (Iter != E && Iter->isDebugValue())
1517 // It is safe to clobber EFLAGS at the end of a block of no successor has it
1520 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1521 SE = MBB.succ_end(); SI != SE; ++SI)
1522 if ((*SI)->isLiveIn(X86::EFLAGS))
1527 MachineBasicBlock::iterator B = MBB.begin();
1529 for (unsigned i = 0; i < 4; ++i) {
1530 // If we make it to the beginning of the block, it's safe to clobber
1531 // EFLAGS iff EFLAGS is not live-in.
1533 return !MBB.isLiveIn(X86::EFLAGS);
1536 // Skip over DBG_VALUE.
1537 while (Iter != B && Iter->isDebugValue())
1540 bool SawKill = false;
1541 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1542 MachineOperand &MO = Iter->getOperand(j);
1543 // A register mask may clobber EFLAGS, but we should still look for a
1545 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1547 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1548 if (MO.isDef()) return MO.isDead();
1549 if (MO.isKill()) SawKill = true;
1554 // This instruction kills EFLAGS and doesn't redefine it, so
1555 // there's no need to look further.
1559 // Conservative answer.
1563 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1564 MachineBasicBlock::iterator I,
1565 unsigned DestReg, unsigned SubIdx,
1566 const MachineInstr *Orig,
1567 const TargetRegisterInfo &TRI) const {
1568 DebugLoc DL = Orig->getDebugLoc();
1570 // MOV32r0 etc. are implemented with xor which clobbers condition code.
1571 // Re-materialize them as movri instructions to avoid side effects.
1573 unsigned Opc = Orig->getOpcode();
1579 case X86::MOV64r0: {
1580 if (!isSafeToClobberEFLAGS(MBB, I)) {
1583 case X86::MOV8r0: Opc = X86::MOV8ri; break;
1584 case X86::MOV16r0: Opc = X86::MOV16ri; break;
1585 case X86::MOV32r0: Opc = X86::MOV32ri; break;
1586 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
1595 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1598 BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0);
1601 MachineInstr *NewMI = prior(I);
1602 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1605 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1606 /// is not marked dead.
1607 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1608 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1609 MachineOperand &MO = MI->getOperand(i);
1610 if (MO.isReg() && MO.isDef() &&
1611 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1618 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1619 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1620 /// to a 32-bit superregister and then truncating back down to a 16-bit
1623 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1624 MachineFunction::iterator &MFI,
1625 MachineBasicBlock::iterator &MBBI,
1626 LiveVariables *LV) const {
1627 MachineInstr *MI = MBBI;
1628 unsigned Dest = MI->getOperand(0).getReg();
1629 unsigned Src = MI->getOperand(1).getReg();
1630 bool isDead = MI->getOperand(0).isDead();
1631 bool isKill = MI->getOperand(1).isKill();
1633 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1634 ? X86::LEA64_32r : X86::LEA32r;
1635 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1636 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1637 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1639 // Build and insert into an implicit UNDEF value. This is OK because
1640 // well be shifting and then extracting the lower 16-bits.
1641 // This has the potential to cause partial register stall. e.g.
1642 // movw (%rbp,%rcx,2), %dx
1643 // leal -65(%rdx), %esi
1644 // But testing has shown this *does* help performance in 64-bit mode (at
1645 // least on modern x86 machines).
1646 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1647 MachineInstr *InsMI =
1648 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1649 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1650 .addReg(Src, getKillRegState(isKill));
1652 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1653 get(Opc), leaOutReg);
1656 llvm_unreachable(0);
1657 case X86::SHL16ri: {
1658 unsigned ShAmt = MI->getOperand(2).getImm();
1659 MIB.addReg(0).addImm(1 << ShAmt)
1660 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
1664 case X86::INC64_16r:
1665 addRegOffset(MIB, leaInReg, true, 1);
1668 case X86::DEC64_16r:
1669 addRegOffset(MIB, leaInReg, true, -1);
1673 case X86::ADD16ri_DB:
1674 case X86::ADD16ri8_DB:
1675 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1678 case X86::ADD16rr_DB: {
1679 unsigned Src2 = MI->getOperand(2).getReg();
1680 bool isKill2 = MI->getOperand(2).isKill();
1681 unsigned leaInReg2 = 0;
1682 MachineInstr *InsMI2 = 0;
1684 // ADD16rr %reg1028<kill>, %reg1028
1685 // just a single insert_subreg.
1686 addRegReg(MIB, leaInReg, true, leaInReg, false);
1688 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1689 // Build and insert into an implicit UNDEF value. This is OK because
1690 // well be shifting and then extracting the lower 16-bits.
1691 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
1693 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
1694 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
1695 .addReg(Src2, getKillRegState(isKill2));
1696 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1698 if (LV && isKill2 && InsMI2)
1699 LV->replaceKillInstruction(Src2, MI, InsMI2);
1704 MachineInstr *NewMI = MIB;
1705 MachineInstr *ExtMI =
1706 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1707 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1708 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
1711 // Update live variables
1712 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1713 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1715 LV->replaceKillInstruction(Src, MI, InsMI);
1717 LV->replaceKillInstruction(Dest, MI, ExtMI);
1723 /// convertToThreeAddress - This method must be implemented by targets that
1724 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1725 /// may be able to convert a two-address instruction into a true
1726 /// three-address instruction on demand. This allows the X86 target (for
1727 /// example) to convert ADD and SHL instructions into LEA instructions if they
1728 /// would require register copies due to two-addressness.
1730 /// This method returns a null pointer if the transformation cannot be
1731 /// performed, otherwise it returns the new instruction.
1734 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1735 MachineBasicBlock::iterator &MBBI,
1736 LiveVariables *LV) const {
1737 MachineInstr *MI = MBBI;
1738 MachineFunction &MF = *MI->getParent()->getParent();
1739 // All instructions input are two-addr instructions. Get the known operands.
1740 unsigned Dest = MI->getOperand(0).getReg();
1741 unsigned Src = MI->getOperand(1).getReg();
1742 bool isDead = MI->getOperand(0).isDead();
1743 bool isKill = MI->getOperand(1).isKill();
1745 MachineInstr *NewMI = NULL;
1746 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1747 // we have better subtarget support, enable the 16-bit LEA generation here.
1748 // 16-bit LEA is also slow on Core2.
1749 bool DisableLEA16 = true;
1750 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1752 unsigned MIOpc = MI->getOpcode();
1754 case X86::SHUFPSrri: {
1755 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1756 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1758 unsigned B = MI->getOperand(1).getReg();
1759 unsigned C = MI->getOperand(2).getReg();
1760 if (B != C) return 0;
1761 unsigned A = MI->getOperand(0).getReg();
1762 unsigned M = MI->getOperand(3).getImm();
1763 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1764 .addReg(A, RegState::Define | getDeadRegState(isDead))
1765 .addReg(B, getKillRegState(isKill)).addImm(M);
1768 case X86::SHUFPDrri: {
1769 assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!");
1770 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1772 unsigned B = MI->getOperand(1).getReg();
1773 unsigned C = MI->getOperand(2).getReg();
1774 if (B != C) return 0;
1775 unsigned A = MI->getOperand(0).getReg();
1776 unsigned M = MI->getOperand(3).getImm();
1778 // Convert to PSHUFD mask.
1779 M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44;
1781 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1782 .addReg(A, RegState::Define | getDeadRegState(isDead))
1783 .addReg(B, getKillRegState(isKill)).addImm(M);
1786 case X86::SHL64ri: {
1787 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1788 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1789 // the flags produced by a shift yet, so this is safe.
1790 unsigned ShAmt = MI->getOperand(2).getImm();
1791 if (ShAmt == 0 || ShAmt >= 4) return 0;
1793 // LEA can't handle RSP.
1794 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1795 !MF.getRegInfo().constrainRegClass(Src, &X86::GR64_NOSPRegClass))
1798 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1799 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1800 .addReg(0).addImm(1 << ShAmt)
1801 .addReg(Src, getKillRegState(isKill))
1802 .addImm(0).addReg(0);
1805 case X86::SHL32ri: {
1806 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1807 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1808 // the flags produced by a shift yet, so this is safe.
1809 unsigned ShAmt = MI->getOperand(2).getImm();
1810 if (ShAmt == 0 || ShAmt >= 4) return 0;
1812 // LEA can't handle ESP.
1813 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1814 !MF.getRegInfo().constrainRegClass(Src, &X86::GR32_NOSPRegClass))
1817 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1818 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1819 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1820 .addReg(0).addImm(1 << ShAmt)
1821 .addReg(Src, getKillRegState(isKill)).addImm(0).addReg(0);
1824 case X86::SHL16ri: {
1825 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1826 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1827 // the flags produced by a shift yet, so this is safe.
1828 unsigned ShAmt = MI->getOperand(2).getImm();
1829 if (ShAmt == 0 || ShAmt >= 4) return 0;
1832 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1833 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1834 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1835 .addReg(0).addImm(1 << ShAmt)
1836 .addReg(Src, getKillRegState(isKill))
1837 .addImm(0).addReg(0);
1841 // The following opcodes also sets the condition code register(s). Only
1842 // convert them to equivalent lea if the condition code register def's
1844 if (hasLiveCondCodeDef(MI))
1851 case X86::INC64_32r: {
1852 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1853 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1854 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1855 const TargetRegisterClass *RC = MIOpc == X86::INC64r ?
1856 (const TargetRegisterClass*)&X86::GR64_NOSPRegClass :
1857 (const TargetRegisterClass*)&X86::GR32_NOSPRegClass;
1859 // LEA can't handle RSP.
1860 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1861 !MF.getRegInfo().constrainRegClass(Src, RC))
1864 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1865 .addReg(Dest, RegState::Define |
1866 getDeadRegState(isDead)),
1871 case X86::INC64_16r:
1873 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1874 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1875 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1876 .addReg(Dest, RegState::Define |
1877 getDeadRegState(isDead)),
1882 case X86::DEC64_32r: {
1883 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1884 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1885 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1886 const TargetRegisterClass *RC = MIOpc == X86::DEC64r ?
1887 (const TargetRegisterClass*)&X86::GR64_NOSPRegClass :
1888 (const TargetRegisterClass*)&X86::GR32_NOSPRegClass;
1889 // LEA can't handle RSP.
1890 if (TargetRegisterInfo::isVirtualRegister(Src) &&
1891 !MF.getRegInfo().constrainRegClass(Src, RC))
1894 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1895 .addReg(Dest, RegState::Define |
1896 getDeadRegState(isDead)),
1901 case X86::DEC64_16r:
1903 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1904 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1905 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1906 .addReg(Dest, RegState::Define |
1907 getDeadRegState(isDead)),
1911 case X86::ADD64rr_DB:
1913 case X86::ADD32rr_DB: {
1914 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1916 const TargetRegisterClass *RC;
1917 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) {
1919 RC = &X86::GR64_NOSPRegClass;
1921 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1922 RC = &X86::GR32_NOSPRegClass;
1926 unsigned Src2 = MI->getOperand(2).getReg();
1927 bool isKill2 = MI->getOperand(2).isKill();
1929 // LEA can't handle RSP.
1930 if (TargetRegisterInfo::isVirtualRegister(Src2) &&
1931 !MF.getRegInfo().constrainRegClass(Src2, RC))
1934 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1935 .addReg(Dest, RegState::Define |
1936 getDeadRegState(isDead)),
1937 Src, isKill, Src2, isKill2);
1939 LV->replaceKillInstruction(Src2, MI, NewMI);
1943 case X86::ADD16rr_DB: {
1945 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1946 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1947 unsigned Src2 = MI->getOperand(2).getReg();
1948 bool isKill2 = MI->getOperand(2).isKill();
1949 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1950 .addReg(Dest, RegState::Define |
1951 getDeadRegState(isDead)),
1952 Src, isKill, Src2, isKill2);
1954 LV->replaceKillInstruction(Src2, MI, NewMI);
1957 case X86::ADD64ri32:
1959 case X86::ADD64ri32_DB:
1960 case X86::ADD64ri8_DB:
1961 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1962 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1963 .addReg(Dest, RegState::Define |
1964 getDeadRegState(isDead)),
1965 Src, isKill, MI->getOperand(2).getImm());
1969 case X86::ADD32ri_DB:
1970 case X86::ADD32ri8_DB: {
1971 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1972 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1973 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1974 .addReg(Dest, RegState::Define |
1975 getDeadRegState(isDead)),
1976 Src, isKill, MI->getOperand(2).getImm());
1981 case X86::ADD16ri_DB:
1982 case X86::ADD16ri8_DB:
1984 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1985 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1986 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1987 .addReg(Dest, RegState::Define |
1988 getDeadRegState(isDead)),
1989 Src, isKill, MI->getOperand(2).getImm());
1995 if (!NewMI) return 0;
1997 if (LV) { // Update live variables
1999 LV->replaceKillInstruction(Src, MI, NewMI);
2001 LV->replaceKillInstruction(Dest, MI, NewMI);
2004 MFI->insert(MBBI, NewMI); // Insert the new inst
2008 /// commuteInstruction - We have a few instructions that must be hacked on to
2012 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
2013 switch (MI->getOpcode()) {
2014 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2015 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2016 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2017 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2018 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2019 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2022 switch (MI->getOpcode()) {
2023 default: llvm_unreachable("Unreachable!");
2024 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2025 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2026 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2027 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2028 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2029 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2031 unsigned Amt = MI->getOperand(3).getImm();
2033 MachineFunction &MF = *MI->getParent()->getParent();
2034 MI = MF.CloneMachineInstr(MI);
2037 MI->setDesc(get(Opc));
2038 MI->getOperand(3).setImm(Size-Amt);
2039 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
2041 case X86::CMOVB16rr:
2042 case X86::CMOVB32rr:
2043 case X86::CMOVB64rr:
2044 case X86::CMOVAE16rr:
2045 case X86::CMOVAE32rr:
2046 case X86::CMOVAE64rr:
2047 case X86::CMOVE16rr:
2048 case X86::CMOVE32rr:
2049 case X86::CMOVE64rr:
2050 case X86::CMOVNE16rr:
2051 case X86::CMOVNE32rr:
2052 case X86::CMOVNE64rr:
2053 case X86::CMOVBE16rr:
2054 case X86::CMOVBE32rr:
2055 case X86::CMOVBE64rr:
2056 case X86::CMOVA16rr:
2057 case X86::CMOVA32rr:
2058 case X86::CMOVA64rr:
2059 case X86::CMOVL16rr:
2060 case X86::CMOVL32rr:
2061 case X86::CMOVL64rr:
2062 case X86::CMOVGE16rr:
2063 case X86::CMOVGE32rr:
2064 case X86::CMOVGE64rr:
2065 case X86::CMOVLE16rr:
2066 case X86::CMOVLE32rr:
2067 case X86::CMOVLE64rr:
2068 case X86::CMOVG16rr:
2069 case X86::CMOVG32rr:
2070 case X86::CMOVG64rr:
2071 case X86::CMOVS16rr:
2072 case X86::CMOVS32rr:
2073 case X86::CMOVS64rr:
2074 case X86::CMOVNS16rr:
2075 case X86::CMOVNS32rr:
2076 case X86::CMOVNS64rr:
2077 case X86::CMOVP16rr:
2078 case X86::CMOVP32rr:
2079 case X86::CMOVP64rr:
2080 case X86::CMOVNP16rr:
2081 case X86::CMOVNP32rr:
2082 case X86::CMOVNP64rr:
2083 case X86::CMOVO16rr:
2084 case X86::CMOVO32rr:
2085 case X86::CMOVO64rr:
2086 case X86::CMOVNO16rr:
2087 case X86::CMOVNO32rr:
2088 case X86::CMOVNO64rr: {
2090 switch (MI->getOpcode()) {
2092 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
2093 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
2094 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
2095 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2096 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2097 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2098 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
2099 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
2100 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
2101 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2102 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2103 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
2104 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2105 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2106 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2107 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
2108 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
2109 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
2110 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
2111 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
2112 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
2113 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2114 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2115 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2116 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2117 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2118 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2119 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
2120 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
2121 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
2122 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
2123 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
2124 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
2125 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2126 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2127 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2128 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
2129 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
2130 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
2131 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2132 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2133 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
2134 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
2135 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
2136 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
2137 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2138 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2139 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
2142 MachineFunction &MF = *MI->getParent()->getParent();
2143 MI = MF.CloneMachineInstr(MI);
2146 MI->setDesc(get(Opc));
2147 // Fallthrough intended.
2150 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
2154 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
2156 default: return X86::COND_INVALID;
2157 case X86::JE_4: return X86::COND_E;
2158 case X86::JNE_4: return X86::COND_NE;
2159 case X86::JL_4: return X86::COND_L;
2160 case X86::JLE_4: return X86::COND_LE;
2161 case X86::JG_4: return X86::COND_G;
2162 case X86::JGE_4: return X86::COND_GE;
2163 case X86::JB_4: return X86::COND_B;
2164 case X86::JBE_4: return X86::COND_BE;
2165 case X86::JA_4: return X86::COND_A;
2166 case X86::JAE_4: return X86::COND_AE;
2167 case X86::JS_4: return X86::COND_S;
2168 case X86::JNS_4: return X86::COND_NS;
2169 case X86::JP_4: return X86::COND_P;
2170 case X86::JNP_4: return X86::COND_NP;
2171 case X86::JO_4: return X86::COND_O;
2172 case X86::JNO_4: return X86::COND_NO;
2176 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2178 default: llvm_unreachable("Illegal condition code!");
2179 case X86::COND_E: return X86::JE_4;
2180 case X86::COND_NE: return X86::JNE_4;
2181 case X86::COND_L: return X86::JL_4;
2182 case X86::COND_LE: return X86::JLE_4;
2183 case X86::COND_G: return X86::JG_4;
2184 case X86::COND_GE: return X86::JGE_4;
2185 case X86::COND_B: return X86::JB_4;
2186 case X86::COND_BE: return X86::JBE_4;
2187 case X86::COND_A: return X86::JA_4;
2188 case X86::COND_AE: return X86::JAE_4;
2189 case X86::COND_S: return X86::JS_4;
2190 case X86::COND_NS: return X86::JNS_4;
2191 case X86::COND_P: return X86::JP_4;
2192 case X86::COND_NP: return X86::JNP_4;
2193 case X86::COND_O: return X86::JO_4;
2194 case X86::COND_NO: return X86::JNO_4;
2198 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
2199 /// e.g. turning COND_E to COND_NE.
2200 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2202 default: llvm_unreachable("Illegal condition code!");
2203 case X86::COND_E: return X86::COND_NE;
2204 case X86::COND_NE: return X86::COND_E;
2205 case X86::COND_L: return X86::COND_GE;
2206 case X86::COND_LE: return X86::COND_G;
2207 case X86::COND_G: return X86::COND_LE;
2208 case X86::COND_GE: return X86::COND_L;
2209 case X86::COND_B: return X86::COND_AE;
2210 case X86::COND_BE: return X86::COND_A;
2211 case X86::COND_A: return X86::COND_BE;
2212 case X86::COND_AE: return X86::COND_B;
2213 case X86::COND_S: return X86::COND_NS;
2214 case X86::COND_NS: return X86::COND_S;
2215 case X86::COND_P: return X86::COND_NP;
2216 case X86::COND_NP: return X86::COND_P;
2217 case X86::COND_O: return X86::COND_NO;
2218 case X86::COND_NO: return X86::COND_O;
2222 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
2223 if (!MI->isTerminator()) return false;
2225 // Conditional branch is a special case.
2226 if (MI->isBranch() && !MI->isBarrier())
2228 if (!MI->isPredicable())
2230 return !isPredicated(MI);
2233 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
2234 MachineBasicBlock *&TBB,
2235 MachineBasicBlock *&FBB,
2236 SmallVectorImpl<MachineOperand> &Cond,
2237 bool AllowModify) const {
2238 // Start from the bottom of the block and work up, examining the
2239 // terminator instructions.
2240 MachineBasicBlock::iterator I = MBB.end();
2241 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2242 while (I != MBB.begin()) {
2244 if (I->isDebugValue())
2247 // Working from the bottom, when we see a non-terminator instruction, we're
2249 if (!isUnpredicatedTerminator(I))
2252 // A terminator that isn't a branch can't easily be handled by this
2257 // Handle unconditional branches.
2258 if (I->getOpcode() == X86::JMP_4) {
2262 TBB = I->getOperand(0).getMBB();
2266 // If the block has any instructions after a JMP, delete them.
2267 while (llvm::next(I) != MBB.end())
2268 llvm::next(I)->eraseFromParent();
2273 // Delete the JMP if it's equivalent to a fall-through.
2274 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2276 I->eraseFromParent();
2278 UnCondBrIter = MBB.end();
2282 // TBB is used to indicate the unconditional destination.
2283 TBB = I->getOperand(0).getMBB();
2287 // Handle conditional branches.
2288 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
2289 if (BranchCode == X86::COND_INVALID)
2290 return true; // Can't handle indirect branch.
2292 // Working from the bottom, handle the first conditional branch.
2294 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2295 if (AllowModify && UnCondBrIter != MBB.end() &&
2296 MBB.isLayoutSuccessor(TargetBB)) {
2297 // If we can modify the code and it ends in something like:
2305 // Then we can change this to:
2312 // Which is a bit more efficient.
2313 // We conditionally jump to the fall-through block.
2314 BranchCode = GetOppositeBranchCondition(BranchCode);
2315 unsigned JNCC = GetCondBranchFromCond(BranchCode);
2316 MachineBasicBlock::iterator OldInst = I;
2318 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2319 .addMBB(UnCondBrIter->getOperand(0).getMBB());
2320 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2323 OldInst->eraseFromParent();
2324 UnCondBrIter->eraseFromParent();
2326 // Restart the analysis.
2327 UnCondBrIter = MBB.end();
2333 TBB = I->getOperand(0).getMBB();
2334 Cond.push_back(MachineOperand::CreateImm(BranchCode));
2338 // Handle subsequent conditional branches. Only handle the case where all
2339 // conditional branches branch to the same destination and their condition
2340 // opcodes fit one of the special multi-branch idioms.
2341 assert(Cond.size() == 1);
2344 // Only handle the case where all conditional branches branch to the same
2346 if (TBB != I->getOperand(0).getMBB())
2349 // If the conditions are the same, we can leave them alone.
2350 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2351 if (OldBranchCode == BranchCode)
2354 // If they differ, see if they fit one of the known patterns. Theoretically,
2355 // we could handle more patterns here, but we shouldn't expect to see them
2356 // if instruction selection has done a reasonable job.
2357 if ((OldBranchCode == X86::COND_NP &&
2358 BranchCode == X86::COND_E) ||
2359 (OldBranchCode == X86::COND_E &&
2360 BranchCode == X86::COND_NP))
2361 BranchCode = X86::COND_NP_OR_E;
2362 else if ((OldBranchCode == X86::COND_P &&
2363 BranchCode == X86::COND_NE) ||
2364 (OldBranchCode == X86::COND_NE &&
2365 BranchCode == X86::COND_P))
2366 BranchCode = X86::COND_NE_OR_P;
2370 // Update the MachineOperand.
2371 Cond[0].setImm(BranchCode);
2377 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
2378 MachineBasicBlock::iterator I = MBB.end();
2381 while (I != MBB.begin()) {
2383 if (I->isDebugValue())
2385 if (I->getOpcode() != X86::JMP_4 &&
2386 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2388 // Remove the branch.
2389 I->eraseFromParent();
2398 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
2399 MachineBasicBlock *FBB,
2400 const SmallVectorImpl<MachineOperand> &Cond,
2401 DebugLoc DL) const {
2402 // Shouldn't be a fall through.
2403 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
2404 assert((Cond.size() == 1 || Cond.size() == 0) &&
2405 "X86 branch conditions have one component!");
2408 // Unconditional branch?
2409 assert(!FBB && "Unconditional branch with multiple successors!");
2410 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
2414 // Conditional branch.
2416 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2418 case X86::COND_NP_OR_E:
2419 // Synthesize NP_OR_E with two branches.
2420 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
2422 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
2425 case X86::COND_NE_OR_P:
2426 // Synthesize NE_OR_P with two branches.
2427 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
2429 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
2433 unsigned Opc = GetCondBranchFromCond(CC);
2434 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
2439 // Two-way Conditional branch. Insert the second branch.
2440 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
2446 /// isHReg - Test if the given register is a physical h register.
2447 static bool isHReg(unsigned Reg) {
2448 return X86::GR8_ABCD_HRegClass.contains(Reg);
2451 // Try and copy between VR128/VR64 and GR64 registers.
2452 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2454 // SrcReg(VR128) -> DestReg(GR64)
2455 // SrcReg(VR64) -> DestReg(GR64)
2456 // SrcReg(GR64) -> DestReg(VR128)
2457 // SrcReg(GR64) -> DestReg(VR64)
2459 if (X86::GR64RegClass.contains(DestReg)) {
2460 if (X86::VR128RegClass.contains(SrcReg)) {
2461 // Copy from a VR128 register to a GR64 register.
2462 return HasAVX ? X86::VMOVPQIto64rr : X86::MOVPQIto64rr;
2463 } else if (X86::VR64RegClass.contains(SrcReg)) {
2464 // Copy from a VR64 register to a GR64 register.
2465 return X86::MOVSDto64rr;
2467 } else if (X86::GR64RegClass.contains(SrcReg)) {
2468 // Copy from a GR64 register to a VR128 register.
2469 if (X86::VR128RegClass.contains(DestReg))
2470 return HasAVX ? X86::VMOV64toPQIrr : X86::MOV64toPQIrr;
2471 // Copy from a GR64 register to a VR64 register.
2472 else if (X86::VR64RegClass.contains(DestReg))
2473 return X86::MOV64toSDrr;
2476 // SrcReg(FR32) -> DestReg(GR32)
2477 // SrcReg(GR32) -> DestReg(FR32)
2479 if (X86::GR32RegClass.contains(DestReg) && X86::FR32RegClass.contains(SrcReg))
2480 // Copy from a FR32 register to a GR32 register.
2481 return HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr;
2483 if (X86::FR32RegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
2484 // Copy from a GR32 register to a FR32 register.
2485 return HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr;
2490 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
2491 MachineBasicBlock::iterator MI, DebugLoc DL,
2492 unsigned DestReg, unsigned SrcReg,
2493 bool KillSrc) const {
2494 // First deal with the normal symmetric copies.
2495 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2497 if (X86::GR64RegClass.contains(DestReg, SrcReg))
2499 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
2501 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
2503 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
2504 // Copying to or from a physical H register on x86-64 requires a NOREX
2505 // move. Otherwise use a normal move.
2506 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
2507 TM.getSubtarget<X86Subtarget>().is64Bit()) {
2508 Opc = X86::MOV8rr_NOREX;
2509 // Both operands must be encodable without an REX prefix.
2510 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
2511 "8-bit H register can not be copied outside GR8_NOREX");
2514 } else if (X86::VR128RegClass.contains(DestReg, SrcReg))
2515 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
2516 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
2517 Opc = X86::VMOVAPSYrr;
2518 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
2519 Opc = X86::MMX_MOVQ64rr;
2521 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, HasAVX);
2524 BuildMI(MBB, MI, DL, get(Opc), DestReg)
2525 .addReg(SrcReg, getKillRegState(KillSrc));
2529 // Moving EFLAGS to / from another register requires a push and a pop.
2530 if (SrcReg == X86::EFLAGS) {
2531 if (X86::GR64RegClass.contains(DestReg)) {
2532 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
2533 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
2535 } else if (X86::GR32RegClass.contains(DestReg)) {
2536 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
2537 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
2541 if (DestReg == X86::EFLAGS) {
2542 if (X86::GR64RegClass.contains(SrcReg)) {
2543 BuildMI(MBB, MI, DL, get(X86::PUSH64r))
2544 .addReg(SrcReg, getKillRegState(KillSrc));
2545 BuildMI(MBB, MI, DL, get(X86::POPF64));
2547 } else if (X86::GR32RegClass.contains(SrcReg)) {
2548 BuildMI(MBB, MI, DL, get(X86::PUSH32r))
2549 .addReg(SrcReg, getKillRegState(KillSrc));
2550 BuildMI(MBB, MI, DL, get(X86::POPF32));
2555 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
2556 << " to " << RI.getName(DestReg) << '\n');
2557 llvm_unreachable("Cannot emit physreg copy instruction");
2560 static unsigned getLoadStoreRegOpcode(unsigned Reg,
2561 const TargetRegisterClass *RC,
2562 bool isStackAligned,
2563 const TargetMachine &TM,
2565 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2566 switch (RC->getSize()) {
2568 llvm_unreachable("Unknown spill size");
2570 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
2571 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2572 // Copying to or from a physical H register on x86-64 requires a NOREX
2573 // move. Otherwise use a normal move.
2574 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
2575 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2576 return load ? X86::MOV8rm : X86::MOV8mr;
2578 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
2579 return load ? X86::MOV16rm : X86::MOV16mr;
2581 if (X86::GR32RegClass.hasSubClassEq(RC))
2582 return load ? X86::MOV32rm : X86::MOV32mr;
2583 if (X86::FR32RegClass.hasSubClassEq(RC))
2585 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
2586 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
2587 if (X86::RFP32RegClass.hasSubClassEq(RC))
2588 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
2589 llvm_unreachable("Unknown 4-byte regclass");
2591 if (X86::GR64RegClass.hasSubClassEq(RC))
2592 return load ? X86::MOV64rm : X86::MOV64mr;
2593 if (X86::FR64RegClass.hasSubClassEq(RC))
2595 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
2596 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
2597 if (X86::VR64RegClass.hasSubClassEq(RC))
2598 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
2599 if (X86::RFP64RegClass.hasSubClassEq(RC))
2600 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
2601 llvm_unreachable("Unknown 8-byte regclass");
2603 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
2604 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
2606 assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
2607 // If stack is realigned we can use aligned stores.
2610 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
2611 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
2614 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
2615 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
2618 assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
2619 // If stack is realigned we can use aligned stores.
2621 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
2623 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
2627 static unsigned getStoreRegOpcode(unsigned SrcReg,
2628 const TargetRegisterClass *RC,
2629 bool isStackAligned,
2630 TargetMachine &TM) {
2631 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
2635 static unsigned getLoadRegOpcode(unsigned DestReg,
2636 const TargetRegisterClass *RC,
2637 bool isStackAligned,
2638 const TargetMachine &TM) {
2639 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
2642 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2643 MachineBasicBlock::iterator MI,
2644 unsigned SrcReg, bool isKill, int FrameIdx,
2645 const TargetRegisterClass *RC,
2646 const TargetRegisterInfo *TRI) const {
2647 const MachineFunction &MF = *MBB.getParent();
2648 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
2649 "Stack slot too small for store");
2650 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2651 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
2652 RI.canRealignStack(MF);
2653 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2654 DebugLoc DL = MBB.findDebugLoc(MI);
2655 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
2656 .addReg(SrcReg, getKillRegState(isKill));
2659 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2661 SmallVectorImpl<MachineOperand> &Addr,
2662 const TargetRegisterClass *RC,
2663 MachineInstr::mmo_iterator MMOBegin,
2664 MachineInstr::mmo_iterator MMOEnd,
2665 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2666 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2667 bool isAligned = MMOBegin != MMOEnd &&
2668 (*MMOBegin)->getAlignment() >= Alignment;
2669 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2671 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2672 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2673 MIB.addOperand(Addr[i]);
2674 MIB.addReg(SrcReg, getKillRegState(isKill));
2675 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2676 NewMIs.push_back(MIB);
2680 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2681 MachineBasicBlock::iterator MI,
2682 unsigned DestReg, int FrameIdx,
2683 const TargetRegisterClass *RC,
2684 const TargetRegisterInfo *TRI) const {
2685 const MachineFunction &MF = *MBB.getParent();
2686 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2687 bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
2688 RI.canRealignStack(MF);
2689 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2690 DebugLoc DL = MBB.findDebugLoc(MI);
2691 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2694 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2695 SmallVectorImpl<MachineOperand> &Addr,
2696 const TargetRegisterClass *RC,
2697 MachineInstr::mmo_iterator MMOBegin,
2698 MachineInstr::mmo_iterator MMOEnd,
2699 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2700 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
2701 bool isAligned = MMOBegin != MMOEnd &&
2702 (*MMOBegin)->getAlignment() >= Alignment;
2703 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2705 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2706 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2707 MIB.addOperand(Addr[i]);
2708 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2709 NewMIs.push_back(MIB);
2713 OptimizeSubInstr(MachineInstr *SubInstr, const MachineRegisterInfo *MRI) const {
2714 // If destination is a memory operand, do not perform this optimization.
2715 if ((SubInstr->getOpcode() != X86::SUB64rr) &&
2716 (SubInstr->getOpcode() != X86::SUB32rr) &&
2717 (SubInstr->getOpcode() != X86::SUB16rr) &&
2718 (SubInstr->getOpcode() != X86::SUB8rr) &&
2719 (SubInstr->getOpcode() != X86::SUB64ri32) &&
2720 (SubInstr->getOpcode() != X86::SUB64ri8) &&
2721 (SubInstr->getOpcode() != X86::SUB32ri) &&
2722 (SubInstr->getOpcode() != X86::SUB32ri8) &&
2723 (SubInstr->getOpcode() != X86::SUB16ri) &&
2724 (SubInstr->getOpcode() != X86::SUB16ri8) &&
2725 (SubInstr->getOpcode() != X86::SUB8ri))
2727 unsigned DestReg = SubInstr->getOperand(0).getReg();
2728 if (MRI->use_begin(DestReg) != MRI->use_end())
2731 // There is no use of the destination register, we can replace SUB with CMP.
2732 switch (SubInstr->getOpcode()) {
2734 case X86::SUB64rr: SubInstr->setDesc(get(X86::CMP64rr)); break;
2735 case X86::SUB32rr: SubInstr->setDesc(get(X86::CMP32rr)); break;
2736 case X86::SUB16rr: SubInstr->setDesc(get(X86::CMP16rr)); break;
2737 case X86::SUB8rr: SubInstr->setDesc(get(X86::CMP8rr)); break;
2738 case X86::SUB64ri32: SubInstr->setDesc(get(X86::CMP64ri32)); break;
2739 case X86::SUB64ri8: SubInstr->setDesc(get(X86::CMP64ri8)); break;
2740 case X86::SUB32ri: SubInstr->setDesc(get(X86::CMP32ri)); break;
2741 case X86::SUB32ri8: SubInstr->setDesc(get(X86::CMP32ri8)); break;
2742 case X86::SUB16ri: SubInstr->setDesc(get(X86::CMP16ri)); break;
2743 case X86::SUB16ri8: SubInstr->setDesc(get(X86::CMP16ri8)); break;
2744 case X86::SUB8ri: SubInstr->setDesc(get(X86::CMP8ri)); break;
2746 SubInstr->RemoveOperand(0);
2750 /// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
2751 /// instruction with two undef reads of the register being defined. This is
2752 /// used for mapping:
2755 /// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
2757 static bool Expand2AddrUndef(MachineInstr *MI, const MCInstrDesc &Desc) {
2758 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
2759 unsigned Reg = MI->getOperand(0).getReg();
2762 // MachineInstr::addOperand() will insert explicit operands before any
2763 // implicit operands.
2764 MachineInstrBuilder(MI).addReg(Reg, RegState::Undef)
2765 .addReg(Reg, RegState::Undef);
2766 // But we don't trust that.
2767 assert(MI->getOperand(1).getReg() == Reg &&
2768 MI->getOperand(2).getReg() == Reg && "Misplaced operand");
2772 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
2773 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2774 switch (MI->getOpcode()) {
2778 return Expand2AddrUndef(MI, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
2779 case X86::TEST8ri_NOREX:
2780 MI->setDesc(get(X86::TEST8ri));
2787 X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
2788 int FrameIx, uint64_t Offset,
2789 const MDNode *MDPtr,
2790 DebugLoc DL) const {
2792 AM.BaseType = X86AddressMode::FrameIndexBase;
2793 AM.Base.FrameIndex = FrameIx;
2794 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
2795 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
2799 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2800 const SmallVectorImpl<MachineOperand> &MOs,
2802 const TargetInstrInfo &TII) {
2803 // Create the base instruction with the memory operand as the first part.
2804 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2805 MI->getDebugLoc(), true);
2806 MachineInstrBuilder MIB(NewMI);
2807 unsigned NumAddrOps = MOs.size();
2808 for (unsigned i = 0; i != NumAddrOps; ++i)
2809 MIB.addOperand(MOs[i]);
2810 if (NumAddrOps < 4) // FrameIndex only
2813 // Loop over the rest of the ri operands, converting them over.
2814 unsigned NumOps = MI->getDesc().getNumOperands()-2;
2815 for (unsigned i = 0; i != NumOps; ++i) {
2816 MachineOperand &MO = MI->getOperand(i+2);
2819 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2820 MachineOperand &MO = MI->getOperand(i);
2826 static MachineInstr *FuseInst(MachineFunction &MF,
2827 unsigned Opcode, unsigned OpNo,
2828 const SmallVectorImpl<MachineOperand> &MOs,
2829 MachineInstr *MI, const TargetInstrInfo &TII) {
2830 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2831 MI->getDebugLoc(), true);
2832 MachineInstrBuilder MIB(NewMI);
2834 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2835 MachineOperand &MO = MI->getOperand(i);
2837 assert(MO.isReg() && "Expected to fold into reg operand!");
2838 unsigned NumAddrOps = MOs.size();
2839 for (unsigned i = 0; i != NumAddrOps; ++i)
2840 MIB.addOperand(MOs[i]);
2841 if (NumAddrOps < 4) // FrameIndex only
2850 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2851 const SmallVectorImpl<MachineOperand> &MOs,
2853 MachineFunction &MF = *MI->getParent()->getParent();
2854 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2856 unsigned NumAddrOps = MOs.size();
2857 for (unsigned i = 0; i != NumAddrOps; ++i)
2858 MIB.addOperand(MOs[i]);
2859 if (NumAddrOps < 4) // FrameIndex only
2861 return MIB.addImm(0);
2865 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2866 MachineInstr *MI, unsigned i,
2867 const SmallVectorImpl<MachineOperand> &MOs,
2868 unsigned Size, unsigned Align) const {
2869 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
2870 bool isTwoAddrFold = false;
2871 unsigned NumOps = MI->getDesc().getNumOperands();
2872 bool isTwoAddr = NumOps > 1 &&
2873 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
2875 // FIXME: AsmPrinter doesn't know how to handle
2876 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
2877 if (MI->getOpcode() == X86::ADD32ri &&
2878 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
2881 MachineInstr *NewMI = NULL;
2882 // Folding a memory location into the two-address part of a two-address
2883 // instruction is different than folding it other places. It requires
2884 // replacing the *two* registers with the memory location.
2885 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2886 MI->getOperand(0).isReg() &&
2887 MI->getOperand(1).isReg() &&
2888 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2889 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2890 isTwoAddrFold = true;
2891 } else if (i == 0) { // If operand 0
2892 if (MI->getOpcode() == X86::MOV64r0)
2893 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2894 else if (MI->getOpcode() == X86::MOV32r0)
2895 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2896 else if (MI->getOpcode() == X86::MOV16r0)
2897 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2898 else if (MI->getOpcode() == X86::MOV8r0)
2899 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2903 OpcodeTablePtr = &RegOp2MemOpTable0;
2904 } else if (i == 1) {
2905 OpcodeTablePtr = &RegOp2MemOpTable1;
2906 } else if (i == 2) {
2907 OpcodeTablePtr = &RegOp2MemOpTable2;
2910 // If table selected...
2911 if (OpcodeTablePtr) {
2912 // Find the Opcode to fuse
2913 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
2914 OpcodeTablePtr->find(MI->getOpcode());
2915 if (I != OpcodeTablePtr->end()) {
2916 unsigned Opcode = I->second.first;
2917 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
2918 if (Align < MinAlign)
2920 bool NarrowToMOV32rm = false;
2922 unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize();
2923 if (Size < RCSize) {
2924 // Check if it's safe to fold the load. If the size of the object is
2925 // narrower than the load width, then it's not.
2926 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2928 // If this is a 64-bit load, but the spill slot is 32, then we can do
2929 // a 32-bit load which is implicitly zero-extended. This likely is due
2930 // to liveintervalanalysis remat'ing a load from stack slot.
2931 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2933 Opcode = X86::MOV32rm;
2934 NarrowToMOV32rm = true;
2939 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2941 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2943 if (NarrowToMOV32rm) {
2944 // If this is the special case where we use a MOV32rm to load a 32-bit
2945 // value and zero-extend the top bits. Change the destination register
2947 unsigned DstReg = NewMI->getOperand(0).getReg();
2948 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2949 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2952 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
2959 if (PrintFailedFusing && !MI->isCopy())
2960 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
2964 /// hasPartialRegUpdate - Return true for all instructions that only update
2965 /// the first 32 or 64-bits of the destination register and leave the rest
2966 /// unmodified. This can be used to avoid folding loads if the instructions
2967 /// only update part of the destination register, and the non-updated part is
2968 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
2969 /// instructions breaks the partial register dependency and it can improve
2970 /// performance. e.g.:
2972 /// movss (%rdi), %xmm0
2973 /// cvtss2sd %xmm0, %xmm0
2976 /// cvtss2sd (%rdi), %xmm0
2978 /// FIXME: This should be turned into a TSFlags.
2980 static bool hasPartialRegUpdate(unsigned Opcode) {
2982 case X86::CVTSI2SSrr:
2983 case X86::CVTSI2SS64rr:
2984 case X86::CVTSI2SDrr:
2985 case X86::CVTSI2SD64rr:
2986 case X86::CVTSD2SSrr:
2987 case X86::Int_CVTSD2SSrr:
2988 case X86::CVTSS2SDrr:
2989 case X86::Int_CVTSS2SDrr:
2991 case X86::RCPSSr_Int:
2993 case X86::ROUNDSDr_Int:
2995 case X86::ROUNDSSr_Int:
2997 case X86::RSQRTSSr_Int:
2999 case X86::SQRTSSr_Int:
3000 // AVX encoded versions
3001 case X86::VCVTSD2SSrr:
3002 case X86::Int_VCVTSD2SSrr:
3003 case X86::VCVTSS2SDrr:
3004 case X86::Int_VCVTSS2SDrr:
3006 case X86::VROUNDSDr:
3007 case X86::VROUNDSDr_Int:
3008 case X86::VROUNDSSr:
3009 case X86::VROUNDSSr_Int:
3010 case X86::VRSQRTSSr:
3018 /// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
3019 /// instructions we would like before a partial register update.
3020 unsigned X86InstrInfo::
3021 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
3022 const TargetRegisterInfo *TRI) const {
3023 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
3026 // If MI is marked as reading Reg, the partial register update is wanted.
3027 const MachineOperand &MO = MI->getOperand(0);
3028 unsigned Reg = MO.getReg();
3029 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
3030 if (MO.readsReg() || MI->readsVirtualRegister(Reg))
3033 if (MI->readsRegister(Reg, TRI))
3037 // If any of the preceding 16 instructions are reading Reg, insert a
3038 // dependency breaking instruction. The magic number is based on a few
3039 // Nehalem experiments.
3044 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
3045 const TargetRegisterInfo *TRI) const {
3046 unsigned Reg = MI->getOperand(OpNum).getReg();
3047 if (X86::VR128RegClass.contains(Reg)) {
3048 // These instructions are all floating point domain, so xorps is the best
3050 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3051 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
3052 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
3053 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3054 } else if (X86::VR256RegClass.contains(Reg)) {
3055 // Use vxorps to clear the full ymm register.
3056 // It wants to read and write the xmm sub-register.
3057 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
3058 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
3059 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
3060 .addReg(Reg, RegState::ImplicitDefine);
3063 MI->addRegisterKilled(Reg, TRI, true);
3066 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
3068 const SmallVectorImpl<unsigned> &Ops,
3069 int FrameIndex) const {
3070 // Check switch flag
3071 if (NoFusing) return NULL;
3073 // Unless optimizing for size, don't fold to avoid partial
3074 // register update stalls
3075 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
3076 hasPartialRegUpdate(MI->getOpcode()))
3079 const MachineFrameInfo *MFI = MF.getFrameInfo();
3080 unsigned Size = MFI->getObjectSize(FrameIndex);
3081 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
3082 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
3083 unsigned NewOpc = 0;
3084 unsigned RCSize = 0;
3085 switch (MI->getOpcode()) {
3086 default: return NULL;
3087 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
3088 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
3089 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
3090 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
3092 // Check if it's safe to fold the load. If the size of the object is
3093 // narrower than the load width, then it's not.
3096 // Change to CMPXXri r, 0 first.
3097 MI->setDesc(get(NewOpc));
3098 MI->getOperand(1).ChangeToImmediate(0);
3099 } else if (Ops.size() != 1)
3102 SmallVector<MachineOperand,4> MOs;
3103 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
3104 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
3107 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
3109 const SmallVectorImpl<unsigned> &Ops,
3110 MachineInstr *LoadMI) const {
3111 // Check switch flag
3112 if (NoFusing) return NULL;
3114 // Unless optimizing for size, don't fold to avoid partial
3115 // register update stalls
3116 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
3117 hasPartialRegUpdate(MI->getOpcode()))
3120 // Determine the alignment of the load.
3121 unsigned Alignment = 0;
3122 if (LoadMI->hasOneMemOperand())
3123 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
3125 switch (LoadMI->getOpcode()) {
3126 case X86::AVX_SET0PSY:
3127 case X86::AVX_SET0PDY:
3128 case X86::AVX2_SETALLONES:
3129 case X86::AVX2_SET0:
3133 case X86::V_SETALLONES:
3134 case X86::AVX_SETALLONES:
3146 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
3147 unsigned NewOpc = 0;
3148 switch (MI->getOpcode()) {
3149 default: return NULL;
3150 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
3151 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
3152 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
3153 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
3155 // Change to CMPXXri r, 0 first.
3156 MI->setDesc(get(NewOpc));
3157 MI->getOperand(1).ChangeToImmediate(0);
3158 } else if (Ops.size() != 1)
3161 // Make sure the subregisters match.
3162 // Otherwise we risk changing the size of the load.
3163 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
3166 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
3167 switch (LoadMI->getOpcode()) {
3169 case X86::V_SETALLONES:
3170 case X86::AVX_SET0PSY:
3171 case X86::AVX_SET0PDY:
3172 case X86::AVX_SETALLONES:
3173 case X86::AVX2_SETALLONES:
3174 case X86::AVX2_SET0:
3176 case X86::FsFLD0SS: {
3177 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
3178 // Create a constant-pool entry and operands to load from it.
3180 // Medium and large mode can't fold loads this way.
3181 if (TM.getCodeModel() != CodeModel::Small &&
3182 TM.getCodeModel() != CodeModel::Kernel)
3185 // x86-32 PIC requires a PIC base register for constant pools.
3186 unsigned PICBase = 0;
3187 if (TM.getRelocationModel() == Reloc::PIC_) {
3188 if (TM.getSubtarget<X86Subtarget>().is64Bit())
3191 // FIXME: PICBase = getGlobalBaseReg(&MF);
3192 // This doesn't work for several reasons.
3193 // 1. GlobalBaseReg may have been spilled.
3194 // 2. It may not be live at MI.
3198 // Create a constant-pool entry.
3199 MachineConstantPool &MCP = *MF.getConstantPool();
3201 unsigned Opc = LoadMI->getOpcode();
3202 if (Opc == X86::FsFLD0SS)
3203 Ty = Type::getFloatTy(MF.getFunction()->getContext());
3204 else if (Opc == X86::FsFLD0SD)
3205 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
3206 else if (Opc == X86::AVX_SET0PSY || Opc == X86::AVX_SET0PDY)
3207 Ty = VectorType::get(Type::getFloatTy(MF.getFunction()->getContext()), 8);
3208 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX2_SET0)
3209 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
3211 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
3213 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX_SETALLONES ||
3214 Opc == X86::AVX2_SETALLONES);
3215 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
3216 Constant::getNullValue(Ty);
3217 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
3219 // Create operands to load from the constant pool entry.
3220 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
3221 MOs.push_back(MachineOperand::CreateImm(1));
3222 MOs.push_back(MachineOperand::CreateReg(0, false));
3223 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
3224 MOs.push_back(MachineOperand::CreateReg(0, false));
3228 // Folding a normal load. Just copy the load's address operands.
3229 unsigned NumOps = LoadMI->getDesc().getNumOperands();
3230 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
3231 MOs.push_back(LoadMI->getOperand(i));
3235 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
3239 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
3240 const SmallVectorImpl<unsigned> &Ops) const {
3241 // Check switch flag
3242 if (NoFusing) return 0;
3244 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
3245 switch (MI->getOpcode()) {
3246 default: return false;
3253 // FIXME: AsmPrinter doesn't know how to handle
3254 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
3255 if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
3261 if (Ops.size() != 1)
3264 unsigned OpNum = Ops[0];
3265 unsigned Opc = MI->getOpcode();
3266 unsigned NumOps = MI->getDesc().getNumOperands();
3267 bool isTwoAddr = NumOps > 1 &&
3268 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
3270 // Folding a memory location into the two-address part of a two-address
3271 // instruction is different than folding it other places. It requires
3272 // replacing the *two* registers with the memory location.
3273 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
3274 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
3275 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
3276 } else if (OpNum == 0) { // If operand 0
3281 case X86::MOV64r0: return true;
3284 OpcodeTablePtr = &RegOp2MemOpTable0;
3285 } else if (OpNum == 1) {
3286 OpcodeTablePtr = &RegOp2MemOpTable1;
3287 } else if (OpNum == 2) {
3288 OpcodeTablePtr = &RegOp2MemOpTable2;
3291 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
3293 return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops);
3296 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
3297 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
3298 SmallVectorImpl<MachineInstr*> &NewMIs) const {
3299 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3300 MemOp2RegOpTable.find(MI->getOpcode());
3301 if (I == MemOp2RegOpTable.end())
3303 unsigned Opc = I->second.first;
3304 unsigned Index = I->second.second & TB_INDEX_MASK;
3305 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3306 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3307 if (UnfoldLoad && !FoldedLoad)
3309 UnfoldLoad &= FoldedLoad;
3310 if (UnfoldStore && !FoldedStore)
3312 UnfoldStore &= FoldedStore;
3314 const MCInstrDesc &MCID = get(Opc);
3315 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
3316 if (!MI->hasOneMemOperand() &&
3317 RC == &X86::VR128RegClass &&
3318 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3319 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
3320 // conservatively assume the address is unaligned. That's bad for
3323 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
3324 SmallVector<MachineOperand,2> BeforeOps;
3325 SmallVector<MachineOperand,2> AfterOps;
3326 SmallVector<MachineOperand,4> ImpOps;
3327 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
3328 MachineOperand &Op = MI->getOperand(i);
3329 if (i >= Index && i < Index + X86::AddrNumOperands)
3330 AddrOps.push_back(Op);
3331 else if (Op.isReg() && Op.isImplicit())
3332 ImpOps.push_back(Op);
3334 BeforeOps.push_back(Op);
3336 AfterOps.push_back(Op);
3339 // Emit the load instruction.
3341 std::pair<MachineInstr::mmo_iterator,
3342 MachineInstr::mmo_iterator> MMOs =
3343 MF.extractLoadMemRefs(MI->memoperands_begin(),
3344 MI->memoperands_end());
3345 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
3347 // Address operands cannot be marked isKill.
3348 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
3349 MachineOperand &MO = NewMIs[0]->getOperand(i);
3351 MO.setIsKill(false);
3356 // Emit the data processing instruction.
3357 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
3358 MachineInstrBuilder MIB(DataMI);
3361 MIB.addReg(Reg, RegState::Define);
3362 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
3363 MIB.addOperand(BeforeOps[i]);
3366 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
3367 MIB.addOperand(AfterOps[i]);
3368 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
3369 MachineOperand &MO = ImpOps[i];
3370 MIB.addReg(MO.getReg(),
3371 getDefRegState(MO.isDef()) |
3372 RegState::Implicit |
3373 getKillRegState(MO.isKill()) |
3374 getDeadRegState(MO.isDead()) |
3375 getUndefRegState(MO.isUndef()));
3377 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
3378 unsigned NewOpc = 0;
3379 switch (DataMI->getOpcode()) {
3381 case X86::CMP64ri32:
3388 MachineOperand &MO0 = DataMI->getOperand(0);
3389 MachineOperand &MO1 = DataMI->getOperand(1);
3390 if (MO1.getImm() == 0) {
3391 switch (DataMI->getOpcode()) {
3394 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
3396 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
3398 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
3399 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
3401 DataMI->setDesc(get(NewOpc));
3402 MO1.ChangeToRegister(MO0.getReg(), false);
3406 NewMIs.push_back(DataMI);
3408 // Emit the store instruction.
3410 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
3411 std::pair<MachineInstr::mmo_iterator,
3412 MachineInstr::mmo_iterator> MMOs =
3413 MF.extractStoreMemRefs(MI->memoperands_begin(),
3414 MI->memoperands_end());
3415 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
3422 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
3423 SmallVectorImpl<SDNode*> &NewNodes) const {
3424 if (!N->isMachineOpcode())
3427 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3428 MemOp2RegOpTable.find(N->getMachineOpcode());
3429 if (I == MemOp2RegOpTable.end())
3431 unsigned Opc = I->second.first;
3432 unsigned Index = I->second.second & TB_INDEX_MASK;
3433 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3434 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3435 const MCInstrDesc &MCID = get(Opc);
3436 MachineFunction &MF = DAG.getMachineFunction();
3437 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
3438 unsigned NumDefs = MCID.NumDefs;
3439 std::vector<SDValue> AddrOps;
3440 std::vector<SDValue> BeforeOps;
3441 std::vector<SDValue> AfterOps;
3442 DebugLoc dl = N->getDebugLoc();
3443 unsigned NumOps = N->getNumOperands();
3444 for (unsigned i = 0; i != NumOps-1; ++i) {
3445 SDValue Op = N->getOperand(i);
3446 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
3447 AddrOps.push_back(Op);
3448 else if (i < Index-NumDefs)
3449 BeforeOps.push_back(Op);
3450 else if (i > Index-NumDefs)
3451 AfterOps.push_back(Op);
3453 SDValue Chain = N->getOperand(NumOps-1);
3454 AddrOps.push_back(Chain);
3456 // Emit the load instruction.
3459 EVT VT = *RC->vt_begin();
3460 std::pair<MachineInstr::mmo_iterator,
3461 MachineInstr::mmo_iterator> MMOs =
3462 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
3463 cast<MachineSDNode>(N)->memoperands_end());
3464 if (!(*MMOs.first) &&
3465 RC == &X86::VR128RegClass &&
3466 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3467 // Do not introduce a slow unaligned load.
3469 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3470 bool isAligned = (*MMOs.first) &&
3471 (*MMOs.first)->getAlignment() >= Alignment;
3472 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
3473 VT, MVT::Other, &AddrOps[0], AddrOps.size());
3474 NewNodes.push_back(Load);
3476 // Preserve memory reference information.
3477 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
3480 // Emit the data processing instruction.
3481 std::vector<EVT> VTs;
3482 const TargetRegisterClass *DstRC = 0;
3483 if (MCID.getNumDefs() > 0) {
3484 DstRC = getRegClass(MCID, 0, &RI, MF);
3485 VTs.push_back(*DstRC->vt_begin());
3487 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
3488 EVT VT = N->getValueType(i);
3489 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
3493 BeforeOps.push_back(SDValue(Load, 0));
3494 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
3495 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
3497 NewNodes.push_back(NewNode);
3499 // Emit the store instruction.
3502 AddrOps.push_back(SDValue(NewNode, 0));
3503 AddrOps.push_back(Chain);
3504 std::pair<MachineInstr::mmo_iterator,
3505 MachineInstr::mmo_iterator> MMOs =
3506 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
3507 cast<MachineSDNode>(N)->memoperands_end());
3508 if (!(*MMOs.first) &&
3509 RC == &X86::VR128RegClass &&
3510 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
3511 // Do not introduce a slow unaligned store.
3513 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3514 bool isAligned = (*MMOs.first) &&
3515 (*MMOs.first)->getAlignment() >= Alignment;
3516 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
3519 &AddrOps[0], AddrOps.size());
3520 NewNodes.push_back(Store);
3522 // Preserve memory reference information.
3523 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
3529 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
3530 bool UnfoldLoad, bool UnfoldStore,
3531 unsigned *LoadRegIndex) const {
3532 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3533 MemOp2RegOpTable.find(Opc);
3534 if (I == MemOp2RegOpTable.end())
3536 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
3537 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
3538 if (UnfoldLoad && !FoldedLoad)
3540 if (UnfoldStore && !FoldedStore)
3543 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
3544 return I->second.first;
3548 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
3549 int64_t &Offset1, int64_t &Offset2) const {
3550 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
3552 unsigned Opc1 = Load1->getMachineOpcode();
3553 unsigned Opc2 = Load2->getMachineOpcode();
3555 default: return false;
3565 case X86::MMX_MOVD64rm:
3566 case X86::MMX_MOVQ64rm:
3567 case X86::FsMOVAPSrm:
3568 case X86::FsMOVAPDrm:
3574 // AVX load instructions
3577 case X86::FsVMOVAPSrm:
3578 case X86::FsVMOVAPDrm:
3579 case X86::VMOVAPSrm:
3580 case X86::VMOVUPSrm:
3581 case X86::VMOVAPDrm:
3582 case X86::VMOVDQArm:
3583 case X86::VMOVDQUrm:
3584 case X86::VMOVAPSYrm:
3585 case X86::VMOVUPSYrm:
3586 case X86::VMOVAPDYrm:
3587 case X86::VMOVDQAYrm:
3588 case X86::VMOVDQUYrm:
3592 default: return false;
3602 case X86::MMX_MOVD64rm:
3603 case X86::MMX_MOVQ64rm:
3604 case X86::FsMOVAPSrm:
3605 case X86::FsMOVAPDrm:
3611 // AVX load instructions
3614 case X86::FsVMOVAPSrm:
3615 case X86::FsVMOVAPDrm:
3616 case X86::VMOVAPSrm:
3617 case X86::VMOVUPSrm:
3618 case X86::VMOVAPDrm:
3619 case X86::VMOVDQArm:
3620 case X86::VMOVDQUrm:
3621 case X86::VMOVAPSYrm:
3622 case X86::VMOVUPSYrm:
3623 case X86::VMOVAPDYrm:
3624 case X86::VMOVDQAYrm:
3625 case X86::VMOVDQUYrm:
3629 // Check if chain operands and base addresses match.
3630 if (Load1->getOperand(0) != Load2->getOperand(0) ||
3631 Load1->getOperand(5) != Load2->getOperand(5))
3633 // Segment operands should match as well.
3634 if (Load1->getOperand(4) != Load2->getOperand(4))
3636 // Scale should be 1, Index should be Reg0.
3637 if (Load1->getOperand(1) == Load2->getOperand(1) &&
3638 Load1->getOperand(2) == Load2->getOperand(2)) {
3639 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
3642 // Now let's examine the displacements.
3643 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
3644 isa<ConstantSDNode>(Load2->getOperand(3))) {
3645 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
3646 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
3653 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
3654 int64_t Offset1, int64_t Offset2,
3655 unsigned NumLoads) const {
3656 assert(Offset2 > Offset1);
3657 if ((Offset2 - Offset1) / 8 > 64)
3660 unsigned Opc1 = Load1->getMachineOpcode();
3661 unsigned Opc2 = Load2->getMachineOpcode();
3663 return false; // FIXME: overly conservative?
3670 case X86::MMX_MOVD64rm:
3671 case X86::MMX_MOVQ64rm:
3675 EVT VT = Load1->getValueType(0);
3676 switch (VT.getSimpleVT().SimpleTy) {
3678 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
3679 // have 16 of them to play with.
3680 if (TM.getSubtargetImpl()->is64Bit()) {
3683 } else if (NumLoads) {
3703 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
3704 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
3705 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
3706 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
3708 Cond[0].setImm(GetOppositeBranchCondition(CC));
3713 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
3714 // FIXME: Return false for x87 stack register classes for now. We can't
3715 // allow any loads of these registers before FpGet_ST0_80.
3716 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
3717 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
3720 /// getGlobalBaseReg - Return a virtual register initialized with the
3721 /// the global base register value. Output instructions required to
3722 /// initialize the register in the function entry block, if necessary.
3724 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
3726 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3727 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3728 "X86-64 PIC uses RIP relative addressing");
3730 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3731 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3732 if (GlobalBaseReg != 0)
3733 return GlobalBaseReg;
3735 // Create the register. The code to initialize it is inserted
3736 // later, by the CGBR pass (below).
3737 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3738 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
3739 X86FI->setGlobalBaseReg(GlobalBaseReg);
3740 return GlobalBaseReg;
3743 // These are the replaceable SSE instructions. Some of these have Int variants
3744 // that we don't include here. We don't want to replace instructions selected
3746 static const uint16_t ReplaceableInstrs[][3] = {
3747 //PackedSingle PackedDouble PackedInt
3748 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
3749 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
3750 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
3751 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
3752 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
3753 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
3754 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
3755 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
3756 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
3757 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
3758 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
3759 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
3760 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
3761 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
3762 // AVX 128-bit support
3763 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
3764 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
3765 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
3766 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
3767 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
3768 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
3769 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
3770 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
3771 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
3772 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
3773 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
3774 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
3775 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
3776 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
3777 // AVX 256-bit support
3778 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
3779 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
3780 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
3781 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
3782 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
3783 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
3786 static const uint16_t ReplaceableInstrsAVX2[][3] = {
3787 //PackedSingle PackedDouble PackedInt
3788 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
3789 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
3790 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
3791 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
3792 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
3793 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
3794 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
3795 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
3796 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
3797 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
3798 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
3799 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
3800 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
3801 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr }
3804 // FIXME: Some shuffle and unpack instructions have equivalents in different
3805 // domains, but they require a bit more work than just switching opcodes.
3807 static const uint16_t *lookup(unsigned opcode, unsigned domain) {
3808 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
3809 if (ReplaceableInstrs[i][domain-1] == opcode)
3810 return ReplaceableInstrs[i];
3814 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
3815 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
3816 if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
3817 return ReplaceableInstrsAVX2[i];
3821 std::pair<uint16_t, uint16_t>
3822 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
3823 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3824 bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2();
3825 uint16_t validDomains = 0;
3826 if (domain && lookup(MI->getOpcode(), domain))
3828 else if (domain && lookupAVX2(MI->getOpcode(), domain))
3829 validDomains = hasAVX2 ? 0xe : 0x6;
3830 return std::make_pair(domain, validDomains);
3833 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
3834 assert(Domain>0 && Domain<4 && "Invalid execution domain");
3835 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3836 assert(dom && "Not an SSE instruction");
3837 const uint16_t *table = lookup(MI->getOpcode(), dom);
3838 if (!table) { // try the other table
3839 assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) &&
3840 "256-bit vector operations only available in AVX2");
3841 table = lookupAVX2(MI->getOpcode(), dom);
3843 assert(table && "Cannot change domain");
3844 MI->setDesc(get(table[Domain-1]));
3847 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
3848 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
3849 NopInst.setOpcode(X86::NOOP);
3852 bool X86InstrInfo::isHighLatencyDef(int opc) const {
3854 default: return false;
3856 case X86::DIVSDrm_Int:
3858 case X86::DIVSDrr_Int:
3860 case X86::DIVSSrm_Int:
3862 case X86::DIVSSrr_Int:
3864 case X86::SQRTPDm_Int:
3866 case X86::SQRTPDr_Int:
3868 case X86::SQRTPSm_Int:
3870 case X86::SQRTPSr_Int:
3872 case X86::SQRTSDm_Int:
3874 case X86::SQRTSDr_Int:
3876 case X86::SQRTSSm_Int:
3878 case X86::SQRTSSr_Int:
3879 // AVX instructions with high latency
3881 case X86::VDIVSDrm_Int:
3883 case X86::VDIVSDrr_Int:
3885 case X86::VDIVSSrm_Int:
3887 case X86::VDIVSSrr_Int:
3889 case X86::VSQRTPDm_Int:
3891 case X86::VSQRTPDr_Int:
3893 case X86::VSQRTPSm_Int:
3895 case X86::VSQRTPSr_Int:
3897 case X86::VSQRTSDm_Int:
3900 case X86::VSQRTSSm_Int:
3907 hasHighOperandLatency(const InstrItineraryData *ItinData,
3908 const MachineRegisterInfo *MRI,
3909 const MachineInstr *DefMI, unsigned DefIdx,
3910 const MachineInstr *UseMI, unsigned UseIdx) const {
3911 return isHighLatencyDef(DefMI->getOpcode());
3915 /// CGBR - Create Global Base Reg pass. This initializes the PIC
3916 /// global base register for x86-32.
3917 struct CGBR : public MachineFunctionPass {
3919 CGBR() : MachineFunctionPass(ID) {}
3921 virtual bool runOnMachineFunction(MachineFunction &MF) {
3922 const X86TargetMachine *TM =
3923 static_cast<const X86TargetMachine *>(&MF.getTarget());
3925 assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
3926 "X86-64 PIC uses RIP relative addressing");
3928 // Only emit a global base reg in PIC mode.
3929 if (TM->getRelocationModel() != Reloc::PIC_)
3932 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
3933 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3935 // If we didn't need a GlobalBaseReg, don't insert code.
3936 if (GlobalBaseReg == 0)
3939 // Insert the set of GlobalBaseReg into the first MBB of the function
3940 MachineBasicBlock &FirstMBB = MF.front();
3941 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3942 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
3943 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3944 const X86InstrInfo *TII = TM->getInstrInfo();
3947 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
3948 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
3952 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3953 // only used in JIT code emission as displacement to pc.
3954 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3956 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3957 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3958 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3959 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3960 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3961 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3962 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3968 virtual const char *getPassName() const {
3969 return "X86 PIC Global Base Reg Initialization";
3972 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
3973 AU.setPreservesCFG();
3974 MachineFunctionPass::getAnalysisUsage(AU);
3981 llvm::createGlobalBaseRegPass() { return new CGBR(); }
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