1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/LiveVariables.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Target/TargetOptions.h"
33 NoFusing("disable-spill-fusing",
34 cl::desc("Disable fusing of spill code into instructions"));
36 PrintFailedFusing("print-failed-fuse-candidates",
37 cl::desc("Print instructions that the allocator wants to"
38 " fuse, but the X86 backend currently can't"),
41 ReMatPICLoad("remat-pic-load",
42 cl::desc("Allow rematerializing pic load"),
43 cl::init(true), cl::Hidden);
46 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
47 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
48 TM(tm), RI(tm, *this) {
49 SmallVector<unsigned,16> AmbEntries;
50 static const unsigned OpTbl2Addr[][2] = {
51 { X86::ADC32ri, X86::ADC32mi },
52 { X86::ADC32ri8, X86::ADC32mi8 },
53 { X86::ADC32rr, X86::ADC32mr },
54 { X86::ADC64ri32, X86::ADC64mi32 },
55 { X86::ADC64ri8, X86::ADC64mi8 },
56 { X86::ADC64rr, X86::ADC64mr },
57 { X86::ADD16ri, X86::ADD16mi },
58 { X86::ADD16ri8, X86::ADD16mi8 },
59 { X86::ADD16rr, X86::ADD16mr },
60 { X86::ADD32ri, X86::ADD32mi },
61 { X86::ADD32ri8, X86::ADD32mi8 },
62 { X86::ADD32rr, X86::ADD32mr },
63 { X86::ADD64ri32, X86::ADD64mi32 },
64 { X86::ADD64ri8, X86::ADD64mi8 },
65 { X86::ADD64rr, X86::ADD64mr },
66 { X86::ADD8ri, X86::ADD8mi },
67 { X86::ADD8rr, X86::ADD8mr },
68 { X86::AND16ri, X86::AND16mi },
69 { X86::AND16ri8, X86::AND16mi8 },
70 { X86::AND16rr, X86::AND16mr },
71 { X86::AND32ri, X86::AND32mi },
72 { X86::AND32ri8, X86::AND32mi8 },
73 { X86::AND32rr, X86::AND32mr },
74 { X86::AND64ri32, X86::AND64mi32 },
75 { X86::AND64ri8, X86::AND64mi8 },
76 { X86::AND64rr, X86::AND64mr },
77 { X86::AND8ri, X86::AND8mi },
78 { X86::AND8rr, X86::AND8mr },
79 { X86::DEC16r, X86::DEC16m },
80 { X86::DEC32r, X86::DEC32m },
81 { X86::DEC64_16r, X86::DEC64_16m },
82 { X86::DEC64_32r, X86::DEC64_32m },
83 { X86::DEC64r, X86::DEC64m },
84 { X86::DEC8r, X86::DEC8m },
85 { X86::INC16r, X86::INC16m },
86 { X86::INC32r, X86::INC32m },
87 { X86::INC64_16r, X86::INC64_16m },
88 { X86::INC64_32r, X86::INC64_32m },
89 { X86::INC64r, X86::INC64m },
90 { X86::INC8r, X86::INC8m },
91 { X86::NEG16r, X86::NEG16m },
92 { X86::NEG32r, X86::NEG32m },
93 { X86::NEG64r, X86::NEG64m },
94 { X86::NEG8r, X86::NEG8m },
95 { X86::NOT16r, X86::NOT16m },
96 { X86::NOT32r, X86::NOT32m },
97 { X86::NOT64r, X86::NOT64m },
98 { X86::NOT8r, X86::NOT8m },
99 { X86::OR16ri, X86::OR16mi },
100 { X86::OR16ri8, X86::OR16mi8 },
101 { X86::OR16rr, X86::OR16mr },
102 { X86::OR32ri, X86::OR32mi },
103 { X86::OR32ri8, X86::OR32mi8 },
104 { X86::OR32rr, X86::OR32mr },
105 { X86::OR64ri32, X86::OR64mi32 },
106 { X86::OR64ri8, X86::OR64mi8 },
107 { X86::OR64rr, X86::OR64mr },
108 { X86::OR8ri, X86::OR8mi },
109 { X86::OR8rr, X86::OR8mr },
110 { X86::ROL16r1, X86::ROL16m1 },
111 { X86::ROL16rCL, X86::ROL16mCL },
112 { X86::ROL16ri, X86::ROL16mi },
113 { X86::ROL32r1, X86::ROL32m1 },
114 { X86::ROL32rCL, X86::ROL32mCL },
115 { X86::ROL32ri, X86::ROL32mi },
116 { X86::ROL64r1, X86::ROL64m1 },
117 { X86::ROL64rCL, X86::ROL64mCL },
118 { X86::ROL64ri, X86::ROL64mi },
119 { X86::ROL8r1, X86::ROL8m1 },
120 { X86::ROL8rCL, X86::ROL8mCL },
121 { X86::ROL8ri, X86::ROL8mi },
122 { X86::ROR16r1, X86::ROR16m1 },
123 { X86::ROR16rCL, X86::ROR16mCL },
124 { X86::ROR16ri, X86::ROR16mi },
125 { X86::ROR32r1, X86::ROR32m1 },
126 { X86::ROR32rCL, X86::ROR32mCL },
127 { X86::ROR32ri, X86::ROR32mi },
128 { X86::ROR64r1, X86::ROR64m1 },
129 { X86::ROR64rCL, X86::ROR64mCL },
130 { X86::ROR64ri, X86::ROR64mi },
131 { X86::ROR8r1, X86::ROR8m1 },
132 { X86::ROR8rCL, X86::ROR8mCL },
133 { X86::ROR8ri, X86::ROR8mi },
134 { X86::SAR16r1, X86::SAR16m1 },
135 { X86::SAR16rCL, X86::SAR16mCL },
136 { X86::SAR16ri, X86::SAR16mi },
137 { X86::SAR32r1, X86::SAR32m1 },
138 { X86::SAR32rCL, X86::SAR32mCL },
139 { X86::SAR32ri, X86::SAR32mi },
140 { X86::SAR64r1, X86::SAR64m1 },
141 { X86::SAR64rCL, X86::SAR64mCL },
142 { X86::SAR64ri, X86::SAR64mi },
143 { X86::SAR8r1, X86::SAR8m1 },
144 { X86::SAR8rCL, X86::SAR8mCL },
145 { X86::SAR8ri, X86::SAR8mi },
146 { X86::SBB32ri, X86::SBB32mi },
147 { X86::SBB32ri8, X86::SBB32mi8 },
148 { X86::SBB32rr, X86::SBB32mr },
149 { X86::SBB64ri32, X86::SBB64mi32 },
150 { X86::SBB64ri8, X86::SBB64mi8 },
151 { X86::SBB64rr, X86::SBB64mr },
152 { X86::SHL16rCL, X86::SHL16mCL },
153 { X86::SHL16ri, X86::SHL16mi },
154 { X86::SHL32rCL, X86::SHL32mCL },
155 { X86::SHL32ri, X86::SHL32mi },
156 { X86::SHL64rCL, X86::SHL64mCL },
157 { X86::SHL64ri, X86::SHL64mi },
158 { X86::SHL8rCL, X86::SHL8mCL },
159 { X86::SHL8ri, X86::SHL8mi },
160 { X86::SHLD16rrCL, X86::SHLD16mrCL },
161 { X86::SHLD16rri8, X86::SHLD16mri8 },
162 { X86::SHLD32rrCL, X86::SHLD32mrCL },
163 { X86::SHLD32rri8, X86::SHLD32mri8 },
164 { X86::SHLD64rrCL, X86::SHLD64mrCL },
165 { X86::SHLD64rri8, X86::SHLD64mri8 },
166 { X86::SHR16r1, X86::SHR16m1 },
167 { X86::SHR16rCL, X86::SHR16mCL },
168 { X86::SHR16ri, X86::SHR16mi },
169 { X86::SHR32r1, X86::SHR32m1 },
170 { X86::SHR32rCL, X86::SHR32mCL },
171 { X86::SHR32ri, X86::SHR32mi },
172 { X86::SHR64r1, X86::SHR64m1 },
173 { X86::SHR64rCL, X86::SHR64mCL },
174 { X86::SHR64ri, X86::SHR64mi },
175 { X86::SHR8r1, X86::SHR8m1 },
176 { X86::SHR8rCL, X86::SHR8mCL },
177 { X86::SHR8ri, X86::SHR8mi },
178 { X86::SHRD16rrCL, X86::SHRD16mrCL },
179 { X86::SHRD16rri8, X86::SHRD16mri8 },
180 { X86::SHRD32rrCL, X86::SHRD32mrCL },
181 { X86::SHRD32rri8, X86::SHRD32mri8 },
182 { X86::SHRD64rrCL, X86::SHRD64mrCL },
183 { X86::SHRD64rri8, X86::SHRD64mri8 },
184 { X86::SUB16ri, X86::SUB16mi },
185 { X86::SUB16ri8, X86::SUB16mi8 },
186 { X86::SUB16rr, X86::SUB16mr },
187 { X86::SUB32ri, X86::SUB32mi },
188 { X86::SUB32ri8, X86::SUB32mi8 },
189 { X86::SUB32rr, X86::SUB32mr },
190 { X86::SUB64ri32, X86::SUB64mi32 },
191 { X86::SUB64ri8, X86::SUB64mi8 },
192 { X86::SUB64rr, X86::SUB64mr },
193 { X86::SUB8ri, X86::SUB8mi },
194 { X86::SUB8rr, X86::SUB8mr },
195 { X86::XOR16ri, X86::XOR16mi },
196 { X86::XOR16ri8, X86::XOR16mi8 },
197 { X86::XOR16rr, X86::XOR16mr },
198 { X86::XOR32ri, X86::XOR32mi },
199 { X86::XOR32ri8, X86::XOR32mi8 },
200 { X86::XOR32rr, X86::XOR32mr },
201 { X86::XOR64ri32, X86::XOR64mi32 },
202 { X86::XOR64ri8, X86::XOR64mi8 },
203 { X86::XOR64rr, X86::XOR64mr },
204 { X86::XOR8ri, X86::XOR8mi },
205 { X86::XOR8rr, X86::XOR8mr }
208 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
209 unsigned RegOp = OpTbl2Addr[i][0];
210 unsigned MemOp = OpTbl2Addr[i][1];
211 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp, MemOp)))
212 assert(false && "Duplicated entries?");
213 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); // Index 0,folded load and store
214 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
215 std::make_pair(RegOp, AuxInfo))))
216 AmbEntries.push_back(MemOp);
219 // If the third value is 1, then it's folding either a load or a store.
220 static const unsigned OpTbl0[][3] = {
221 { X86::CALL32r, X86::CALL32m, 1 },
222 { X86::CALL64r, X86::CALL64m, 1 },
223 { X86::CMP16ri, X86::CMP16mi, 1 },
224 { X86::CMP16ri8, X86::CMP16mi8, 1 },
225 { X86::CMP32ri, X86::CMP32mi, 1 },
226 { X86::CMP32ri8, X86::CMP32mi8, 1 },
227 { X86::CMP64ri32, X86::CMP64mi32, 1 },
228 { X86::CMP64ri8, X86::CMP64mi8, 1 },
229 { X86::CMP8ri, X86::CMP8mi, 1 },
230 { X86::DIV16r, X86::DIV16m, 1 },
231 { X86::DIV32r, X86::DIV32m, 1 },
232 { X86::DIV64r, X86::DIV64m, 1 },
233 { X86::DIV8r, X86::DIV8m, 1 },
234 { X86::FsMOVAPDrr, X86::MOVSDmr, 0 },
235 { X86::FsMOVAPSrr, X86::MOVSSmr, 0 },
236 { X86::IDIV16r, X86::IDIV16m, 1 },
237 { X86::IDIV32r, X86::IDIV32m, 1 },
238 { X86::IDIV64r, X86::IDIV64m, 1 },
239 { X86::IDIV8r, X86::IDIV8m, 1 },
240 { X86::IMUL16r, X86::IMUL16m, 1 },
241 { X86::IMUL32r, X86::IMUL32m, 1 },
242 { X86::IMUL64r, X86::IMUL64m, 1 },
243 { X86::IMUL8r, X86::IMUL8m, 1 },
244 { X86::JMP32r, X86::JMP32m, 1 },
245 { X86::JMP64r, X86::JMP64m, 1 },
246 { X86::MOV16ri, X86::MOV16mi, 0 },
247 { X86::MOV16rr, X86::MOV16mr, 0 },
248 { X86::MOV16to16_, X86::MOV16_mr, 0 },
249 { X86::MOV32ri, X86::MOV32mi, 0 },
250 { X86::MOV32rr, X86::MOV32mr, 0 },
251 { X86::MOV32to32_, X86::MOV32_mr, 0 },
252 { X86::MOV64ri32, X86::MOV64mi32, 0 },
253 { X86::MOV64rr, X86::MOV64mr, 0 },
254 { X86::MOV8ri, X86::MOV8mi, 0 },
255 { X86::MOV8rr, X86::MOV8mr, 0 },
256 { X86::MOVAPDrr, X86::MOVAPDmr, 0 },
257 { X86::MOVAPSrr, X86::MOVAPSmr, 0 },
258 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0 },
259 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0 },
260 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0 },
261 { X86::MOVSDrr, X86::MOVSDmr, 0 },
262 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0 },
263 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0 },
264 { X86::MOVSSrr, X86::MOVSSmr, 0 },
265 { X86::MOVUPDrr, X86::MOVUPDmr, 0 },
266 { X86::MOVUPSrr, X86::MOVUPSmr, 0 },
267 { X86::MUL16r, X86::MUL16m, 1 },
268 { X86::MUL32r, X86::MUL32m, 1 },
269 { X86::MUL64r, X86::MUL64m, 1 },
270 { X86::MUL8r, X86::MUL8m, 1 },
271 { X86::SETAEr, X86::SETAEm, 0 },
272 { X86::SETAr, X86::SETAm, 0 },
273 { X86::SETBEr, X86::SETBEm, 0 },
274 { X86::SETBr, X86::SETBm, 0 },
275 { X86::SETEr, X86::SETEm, 0 },
276 { X86::SETGEr, X86::SETGEm, 0 },
277 { X86::SETGr, X86::SETGm, 0 },
278 { X86::SETLEr, X86::SETLEm, 0 },
279 { X86::SETLr, X86::SETLm, 0 },
280 { X86::SETNEr, X86::SETNEm, 0 },
281 { X86::SETNPr, X86::SETNPm, 0 },
282 { X86::SETNSr, X86::SETNSm, 0 },
283 { X86::SETPr, X86::SETPm, 0 },
284 { X86::SETSr, X86::SETSm, 0 },
285 { X86::TAILJMPr, X86::TAILJMPm, 1 },
286 { X86::TEST16ri, X86::TEST16mi, 1 },
287 { X86::TEST32ri, X86::TEST32mi, 1 },
288 { X86::TEST64ri32, X86::TEST64mi32, 1 },
289 { X86::TEST8ri, X86::TEST8mi, 1 }
292 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
293 unsigned RegOp = OpTbl0[i][0];
294 unsigned MemOp = OpTbl0[i][1];
295 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp, MemOp)))
296 assert(false && "Duplicated entries?");
297 unsigned FoldedLoad = OpTbl0[i][2];
298 // Index 0, folded load or store.
299 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
300 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
301 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
302 std::make_pair(RegOp, AuxInfo))))
303 AmbEntries.push_back(MemOp);
306 static const unsigned OpTbl1[][2] = {
307 { X86::CMP16rr, X86::CMP16rm },
308 { X86::CMP32rr, X86::CMP32rm },
309 { X86::CMP64rr, X86::CMP64rm },
310 { X86::CMP8rr, X86::CMP8rm },
311 { X86::CVTSD2SSrr, X86::CVTSD2SSrm },
312 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm },
313 { X86::CVTSI2SDrr, X86::CVTSI2SDrm },
314 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm },
315 { X86::CVTSI2SSrr, X86::CVTSI2SSrm },
316 { X86::CVTSS2SDrr, X86::CVTSS2SDrm },
317 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm },
318 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm },
319 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm },
320 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm },
321 { X86::FsMOVAPDrr, X86::MOVSDrm },
322 { X86::FsMOVAPSrr, X86::MOVSSrm },
323 { X86::IMUL16rri, X86::IMUL16rmi },
324 { X86::IMUL16rri8, X86::IMUL16rmi8 },
325 { X86::IMUL32rri, X86::IMUL32rmi },
326 { X86::IMUL32rri8, X86::IMUL32rmi8 },
327 { X86::IMUL64rri32, X86::IMUL64rmi32 },
328 { X86::IMUL64rri8, X86::IMUL64rmi8 },
329 { X86::Int_CMPSDrr, X86::Int_CMPSDrm },
330 { X86::Int_CMPSSrr, X86::Int_CMPSSrm },
331 { X86::Int_COMISDrr, X86::Int_COMISDrm },
332 { X86::Int_COMISSrr, X86::Int_COMISSrm },
333 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm },
334 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm },
335 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm },
336 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm },
337 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm },
338 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm },
339 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
340 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm },
341 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm },
342 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
343 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm },
344 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
345 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm },
346 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm },
347 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
348 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm },
349 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
350 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
351 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
352 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
353 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
354 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
355 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm },
356 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm },
357 { X86::MOV16rr, X86::MOV16rm },
358 { X86::MOV16to16_, X86::MOV16_rm },
359 { X86::MOV32rr, X86::MOV32rm },
360 { X86::MOV32to32_, X86::MOV32_rm },
361 { X86::MOV64rr, X86::MOV64rm },
362 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm },
363 { X86::MOV64toSDrr, X86::MOV64toSDrm },
364 { X86::MOV8rr, X86::MOV8rm },
365 { X86::MOVAPDrr, X86::MOVAPDrm },
366 { X86::MOVAPSrr, X86::MOVAPSrm },
367 { X86::MOVDDUPrr, X86::MOVDDUPrm },
368 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm },
369 { X86::MOVDI2SSrr, X86::MOVDI2SSrm },
370 { X86::MOVSD2PDrr, X86::MOVSD2PDrm },
371 { X86::MOVSDrr, X86::MOVSDrm },
372 { X86::MOVSHDUPrr, X86::MOVSHDUPrm },
373 { X86::MOVSLDUPrr, X86::MOVSLDUPrm },
374 { X86::MOVSS2PSrr, X86::MOVSS2PSrm },
375 { X86::MOVSSrr, X86::MOVSSrm },
376 { X86::MOVSX16rr8, X86::MOVSX16rm8 },
377 { X86::MOVSX32rr16, X86::MOVSX32rm16 },
378 { X86::MOVSX32rr8, X86::MOVSX32rm8 },
379 { X86::MOVSX64rr16, X86::MOVSX64rm16 },
380 { X86::MOVSX64rr32, X86::MOVSX64rm32 },
381 { X86::MOVSX64rr8, X86::MOVSX64rm8 },
382 { X86::MOVUPDrr, X86::MOVUPDrm },
383 { X86::MOVUPSrr, X86::MOVUPSrm },
384 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm },
385 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm },
386 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm },
387 { X86::MOVZX16rr8, X86::MOVZX16rm8 },
388 { X86::MOVZX32rr16, X86::MOVZX32rm16 },
389 { X86::MOVZX32rr8, X86::MOVZX32rm8 },
390 { X86::MOVZX64rr16, X86::MOVZX64rm16 },
391 { X86::MOVZX64rr8, X86::MOVZX64rm8 },
392 { X86::PSHUFDri, X86::PSHUFDmi },
393 { X86::PSHUFHWri, X86::PSHUFHWmi },
394 { X86::PSHUFLWri, X86::PSHUFLWmi },
395 { X86::RCPPSr, X86::RCPPSm },
396 { X86::RCPPSr_Int, X86::RCPPSm_Int },
397 { X86::RSQRTPSr, X86::RSQRTPSm },
398 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int },
399 { X86::RSQRTSSr, X86::RSQRTSSm },
400 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int },
401 { X86::SQRTPDr, X86::SQRTPDm },
402 { X86::SQRTPDr_Int, X86::SQRTPDm_Int },
403 { X86::SQRTPSr, X86::SQRTPSm },
404 { X86::SQRTPSr_Int, X86::SQRTPSm_Int },
405 { X86::SQRTSDr, X86::SQRTSDm },
406 { X86::SQRTSDr_Int, X86::SQRTSDm_Int },
407 { X86::SQRTSSr, X86::SQRTSSm },
408 { X86::SQRTSSr_Int, X86::SQRTSSm_Int },
409 { X86::TEST16rr, X86::TEST16rm },
410 { X86::TEST32rr, X86::TEST32rm },
411 { X86::TEST64rr, X86::TEST64rm },
412 { X86::TEST8rr, X86::TEST8rm },
413 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
414 { X86::UCOMISDrr, X86::UCOMISDrm },
415 { X86::UCOMISSrr, X86::UCOMISSrm }
418 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
419 unsigned RegOp = OpTbl1[i][0];
420 unsigned MemOp = OpTbl1[i][1];
421 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp, MemOp)))
422 assert(false && "Duplicated entries?");
423 unsigned AuxInfo = 1 | (1 << 4); // Index 1, folded load
424 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
425 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
426 std::make_pair(RegOp, AuxInfo))))
427 AmbEntries.push_back(MemOp);
430 static const unsigned OpTbl2[][2] = {
431 { X86::ADC32rr, X86::ADC32rm },
432 { X86::ADC64rr, X86::ADC64rm },
433 { X86::ADD16rr, X86::ADD16rm },
434 { X86::ADD32rr, X86::ADD32rm },
435 { X86::ADD64rr, X86::ADD64rm },
436 { X86::ADD8rr, X86::ADD8rm },
437 { X86::ADDPDrr, X86::ADDPDrm },
438 { X86::ADDPSrr, X86::ADDPSrm },
439 { X86::ADDSDrr, X86::ADDSDrm },
440 { X86::ADDSSrr, X86::ADDSSrm },
441 { X86::ADDSUBPDrr, X86::ADDSUBPDrm },
442 { X86::ADDSUBPSrr, X86::ADDSUBPSrm },
443 { X86::AND16rr, X86::AND16rm },
444 { X86::AND32rr, X86::AND32rm },
445 { X86::AND64rr, X86::AND64rm },
446 { X86::AND8rr, X86::AND8rm },
447 { X86::ANDNPDrr, X86::ANDNPDrm },
448 { X86::ANDNPSrr, X86::ANDNPSrm },
449 { X86::ANDPDrr, X86::ANDPDrm },
450 { X86::ANDPSrr, X86::ANDPSrm },
451 { X86::CMOVA16rr, X86::CMOVA16rm },
452 { X86::CMOVA32rr, X86::CMOVA32rm },
453 { X86::CMOVA64rr, X86::CMOVA64rm },
454 { X86::CMOVAE16rr, X86::CMOVAE16rm },
455 { X86::CMOVAE32rr, X86::CMOVAE32rm },
456 { X86::CMOVAE64rr, X86::CMOVAE64rm },
457 { X86::CMOVB16rr, X86::CMOVB16rm },
458 { X86::CMOVB32rr, X86::CMOVB32rm },
459 { X86::CMOVB64rr, X86::CMOVB64rm },
460 { X86::CMOVBE16rr, X86::CMOVBE16rm },
461 { X86::CMOVBE32rr, X86::CMOVBE32rm },
462 { X86::CMOVBE64rr, X86::CMOVBE64rm },
463 { X86::CMOVE16rr, X86::CMOVE16rm },
464 { X86::CMOVE32rr, X86::CMOVE32rm },
465 { X86::CMOVE64rr, X86::CMOVE64rm },
466 { X86::CMOVG16rr, X86::CMOVG16rm },
467 { X86::CMOVG32rr, X86::CMOVG32rm },
468 { X86::CMOVG64rr, X86::CMOVG64rm },
469 { X86::CMOVGE16rr, X86::CMOVGE16rm },
470 { X86::CMOVGE32rr, X86::CMOVGE32rm },
471 { X86::CMOVGE64rr, X86::CMOVGE64rm },
472 { X86::CMOVL16rr, X86::CMOVL16rm },
473 { X86::CMOVL32rr, X86::CMOVL32rm },
474 { X86::CMOVL64rr, X86::CMOVL64rm },
475 { X86::CMOVLE16rr, X86::CMOVLE16rm },
476 { X86::CMOVLE32rr, X86::CMOVLE32rm },
477 { X86::CMOVLE64rr, X86::CMOVLE64rm },
478 { X86::CMOVNE16rr, X86::CMOVNE16rm },
479 { X86::CMOVNE32rr, X86::CMOVNE32rm },
480 { X86::CMOVNE64rr, X86::CMOVNE64rm },
481 { X86::CMOVNP16rr, X86::CMOVNP16rm },
482 { X86::CMOVNP32rr, X86::CMOVNP32rm },
483 { X86::CMOVNP64rr, X86::CMOVNP64rm },
484 { X86::CMOVNS16rr, X86::CMOVNS16rm },
485 { X86::CMOVNS32rr, X86::CMOVNS32rm },
486 { X86::CMOVNS64rr, X86::CMOVNS64rm },
487 { X86::CMOVP16rr, X86::CMOVP16rm },
488 { X86::CMOVP32rr, X86::CMOVP32rm },
489 { X86::CMOVP64rr, X86::CMOVP64rm },
490 { X86::CMOVS16rr, X86::CMOVS16rm },
491 { X86::CMOVS32rr, X86::CMOVS32rm },
492 { X86::CMOVS64rr, X86::CMOVS64rm },
493 { X86::CMPPDrri, X86::CMPPDrmi },
494 { X86::CMPPSrri, X86::CMPPSrmi },
495 { X86::CMPSDrr, X86::CMPSDrm },
496 { X86::CMPSSrr, X86::CMPSSrm },
497 { X86::DIVPDrr, X86::DIVPDrm },
498 { X86::DIVPSrr, X86::DIVPSrm },
499 { X86::DIVSDrr, X86::DIVSDrm },
500 { X86::DIVSSrr, X86::DIVSSrm },
501 { X86::FsANDNPDrr, X86::FsANDNPDrm },
502 { X86::FsANDNPSrr, X86::FsANDNPSrm },
503 { X86::FsANDPDrr, X86::FsANDPDrm },
504 { X86::FsANDPSrr, X86::FsANDPSrm },
505 { X86::FsORPDrr, X86::FsORPDrm },
506 { X86::FsORPSrr, X86::FsORPSrm },
507 { X86::FsXORPDrr, X86::FsXORPDrm },
508 { X86::FsXORPSrr, X86::FsXORPSrm },
509 { X86::HADDPDrr, X86::HADDPDrm },
510 { X86::HADDPSrr, X86::HADDPSrm },
511 { X86::HSUBPDrr, X86::HSUBPDrm },
512 { X86::HSUBPSrr, X86::HSUBPSrm },
513 { X86::IMUL16rr, X86::IMUL16rm },
514 { X86::IMUL32rr, X86::IMUL32rm },
515 { X86::IMUL64rr, X86::IMUL64rm },
516 { X86::MAXPDrr, X86::MAXPDrm },
517 { X86::MAXPDrr_Int, X86::MAXPDrm_Int },
518 { X86::MAXPSrr, X86::MAXPSrm },
519 { X86::MAXPSrr_Int, X86::MAXPSrm_Int },
520 { X86::MAXSDrr, X86::MAXSDrm },
521 { X86::MAXSDrr_Int, X86::MAXSDrm_Int },
522 { X86::MAXSSrr, X86::MAXSSrm },
523 { X86::MAXSSrr_Int, X86::MAXSSrm_Int },
524 { X86::MINPDrr, X86::MINPDrm },
525 { X86::MINPDrr_Int, X86::MINPDrm_Int },
526 { X86::MINPSrr, X86::MINPSrm },
527 { X86::MINPSrr_Int, X86::MINPSrm_Int },
528 { X86::MINSDrr, X86::MINSDrm },
529 { X86::MINSDrr_Int, X86::MINSDrm_Int },
530 { X86::MINSSrr, X86::MINSSrm },
531 { X86::MINSSrr_Int, X86::MINSSrm_Int },
532 { X86::MULPDrr, X86::MULPDrm },
533 { X86::MULPSrr, X86::MULPSrm },
534 { X86::MULSDrr, X86::MULSDrm },
535 { X86::MULSSrr, X86::MULSSrm },
536 { X86::OR16rr, X86::OR16rm },
537 { X86::OR32rr, X86::OR32rm },
538 { X86::OR64rr, X86::OR64rm },
539 { X86::OR8rr, X86::OR8rm },
540 { X86::ORPDrr, X86::ORPDrm },
541 { X86::ORPSrr, X86::ORPSrm },
542 { X86::PACKSSDWrr, X86::PACKSSDWrm },
543 { X86::PACKSSWBrr, X86::PACKSSWBrm },
544 { X86::PACKUSWBrr, X86::PACKUSWBrm },
545 { X86::PADDBrr, X86::PADDBrm },
546 { X86::PADDDrr, X86::PADDDrm },
547 { X86::PADDQrr, X86::PADDQrm },
548 { X86::PADDSBrr, X86::PADDSBrm },
549 { X86::PADDSWrr, X86::PADDSWrm },
550 { X86::PADDWrr, X86::PADDWrm },
551 { X86::PANDNrr, X86::PANDNrm },
552 { X86::PANDrr, X86::PANDrm },
553 { X86::PAVGBrr, X86::PAVGBrm },
554 { X86::PAVGWrr, X86::PAVGWrm },
555 { X86::PCMPEQBrr, X86::PCMPEQBrm },
556 { X86::PCMPEQDrr, X86::PCMPEQDrm },
557 { X86::PCMPEQWrr, X86::PCMPEQWrm },
558 { X86::PCMPGTBrr, X86::PCMPGTBrm },
559 { X86::PCMPGTDrr, X86::PCMPGTDrm },
560 { X86::PCMPGTWrr, X86::PCMPGTWrm },
561 { X86::PINSRWrri, X86::PINSRWrmi },
562 { X86::PMADDWDrr, X86::PMADDWDrm },
563 { X86::PMAXSWrr, X86::PMAXSWrm },
564 { X86::PMAXUBrr, X86::PMAXUBrm },
565 { X86::PMINSWrr, X86::PMINSWrm },
566 { X86::PMINUBrr, X86::PMINUBrm },
567 { X86::PMULHUWrr, X86::PMULHUWrm },
568 { X86::PMULHWrr, X86::PMULHWrm },
569 { X86::PMULLWrr, X86::PMULLWrm },
570 { X86::PMULUDQrr, X86::PMULUDQrm },
571 { X86::PORrr, X86::PORrm },
572 { X86::PSADBWrr, X86::PSADBWrm },
573 { X86::PSLLDrr, X86::PSLLDrm },
574 { X86::PSLLQrr, X86::PSLLQrm },
575 { X86::PSLLWrr, X86::PSLLWrm },
576 { X86::PSRADrr, X86::PSRADrm },
577 { X86::PSRAWrr, X86::PSRAWrm },
578 { X86::PSRLDrr, X86::PSRLDrm },
579 { X86::PSRLQrr, X86::PSRLQrm },
580 { X86::PSRLWrr, X86::PSRLWrm },
581 { X86::PSUBBrr, X86::PSUBBrm },
582 { X86::PSUBDrr, X86::PSUBDrm },
583 { X86::PSUBSBrr, X86::PSUBSBrm },
584 { X86::PSUBSWrr, X86::PSUBSWrm },
585 { X86::PSUBWrr, X86::PSUBWrm },
586 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm },
587 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm },
588 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm },
589 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm },
590 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm },
591 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm },
592 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm },
593 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm },
594 { X86::PXORrr, X86::PXORrm },
595 { X86::SBB32rr, X86::SBB32rm },
596 { X86::SBB64rr, X86::SBB64rm },
597 { X86::SHUFPDrri, X86::SHUFPDrmi },
598 { X86::SHUFPSrri, X86::SHUFPSrmi },
599 { X86::SUB16rr, X86::SUB16rm },
600 { X86::SUB32rr, X86::SUB32rm },
601 { X86::SUB64rr, X86::SUB64rm },
602 { X86::SUB8rr, X86::SUB8rm },
603 { X86::SUBPDrr, X86::SUBPDrm },
604 { X86::SUBPSrr, X86::SUBPSrm },
605 { X86::SUBSDrr, X86::SUBSDrm },
606 { X86::SUBSSrr, X86::SUBSSrm },
607 // FIXME: TEST*rr -> swapped operand of TEST*mr.
608 { X86::UNPCKHPDrr, X86::UNPCKHPDrm },
609 { X86::UNPCKHPSrr, X86::UNPCKHPSrm },
610 { X86::UNPCKLPDrr, X86::UNPCKLPDrm },
611 { X86::UNPCKLPSrr, X86::UNPCKLPSrm },
612 { X86::XOR16rr, X86::XOR16rm },
613 { X86::XOR32rr, X86::XOR32rm },
614 { X86::XOR64rr, X86::XOR64rm },
615 { X86::XOR8rr, X86::XOR8rm },
616 { X86::XORPDrr, X86::XORPDrm },
617 { X86::XORPSrr, X86::XORPSrm }
620 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
621 unsigned RegOp = OpTbl2[i][0];
622 unsigned MemOp = OpTbl2[i][1];
623 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp, MemOp)))
624 assert(false && "Duplicated entries?");
625 unsigned AuxInfo = 2 | (1 << 4); // Index 1, folded load
626 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
627 std::make_pair(RegOp, AuxInfo))))
628 AmbEntries.push_back(MemOp);
631 // Remove ambiguous entries.
632 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
635 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
637 unsigned& destReg) const {
638 switch (MI.getOpcode()) {
645 case X86::MOV16to16_:
646 case X86::MOV32to32_:
650 // FP Stack register class copies
651 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
652 case X86::MOV_Fp3264: case X86::MOV_Fp3280:
653 case X86::MOV_Fp6432: case X86::MOV_Fp8032:
655 case X86::FsMOVAPSrr:
656 case X86::FsMOVAPDrr:
659 case X86::MOVSS2PSrr:
660 case X86::MOVSD2PDrr:
661 case X86::MOVPS2SSrr:
662 case X86::MOVPD2SDrr:
663 case X86::MMX_MOVD64rr:
664 case X86::MMX_MOVQ64rr:
665 assert(MI.getNumOperands() >= 2 &&
666 MI.getOperand(0).isRegister() &&
667 MI.getOperand(1).isRegister() &&
668 "invalid register-register move instruction");
669 sourceReg = MI.getOperand(1).getReg();
670 destReg = MI.getOperand(0).getReg();
675 unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
676 int &FrameIndex) const {
677 switch (MI->getOpcode()) {
690 case X86::MMX_MOVD64rm:
691 case X86::MMX_MOVQ64rm:
692 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
693 MI->getOperand(3).isReg() && MI->getOperand(4).isImm() &&
694 MI->getOperand(2).getImm() == 1 &&
695 MI->getOperand(3).getReg() == 0 &&
696 MI->getOperand(4).getImm() == 0) {
697 FrameIndex = MI->getOperand(1).getIndex();
698 return MI->getOperand(0).getReg();
705 unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
706 int &FrameIndex) const {
707 switch (MI->getOpcode()) {
720 case X86::MMX_MOVD64mr:
721 case X86::MMX_MOVQ64mr:
722 case X86::MMX_MOVNTQmr:
723 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
724 MI->getOperand(2).isReg() && MI->getOperand(3).isImm() &&
725 MI->getOperand(1).getImm() == 1 &&
726 MI->getOperand(2).getReg() == 0 &&
727 MI->getOperand(3).getImm() == 0) {
728 FrameIndex = MI->getOperand(0).getIndex();
729 return MI->getOperand(4).getReg();
737 bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const {
738 switch (MI->getOpcode()) {
751 case X86::MMX_MOVD64rm:
752 case X86::MMX_MOVQ64rm:
753 // Loads from constant pools are trivially rematerializable.
754 if (MI->getOperand(1).isReg() && MI->getOperand(2).isImm() &&
755 MI->getOperand(3).isReg() && MI->getOperand(4).isCPI() &&
756 MI->getOperand(2).getImm() == 1 &&
757 MI->getOperand(3).getReg() == 0) {
758 unsigned BaseReg = MI->getOperand(1).getReg();
763 // Allow re-materialization of PIC load.
764 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
765 bool isPICBase = false;
766 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
767 E = MRI.def_end(); I != E; ++I) {
768 MachineInstr *DefMI = I.getOperand().getParent();
769 if (DefMI->getOpcode() != X86::MOVPC32r)
771 assert(!isPICBase && "More than one PIC base?");
779 // All other instructions marked M_REMATERIALIZABLE are always trivially
784 /// isInvariantLoad - Return true if the specified instruction (which is marked
785 /// mayLoad) is loading from a location whose value is invariant across the
786 /// function. For example, loading a value from the constant pool or from
787 /// from the argument area of a function if it does not change. This should
788 /// only return true of *all* loads the instruction does are invariant (if it
789 /// does multiple loads).
790 bool X86InstrInfo::isInvariantLoad(MachineInstr *MI) const {
791 // This code cares about loads from three cases: constant pool entries,
792 // invariant argument slots, and global stubs. In order to handle these cases
793 // for all of the myriad of X86 instructions, we just scan for a CP/FI/GV
794 // operand and base our analysis on it. This is safe because the address of
795 // none of these three cases is ever used as anything other than a load base
796 // and X86 doesn't have any instructions that load from multiple places.
798 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
799 const MachineOperand &MO = MI->getOperand(i);
800 // Loads from constant pools are trivially invariant.
805 if (TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(MO.getGlobal(),
811 // If this is a load from an invariant stack slot, the load is a constant.
813 const MachineFrameInfo &MFI =
814 *MI->getParent()->getParent()->getFrameInfo();
815 int Idx = MO.getIndex();
816 return MFI.isFixedObjectIndex(Idx) && MFI.isImmutableObjectIndex(Idx);
820 // All other instances of these instructions are presumed to have other
825 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
826 /// is not marked dead.
827 static bool hasLiveCondCodeDef(MachineInstr *MI) {
828 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
829 MachineOperand &MO = MI->getOperand(i);
830 if (MO.isRegister() && MO.isDef() &&
831 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
838 /// convertToThreeAddress - This method must be implemented by targets that
839 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
840 /// may be able to convert a two-address instruction into a true
841 /// three-address instruction on demand. This allows the X86 target (for
842 /// example) to convert ADD and SHL instructions into LEA instructions if they
843 /// would require register copies due to two-addressness.
845 /// This method returns a null pointer if the transformation cannot be
846 /// performed, otherwise it returns the new instruction.
849 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
850 MachineBasicBlock::iterator &MBBI,
851 LiveVariables &LV) const {
852 MachineInstr *MI = MBBI;
853 // All instructions input are two-addr instructions. Get the known operands.
854 unsigned Dest = MI->getOperand(0).getReg();
855 unsigned Src = MI->getOperand(1).getReg();
857 MachineInstr *NewMI = NULL;
858 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
859 // we have better subtarget support, enable the 16-bit LEA generation here.
860 bool DisableLEA16 = true;
862 unsigned MIOpc = MI->getOpcode();
864 case X86::SHUFPSrri: {
865 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
866 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
868 unsigned A = MI->getOperand(0).getReg();
869 unsigned B = MI->getOperand(1).getReg();
870 unsigned C = MI->getOperand(2).getReg();
871 unsigned M = MI->getOperand(3).getImm();
872 if (B != C) return 0;
873 NewMI = BuildMI(get(X86::PSHUFDri), A).addReg(B).addImm(M);
877 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
878 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
879 // the flags produced by a shift yet, so this is safe.
880 unsigned Dest = MI->getOperand(0).getReg();
881 unsigned Src = MI->getOperand(1).getReg();
882 unsigned ShAmt = MI->getOperand(2).getImm();
883 if (ShAmt == 0 || ShAmt >= 4) return 0;
885 NewMI = BuildMI(get(X86::LEA64r), Dest)
886 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
890 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
891 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
892 // the flags produced by a shift yet, so this is safe.
893 unsigned Dest = MI->getOperand(0).getReg();
894 unsigned Src = MI->getOperand(1).getReg();
895 unsigned ShAmt = MI->getOperand(2).getImm();
896 if (ShAmt == 0 || ShAmt >= 4) return 0;
898 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
899 X86::LEA64_32r : X86::LEA32r;
900 NewMI = BuildMI(get(Opc), Dest)
901 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
905 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
906 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
907 // the flags produced by a shift yet, so this is safe.
908 unsigned Dest = MI->getOperand(0).getReg();
909 unsigned Src = MI->getOperand(1).getReg();
910 unsigned ShAmt = MI->getOperand(2).getImm();
911 if (ShAmt == 0 || ShAmt >= 4) return 0;
914 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
915 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
916 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
917 ? X86::LEA64_32r : X86::LEA32r;
918 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
919 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
921 // Build and insert into an implicit UNDEF value. This is OK because
922 // well be shifting and then extracting the lower 16-bits.
923 MachineInstr *Undef = BuildMI(get(X86::IMPLICIT_DEF), leaInReg);
926 BuildMI(get(X86::INSERT_SUBREG),leaInReg)
927 .addReg(leaInReg).addReg(Src).addImm(X86::SUBREG_16BIT);
929 NewMI = BuildMI(get(Opc), leaOutReg)
930 .addReg(0).addImm(1 << ShAmt).addReg(leaInReg).addImm(0);
933 BuildMI(get(X86::EXTRACT_SUBREG), Dest)
934 .addReg(leaOutReg).addImm(X86::SUBREG_16BIT);
935 Ext->copyKillDeadInfo(MI);
937 MFI->insert(MBBI, Undef);
938 MFI->insert(MBBI, Ins); // Insert the insert_subreg
939 LV.instructionChanged(MI, NewMI); // Update live variables
940 LV.addVirtualRegisterKilled(leaInReg, NewMI);
941 MFI->insert(MBBI, NewMI); // Insert the new inst
942 LV.addVirtualRegisterKilled(leaOutReg, Ext);
943 MFI->insert(MBBI, Ext); // Insert the extract_subreg
946 NewMI = BuildMI(get(X86::LEA16r), Dest)
947 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
952 // The following opcodes also sets the condition code register(s). Only
953 // convert them to equivalent lea if the condition code register def's
955 if (hasLiveCondCodeDef(MI))
958 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
963 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
964 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
965 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
966 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, 1);
971 if (DisableLEA16) return 0;
972 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
973 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 1);
977 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
978 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
979 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
980 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, -1);
985 if (DisableLEA16) return 0;
986 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
987 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, -1);
991 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
992 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
993 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
994 NewMI = addRegReg(BuildMI(get(Opc), Dest), Src,
995 MI->getOperand(2).getReg());
999 if (DisableLEA16) return 0;
1000 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1001 NewMI = addRegReg(BuildMI(get(X86::LEA16r), Dest), Src,
1002 MI->getOperand(2).getReg());
1004 case X86::ADD64ri32:
1006 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1007 if (MI->getOperand(2).isImmediate())
1008 NewMI = addRegOffset(BuildMI(get(X86::LEA64r), Dest), Src,
1009 MI->getOperand(2).getImm());
1013 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1014 if (MI->getOperand(2).isImmediate()) {
1015 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1016 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src,
1017 MI->getOperand(2).getImm());
1022 if (DisableLEA16) return 0;
1023 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1024 if (MI->getOperand(2).isImmediate())
1025 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src,
1026 MI->getOperand(2).getImm());
1029 if (DisableLEA16) return 0;
1031 case X86::SHL64ri: {
1032 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImmediate() &&
1033 "Unknown shl instruction!");
1034 unsigned ShAmt = MI->getOperand(2).getImm();
1035 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
1037 AM.Scale = 1 << ShAmt;
1039 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
1040 : (MIOpc == X86::SHL32ri
1041 ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
1042 NewMI = addFullAddress(BuildMI(get(Opc), Dest), AM);
1050 if (!NewMI) return 0;
1052 NewMI->copyKillDeadInfo(MI);
1053 LV.instructionChanged(MI, NewMI); // Update live variables
1054 MFI->insert(MBBI, NewMI); // Insert the new inst
1058 /// commuteInstruction - We have a few instructions that must be hacked on to
1061 MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
1062 switch (MI->getOpcode()) {
1063 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1064 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1065 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1066 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1067 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1068 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1071 switch (MI->getOpcode()) {
1072 default: assert(0 && "Unreachable!");
1073 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1074 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1075 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1076 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1077 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1078 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1080 unsigned Amt = MI->getOperand(3).getImm();
1081 unsigned A = MI->getOperand(0).getReg();
1082 unsigned B = MI->getOperand(1).getReg();
1083 unsigned C = MI->getOperand(2).getReg();
1084 bool BisKill = MI->getOperand(1).isKill();
1085 bool CisKill = MI->getOperand(2).isKill();
1086 // If machine instrs are no longer in two-address forms, update
1087 // destination register as well.
1089 // Must be two address instruction!
1090 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
1091 "Expecting a two-address instruction!");
1095 return BuildMI(get(Opc), A).addReg(C, false, false, CisKill)
1096 .addReg(B, false, false, BisKill).addImm(Size-Amt);
1098 case X86::CMOVB16rr:
1099 case X86::CMOVB32rr:
1100 case X86::CMOVB64rr:
1101 case X86::CMOVAE16rr:
1102 case X86::CMOVAE32rr:
1103 case X86::CMOVAE64rr:
1104 case X86::CMOVE16rr:
1105 case X86::CMOVE32rr:
1106 case X86::CMOVE64rr:
1107 case X86::CMOVNE16rr:
1108 case X86::CMOVNE32rr:
1109 case X86::CMOVNE64rr:
1110 case X86::CMOVBE16rr:
1111 case X86::CMOVBE32rr:
1112 case X86::CMOVBE64rr:
1113 case X86::CMOVA16rr:
1114 case X86::CMOVA32rr:
1115 case X86::CMOVA64rr:
1116 case X86::CMOVL16rr:
1117 case X86::CMOVL32rr:
1118 case X86::CMOVL64rr:
1119 case X86::CMOVGE16rr:
1120 case X86::CMOVGE32rr:
1121 case X86::CMOVGE64rr:
1122 case X86::CMOVLE16rr:
1123 case X86::CMOVLE32rr:
1124 case X86::CMOVLE64rr:
1125 case X86::CMOVG16rr:
1126 case X86::CMOVG32rr:
1127 case X86::CMOVG64rr:
1128 case X86::CMOVS16rr:
1129 case X86::CMOVS32rr:
1130 case X86::CMOVS64rr:
1131 case X86::CMOVNS16rr:
1132 case X86::CMOVNS32rr:
1133 case X86::CMOVNS64rr:
1134 case X86::CMOVP16rr:
1135 case X86::CMOVP32rr:
1136 case X86::CMOVP64rr:
1137 case X86::CMOVNP16rr:
1138 case X86::CMOVNP32rr:
1139 case X86::CMOVNP64rr: {
1141 switch (MI->getOpcode()) {
1143 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1144 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1145 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1146 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1147 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1148 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1149 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1150 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1151 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1152 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1153 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1154 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1155 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1156 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1157 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1158 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1159 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1160 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1161 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1162 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1163 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1164 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1165 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1166 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1167 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1168 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1169 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1170 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1171 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1172 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1173 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1174 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1175 case X86::CMOVS64rr: Opc = X86::CMOVNS32rr; break;
1176 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1177 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1178 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1179 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1180 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1181 case X86::CMOVP64rr: Opc = X86::CMOVNP32rr; break;
1182 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1183 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1184 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1187 MI->setDesc(get(Opc));
1188 // Fallthrough intended.
1191 return TargetInstrInfoImpl::commuteInstruction(MI);
1195 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1197 default: return X86::COND_INVALID;
1198 case X86::JE: return X86::COND_E;
1199 case X86::JNE: return X86::COND_NE;
1200 case X86::JL: return X86::COND_L;
1201 case X86::JLE: return X86::COND_LE;
1202 case X86::JG: return X86::COND_G;
1203 case X86::JGE: return X86::COND_GE;
1204 case X86::JB: return X86::COND_B;
1205 case X86::JBE: return X86::COND_BE;
1206 case X86::JA: return X86::COND_A;
1207 case X86::JAE: return X86::COND_AE;
1208 case X86::JS: return X86::COND_S;
1209 case X86::JNS: return X86::COND_NS;
1210 case X86::JP: return X86::COND_P;
1211 case X86::JNP: return X86::COND_NP;
1212 case X86::JO: return X86::COND_O;
1213 case X86::JNO: return X86::COND_NO;
1217 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1219 default: assert(0 && "Illegal condition code!");
1220 case X86::COND_E: return X86::JE;
1221 case X86::COND_NE: return X86::JNE;
1222 case X86::COND_L: return X86::JL;
1223 case X86::COND_LE: return X86::JLE;
1224 case X86::COND_G: return X86::JG;
1225 case X86::COND_GE: return X86::JGE;
1226 case X86::COND_B: return X86::JB;
1227 case X86::COND_BE: return X86::JBE;
1228 case X86::COND_A: return X86::JA;
1229 case X86::COND_AE: return X86::JAE;
1230 case X86::COND_S: return X86::JS;
1231 case X86::COND_NS: return X86::JNS;
1232 case X86::COND_P: return X86::JP;
1233 case X86::COND_NP: return X86::JNP;
1234 case X86::COND_O: return X86::JO;
1235 case X86::COND_NO: return X86::JNO;
1239 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1240 /// e.g. turning COND_E to COND_NE.
1241 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1243 default: assert(0 && "Illegal condition code!");
1244 case X86::COND_E: return X86::COND_NE;
1245 case X86::COND_NE: return X86::COND_E;
1246 case X86::COND_L: return X86::COND_GE;
1247 case X86::COND_LE: return X86::COND_G;
1248 case X86::COND_G: return X86::COND_LE;
1249 case X86::COND_GE: return X86::COND_L;
1250 case X86::COND_B: return X86::COND_AE;
1251 case X86::COND_BE: return X86::COND_A;
1252 case X86::COND_A: return X86::COND_BE;
1253 case X86::COND_AE: return X86::COND_B;
1254 case X86::COND_S: return X86::COND_NS;
1255 case X86::COND_NS: return X86::COND_S;
1256 case X86::COND_P: return X86::COND_NP;
1257 case X86::COND_NP: return X86::COND_P;
1258 case X86::COND_O: return X86::COND_NO;
1259 case X86::COND_NO: return X86::COND_O;
1263 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1264 const TargetInstrDesc &TID = MI->getDesc();
1265 if (!TID.isTerminator()) return false;
1267 // Conditional branch is a special case.
1268 if (TID.isBranch() && !TID.isBarrier())
1270 if (!TID.isPredicable())
1272 return !isPredicated(MI);
1275 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1276 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1277 const X86InstrInfo &TII) {
1278 if (MI->getOpcode() == X86::FP_REG_KILL)
1280 return TII.isUnpredicatedTerminator(MI);
1283 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1284 MachineBasicBlock *&TBB,
1285 MachineBasicBlock *&FBB,
1286 std::vector<MachineOperand> &Cond) const {
1287 // If the block has no terminators, it just falls into the block after it.
1288 MachineBasicBlock::iterator I = MBB.end();
1289 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this))
1292 // Get the last instruction in the block.
1293 MachineInstr *LastInst = I;
1295 // If there is only one terminator instruction, process it.
1296 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) {
1297 if (!LastInst->getDesc().isBranch())
1300 // If the block ends with a branch there are 3 possibilities:
1301 // it's an unconditional, conditional, or indirect branch.
1303 if (LastInst->getOpcode() == X86::JMP) {
1304 TBB = LastInst->getOperand(0).getMBB();
1307 X86::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
1308 if (BranchCode == X86::COND_INVALID)
1309 return true; // Can't handle indirect branch.
1311 // Otherwise, block ends with fall-through condbranch.
1312 TBB = LastInst->getOperand(0).getMBB();
1313 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1317 // Get the instruction before it if it's a terminator.
1318 MachineInstr *SecondLastInst = I;
1320 // If there are three terminators, we don't know what sort of block this is.
1321 if (SecondLastInst && I != MBB.begin() &&
1322 isBrAnalysisUnpredicatedTerminator(--I, *this))
1325 // If the block ends with X86::JMP and a conditional branch, handle it.
1326 X86::CondCode BranchCode = GetCondFromBranchOpc(SecondLastInst->getOpcode());
1327 if (BranchCode != X86::COND_INVALID && LastInst->getOpcode() == X86::JMP) {
1328 TBB = SecondLastInst->getOperand(0).getMBB();
1329 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1330 FBB = LastInst->getOperand(0).getMBB();
1334 // If the block ends with two X86::JMPs, handle it. The second one is not
1335 // executed, so remove it.
1336 if (SecondLastInst->getOpcode() == X86::JMP &&
1337 LastInst->getOpcode() == X86::JMP) {
1338 TBB = SecondLastInst->getOperand(0).getMBB();
1340 I->eraseFromParent();
1344 // Otherwise, can't handle this.
1348 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1349 MachineBasicBlock::iterator I = MBB.end();
1350 if (I == MBB.begin()) return 0;
1352 if (I->getOpcode() != X86::JMP &&
1353 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1356 // Remove the branch.
1357 I->eraseFromParent();
1361 if (I == MBB.begin()) return 1;
1363 if (GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1366 // Remove the branch.
1367 I->eraseFromParent();
1371 static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
1372 MachineOperand &MO) {
1373 if (MO.isRegister())
1374 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(),
1375 false, false, MO.getSubReg());
1376 else if (MO.isImmediate())
1377 MIB = MIB.addImm(MO.getImm());
1378 else if (MO.isFrameIndex())
1379 MIB = MIB.addFrameIndex(MO.getIndex());
1380 else if (MO.isGlobalAddress())
1381 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
1382 else if (MO.isConstantPoolIndex())
1383 MIB = MIB.addConstantPoolIndex(MO.getIndex(), MO.getOffset());
1384 else if (MO.isJumpTableIndex())
1385 MIB = MIB.addJumpTableIndex(MO.getIndex());
1386 else if (MO.isExternalSymbol())
1387 MIB = MIB.addExternalSymbol(MO.getSymbolName());
1389 assert(0 && "Unknown operand for X86InstrAddOperand!");
1395 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1396 MachineBasicBlock *FBB,
1397 const std::vector<MachineOperand> &Cond) const {
1398 // Shouldn't be a fall through.
1399 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1400 assert((Cond.size() == 1 || Cond.size() == 0) &&
1401 "X86 branch conditions have one component!");
1403 if (FBB == 0) { // One way branch.
1405 // Unconditional branch?
1406 BuildMI(&MBB, get(X86::JMP)).addMBB(TBB);
1408 // Conditional branch.
1409 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
1410 BuildMI(&MBB, get(Opc)).addMBB(TBB);
1415 // Two-way Conditional branch.
1416 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
1417 BuildMI(&MBB, get(Opc)).addMBB(TBB);
1418 BuildMI(&MBB, get(X86::JMP)).addMBB(FBB);
1422 void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1423 MachineBasicBlock::iterator MI,
1424 unsigned DestReg, unsigned SrcReg,
1425 const TargetRegisterClass *DestRC,
1426 const TargetRegisterClass *SrcRC) const {
1427 if (DestRC == SrcRC) {
1429 if (DestRC == &X86::GR64RegClass) {
1431 } else if (DestRC == &X86::GR32RegClass) {
1433 } else if (DestRC == &X86::GR16RegClass) {
1435 } else if (DestRC == &X86::GR8RegClass) {
1437 } else if (DestRC == &X86::GR32_RegClass) {
1438 Opc = X86::MOV32_rr;
1439 } else if (DestRC == &X86::GR16_RegClass) {
1440 Opc = X86::MOV16_rr;
1441 } else if (DestRC == &X86::RFP32RegClass) {
1442 Opc = X86::MOV_Fp3232;
1443 } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) {
1444 Opc = X86::MOV_Fp6464;
1445 } else if (DestRC == &X86::RFP80RegClass) {
1446 Opc = X86::MOV_Fp8080;
1447 } else if (DestRC == &X86::FR32RegClass) {
1448 Opc = X86::FsMOVAPSrr;
1449 } else if (DestRC == &X86::FR64RegClass) {
1450 Opc = X86::FsMOVAPDrr;
1451 } else if (DestRC == &X86::VR128RegClass) {
1452 Opc = X86::MOVAPSrr;
1453 } else if (DestRC == &X86::VR64RegClass) {
1454 Opc = X86::MMX_MOVQ64rr;
1456 assert(0 && "Unknown regclass");
1459 BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
1463 // Moving EFLAGS to / from another register requires a push and a pop.
1464 if (SrcRC == &X86::CCRRegClass) {
1465 assert(SrcReg == X86::EFLAGS);
1466 if (DestRC == &X86::GR64RegClass) {
1467 BuildMI(MBB, MI, get(X86::PUSHFQ));
1468 BuildMI(MBB, MI, get(X86::POP64r), DestReg);
1470 } else if (DestRC == &X86::GR32RegClass) {
1471 BuildMI(MBB, MI, get(X86::PUSHFD));
1472 BuildMI(MBB, MI, get(X86::POP32r), DestReg);
1475 } else if (DestRC == &X86::CCRRegClass) {
1476 assert(DestReg == X86::EFLAGS);
1477 if (SrcRC == &X86::GR64RegClass) {
1478 BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
1479 BuildMI(MBB, MI, get(X86::POPFQ));
1481 } else if (SrcRC == &X86::GR32RegClass) {
1482 BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg);
1483 BuildMI(MBB, MI, get(X86::POPFD));
1488 // Moving from ST(0) turns into FpGET_ST0_32 etc.
1489 if (SrcRC == &X86::RSTRegClass) {
1490 // Copying from ST(0)/ST(1).
1491 assert((SrcReg == X86::ST0 || SrcReg == X86::ST1) &&
1492 "Can only copy from ST(0)/ST(1) right now");
1493 bool isST0 = SrcReg == X86::ST0;
1495 if (DestRC == &X86::RFP32RegClass)
1496 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
1497 else if (DestRC == &X86::RFP64RegClass)
1498 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
1500 assert(DestRC == &X86::RFP80RegClass);
1501 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
1503 BuildMI(MBB, MI, get(Opc), DestReg);
1507 // Moving to ST(0) turns into FpSET_ST0_32 etc.
1508 if (DestRC == &X86::RSTRegClass) {
1509 // Copying to ST(0). FIXME: handle ST(1) also
1510 assert(DestReg == X86::ST0 && "Can only copy to TOS right now");
1512 if (SrcRC == &X86::RFP32RegClass)
1513 Opc = X86::FpSET_ST0_32;
1514 else if (SrcRC == &X86::RFP64RegClass)
1515 Opc = X86::FpSET_ST0_64;
1517 assert(SrcRC == &X86::RFP80RegClass);
1518 Opc = X86::FpSET_ST0_80;
1520 BuildMI(MBB, MI, get(Opc)).addReg(SrcReg);
1524 assert(0 && "Not yet supported!");
1528 static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
1529 unsigned StackAlign) {
1531 if (RC == &X86::GR64RegClass) {
1533 } else if (RC == &X86::GR32RegClass) {
1535 } else if (RC == &X86::GR16RegClass) {
1537 } else if (RC == &X86::GR8RegClass) {
1539 } else if (RC == &X86::GR32_RegClass) {
1540 Opc = X86::MOV32_mr;
1541 } else if (RC == &X86::GR16_RegClass) {
1542 Opc = X86::MOV16_mr;
1543 } else if (RC == &X86::RFP80RegClass) {
1544 Opc = X86::ST_FpP80m; // pops
1545 } else if (RC == &X86::RFP64RegClass) {
1546 Opc = X86::ST_Fp64m;
1547 } else if (RC == &X86::RFP32RegClass) {
1548 Opc = X86::ST_Fp32m;
1549 } else if (RC == &X86::FR32RegClass) {
1551 } else if (RC == &X86::FR64RegClass) {
1553 } else if (RC == &X86::VR128RegClass) {
1554 // FIXME: Use movaps once we are capable of selectively
1555 // aligning functions that spill SSE registers on 16-byte boundaries.
1556 Opc = StackAlign >= 16 ? X86::MOVAPSmr : X86::MOVUPSmr;
1557 } else if (RC == &X86::VR64RegClass) {
1558 Opc = X86::MMX_MOVQ64mr;
1560 assert(0 && "Unknown regclass");
1567 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1568 MachineBasicBlock::iterator MI,
1569 unsigned SrcReg, bool isKill, int FrameIdx,
1570 const TargetRegisterClass *RC) const {
1571 unsigned Opc = getStoreRegOpcode(RC, RI.getStackAlignment());
1572 addFrameReference(BuildMI(MBB, MI, get(Opc)), FrameIdx)
1573 .addReg(SrcReg, false, false, isKill);
1576 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
1578 SmallVectorImpl<MachineOperand> &Addr,
1579 const TargetRegisterClass *RC,
1580 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1581 unsigned Opc = getStoreRegOpcode(RC, RI.getStackAlignment());
1582 MachineInstrBuilder MIB = BuildMI(get(Opc));
1583 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1584 MIB = X86InstrAddOperand(MIB, Addr[i]);
1585 MIB.addReg(SrcReg, false, false, isKill);
1586 NewMIs.push_back(MIB);
1589 static unsigned getLoadRegOpcode(const TargetRegisterClass *RC,
1590 unsigned StackAlign) {
1592 if (RC == &X86::GR64RegClass) {
1594 } else if (RC == &X86::GR32RegClass) {
1596 } else if (RC == &X86::GR16RegClass) {
1598 } else if (RC == &X86::GR8RegClass) {
1600 } else if (RC == &X86::GR32_RegClass) {
1601 Opc = X86::MOV32_rm;
1602 } else if (RC == &X86::GR16_RegClass) {
1603 Opc = X86::MOV16_rm;
1604 } else if (RC == &X86::RFP80RegClass) {
1605 Opc = X86::LD_Fp80m;
1606 } else if (RC == &X86::RFP64RegClass) {
1607 Opc = X86::LD_Fp64m;
1608 } else if (RC == &X86::RFP32RegClass) {
1609 Opc = X86::LD_Fp32m;
1610 } else if (RC == &X86::FR32RegClass) {
1612 } else if (RC == &X86::FR64RegClass) {
1614 } else if (RC == &X86::VR128RegClass) {
1615 // FIXME: Use movaps once we are capable of selectively
1616 // aligning functions that spill SSE registers on 16-byte boundaries.
1617 Opc = StackAlign >= 16 ? X86::MOVAPSrm : X86::MOVUPSrm;
1618 } else if (RC == &X86::VR64RegClass) {
1619 Opc = X86::MMX_MOVQ64rm;
1621 assert(0 && "Unknown regclass");
1628 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1629 MachineBasicBlock::iterator MI,
1630 unsigned DestReg, int FrameIdx,
1631 const TargetRegisterClass *RC) const{
1632 unsigned Opc = getLoadRegOpcode(RC, RI.getStackAlignment());
1633 addFrameReference(BuildMI(MBB, MI, get(Opc), DestReg), FrameIdx);
1636 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
1637 SmallVectorImpl<MachineOperand> &Addr,
1638 const TargetRegisterClass *RC,
1639 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1640 unsigned Opc = getLoadRegOpcode(RC, RI.getStackAlignment());
1641 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
1642 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1643 MIB = X86InstrAddOperand(MIB, Addr[i]);
1644 NewMIs.push_back(MIB);
1647 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1648 MachineBasicBlock::iterator MI,
1649 const std::vector<CalleeSavedInfo> &CSI) const {
1653 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1654 unsigned SlotSize = is64Bit ? 8 : 4;
1656 MachineFunction &MF = *MBB.getParent();
1657 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1658 X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize);
1660 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
1661 for (unsigned i = CSI.size(); i != 0; --i) {
1662 unsigned Reg = CSI[i-1].getReg();
1663 // Add the callee-saved register as live-in. It's killed at the spill.
1665 BuildMI(MBB, MI, get(Opc)).addReg(Reg);
1670 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1671 MachineBasicBlock::iterator MI,
1672 const std::vector<CalleeSavedInfo> &CSI) const {
1676 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1678 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
1679 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1680 unsigned Reg = CSI[i].getReg();
1681 BuildMI(MBB, MI, get(Opc), Reg);
1686 static MachineInstr *FuseTwoAddrInst(unsigned Opcode,
1687 SmallVector<MachineOperand,4> &MOs,
1688 MachineInstr *MI, const TargetInstrInfo &TII) {
1689 // Create the base instruction with the memory operand as the first part.
1690 MachineInstr *NewMI = new MachineInstr(TII.get(Opcode), true);
1691 MachineInstrBuilder MIB(NewMI);
1692 unsigned NumAddrOps = MOs.size();
1693 for (unsigned i = 0; i != NumAddrOps; ++i)
1694 MIB = X86InstrAddOperand(MIB, MOs[i]);
1695 if (NumAddrOps < 4) // FrameIndex only
1696 MIB.addImm(1).addReg(0).addImm(0);
1698 // Loop over the rest of the ri operands, converting them over.
1699 unsigned NumOps = MI->getDesc().getNumOperands()-2;
1700 for (unsigned i = 0; i != NumOps; ++i) {
1701 MachineOperand &MO = MI->getOperand(i+2);
1702 MIB = X86InstrAddOperand(MIB, MO);
1704 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
1705 MachineOperand &MO = MI->getOperand(i);
1706 MIB = X86InstrAddOperand(MIB, MO);
1711 static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
1712 SmallVector<MachineOperand,4> &MOs,
1713 MachineInstr *MI, const TargetInstrInfo &TII) {
1714 MachineInstr *NewMI = new MachineInstr(TII.get(Opcode), true);
1715 MachineInstrBuilder MIB(NewMI);
1717 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1718 MachineOperand &MO = MI->getOperand(i);
1720 assert(MO.isRegister() && "Expected to fold into reg operand!");
1721 unsigned NumAddrOps = MOs.size();
1722 for (unsigned i = 0; i != NumAddrOps; ++i)
1723 MIB = X86InstrAddOperand(MIB, MOs[i]);
1724 if (NumAddrOps < 4) // FrameIndex only
1725 MIB.addImm(1).addReg(0).addImm(0);
1727 MIB = X86InstrAddOperand(MIB, MO);
1733 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
1734 SmallVector<MachineOperand,4> &MOs,
1736 MachineInstrBuilder MIB = BuildMI(TII.get(Opcode));
1738 unsigned NumAddrOps = MOs.size();
1739 for (unsigned i = 0; i != NumAddrOps; ++i)
1740 MIB = X86InstrAddOperand(MIB, MOs[i]);
1741 if (NumAddrOps < 4) // FrameIndex only
1742 MIB.addImm(1).addReg(0).addImm(0);
1743 return MIB.addImm(0);
1747 X86InstrInfo::foldMemoryOperand(MachineInstr *MI, unsigned i,
1748 SmallVector<MachineOperand,4> &MOs) const {
1749 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
1750 bool isTwoAddrFold = false;
1751 unsigned NumOps = MI->getDesc().getNumOperands();
1752 bool isTwoAddr = NumOps > 1 &&
1753 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
1755 MachineInstr *NewMI = NULL;
1756 // Folding a memory location into the two-address part of a two-address
1757 // instruction is different than folding it other places. It requires
1758 // replacing the *two* registers with the memory location.
1759 if (isTwoAddr && NumOps >= 2 && i < 2 &&
1760 MI->getOperand(0).isRegister() &&
1761 MI->getOperand(1).isRegister() &&
1762 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
1763 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
1764 isTwoAddrFold = true;
1765 } else if (i == 0) { // If operand 0
1766 if (MI->getOpcode() == X86::MOV16r0)
1767 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
1768 else if (MI->getOpcode() == X86::MOV32r0)
1769 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
1770 else if (MI->getOpcode() == X86::MOV64r0)
1771 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
1772 else if (MI->getOpcode() == X86::MOV8r0)
1773 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
1775 NewMI->copyKillDeadInfo(MI);
1779 OpcodeTablePtr = &RegOp2MemOpTable0;
1780 } else if (i == 1) {
1781 OpcodeTablePtr = &RegOp2MemOpTable1;
1782 } else if (i == 2) {
1783 OpcodeTablePtr = &RegOp2MemOpTable2;
1786 // If table selected...
1787 if (OpcodeTablePtr) {
1788 // Find the Opcode to fuse
1789 DenseMap<unsigned*, unsigned>::iterator I =
1790 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
1791 if (I != OpcodeTablePtr->end()) {
1793 NewMI = FuseTwoAddrInst(I->second, MOs, MI, *this);
1795 NewMI = FuseInst(I->second, i, MOs, MI, *this);
1796 NewMI->copyKillDeadInfo(MI);
1802 if (PrintFailedFusing)
1803 cerr << "We failed to fuse operand " << i << *MI;
1808 MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
1810 SmallVectorImpl<unsigned> &Ops,
1811 int FrameIndex) const {
1812 // Check switch flag
1813 if (NoFusing) return NULL;
1815 const MachineFrameInfo *MFI = MF.getFrameInfo();
1816 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
1817 // FIXME: Move alignment requirement into tables?
1818 if (Alignment < 16) {
1819 switch (MI->getOpcode()) {
1821 // Not always safe to fold movsd into these instructions since their load
1822 // folding variants expects the address to be 16 byte aligned.
1823 case X86::FsANDNPDrr:
1824 case X86::FsANDNPSrr:
1825 case X86::FsANDPDrr:
1826 case X86::FsANDPSrr:
1829 case X86::FsXORPDrr:
1830 case X86::FsXORPSrr:
1835 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1836 unsigned NewOpc = 0;
1837 switch (MI->getOpcode()) {
1838 default: return NULL;
1839 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
1840 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
1841 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
1842 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
1844 // Change to CMPXXri r, 0 first.
1845 MI->setDesc(get(NewOpc));
1846 MI->getOperand(1).ChangeToImmediate(0);
1847 } else if (Ops.size() != 1)
1850 SmallVector<MachineOperand,4> MOs;
1851 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
1852 return foldMemoryOperand(MI, Ops[0], MOs);
1855 MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
1857 SmallVectorImpl<unsigned> &Ops,
1858 MachineInstr *LoadMI) const {
1859 // Check switch flag
1860 if (NoFusing) return NULL;
1862 unsigned Alignment = 0;
1863 for (unsigned i = 0, e = LoadMI->getNumMemOperands(); i != e; ++i) {
1864 const MemOperand &MRO = LoadMI->getMemOperand(i);
1865 unsigned Align = MRO.getAlignment();
1866 if (Align > Alignment)
1870 // FIXME: Move alignment requirement into tables?
1871 if (Alignment < 16) {
1872 switch (MI->getOpcode()) {
1874 // Not always safe to fold movsd into these instructions since their load
1875 // folding variants expects the address to be 16 byte aligned.
1876 case X86::FsANDNPDrr:
1877 case X86::FsANDNPSrr:
1878 case X86::FsANDPDrr:
1879 case X86::FsANDPSrr:
1882 case X86::FsXORPDrr:
1883 case X86::FsXORPSrr:
1888 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1889 unsigned NewOpc = 0;
1890 switch (MI->getOpcode()) {
1891 default: return NULL;
1892 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
1893 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
1894 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
1895 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
1897 // Change to CMPXXri r, 0 first.
1898 MI->setDesc(get(NewOpc));
1899 MI->getOperand(1).ChangeToImmediate(0);
1900 } else if (Ops.size() != 1)
1903 SmallVector<MachineOperand,4> MOs;
1904 unsigned NumOps = LoadMI->getDesc().getNumOperands();
1905 for (unsigned i = NumOps - 4; i != NumOps; ++i)
1906 MOs.push_back(LoadMI->getOperand(i));
1907 return foldMemoryOperand(MI, Ops[0], MOs);
1911 bool X86InstrInfo::canFoldMemoryOperand(MachineInstr *MI,
1912 SmallVectorImpl<unsigned> &Ops) const {
1913 // Check switch flag
1914 if (NoFusing) return 0;
1916 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1917 switch (MI->getOpcode()) {
1918 default: return false;
1927 if (Ops.size() != 1)
1930 unsigned OpNum = Ops[0];
1931 unsigned Opc = MI->getOpcode();
1932 unsigned NumOps = MI->getDesc().getNumOperands();
1933 bool isTwoAddr = NumOps > 1 &&
1934 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
1936 // Folding a memory location into the two-address part of a two-address
1937 // instruction is different than folding it other places. It requires
1938 // replacing the *two* registers with the memory location.
1939 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
1940 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
1941 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
1942 } else if (OpNum == 0) { // If operand 0
1951 OpcodeTablePtr = &RegOp2MemOpTable0;
1952 } else if (OpNum == 1) {
1953 OpcodeTablePtr = &RegOp2MemOpTable1;
1954 } else if (OpNum == 2) {
1955 OpcodeTablePtr = &RegOp2MemOpTable2;
1958 if (OpcodeTablePtr) {
1959 // Find the Opcode to fuse
1960 DenseMap<unsigned*, unsigned>::iterator I =
1961 OpcodeTablePtr->find((unsigned*)Opc);
1962 if (I != OpcodeTablePtr->end())
1968 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
1969 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
1970 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1971 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
1972 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
1973 if (I == MemOp2RegOpTable.end())
1975 unsigned Opc = I->second.first;
1976 unsigned Index = I->second.second & 0xf;
1977 bool FoldedLoad = I->second.second & (1 << 4);
1978 bool FoldedStore = I->second.second & (1 << 5);
1979 if (UnfoldLoad && !FoldedLoad)
1981 UnfoldLoad &= FoldedLoad;
1982 if (UnfoldStore && !FoldedStore)
1984 UnfoldStore &= FoldedStore;
1986 const TargetInstrDesc &TID = get(Opc);
1987 const TargetOperandInfo &TOI = TID.OpInfo[Index];
1988 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
1989 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
1990 SmallVector<MachineOperand,4> AddrOps;
1991 SmallVector<MachineOperand,2> BeforeOps;
1992 SmallVector<MachineOperand,2> AfterOps;
1993 SmallVector<MachineOperand,4> ImpOps;
1994 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1995 MachineOperand &Op = MI->getOperand(i);
1996 if (i >= Index && i < Index+4)
1997 AddrOps.push_back(Op);
1998 else if (Op.isRegister() && Op.isImplicit())
1999 ImpOps.push_back(Op);
2001 BeforeOps.push_back(Op);
2003 AfterOps.push_back(Op);
2006 // Emit the load instruction.
2008 loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
2010 // Address operands cannot be marked isKill.
2011 for (unsigned i = 1; i != 5; ++i) {
2012 MachineOperand &MO = NewMIs[0]->getOperand(i);
2013 if (MO.isRegister())
2014 MO.setIsKill(false);
2019 // Emit the data processing instruction.
2020 MachineInstr *DataMI = new MachineInstr(TID, true);
2021 MachineInstrBuilder MIB(DataMI);
2024 MIB.addReg(Reg, true);
2025 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2026 MIB = X86InstrAddOperand(MIB, BeforeOps[i]);
2029 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2030 MIB = X86InstrAddOperand(MIB, AfterOps[i]);
2031 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2032 MachineOperand &MO = ImpOps[i];
2033 MIB.addReg(MO.getReg(), MO.isDef(), true, MO.isKill(), MO.isDead());
2035 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2036 unsigned NewOpc = 0;
2037 switch (DataMI->getOpcode()) {
2039 case X86::CMP64ri32:
2043 MachineOperand &MO0 = DataMI->getOperand(0);
2044 MachineOperand &MO1 = DataMI->getOperand(1);
2045 if (MO1.getImm() == 0) {
2046 switch (DataMI->getOpcode()) {
2048 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2049 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2050 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2051 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2053 DataMI->setDesc(get(NewOpc));
2054 MO1.ChangeToRegister(MO0.getReg(), false);
2058 NewMIs.push_back(DataMI);
2060 // Emit the store instruction.
2062 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
2063 const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass()
2064 ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
2065 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
2072 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2073 SmallVectorImpl<SDNode*> &NewNodes) const {
2074 if (!N->isTargetOpcode())
2077 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2078 MemOp2RegOpTable.find((unsigned*)N->getTargetOpcode());
2079 if (I == MemOp2RegOpTable.end())
2081 unsigned Opc = I->second.first;
2082 unsigned Index = I->second.second & 0xf;
2083 bool FoldedLoad = I->second.second & (1 << 4);
2084 bool FoldedStore = I->second.second & (1 << 5);
2085 const TargetInstrDesc &TID = get(Opc);
2086 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2087 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
2088 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
2089 std::vector<SDOperand> AddrOps;
2090 std::vector<SDOperand> BeforeOps;
2091 std::vector<SDOperand> AfterOps;
2092 unsigned NumOps = N->getNumOperands();
2093 for (unsigned i = 0; i != NumOps-1; ++i) {
2094 SDOperand Op = N->getOperand(i);
2095 if (i >= Index && i < Index+4)
2096 AddrOps.push_back(Op);
2098 BeforeOps.push_back(Op);
2100 AfterOps.push_back(Op);
2102 SDOperand Chain = N->getOperand(NumOps-1);
2103 AddrOps.push_back(Chain);
2105 // Emit the load instruction.
2108 MVT::ValueType VT = *RC->vt_begin();
2109 Load = DAG.getTargetNode(getLoadRegOpcode(RC, RI.getStackAlignment()), VT,
2110 MVT::Other, &AddrOps[0], AddrOps.size());
2111 NewNodes.push_back(Load);
2114 // Emit the data processing instruction.
2115 std::vector<MVT::ValueType> VTs;
2116 const TargetRegisterClass *DstRC = 0;
2117 if (TID.getNumDefs() > 0) {
2118 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
2119 DstRC = DstTOI.isLookupPtrRegClass()
2120 ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
2121 VTs.push_back(*DstRC->vt_begin());
2123 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2124 MVT::ValueType VT = N->getValueType(i);
2125 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2129 BeforeOps.push_back(SDOperand(Load, 0));
2130 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2131 SDNode *NewNode= DAG.getTargetNode(Opc, VTs, &BeforeOps[0], BeforeOps.size());
2132 NewNodes.push_back(NewNode);
2134 // Emit the store instruction.
2137 AddrOps.push_back(SDOperand(NewNode, 0));
2138 AddrOps.push_back(Chain);
2139 SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, RI.getStackAlignment()),
2140 MVT::Other, &AddrOps[0], AddrOps.size());
2141 NewNodes.push_back(Store);
2147 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2148 bool UnfoldLoad, bool UnfoldStore) const {
2149 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2150 MemOp2RegOpTable.find((unsigned*)Opc);
2151 if (I == MemOp2RegOpTable.end())
2153 bool FoldedLoad = I->second.second & (1 << 4);
2154 bool FoldedStore = I->second.second & (1 << 5);
2155 if (UnfoldLoad && !FoldedLoad)
2157 if (UnfoldStore && !FoldedStore)
2159 return I->second.first;
2162 bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
2163 if (MBB.empty()) return false;
2165 switch (MBB.back().getOpcode()) {
2166 case X86::TCRETURNri:
2167 case X86::TCRETURNdi:
2168 case X86::RET: // Return.
2173 case X86::JMP: // Uncond branch.
2174 case X86::JMP32r: // Indirect branch.
2175 case X86::JMP64r: // Indirect branch (64-bit).
2176 case X86::JMP32m: // Indirect branch through mem.
2177 case X86::JMP64m: // Indirect branch through mem (64-bit).
2179 default: return false;
2184 ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
2185 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2186 Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm()));
2190 const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
2191 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
2192 if (Subtarget->is64Bit())
2193 return &X86::GR64RegClass;
2195 return &X86::GR32RegClass;