1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/LiveVariables.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/MC/MCAsmInfo.h"
43 NoFusing("disable-spill-fusing",
44 cl::desc("Disable fusing of spill code into instructions"));
46 PrintFailedFusing("print-failed-fuse-candidates",
47 cl::desc("Print instructions that the allocator wants to"
48 " fuse, but the X86 backend currently can't"),
51 ReMatPICStubLoad("remat-pic-stub-load",
52 cl::desc("Re-materialize load from stub in PIC mode"),
53 cl::init(false), cl::Hidden);
55 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
56 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
57 TM(tm), RI(tm, *this) {
58 SmallVector<unsigned,16> AmbEntries;
59 static const unsigned OpTbl2Addr[][2] = {
60 { X86::ADC32ri, X86::ADC32mi },
61 { X86::ADC32ri8, X86::ADC32mi8 },
62 { X86::ADC32rr, X86::ADC32mr },
63 { X86::ADC64ri32, X86::ADC64mi32 },
64 { X86::ADC64ri8, X86::ADC64mi8 },
65 { X86::ADC64rr, X86::ADC64mr },
66 { X86::ADD16ri, X86::ADD16mi },
67 { X86::ADD16ri8, X86::ADD16mi8 },
68 { X86::ADD16rr, X86::ADD16mr },
69 { X86::ADD32ri, X86::ADD32mi },
70 { X86::ADD32ri8, X86::ADD32mi8 },
71 { X86::ADD32rr, X86::ADD32mr },
72 { X86::ADD64ri32, X86::ADD64mi32 },
73 { X86::ADD64ri8, X86::ADD64mi8 },
74 { X86::ADD64rr, X86::ADD64mr },
75 { X86::ADD8ri, X86::ADD8mi },
76 { X86::ADD8rr, X86::ADD8mr },
77 { X86::AND16ri, X86::AND16mi },
78 { X86::AND16ri8, X86::AND16mi8 },
79 { X86::AND16rr, X86::AND16mr },
80 { X86::AND32ri, X86::AND32mi },
81 { X86::AND32ri8, X86::AND32mi8 },
82 { X86::AND32rr, X86::AND32mr },
83 { X86::AND64ri32, X86::AND64mi32 },
84 { X86::AND64ri8, X86::AND64mi8 },
85 { X86::AND64rr, X86::AND64mr },
86 { X86::AND8ri, X86::AND8mi },
87 { X86::AND8rr, X86::AND8mr },
88 { X86::DEC16r, X86::DEC16m },
89 { X86::DEC32r, X86::DEC32m },
90 { X86::DEC64_16r, X86::DEC64_16m },
91 { X86::DEC64_32r, X86::DEC64_32m },
92 { X86::DEC64r, X86::DEC64m },
93 { X86::DEC8r, X86::DEC8m },
94 { X86::INC16r, X86::INC16m },
95 { X86::INC32r, X86::INC32m },
96 { X86::INC64_16r, X86::INC64_16m },
97 { X86::INC64_32r, X86::INC64_32m },
98 { X86::INC64r, X86::INC64m },
99 { X86::INC8r, X86::INC8m },
100 { X86::NEG16r, X86::NEG16m },
101 { X86::NEG32r, X86::NEG32m },
102 { X86::NEG64r, X86::NEG64m },
103 { X86::NEG8r, X86::NEG8m },
104 { X86::NOT16r, X86::NOT16m },
105 { X86::NOT32r, X86::NOT32m },
106 { X86::NOT64r, X86::NOT64m },
107 { X86::NOT8r, X86::NOT8m },
108 { X86::OR16ri, X86::OR16mi },
109 { X86::OR16ri8, X86::OR16mi8 },
110 { X86::OR16rr, X86::OR16mr },
111 { X86::OR32ri, X86::OR32mi },
112 { X86::OR32ri8, X86::OR32mi8 },
113 { X86::OR32rr, X86::OR32mr },
114 { X86::OR64ri32, X86::OR64mi32 },
115 { X86::OR64ri8, X86::OR64mi8 },
116 { X86::OR64rr, X86::OR64mr },
117 { X86::OR8ri, X86::OR8mi },
118 { X86::OR8rr, X86::OR8mr },
119 { X86::ROL16r1, X86::ROL16m1 },
120 { X86::ROL16rCL, X86::ROL16mCL },
121 { X86::ROL16ri, X86::ROL16mi },
122 { X86::ROL32r1, X86::ROL32m1 },
123 { X86::ROL32rCL, X86::ROL32mCL },
124 { X86::ROL32ri, X86::ROL32mi },
125 { X86::ROL64r1, X86::ROL64m1 },
126 { X86::ROL64rCL, X86::ROL64mCL },
127 { X86::ROL64ri, X86::ROL64mi },
128 { X86::ROL8r1, X86::ROL8m1 },
129 { X86::ROL8rCL, X86::ROL8mCL },
130 { X86::ROL8ri, X86::ROL8mi },
131 { X86::ROR16r1, X86::ROR16m1 },
132 { X86::ROR16rCL, X86::ROR16mCL },
133 { X86::ROR16ri, X86::ROR16mi },
134 { X86::ROR32r1, X86::ROR32m1 },
135 { X86::ROR32rCL, X86::ROR32mCL },
136 { X86::ROR32ri, X86::ROR32mi },
137 { X86::ROR64r1, X86::ROR64m1 },
138 { X86::ROR64rCL, X86::ROR64mCL },
139 { X86::ROR64ri, X86::ROR64mi },
140 { X86::ROR8r1, X86::ROR8m1 },
141 { X86::ROR8rCL, X86::ROR8mCL },
142 { X86::ROR8ri, X86::ROR8mi },
143 { X86::SAR16r1, X86::SAR16m1 },
144 { X86::SAR16rCL, X86::SAR16mCL },
145 { X86::SAR16ri, X86::SAR16mi },
146 { X86::SAR32r1, X86::SAR32m1 },
147 { X86::SAR32rCL, X86::SAR32mCL },
148 { X86::SAR32ri, X86::SAR32mi },
149 { X86::SAR64r1, X86::SAR64m1 },
150 { X86::SAR64rCL, X86::SAR64mCL },
151 { X86::SAR64ri, X86::SAR64mi },
152 { X86::SAR8r1, X86::SAR8m1 },
153 { X86::SAR8rCL, X86::SAR8mCL },
154 { X86::SAR8ri, X86::SAR8mi },
155 { X86::SBB32ri, X86::SBB32mi },
156 { X86::SBB32ri8, X86::SBB32mi8 },
157 { X86::SBB32rr, X86::SBB32mr },
158 { X86::SBB64ri32, X86::SBB64mi32 },
159 { X86::SBB64ri8, X86::SBB64mi8 },
160 { X86::SBB64rr, X86::SBB64mr },
161 { X86::SHL16rCL, X86::SHL16mCL },
162 { X86::SHL16ri, X86::SHL16mi },
163 { X86::SHL32rCL, X86::SHL32mCL },
164 { X86::SHL32ri, X86::SHL32mi },
165 { X86::SHL64rCL, X86::SHL64mCL },
166 { X86::SHL64ri, X86::SHL64mi },
167 { X86::SHL8rCL, X86::SHL8mCL },
168 { X86::SHL8ri, X86::SHL8mi },
169 { X86::SHLD16rrCL, X86::SHLD16mrCL },
170 { X86::SHLD16rri8, X86::SHLD16mri8 },
171 { X86::SHLD32rrCL, X86::SHLD32mrCL },
172 { X86::SHLD32rri8, X86::SHLD32mri8 },
173 { X86::SHLD64rrCL, X86::SHLD64mrCL },
174 { X86::SHLD64rri8, X86::SHLD64mri8 },
175 { X86::SHR16r1, X86::SHR16m1 },
176 { X86::SHR16rCL, X86::SHR16mCL },
177 { X86::SHR16ri, X86::SHR16mi },
178 { X86::SHR32r1, X86::SHR32m1 },
179 { X86::SHR32rCL, X86::SHR32mCL },
180 { X86::SHR32ri, X86::SHR32mi },
181 { X86::SHR64r1, X86::SHR64m1 },
182 { X86::SHR64rCL, X86::SHR64mCL },
183 { X86::SHR64ri, X86::SHR64mi },
184 { X86::SHR8r1, X86::SHR8m1 },
185 { X86::SHR8rCL, X86::SHR8mCL },
186 { X86::SHR8ri, X86::SHR8mi },
187 { X86::SHRD16rrCL, X86::SHRD16mrCL },
188 { X86::SHRD16rri8, X86::SHRD16mri8 },
189 { X86::SHRD32rrCL, X86::SHRD32mrCL },
190 { X86::SHRD32rri8, X86::SHRD32mri8 },
191 { X86::SHRD64rrCL, X86::SHRD64mrCL },
192 { X86::SHRD64rri8, X86::SHRD64mri8 },
193 { X86::SUB16ri, X86::SUB16mi },
194 { X86::SUB16ri8, X86::SUB16mi8 },
195 { X86::SUB16rr, X86::SUB16mr },
196 { X86::SUB32ri, X86::SUB32mi },
197 { X86::SUB32ri8, X86::SUB32mi8 },
198 { X86::SUB32rr, X86::SUB32mr },
199 { X86::SUB64ri32, X86::SUB64mi32 },
200 { X86::SUB64ri8, X86::SUB64mi8 },
201 { X86::SUB64rr, X86::SUB64mr },
202 { X86::SUB8ri, X86::SUB8mi },
203 { X86::SUB8rr, X86::SUB8mr },
204 { X86::XOR16ri, X86::XOR16mi },
205 { X86::XOR16ri8, X86::XOR16mi8 },
206 { X86::XOR16rr, X86::XOR16mr },
207 { X86::XOR32ri, X86::XOR32mi },
208 { X86::XOR32ri8, X86::XOR32mi8 },
209 { X86::XOR32rr, X86::XOR32mr },
210 { X86::XOR64ri32, X86::XOR64mi32 },
211 { X86::XOR64ri8, X86::XOR64mi8 },
212 { X86::XOR64rr, X86::XOR64mr },
213 { X86::XOR8ri, X86::XOR8mi },
214 { X86::XOR8rr, X86::XOR8mr }
217 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
218 unsigned RegOp = OpTbl2Addr[i][0];
219 unsigned MemOp = OpTbl2Addr[i][1];
220 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
221 std::make_pair(MemOp,0))).second)
222 assert(false && "Duplicated entries?");
223 // Index 0, folded load and store, no alignment requirement.
224 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
225 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
226 std::make_pair(RegOp,
228 AmbEntries.push_back(MemOp);
231 // If the third value is 1, then it's folding either a load or a store.
232 static const unsigned OpTbl0[][4] = {
233 { X86::BT16ri8, X86::BT16mi8, 1, 0 },
234 { X86::BT32ri8, X86::BT32mi8, 1, 0 },
235 { X86::BT64ri8, X86::BT64mi8, 1, 0 },
236 { X86::CALL32r, X86::CALL32m, 1, 0 },
237 { X86::CALL64r, X86::CALL64m, 1, 0 },
238 { X86::CMP16ri, X86::CMP16mi, 1, 0 },
239 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 },
240 { X86::CMP16rr, X86::CMP16mr, 1, 0 },
241 { X86::CMP32ri, X86::CMP32mi, 1, 0 },
242 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 },
243 { X86::CMP32rr, X86::CMP32mr, 1, 0 },
244 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 },
245 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 },
246 { X86::CMP64rr, X86::CMP64mr, 1, 0 },
247 { X86::CMP8ri, X86::CMP8mi, 1, 0 },
248 { X86::CMP8rr, X86::CMP8mr, 1, 0 },
249 { X86::DIV16r, X86::DIV16m, 1, 0 },
250 { X86::DIV32r, X86::DIV32m, 1, 0 },
251 { X86::DIV64r, X86::DIV64m, 1, 0 },
252 { X86::DIV8r, X86::DIV8m, 1, 0 },
253 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
254 { X86::FsMOVAPDrr, X86::MOVSDmr, 0, 0 },
255 { X86::FsMOVAPSrr, X86::MOVSSmr, 0, 0 },
256 { X86::IDIV16r, X86::IDIV16m, 1, 0 },
257 { X86::IDIV32r, X86::IDIV32m, 1, 0 },
258 { X86::IDIV64r, X86::IDIV64m, 1, 0 },
259 { X86::IDIV8r, X86::IDIV8m, 1, 0 },
260 { X86::IMUL16r, X86::IMUL16m, 1, 0 },
261 { X86::IMUL32r, X86::IMUL32m, 1, 0 },
262 { X86::IMUL64r, X86::IMUL64m, 1, 0 },
263 { X86::IMUL8r, X86::IMUL8m, 1, 0 },
264 { X86::JMP32r, X86::JMP32m, 1, 0 },
265 { X86::JMP64r, X86::JMP64m, 1, 0 },
266 { X86::MOV16ri, X86::MOV16mi, 0, 0 },
267 { X86::MOV16rr, X86::MOV16mr, 0, 0 },
268 { X86::MOV32ri, X86::MOV32mi, 0, 0 },
269 { X86::MOV32rr, X86::MOV32mr, 0, 0 },
270 { X86::MOV32rr_TC, X86::MOV32mr_TC, 0, 0 },
271 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 },
272 { X86::MOV64rr, X86::MOV64mr, 0, 0 },
273 { X86::MOV8ri, X86::MOV8mi, 0, 0 },
274 { X86::MOV8rr, X86::MOV8mr, 0, 0 },
275 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 },
276 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 },
277 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 },
278 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 },
279 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
280 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
281 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
282 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 },
283 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 },
284 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 },
285 { X86::MUL16r, X86::MUL16m, 1, 0 },
286 { X86::MUL32r, X86::MUL32m, 1, 0 },
287 { X86::MUL64r, X86::MUL64m, 1, 0 },
288 { X86::MUL8r, X86::MUL8m, 1, 0 },
289 { X86::SETAEr, X86::SETAEm, 0, 0 },
290 { X86::SETAr, X86::SETAm, 0, 0 },
291 { X86::SETBEr, X86::SETBEm, 0, 0 },
292 { X86::SETBr, X86::SETBm, 0, 0 },
293 { X86::SETEr, X86::SETEm, 0, 0 },
294 { X86::SETGEr, X86::SETGEm, 0, 0 },
295 { X86::SETGr, X86::SETGm, 0, 0 },
296 { X86::SETLEr, X86::SETLEm, 0, 0 },
297 { X86::SETLr, X86::SETLm, 0, 0 },
298 { X86::SETNEr, X86::SETNEm, 0, 0 },
299 { X86::SETNOr, X86::SETNOm, 0, 0 },
300 { X86::SETNPr, X86::SETNPm, 0, 0 },
301 { X86::SETNSr, X86::SETNSm, 0, 0 },
302 { X86::SETOr, X86::SETOm, 0, 0 },
303 { X86::SETPr, X86::SETPm, 0, 0 },
304 { X86::SETSr, X86::SETSm, 0, 0 },
305 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 },
306 { X86::TAILJMPr64, X86::TAILJMPm64, 1, 0 },
307 { X86::TEST16ri, X86::TEST16mi, 1, 0 },
308 { X86::TEST32ri, X86::TEST32mi, 1, 0 },
309 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 },
310 { X86::TEST8ri, X86::TEST8mi, 1, 0 }
313 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
314 unsigned RegOp = OpTbl0[i][0];
315 unsigned MemOp = OpTbl0[i][1];
316 unsigned Align = OpTbl0[i][3];
317 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
318 std::make_pair(MemOp,Align))).second)
319 assert(false && "Duplicated entries?");
320 unsigned FoldedLoad = OpTbl0[i][2];
321 // Index 0, folded load or store.
322 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
323 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
324 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
325 std::make_pair(RegOp, AuxInfo))).second)
326 AmbEntries.push_back(MemOp);
329 static const unsigned OpTbl1[][3] = {
330 { X86::CMP16rr, X86::CMP16rm, 0 },
331 { X86::CMP32rr, X86::CMP32rm, 0 },
332 { X86::CMP64rr, X86::CMP64rm, 0 },
333 { X86::CMP8rr, X86::CMP8rm, 0 },
334 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
335 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
336 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
337 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
338 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
339 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
340 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
341 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
342 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
343 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
344 { X86::FsMOVAPDrr, X86::MOVSDrm, 0 },
345 { X86::FsMOVAPSrr, X86::MOVSSrm, 0 },
346 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
347 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
348 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
349 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
350 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
351 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
352 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
353 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
354 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
355 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
356 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 },
357 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 },
358 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 },
359 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 },
360 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 },
361 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
362 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm, 0 },
363 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm, 0 },
364 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
365 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
366 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
367 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
368 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
369 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
370 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 },
371 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, 0 },
372 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, 16 },
373 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, 16 },
374 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
375 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
376 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
377 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
378 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
379 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
380 { X86::MOV16rr, X86::MOV16rm, 0 },
381 { X86::MOV32rr, X86::MOV32rm, 0 },
382 { X86::MOV32rr_TC, X86::MOV32rm_TC, 0 },
383 { X86::MOV64rr, X86::MOV64rm, 0 },
384 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
385 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
386 { X86::MOV8rr, X86::MOV8rm, 0 },
387 { X86::MOVAPDrr, X86::MOVAPDrm, 16 },
388 { X86::MOVAPSrr, X86::MOVAPSrm, 16 },
389 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
390 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
391 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
392 { X86::MOVDQArr, X86::MOVDQArm, 16 },
393 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 },
394 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 },
395 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
396 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
397 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
398 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
399 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
400 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
401 { X86::MOVUPDrr, X86::MOVUPDrm, 16 },
402 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
403 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
404 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
405 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
406 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
407 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
408 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
409 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
410 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
411 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
412 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
413 { X86::PSHUFDri, X86::PSHUFDmi, 16 },
414 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 },
415 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 },
416 { X86::RCPPSr, X86::RCPPSm, 16 },
417 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 },
418 { X86::RSQRTPSr, X86::RSQRTPSm, 16 },
419 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 },
420 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
421 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
422 { X86::SQRTPDr, X86::SQRTPDm, 16 },
423 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 },
424 { X86::SQRTPSr, X86::SQRTPSm, 16 },
425 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 },
426 { X86::SQRTSDr, X86::SQRTSDm, 0 },
427 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
428 { X86::SQRTSSr, X86::SQRTSSm, 0 },
429 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
430 { X86::TEST16rr, X86::TEST16rm, 0 },
431 { X86::TEST32rr, X86::TEST32rm, 0 },
432 { X86::TEST64rr, X86::TEST64rm, 0 },
433 { X86::TEST8rr, X86::TEST8rm, 0 },
434 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
435 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
436 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }
439 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
440 unsigned RegOp = OpTbl1[i][0];
441 unsigned MemOp = OpTbl1[i][1];
442 unsigned Align = OpTbl1[i][2];
443 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
444 std::make_pair(MemOp,Align))).second)
445 assert(false && "Duplicated entries?");
446 // Index 1, folded load
447 unsigned AuxInfo = 1 | (1 << 4);
448 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
449 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
450 std::make_pair(RegOp, AuxInfo))).second)
451 AmbEntries.push_back(MemOp);
454 static const unsigned OpTbl2[][3] = {
455 { X86::ADC32rr, X86::ADC32rm, 0 },
456 { X86::ADC64rr, X86::ADC64rm, 0 },
457 { X86::ADD16rr, X86::ADD16rm, 0 },
458 { X86::ADD32rr, X86::ADD32rm, 0 },
459 { X86::ADD64rr, X86::ADD64rm, 0 },
460 { X86::ADD8rr, X86::ADD8rm, 0 },
461 { X86::ADDPDrr, X86::ADDPDrm, 16 },
462 { X86::ADDPSrr, X86::ADDPSrm, 16 },
463 { X86::ADDSDrr, X86::ADDSDrm, 0 },
464 { X86::ADDSSrr, X86::ADDSSrm, 0 },
465 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 },
466 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 },
467 { X86::AND16rr, X86::AND16rm, 0 },
468 { X86::AND32rr, X86::AND32rm, 0 },
469 { X86::AND64rr, X86::AND64rm, 0 },
470 { X86::AND8rr, X86::AND8rm, 0 },
471 { X86::ANDNPDrr, X86::ANDNPDrm, 16 },
472 { X86::ANDNPSrr, X86::ANDNPSrm, 16 },
473 { X86::ANDPDrr, X86::ANDPDrm, 16 },
474 { X86::ANDPSrr, X86::ANDPSrm, 16 },
475 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
476 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
477 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
478 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
479 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
480 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
481 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
482 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
483 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
484 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
485 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
486 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
487 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
488 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
489 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
490 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
491 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
492 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
493 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
494 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
495 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
496 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
497 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
498 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
499 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
500 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
501 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
502 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
503 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
504 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
505 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
506 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
507 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
508 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
509 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
510 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
511 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
512 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
513 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
514 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
515 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
516 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
517 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
518 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
519 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
520 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
521 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
522 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
523 { X86::CMPPDrri, X86::CMPPDrmi, 16 },
524 { X86::CMPPSrri, X86::CMPPSrmi, 16 },
525 { X86::CMPSDrr, X86::CMPSDrm, 0 },
526 { X86::CMPSSrr, X86::CMPSSrm, 0 },
527 { X86::DIVPDrr, X86::DIVPDrm, 16 },
528 { X86::DIVPSrr, X86::DIVPSrm, 16 },
529 { X86::DIVSDrr, X86::DIVSDrm, 0 },
530 { X86::DIVSSrr, X86::DIVSSrm, 0 },
531 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 },
532 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 },
533 { X86::FsANDPDrr, X86::FsANDPDrm, 16 },
534 { X86::FsANDPSrr, X86::FsANDPSrm, 16 },
535 { X86::FsORPDrr, X86::FsORPDrm, 16 },
536 { X86::FsORPSrr, X86::FsORPSrm, 16 },
537 { X86::FsXORPDrr, X86::FsXORPDrm, 16 },
538 { X86::FsXORPSrr, X86::FsXORPSrm, 16 },
539 { X86::HADDPDrr, X86::HADDPDrm, 16 },
540 { X86::HADDPSrr, X86::HADDPSrm, 16 },
541 { X86::HSUBPDrr, X86::HSUBPDrm, 16 },
542 { X86::HSUBPSrr, X86::HSUBPSrm, 16 },
543 { X86::IMUL16rr, X86::IMUL16rm, 0 },
544 { X86::IMUL32rr, X86::IMUL32rm, 0 },
545 { X86::IMUL64rr, X86::IMUL64rm, 0 },
546 { X86::MAXPDrr, X86::MAXPDrm, 16 },
547 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 },
548 { X86::MAXPSrr, X86::MAXPSrm, 16 },
549 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 },
550 { X86::MAXSDrr, X86::MAXSDrm, 0 },
551 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
552 { X86::MAXSSrr, X86::MAXSSrm, 0 },
553 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
554 { X86::MINPDrr, X86::MINPDrm, 16 },
555 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 },
556 { X86::MINPSrr, X86::MINPSrm, 16 },
557 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 },
558 { X86::MINSDrr, X86::MINSDrm, 0 },
559 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
560 { X86::MINSSrr, X86::MINSSrm, 0 },
561 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
562 { X86::MULPDrr, X86::MULPDrm, 16 },
563 { X86::MULPSrr, X86::MULPSrm, 16 },
564 { X86::MULSDrr, X86::MULSDrm, 0 },
565 { X86::MULSSrr, X86::MULSSrm, 0 },
566 { X86::OR16rr, X86::OR16rm, 0 },
567 { X86::OR32rr, X86::OR32rm, 0 },
568 { X86::OR64rr, X86::OR64rm, 0 },
569 { X86::OR8rr, X86::OR8rm, 0 },
570 { X86::ORPDrr, X86::ORPDrm, 16 },
571 { X86::ORPSrr, X86::ORPSrm, 16 },
572 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 },
573 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 },
574 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 },
575 { X86::PADDBrr, X86::PADDBrm, 16 },
576 { X86::PADDDrr, X86::PADDDrm, 16 },
577 { X86::PADDQrr, X86::PADDQrm, 16 },
578 { X86::PADDSBrr, X86::PADDSBrm, 16 },
579 { X86::PADDSWrr, X86::PADDSWrm, 16 },
580 { X86::PADDWrr, X86::PADDWrm, 16 },
581 { X86::PANDNrr, X86::PANDNrm, 16 },
582 { X86::PANDrr, X86::PANDrm, 16 },
583 { X86::PAVGBrr, X86::PAVGBrm, 16 },
584 { X86::PAVGWrr, X86::PAVGWrm, 16 },
585 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 },
586 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 },
587 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 },
588 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 },
589 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 },
590 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 },
591 { X86::PINSRWrri, X86::PINSRWrmi, 16 },
592 { X86::PMADDWDrr, X86::PMADDWDrm, 16 },
593 { X86::PMAXSWrr, X86::PMAXSWrm, 16 },
594 { X86::PMAXUBrr, X86::PMAXUBrm, 16 },
595 { X86::PMINSWrr, X86::PMINSWrm, 16 },
596 { X86::PMINUBrr, X86::PMINUBrm, 16 },
597 { X86::PMULDQrr, X86::PMULDQrm, 16 },
598 { X86::PMULHUWrr, X86::PMULHUWrm, 16 },
599 { X86::PMULHWrr, X86::PMULHWrm, 16 },
600 { X86::PMULLDrr, X86::PMULLDrm, 16 },
601 { X86::PMULLWrr, X86::PMULLWrm, 16 },
602 { X86::PMULUDQrr, X86::PMULUDQrm, 16 },
603 { X86::PORrr, X86::PORrm, 16 },
604 { X86::PSADBWrr, X86::PSADBWrm, 16 },
605 { X86::PSLLDrr, X86::PSLLDrm, 16 },
606 { X86::PSLLQrr, X86::PSLLQrm, 16 },
607 { X86::PSLLWrr, X86::PSLLWrm, 16 },
608 { X86::PSRADrr, X86::PSRADrm, 16 },
609 { X86::PSRAWrr, X86::PSRAWrm, 16 },
610 { X86::PSRLDrr, X86::PSRLDrm, 16 },
611 { X86::PSRLQrr, X86::PSRLQrm, 16 },
612 { X86::PSRLWrr, X86::PSRLWrm, 16 },
613 { X86::PSUBBrr, X86::PSUBBrm, 16 },
614 { X86::PSUBDrr, X86::PSUBDrm, 16 },
615 { X86::PSUBSBrr, X86::PSUBSBrm, 16 },
616 { X86::PSUBSWrr, X86::PSUBSWrm, 16 },
617 { X86::PSUBWrr, X86::PSUBWrm, 16 },
618 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 },
619 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 },
620 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 },
621 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 },
622 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 },
623 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 },
624 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 },
625 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 },
626 { X86::PXORrr, X86::PXORrm, 16 },
627 { X86::SBB32rr, X86::SBB32rm, 0 },
628 { X86::SBB64rr, X86::SBB64rm, 0 },
629 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 },
630 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 },
631 { X86::SUB16rr, X86::SUB16rm, 0 },
632 { X86::SUB32rr, X86::SUB32rm, 0 },
633 { X86::SUB64rr, X86::SUB64rm, 0 },
634 { X86::SUB8rr, X86::SUB8rm, 0 },
635 { X86::SUBPDrr, X86::SUBPDrm, 16 },
636 { X86::SUBPSrr, X86::SUBPSrm, 16 },
637 { X86::SUBSDrr, X86::SUBSDrm, 0 },
638 { X86::SUBSSrr, X86::SUBSSrm, 0 },
639 // FIXME: TEST*rr -> swapped operand of TEST*mr.
640 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 },
641 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 },
642 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 },
643 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 },
644 { X86::XOR16rr, X86::XOR16rm, 0 },
645 { X86::XOR32rr, X86::XOR32rm, 0 },
646 { X86::XOR64rr, X86::XOR64rm, 0 },
647 { X86::XOR8rr, X86::XOR8rm, 0 },
648 { X86::XORPDrr, X86::XORPDrm, 16 },
649 { X86::XORPSrr, X86::XORPSrm, 16 }
652 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
653 unsigned RegOp = OpTbl2[i][0];
654 unsigned MemOp = OpTbl2[i][1];
655 unsigned Align = OpTbl2[i][2];
656 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
657 std::make_pair(MemOp,Align))).second)
658 assert(false && "Duplicated entries?");
659 // Index 2, folded load
660 unsigned AuxInfo = 2 | (1 << 4);
661 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
662 std::make_pair(RegOp, AuxInfo))).second)
663 AmbEntries.push_back(MemOp);
666 // Remove ambiguous entries.
667 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
670 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
671 unsigned &SrcReg, unsigned &DstReg,
672 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
673 switch (MI.getOpcode()) {
677 case X86::MOV8rr_NOREX:
681 case X86::MOV32rr_TC:
682 case X86::MOV64rr_TC:
684 // FP Stack register class copies
685 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
686 case X86::MOV_Fp3264: case X86::MOV_Fp3280:
687 case X86::MOV_Fp6432: case X86::MOV_Fp8032:
689 // Note that MOVSSrr and MOVSDrr are not considered copies. FR32 and FR64
690 // copies are done with FsMOVAPSrr and FsMOVAPDrr.
692 case X86::FsMOVAPSrr:
693 case X86::FsMOVAPDrr:
697 case X86::MMX_MOVQ64rr:
698 assert(MI.getNumOperands() >= 2 &&
699 MI.getOperand(0).isReg() &&
700 MI.getOperand(1).isReg() &&
701 "invalid register-register move instruction");
702 SrcReg = MI.getOperand(1).getReg();
703 DstReg = MI.getOperand(0).getReg();
704 SrcSubIdx = MI.getOperand(1).getSubReg();
705 DstSubIdx = MI.getOperand(0).getSubReg();
711 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
712 unsigned &SrcReg, unsigned &DstReg,
713 unsigned &SubIdx) const {
714 switch (MI.getOpcode()) {
716 case X86::MOVSX16rr8:
717 case X86::MOVZX16rr8:
718 case X86::MOVSX32rr8:
719 case X86::MOVZX32rr8:
720 case X86::MOVSX64rr8:
721 case X86::MOVZX64rr8:
722 if (!TM.getSubtarget<X86Subtarget>().is64Bit())
723 // It's not always legal to reference the low 8-bit of the larger
724 // register in 32-bit mode.
726 case X86::MOVSX32rr16:
727 case X86::MOVZX32rr16:
728 case X86::MOVSX64rr16:
729 case X86::MOVZX64rr16:
730 case X86::MOVSX64rr32:
731 case X86::MOVZX64rr32: {
732 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
735 SrcReg = MI.getOperand(1).getReg();
736 DstReg = MI.getOperand(0).getReg();
737 switch (MI.getOpcode()) {
741 case X86::MOVSX16rr8:
742 case X86::MOVZX16rr8:
743 case X86::MOVSX32rr8:
744 case X86::MOVZX32rr8:
745 case X86::MOVSX64rr8:
746 case X86::MOVZX64rr8:
747 SubIdx = X86::sub_8bit;
749 case X86::MOVSX32rr16:
750 case X86::MOVZX32rr16:
751 case X86::MOVSX64rr16:
752 case X86::MOVZX64rr16:
753 SubIdx = X86::sub_16bit;
755 case X86::MOVSX64rr32:
756 case X86::MOVZX64rr32:
757 SubIdx = X86::sub_32bit;
766 /// isFrameOperand - Return true and the FrameIndex if the specified
767 /// operand and follow operands form a reference to the stack frame.
768 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
769 int &FrameIndex) const {
770 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
771 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
772 MI->getOperand(Op+1).getImm() == 1 &&
773 MI->getOperand(Op+2).getReg() == 0 &&
774 MI->getOperand(Op+3).getImm() == 0) {
775 FrameIndex = MI->getOperand(Op).getIndex();
781 static bool isFrameLoadOpcode(int Opcode) {
794 case X86::MMX_MOVD64rm:
795 case X86::MMX_MOVQ64rm:
802 static bool isFrameStoreOpcode(int Opcode) {
815 case X86::MMX_MOVD64mr:
816 case X86::MMX_MOVQ64mr:
817 case X86::MMX_MOVNTQmr:
823 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
824 int &FrameIndex) const {
825 if (isFrameLoadOpcode(MI->getOpcode()))
826 if (isFrameOperand(MI, 1, FrameIndex))
827 return MI->getOperand(0).getReg();
831 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
832 int &FrameIndex) const {
833 if (isFrameLoadOpcode(MI->getOpcode())) {
835 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
837 // Check for post-frame index elimination operations
838 const MachineMemOperand *Dummy;
839 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
844 bool X86InstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
845 const MachineMemOperand *&MMO,
846 int &FrameIndex) const {
847 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
848 oe = MI->memoperands_end();
851 if ((*o)->isLoad() && (*o)->getValue())
852 if (const FixedStackPseudoSourceValue *Value =
853 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
854 FrameIndex = Value->getFrameIndex();
862 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
863 int &FrameIndex) const {
864 if (isFrameStoreOpcode(MI->getOpcode()))
865 if (isFrameOperand(MI, 0, FrameIndex))
866 return MI->getOperand(X86AddrNumOperands).getReg();
870 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
871 int &FrameIndex) const {
872 if (isFrameStoreOpcode(MI->getOpcode())) {
874 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
876 // Check for post-frame index elimination operations
877 const MachineMemOperand *Dummy;
878 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
883 bool X86InstrInfo::hasStoreToStackSlot(const MachineInstr *MI,
884 const MachineMemOperand *&MMO,
885 int &FrameIndex) const {
886 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
887 oe = MI->memoperands_end();
890 if ((*o)->isStore() && (*o)->getValue())
891 if (const FixedStackPseudoSourceValue *Value =
892 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
893 FrameIndex = Value->getFrameIndex();
901 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
903 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
904 bool isPICBase = false;
905 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
906 E = MRI.def_end(); I != E; ++I) {
907 MachineInstr *DefMI = I.getOperand().getParent();
908 if (DefMI->getOpcode() != X86::MOVPC32r)
910 assert(!isPICBase && "More than one PIC base?");
917 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
918 AliasAnalysis *AA) const {
919 switch (MI->getOpcode()) {
930 case X86::MOVUPSrm_Int:
933 case X86::MMX_MOVD64rm:
934 case X86::MMX_MOVQ64rm:
935 case X86::FsMOVAPSrm:
936 case X86::FsMOVAPDrm: {
937 // Loads from constant pools are trivially rematerializable.
938 if (MI->getOperand(1).isReg() &&
939 MI->getOperand(2).isImm() &&
940 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
941 MI->isInvariantLoad(AA)) {
942 unsigned BaseReg = MI->getOperand(1).getReg();
943 if (BaseReg == 0 || BaseReg == X86::RIP)
945 // Allow re-materialization of PIC load.
946 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
948 const MachineFunction &MF = *MI->getParent()->getParent();
949 const MachineRegisterInfo &MRI = MF.getRegInfo();
950 bool isPICBase = false;
951 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
952 E = MRI.def_end(); I != E; ++I) {
953 MachineInstr *DefMI = I.getOperand().getParent();
954 if (DefMI->getOpcode() != X86::MOVPC32r)
956 assert(!isPICBase && "More than one PIC base?");
966 if (MI->getOperand(2).isImm() &&
967 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
968 !MI->getOperand(4).isReg()) {
969 // lea fi#, lea GV, etc. are all rematerializable.
970 if (!MI->getOperand(1).isReg())
972 unsigned BaseReg = MI->getOperand(1).getReg();
975 // Allow re-materialization of lea PICBase + x.
976 const MachineFunction &MF = *MI->getParent()->getParent();
977 const MachineRegisterInfo &MRI = MF.getRegInfo();
978 return regIsPICBase(BaseReg, MRI);
984 // All other instructions marked M_REMATERIALIZABLE are always trivially
989 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
990 /// would clobber the EFLAGS condition register. Note the result may be
991 /// conservative. If it cannot definitely determine the safety after visiting
992 /// a few instructions in each direction it assumes it's not safe.
993 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
994 MachineBasicBlock::iterator I) {
995 MachineBasicBlock::iterator E = MBB.end();
997 // It's always safe to clobber EFLAGS at the end of a block.
1001 // For compile time consideration, if we are not able to determine the
1002 // safety after visiting 4 instructions in each direction, we will assume
1004 MachineBasicBlock::iterator Iter = I;
1005 for (unsigned i = 0; i < 4; ++i) {
1006 bool SeenDef = false;
1007 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1008 MachineOperand &MO = Iter->getOperand(j);
1011 if (MO.getReg() == X86::EFLAGS) {
1019 // This instruction defines EFLAGS, no need to look any further.
1022 // Skip over DBG_VALUE.
1023 while (Iter != E && Iter->isDebugValue())
1026 // If we make it to the end of the block, it's safe to clobber EFLAGS.
1031 MachineBasicBlock::iterator B = MBB.begin();
1033 for (unsigned i = 0; i < 4; ++i) {
1034 // If we make it to the beginning of the block, it's safe to clobber
1035 // EFLAGS iff EFLAGS is not live-in.
1037 return !MBB.isLiveIn(X86::EFLAGS);
1040 // Skip over DBG_VALUE.
1041 while (Iter != B && Iter->isDebugValue())
1044 bool SawKill = false;
1045 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1046 MachineOperand &MO = Iter->getOperand(j);
1047 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1048 if (MO.isDef()) return MO.isDead();
1049 if (MO.isKill()) SawKill = true;
1054 // This instruction kills EFLAGS and doesn't redefine it, so
1055 // there's no need to look further.
1059 // Conservative answer.
1063 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1064 MachineBasicBlock::iterator I,
1065 unsigned DestReg, unsigned SubIdx,
1066 const MachineInstr *Orig,
1067 const TargetRegisterInfo &TRI) const {
1068 DebugLoc DL = Orig->getDebugLoc();
1070 // MOV32r0 etc. are implemented with xor which clobbers condition code.
1071 // Re-materialize them as movri instructions to avoid side effects.
1073 unsigned Opc = Orig->getOpcode();
1079 case X86::MOV64r0: {
1080 if (!isSafeToClobberEFLAGS(MBB, I)) {
1083 case X86::MOV8r0: Opc = X86::MOV8ri; break;
1084 case X86::MOV16r0: Opc = X86::MOV16ri; break;
1085 case X86::MOV32r0: Opc = X86::MOV32ri; break;
1086 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
1095 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1098 BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0);
1101 MachineInstr *NewMI = prior(I);
1102 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1105 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1106 /// is not marked dead.
1107 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1108 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1109 MachineOperand &MO = MI->getOperand(i);
1110 if (MO.isReg() && MO.isDef() &&
1111 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1118 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1119 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1120 /// to a 32-bit superregister and then truncating back down to a 16-bit
1123 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1124 MachineFunction::iterator &MFI,
1125 MachineBasicBlock::iterator &MBBI,
1126 LiveVariables *LV) const {
1127 MachineInstr *MI = MBBI;
1128 unsigned Dest = MI->getOperand(0).getReg();
1129 unsigned Src = MI->getOperand(1).getReg();
1130 bool isDead = MI->getOperand(0).isDead();
1131 bool isKill = MI->getOperand(1).isKill();
1133 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1134 ? X86::LEA64_32r : X86::LEA32r;
1135 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1136 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1137 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1139 // Build and insert into an implicit UNDEF value. This is OK because
1140 // well be shifting and then extracting the lower 16-bits.
1141 // This has the potential to cause partial register stall. e.g.
1142 // movw (%rbp,%rcx,2), %dx
1143 // leal -65(%rdx), %esi
1144 // But testing has shown this *does* help performance in 64-bit mode (at
1145 // least on modern x86 machines).
1146 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1147 MachineInstr *InsMI =
1148 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
1150 .addReg(Src, getKillRegState(isKill))
1151 .addImm(X86::sub_16bit);
1153 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1154 get(Opc), leaOutReg);
1157 llvm_unreachable(0);
1159 case X86::SHL16ri: {
1160 unsigned ShAmt = MI->getOperand(2).getImm();
1161 MIB.addReg(0).addImm(1 << ShAmt)
1162 .addReg(leaInReg, RegState::Kill).addImm(0);
1166 case X86::INC64_16r:
1167 addLeaRegOffset(MIB, leaInReg, true, 1);
1170 case X86::DEC64_16r:
1171 addLeaRegOffset(MIB, leaInReg, true, -1);
1175 addLeaRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1177 case X86::ADD16rr: {
1178 unsigned Src2 = MI->getOperand(2).getReg();
1179 bool isKill2 = MI->getOperand(2).isKill();
1180 unsigned leaInReg2 = 0;
1181 MachineInstr *InsMI2 = 0;
1183 // ADD16rr %reg1028<kill>, %reg1028
1184 // just a single insert_subreg.
1185 addRegReg(MIB, leaInReg, true, leaInReg, false);
1187 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1188 // Build and insert into an implicit UNDEF value. This is OK because
1189 // well be shifting and then extracting the lower 16-bits.
1190 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
1192 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg2)
1194 .addReg(Src2, getKillRegState(isKill2))
1195 .addImm(X86::sub_16bit);
1196 addRegReg(MIB, leaInReg, true, leaInReg2, true);
1198 if (LV && isKill2 && InsMI2)
1199 LV->replaceKillInstruction(Src2, MI, InsMI2);
1204 MachineInstr *NewMI = MIB;
1205 MachineInstr *ExtMI =
1206 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
1207 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1208 .addReg(leaOutReg, RegState::Kill)
1209 .addImm(X86::sub_16bit);
1212 // Update live variables
1213 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1214 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1216 LV->replaceKillInstruction(Src, MI, InsMI);
1218 LV->replaceKillInstruction(Dest, MI, ExtMI);
1224 /// convertToThreeAddress - This method must be implemented by targets that
1225 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1226 /// may be able to convert a two-address instruction into a true
1227 /// three-address instruction on demand. This allows the X86 target (for
1228 /// example) to convert ADD and SHL instructions into LEA instructions if they
1229 /// would require register copies due to two-addressness.
1231 /// This method returns a null pointer if the transformation cannot be
1232 /// performed, otherwise it returns the new instruction.
1235 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1236 MachineBasicBlock::iterator &MBBI,
1237 LiveVariables *LV) const {
1238 MachineInstr *MI = MBBI;
1239 MachineFunction &MF = *MI->getParent()->getParent();
1240 // All instructions input are two-addr instructions. Get the known operands.
1241 unsigned Dest = MI->getOperand(0).getReg();
1242 unsigned Src = MI->getOperand(1).getReg();
1243 bool isDead = MI->getOperand(0).isDead();
1244 bool isKill = MI->getOperand(1).isKill();
1246 MachineInstr *NewMI = NULL;
1247 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1248 // we have better subtarget support, enable the 16-bit LEA generation here.
1249 // 16-bit LEA is also slow on Core2.
1250 bool DisableLEA16 = true;
1251 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1253 unsigned MIOpc = MI->getOpcode();
1255 case X86::SHUFPSrri: {
1256 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1257 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1259 unsigned B = MI->getOperand(1).getReg();
1260 unsigned C = MI->getOperand(2).getReg();
1261 if (B != C) return 0;
1262 unsigned A = MI->getOperand(0).getReg();
1263 unsigned M = MI->getOperand(3).getImm();
1264 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1265 .addReg(A, RegState::Define | getDeadRegState(isDead))
1266 .addReg(B, getKillRegState(isKill)).addImm(M);
1269 case X86::SHL64ri: {
1270 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1271 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1272 // the flags produced by a shift yet, so this is safe.
1273 unsigned ShAmt = MI->getOperand(2).getImm();
1274 if (ShAmt == 0 || ShAmt >= 4) return 0;
1276 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1277 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1278 .addReg(0).addImm(1 << ShAmt)
1279 .addReg(Src, getKillRegState(isKill))
1283 case X86::SHL32ri: {
1284 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1285 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1286 // the flags produced by a shift yet, so this is safe.
1287 unsigned ShAmt = MI->getOperand(2).getImm();
1288 if (ShAmt == 0 || ShAmt >= 4) return 0;
1290 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1291 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1292 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1293 .addReg(0).addImm(1 << ShAmt)
1294 .addReg(Src, getKillRegState(isKill)).addImm(0);
1297 case X86::SHL16ri: {
1298 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1299 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1300 // the flags produced by a shift yet, so this is safe.
1301 unsigned ShAmt = MI->getOperand(2).getImm();
1302 if (ShAmt == 0 || ShAmt >= 4) return 0;
1305 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1306 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1307 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1308 .addReg(0).addImm(1 << ShAmt)
1309 .addReg(Src, getKillRegState(isKill))
1314 // The following opcodes also sets the condition code register(s). Only
1315 // convert them to equivalent lea if the condition code register def's
1317 if (hasLiveCondCodeDef(MI))
1324 case X86::INC64_32r: {
1325 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1326 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1327 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1328 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1329 .addReg(Dest, RegState::Define |
1330 getDeadRegState(isDead)),
1335 case X86::INC64_16r:
1337 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1338 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1339 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1340 .addReg(Dest, RegState::Define |
1341 getDeadRegState(isDead)),
1346 case X86::DEC64_32r: {
1347 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1348 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1349 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1350 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1351 .addReg(Dest, RegState::Define |
1352 getDeadRegState(isDead)),
1357 case X86::DEC64_16r:
1359 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1360 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1361 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1362 .addReg(Dest, RegState::Define |
1363 getDeadRegState(isDead)),
1367 case X86::ADD32rr: {
1368 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1369 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1370 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1371 unsigned Src2 = MI->getOperand(2).getReg();
1372 bool isKill2 = MI->getOperand(2).isKill();
1373 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1374 .addReg(Dest, RegState::Define |
1375 getDeadRegState(isDead)),
1376 Src, isKill, Src2, isKill2);
1378 LV->replaceKillInstruction(Src2, MI, NewMI);
1381 case X86::ADD16rr: {
1383 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1384 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1385 unsigned Src2 = MI->getOperand(2).getReg();
1386 bool isKill2 = MI->getOperand(2).isKill();
1387 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1388 .addReg(Dest, RegState::Define |
1389 getDeadRegState(isDead)),
1390 Src, isKill, Src2, isKill2);
1392 LV->replaceKillInstruction(Src2, MI, NewMI);
1395 case X86::ADD64ri32:
1397 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1398 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1399 .addReg(Dest, RegState::Define |
1400 getDeadRegState(isDead)),
1401 Src, isKill, MI->getOperand(2).getImm());
1404 case X86::ADD32ri8: {
1405 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1406 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1407 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1408 .addReg(Dest, RegState::Define |
1409 getDeadRegState(isDead)),
1410 Src, isKill, MI->getOperand(2).getImm());
1416 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1417 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1418 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1419 .addReg(Dest, RegState::Define |
1420 getDeadRegState(isDead)),
1421 Src, isKill, MI->getOperand(2).getImm());
1427 if (!NewMI) return 0;
1429 if (LV) { // Update live variables
1431 LV->replaceKillInstruction(Src, MI, NewMI);
1433 LV->replaceKillInstruction(Dest, MI, NewMI);
1436 MFI->insert(MBBI, NewMI); // Insert the new inst
1440 /// commuteInstruction - We have a few instructions that must be hacked on to
1444 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1445 switch (MI->getOpcode()) {
1446 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1447 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1448 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1449 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1450 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1451 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1454 switch (MI->getOpcode()) {
1455 default: llvm_unreachable("Unreachable!");
1456 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1457 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1458 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1459 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1460 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1461 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1463 unsigned Amt = MI->getOperand(3).getImm();
1465 MachineFunction &MF = *MI->getParent()->getParent();
1466 MI = MF.CloneMachineInstr(MI);
1469 MI->setDesc(get(Opc));
1470 MI->getOperand(3).setImm(Size-Amt);
1471 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1473 case X86::CMOVB16rr:
1474 case X86::CMOVB32rr:
1475 case X86::CMOVB64rr:
1476 case X86::CMOVAE16rr:
1477 case X86::CMOVAE32rr:
1478 case X86::CMOVAE64rr:
1479 case X86::CMOVE16rr:
1480 case X86::CMOVE32rr:
1481 case X86::CMOVE64rr:
1482 case X86::CMOVNE16rr:
1483 case X86::CMOVNE32rr:
1484 case X86::CMOVNE64rr:
1485 case X86::CMOVBE16rr:
1486 case X86::CMOVBE32rr:
1487 case X86::CMOVBE64rr:
1488 case X86::CMOVA16rr:
1489 case X86::CMOVA32rr:
1490 case X86::CMOVA64rr:
1491 case X86::CMOVL16rr:
1492 case X86::CMOVL32rr:
1493 case X86::CMOVL64rr:
1494 case X86::CMOVGE16rr:
1495 case X86::CMOVGE32rr:
1496 case X86::CMOVGE64rr:
1497 case X86::CMOVLE16rr:
1498 case X86::CMOVLE32rr:
1499 case X86::CMOVLE64rr:
1500 case X86::CMOVG16rr:
1501 case X86::CMOVG32rr:
1502 case X86::CMOVG64rr:
1503 case X86::CMOVS16rr:
1504 case X86::CMOVS32rr:
1505 case X86::CMOVS64rr:
1506 case X86::CMOVNS16rr:
1507 case X86::CMOVNS32rr:
1508 case X86::CMOVNS64rr:
1509 case X86::CMOVP16rr:
1510 case X86::CMOVP32rr:
1511 case X86::CMOVP64rr:
1512 case X86::CMOVNP16rr:
1513 case X86::CMOVNP32rr:
1514 case X86::CMOVNP64rr:
1515 case X86::CMOVO16rr:
1516 case X86::CMOVO32rr:
1517 case X86::CMOVO64rr:
1518 case X86::CMOVNO16rr:
1519 case X86::CMOVNO32rr:
1520 case X86::CMOVNO64rr: {
1522 switch (MI->getOpcode()) {
1524 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1525 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1526 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1527 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1528 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1529 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1530 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1531 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1532 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1533 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1534 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1535 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1536 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1537 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1538 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1539 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1540 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1541 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1542 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1543 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1544 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1545 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1546 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1547 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1548 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1549 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1550 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1551 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1552 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1553 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1554 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1555 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1556 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1557 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1558 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1559 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1560 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1561 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1562 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1563 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1564 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1565 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1566 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1567 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1568 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1569 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1570 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1571 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1574 MachineFunction &MF = *MI->getParent()->getParent();
1575 MI = MF.CloneMachineInstr(MI);
1578 MI->setDesc(get(Opc));
1579 // Fallthrough intended.
1582 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1586 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1588 default: return X86::COND_INVALID;
1589 case X86::JE_4: return X86::COND_E;
1590 case X86::JNE_4: return X86::COND_NE;
1591 case X86::JL_4: return X86::COND_L;
1592 case X86::JLE_4: return X86::COND_LE;
1593 case X86::JG_4: return X86::COND_G;
1594 case X86::JGE_4: return X86::COND_GE;
1595 case X86::JB_4: return X86::COND_B;
1596 case X86::JBE_4: return X86::COND_BE;
1597 case X86::JA_4: return X86::COND_A;
1598 case X86::JAE_4: return X86::COND_AE;
1599 case X86::JS_4: return X86::COND_S;
1600 case X86::JNS_4: return X86::COND_NS;
1601 case X86::JP_4: return X86::COND_P;
1602 case X86::JNP_4: return X86::COND_NP;
1603 case X86::JO_4: return X86::COND_O;
1604 case X86::JNO_4: return X86::COND_NO;
1608 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1610 default: llvm_unreachable("Illegal condition code!");
1611 case X86::COND_E: return X86::JE_4;
1612 case X86::COND_NE: return X86::JNE_4;
1613 case X86::COND_L: return X86::JL_4;
1614 case X86::COND_LE: return X86::JLE_4;
1615 case X86::COND_G: return X86::JG_4;
1616 case X86::COND_GE: return X86::JGE_4;
1617 case X86::COND_B: return X86::JB_4;
1618 case X86::COND_BE: return X86::JBE_4;
1619 case X86::COND_A: return X86::JA_4;
1620 case X86::COND_AE: return X86::JAE_4;
1621 case X86::COND_S: return X86::JS_4;
1622 case X86::COND_NS: return X86::JNS_4;
1623 case X86::COND_P: return X86::JP_4;
1624 case X86::COND_NP: return X86::JNP_4;
1625 case X86::COND_O: return X86::JO_4;
1626 case X86::COND_NO: return X86::JNO_4;
1630 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1631 /// e.g. turning COND_E to COND_NE.
1632 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1634 default: llvm_unreachable("Illegal condition code!");
1635 case X86::COND_E: return X86::COND_NE;
1636 case X86::COND_NE: return X86::COND_E;
1637 case X86::COND_L: return X86::COND_GE;
1638 case X86::COND_LE: return X86::COND_G;
1639 case X86::COND_G: return X86::COND_LE;
1640 case X86::COND_GE: return X86::COND_L;
1641 case X86::COND_B: return X86::COND_AE;
1642 case X86::COND_BE: return X86::COND_A;
1643 case X86::COND_A: return X86::COND_BE;
1644 case X86::COND_AE: return X86::COND_B;
1645 case X86::COND_S: return X86::COND_NS;
1646 case X86::COND_NS: return X86::COND_S;
1647 case X86::COND_P: return X86::COND_NP;
1648 case X86::COND_NP: return X86::COND_P;
1649 case X86::COND_O: return X86::COND_NO;
1650 case X86::COND_NO: return X86::COND_O;
1654 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1655 const TargetInstrDesc &TID = MI->getDesc();
1656 if (!TID.isTerminator()) return false;
1658 // Conditional branch is a special case.
1659 if (TID.isBranch() && !TID.isBarrier())
1661 if (!TID.isPredicable())
1663 return !isPredicated(MI);
1666 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1667 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1668 const X86InstrInfo &TII) {
1669 if (MI->getOpcode() == X86::FP_REG_KILL)
1671 return TII.isUnpredicatedTerminator(MI);
1674 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1675 MachineBasicBlock *&TBB,
1676 MachineBasicBlock *&FBB,
1677 SmallVectorImpl<MachineOperand> &Cond,
1678 bool AllowModify) const {
1679 // Start from the bottom of the block and work up, examining the
1680 // terminator instructions.
1681 MachineBasicBlock::iterator I = MBB.end();
1682 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
1683 while (I != MBB.begin()) {
1685 if (I->isDebugValue())
1688 // Working from the bottom, when we see a non-terminator instruction, we're
1690 if (!isBrAnalysisUnpredicatedTerminator(I, *this))
1693 // A terminator that isn't a branch can't easily be handled by this
1695 if (!I->getDesc().isBranch())
1698 // Handle unconditional branches.
1699 if (I->getOpcode() == X86::JMP_4) {
1703 TBB = I->getOperand(0).getMBB();
1707 // If the block has any instructions after a JMP, delete them.
1708 while (llvm::next(I) != MBB.end())
1709 llvm::next(I)->eraseFromParent();
1714 // Delete the JMP if it's equivalent to a fall-through.
1715 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1717 I->eraseFromParent();
1719 UnCondBrIter = MBB.end();
1723 // TBB is used to indicate the unconditional destination.
1724 TBB = I->getOperand(0).getMBB();
1728 // Handle conditional branches.
1729 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1730 if (BranchCode == X86::COND_INVALID)
1731 return true; // Can't handle indirect branch.
1733 // Working from the bottom, handle the first conditional branch.
1735 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
1736 if (AllowModify && UnCondBrIter != MBB.end() &&
1737 MBB.isLayoutSuccessor(TargetBB)) {
1738 // If we can modify the code and it ends in something like:
1746 // Then we can change this to:
1753 // Which is a bit more efficient.
1754 // We conditionally jump to the fall-through block.
1755 BranchCode = GetOppositeBranchCondition(BranchCode);
1756 unsigned JNCC = GetCondBranchFromCond(BranchCode);
1757 MachineBasicBlock::iterator OldInst = I;
1759 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
1760 .addMBB(UnCondBrIter->getOperand(0).getMBB());
1761 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
1763 MBB.addSuccessor(TargetBB);
1765 OldInst->eraseFromParent();
1766 UnCondBrIter->eraseFromParent();
1768 // Restart the analysis.
1769 UnCondBrIter = MBB.end();
1775 TBB = I->getOperand(0).getMBB();
1776 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1780 // Handle subsequent conditional branches. Only handle the case where all
1781 // conditional branches branch to the same destination and their condition
1782 // opcodes fit one of the special multi-branch idioms.
1783 assert(Cond.size() == 1);
1786 // Only handle the case where all conditional branches branch to the same
1788 if (TBB != I->getOperand(0).getMBB())
1791 // If the conditions are the same, we can leave them alone.
1792 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1793 if (OldBranchCode == BranchCode)
1796 // If they differ, see if they fit one of the known patterns. Theoretically,
1797 // we could handle more patterns here, but we shouldn't expect to see them
1798 // if instruction selection has done a reasonable job.
1799 if ((OldBranchCode == X86::COND_NP &&
1800 BranchCode == X86::COND_E) ||
1801 (OldBranchCode == X86::COND_E &&
1802 BranchCode == X86::COND_NP))
1803 BranchCode = X86::COND_NP_OR_E;
1804 else if ((OldBranchCode == X86::COND_P &&
1805 BranchCode == X86::COND_NE) ||
1806 (OldBranchCode == X86::COND_NE &&
1807 BranchCode == X86::COND_P))
1808 BranchCode = X86::COND_NE_OR_P;
1812 // Update the MachineOperand.
1813 Cond[0].setImm(BranchCode);
1819 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1820 MachineBasicBlock::iterator I = MBB.end();
1823 while (I != MBB.begin()) {
1825 if (I->isDebugValue())
1827 if (I->getOpcode() != X86::JMP_4 &&
1828 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1830 // Remove the branch.
1831 I->eraseFromParent();
1840 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1841 MachineBasicBlock *FBB,
1842 const SmallVectorImpl<MachineOperand> &Cond,
1843 DebugLoc DL) const {
1844 // Shouldn't be a fall through.
1845 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1846 assert((Cond.size() == 1 || Cond.size() == 0) &&
1847 "X86 branch conditions have one component!");
1850 // Unconditional branch?
1851 assert(!FBB && "Unconditional branch with multiple successors!");
1852 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
1856 // Conditional branch.
1858 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1860 case X86::COND_NP_OR_E:
1861 // Synthesize NP_OR_E with two branches.
1862 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
1864 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
1867 case X86::COND_NE_OR_P:
1868 // Synthesize NE_OR_P with two branches.
1869 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
1871 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
1875 unsigned Opc = GetCondBranchFromCond(CC);
1876 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
1881 // Two-way Conditional branch. Insert the second branch.
1882 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
1888 /// isHReg - Test if the given register is a physical h register.
1889 static bool isHReg(unsigned Reg) {
1890 return X86::GR8_ABCD_HRegClass.contains(Reg);
1893 bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1894 MachineBasicBlock::iterator MI,
1895 unsigned DestReg, unsigned SrcReg,
1896 const TargetRegisterClass *DestRC,
1897 const TargetRegisterClass *SrcRC,
1898 DebugLoc DL) const {
1900 // Determine if DstRC and SrcRC have a common superclass in common.
1901 const TargetRegisterClass *CommonRC = DestRC;
1902 if (DestRC == SrcRC)
1903 /* Source and destination have the same register class. */;
1904 else if (CommonRC->hasSuperClass(SrcRC))
1906 else if (!DestRC->hasSubClass(SrcRC)) {
1907 // Neither of GR64_NOREX or GR64_NOSP is a superclass of the other,
1908 // but we want to copy them as GR64. Similarly, for GR32_NOREX and
1909 // GR32_NOSP, copy as GR32.
1910 if (SrcRC->hasSuperClass(&X86::GR64RegClass) &&
1911 DestRC->hasSuperClass(&X86::GR64RegClass))
1912 CommonRC = &X86::GR64RegClass;
1913 else if (SrcRC->hasSuperClass(&X86::GR32RegClass) &&
1914 DestRC->hasSuperClass(&X86::GR32RegClass))
1915 CommonRC = &X86::GR32RegClass;
1916 else if (SrcRC->hasSuperClass(&X86::GR8RegClass) &&
1917 DestRC->hasSuperClass(&X86::GR8RegClass))
1918 CommonRC = &X86::GR8RegClass;
1925 if (CommonRC == &X86::GR64RegClass || CommonRC == &X86::GR64_NOSPRegClass) {
1927 } else if (CommonRC == &X86::GR32RegClass ||
1928 CommonRC == &X86::GR32_NOSPRegClass) {
1930 } else if (CommonRC == &X86::GR16RegClass) {
1932 } else if (CommonRC == &X86::GR8RegClass) {
1933 // Copying to or from a physical H register on x86-64 requires a NOREX
1934 // move. Otherwise use a normal move.
1935 if ((isHReg(DestReg) || isHReg(SrcReg) ||
1936 SrcRC == &X86::GR8_ABCD_HRegClass ||
1937 DestRC == &X86::GR8_ABCD_HRegClass) &&
1938 TM.getSubtarget<X86Subtarget>().is64Bit())
1939 Opc = X86::MOV8rr_NOREX;
1942 } else if (CommonRC == &X86::GR64_ABCDRegClass) {
1944 } else if (CommonRC == &X86::GR32_ABCDRegClass) {
1946 } else if (CommonRC == &X86::GR16_ABCDRegClass) {
1948 } else if (CommonRC == &X86::GR8_ABCD_LRegClass) {
1950 } else if (CommonRC == &X86::GR8_ABCD_HRegClass) {
1951 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1952 Opc = X86::MOV8rr_NOREX;
1955 } else if (CommonRC == &X86::GR64_NOREXRegClass ||
1956 CommonRC == &X86::GR64_NOREX_NOSPRegClass) {
1958 } else if (CommonRC == &X86::GR32_NOREXRegClass) {
1960 } else if (CommonRC == &X86::GR16_NOREXRegClass) {
1962 } else if (CommonRC == &X86::GR8_NOREXRegClass) {
1964 } else if (CommonRC == &X86::GR64_TCRegClass) {
1965 Opc = X86::MOV64rr_TC;
1966 } else if (CommonRC == &X86::GR32_TCRegClass) {
1967 Opc = X86::MOV32rr_TC;
1968 } else if (CommonRC == &X86::RFP32RegClass) {
1969 Opc = X86::MOV_Fp3232;
1970 } else if (CommonRC == &X86::RFP64RegClass || CommonRC == &X86::RSTRegClass) {
1971 Opc = X86::MOV_Fp6464;
1972 } else if (CommonRC == &X86::RFP80RegClass) {
1973 Opc = X86::MOV_Fp8080;
1974 } else if (CommonRC == &X86::FR32RegClass) {
1975 Opc = X86::FsMOVAPSrr;
1976 } else if (CommonRC == &X86::FR64RegClass) {
1977 Opc = X86::FsMOVAPDrr;
1978 } else if (CommonRC == &X86::VR128RegClass) {
1979 Opc = X86::MOVAPSrr;
1980 } else if (CommonRC == &X86::VR64RegClass) {
1981 Opc = X86::MMX_MOVQ64rr;
1985 BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg);
1989 // Moving EFLAGS to / from another register requires a push and a pop.
1990 if (SrcRC == &X86::CCRRegClass) {
1991 if (SrcReg != X86::EFLAGS)
1993 if (DestRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1994 BuildMI(MBB, MI, DL, get(X86::PUSHF64));
1995 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1997 } else if (DestRC == &X86::GR32RegClass ||
1998 DestRC == &X86::GR32_NOSPRegClass) {
1999 BuildMI(MBB, MI, DL, get(X86::PUSHF32));
2000 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
2003 } else if (DestRC == &X86::CCRRegClass) {
2004 if (DestReg != X86::EFLAGS)
2006 if (SrcRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
2007 BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
2008 BuildMI(MBB, MI, DL, get(X86::POPF64));
2010 } else if (SrcRC == &X86::GR32RegClass ||
2011 DestRC == &X86::GR32_NOSPRegClass) {
2012 BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
2013 BuildMI(MBB, MI, DL, get(X86::POPF32));
2018 // Moving from ST(0) turns into FpGET_ST0_32 etc.
2019 if (SrcRC == &X86::RSTRegClass) {
2020 // Copying from ST(0)/ST(1).
2021 if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
2022 // Can only copy from ST(0)/ST(1) right now
2024 bool isST0 = SrcReg == X86::ST0;
2026 if (DestRC == &X86::RFP32RegClass)
2027 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
2028 else if (DestRC == &X86::RFP64RegClass)
2029 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
2031 if (DestRC != &X86::RFP80RegClass)
2033 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
2035 BuildMI(MBB, MI, DL, get(Opc), DestReg);
2039 // Moving to ST(0) turns into FpSET_ST0_32 etc.
2040 if (DestRC == &X86::RSTRegClass) {
2041 // Copying to ST(0) / ST(1).
2042 if (DestReg != X86::ST0 && DestReg != X86::ST1)
2043 // Can only copy to TOS right now
2045 bool isST0 = DestReg == X86::ST0;
2047 if (SrcRC == &X86::RFP32RegClass)
2048 Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32;
2049 else if (SrcRC == &X86::RFP64RegClass)
2050 Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64;
2052 if (SrcRC != &X86::RFP80RegClass)
2054 Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80;
2056 BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg);
2060 // Not yet supported!
2064 static unsigned getLoadStoreRegOpcode(unsigned Reg,
2065 const TargetRegisterClass *RC,
2066 bool isStackAligned,
2067 const TargetMachine &TM,
2069 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
2070 return load ? X86::MOV64rm : X86::MOV64mr;
2071 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
2072 return load ? X86::MOV32rm : X86::MOV32mr;
2073 } else if (RC == &X86::GR16RegClass) {
2074 return load ? X86::MOV16rm : X86::MOV16mr;
2075 } else if (RC == &X86::GR8RegClass) {
2076 // Copying to or from a physical H register on x86-64 requires a NOREX
2077 // move. Otherwise use a normal move.
2079 TM.getSubtarget<X86Subtarget>().is64Bit())
2080 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2082 return load ? X86::MOV8rm : X86::MOV8mr;
2083 } else if (RC == &X86::GR64_ABCDRegClass) {
2084 return load ? X86::MOV64rm : X86::MOV64mr;
2085 } else if (RC == &X86::GR32_ABCDRegClass) {
2086 return load ? X86::MOV32rm : X86::MOV32mr;
2087 } else if (RC == &X86::GR16_ABCDRegClass) {
2088 return load ? X86::MOV16rm : X86::MOV16mr;
2089 } else if (RC == &X86::GR8_ABCD_LRegClass) {
2090 return load ? X86::MOV8rm :X86::MOV8mr;
2091 } else if (RC == &X86::GR8_ABCD_HRegClass) {
2092 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2093 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2095 return load ? X86::MOV8rm : X86::MOV8mr;
2096 } else if (RC == &X86::GR64_NOREXRegClass ||
2097 RC == &X86::GR64_NOREX_NOSPRegClass) {
2098 return load ? X86::MOV64rm : X86::MOV64mr;
2099 } else if (RC == &X86::GR32_NOREXRegClass) {
2100 return load ? X86::MOV32rm : X86::MOV32mr;
2101 } else if (RC == &X86::GR16_NOREXRegClass) {
2102 return load ? X86::MOV16rm : X86::MOV16mr;
2103 } else if (RC == &X86::GR8_NOREXRegClass) {
2104 return load ? X86::MOV8rm : X86::MOV8mr;
2105 } else if (RC == &X86::GR64_TCRegClass) {
2106 return load ? X86::MOV64rm_TC : X86::MOV64mr_TC;
2107 } else if (RC == &X86::GR32_TCRegClass) {
2108 return load ? X86::MOV32rm_TC : X86::MOV32mr_TC;
2109 } else if (RC == &X86::RFP80RegClass) {
2110 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
2111 } else if (RC == &X86::RFP64RegClass) {
2112 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
2113 } else if (RC == &X86::RFP32RegClass) {
2114 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
2115 } else if (RC == &X86::FR32RegClass) {
2116 return load ? X86::MOVSSrm : X86::MOVSSmr;
2117 } else if (RC == &X86::FR64RegClass) {
2118 return load ? X86::MOVSDrm : X86::MOVSDmr;
2119 } else if (RC == &X86::VR128RegClass) {
2120 // If stack is realigned we can use aligned stores.
2122 return load ? X86::MOVAPSrm : X86::MOVAPSmr;
2124 return load ? X86::MOVUPSrm : X86::MOVUPSmr;
2125 } else if (RC == &X86::VR64RegClass) {
2126 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
2128 llvm_unreachable("Unknown regclass");
2132 static unsigned getStoreRegOpcode(unsigned SrcReg,
2133 const TargetRegisterClass *RC,
2134 bool isStackAligned,
2135 TargetMachine &TM) {
2136 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
2140 static unsigned getLoadRegOpcode(unsigned DestReg,
2141 const TargetRegisterClass *RC,
2142 bool isStackAligned,
2143 const TargetMachine &TM) {
2144 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
2147 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2148 MachineBasicBlock::iterator MI,
2149 unsigned SrcReg, bool isKill, int FrameIdx,
2150 const TargetRegisterClass *RC,
2151 const TargetRegisterInfo *TRI) const {
2152 const MachineFunction &MF = *MBB.getParent();
2153 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
2154 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2155 DebugLoc DL = MBB.findDebugLoc(MI);
2156 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
2157 .addReg(SrcReg, getKillRegState(isKill));
2160 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2162 SmallVectorImpl<MachineOperand> &Addr,
2163 const TargetRegisterClass *RC,
2164 MachineInstr::mmo_iterator MMOBegin,
2165 MachineInstr::mmo_iterator MMOEnd,
2166 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2167 bool isAligned = *MMOBegin && (*MMOBegin)->getAlignment() >= 16;
2168 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2170 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2171 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2172 MIB.addOperand(Addr[i]);
2173 MIB.addReg(SrcReg, getKillRegState(isKill));
2174 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2175 NewMIs.push_back(MIB);
2179 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2180 MachineBasicBlock::iterator MI,
2181 unsigned DestReg, int FrameIdx,
2182 const TargetRegisterClass *RC,
2183 const TargetRegisterInfo *TRI) const {
2184 const MachineFunction &MF = *MBB.getParent();
2185 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
2186 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2187 DebugLoc DL = MBB.findDebugLoc(MI);
2188 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2191 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2192 SmallVectorImpl<MachineOperand> &Addr,
2193 const TargetRegisterClass *RC,
2194 MachineInstr::mmo_iterator MMOBegin,
2195 MachineInstr::mmo_iterator MMOEnd,
2196 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2197 bool isAligned = *MMOBegin && (*MMOBegin)->getAlignment() >= 16;
2198 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2200 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2201 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2202 MIB.addOperand(Addr[i]);
2203 (*MIB).setMemRefs(MMOBegin, MMOEnd);
2204 NewMIs.push_back(MIB);
2207 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
2208 MachineBasicBlock::iterator MI,
2209 const std::vector<CalleeSavedInfo> &CSI,
2210 const TargetRegisterInfo *TRI) const {
2214 DebugLoc DL = MBB.findDebugLoc(MI);
2216 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2217 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2218 unsigned SlotSize = is64Bit ? 8 : 4;
2220 MachineFunction &MF = *MBB.getParent();
2221 unsigned FPReg = RI.getFrameRegister(MF);
2222 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2223 unsigned CalleeFrameSize = 0;
2225 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
2226 for (unsigned i = CSI.size(); i != 0; --i) {
2227 unsigned Reg = CSI[i-1].getReg();
2228 // Add the callee-saved register as live-in. It's killed at the spill.
2231 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
2233 if (!X86::VR128RegClass.contains(Reg) && !isWin64) {
2234 CalleeFrameSize += SlotSize;
2235 BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
2237 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
2238 &X86::VR128RegClass, &RI);
2242 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
2246 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
2247 MachineBasicBlock::iterator MI,
2248 const std::vector<CalleeSavedInfo> &CSI,
2249 const TargetRegisterInfo *TRI) const {
2253 DebugLoc DL = MBB.findDebugLoc(MI);
2255 MachineFunction &MF = *MBB.getParent();
2256 unsigned FPReg = RI.getFrameRegister(MF);
2257 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2258 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2259 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
2260 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2261 unsigned Reg = CSI[i].getReg();
2263 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
2265 if (!X86::VR128RegClass.contains(Reg) && !isWin64) {
2266 BuildMI(MBB, MI, DL, get(Opc), Reg);
2268 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
2269 &X86::VR128RegClass, &RI);
2276 X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
2277 int FrameIx, uint64_t Offset,
2278 const MDNode *MDPtr,
2279 DebugLoc DL) const {
2281 AM.BaseType = X86AddressMode::FrameIndexBase;
2282 AM.Base.FrameIndex = FrameIx;
2283 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
2284 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
2288 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2289 const SmallVectorImpl<MachineOperand> &MOs,
2291 const TargetInstrInfo &TII) {
2292 // Create the base instruction with the memory operand as the first part.
2293 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2294 MI->getDebugLoc(), true);
2295 MachineInstrBuilder MIB(NewMI);
2296 unsigned NumAddrOps = MOs.size();
2297 for (unsigned i = 0; i != NumAddrOps; ++i)
2298 MIB.addOperand(MOs[i]);
2299 if (NumAddrOps < 4) // FrameIndex only
2302 // Loop over the rest of the ri operands, converting them over.
2303 unsigned NumOps = MI->getDesc().getNumOperands()-2;
2304 for (unsigned i = 0; i != NumOps; ++i) {
2305 MachineOperand &MO = MI->getOperand(i+2);
2308 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2309 MachineOperand &MO = MI->getOperand(i);
2315 static MachineInstr *FuseInst(MachineFunction &MF,
2316 unsigned Opcode, unsigned OpNo,
2317 const SmallVectorImpl<MachineOperand> &MOs,
2318 MachineInstr *MI, const TargetInstrInfo &TII) {
2319 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2320 MI->getDebugLoc(), true);
2321 MachineInstrBuilder MIB(NewMI);
2323 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2324 MachineOperand &MO = MI->getOperand(i);
2326 assert(MO.isReg() && "Expected to fold into reg operand!");
2327 unsigned NumAddrOps = MOs.size();
2328 for (unsigned i = 0; i != NumAddrOps; ++i)
2329 MIB.addOperand(MOs[i]);
2330 if (NumAddrOps < 4) // FrameIndex only
2339 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2340 const SmallVectorImpl<MachineOperand> &MOs,
2342 MachineFunction &MF = *MI->getParent()->getParent();
2343 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2345 unsigned NumAddrOps = MOs.size();
2346 for (unsigned i = 0; i != NumAddrOps; ++i)
2347 MIB.addOperand(MOs[i]);
2348 if (NumAddrOps < 4) // FrameIndex only
2350 return MIB.addImm(0);
2354 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2355 MachineInstr *MI, unsigned i,
2356 const SmallVectorImpl<MachineOperand> &MOs,
2357 unsigned Size, unsigned Align) const {
2358 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2359 bool isTwoAddrFold = false;
2360 unsigned NumOps = MI->getDesc().getNumOperands();
2361 bool isTwoAddr = NumOps > 1 &&
2362 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2364 MachineInstr *NewMI = NULL;
2365 // Folding a memory location into the two-address part of a two-address
2366 // instruction is different than folding it other places. It requires
2367 // replacing the *two* registers with the memory location.
2368 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2369 MI->getOperand(0).isReg() &&
2370 MI->getOperand(1).isReg() &&
2371 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2372 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2373 isTwoAddrFold = true;
2374 } else if (i == 0) { // If operand 0
2375 if (MI->getOpcode() == X86::MOV64r0)
2376 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2377 else if (MI->getOpcode() == X86::MOV32r0)
2378 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2379 else if (MI->getOpcode() == X86::MOV16r0)
2380 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2381 else if (MI->getOpcode() == X86::MOV8r0)
2382 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2386 OpcodeTablePtr = &RegOp2MemOpTable0;
2387 } else if (i == 1) {
2388 OpcodeTablePtr = &RegOp2MemOpTable1;
2389 } else if (i == 2) {
2390 OpcodeTablePtr = &RegOp2MemOpTable2;
2393 // If table selected...
2394 if (OpcodeTablePtr) {
2395 // Find the Opcode to fuse
2396 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2397 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
2398 if (I != OpcodeTablePtr->end()) {
2399 unsigned Opcode = I->second.first;
2400 unsigned MinAlign = I->second.second;
2401 if (Align < MinAlign)
2403 bool NarrowToMOV32rm = false;
2405 unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize();
2406 if (Size < RCSize) {
2407 // Check if it's safe to fold the load. If the size of the object is
2408 // narrower than the load width, then it's not.
2409 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2411 // If this is a 64-bit load, but the spill slot is 32, then we can do
2412 // a 32-bit load which is implicitly zero-extended. This likely is due
2413 // to liveintervalanalysis remat'ing a load from stack slot.
2414 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2416 Opcode = X86::MOV32rm;
2417 NarrowToMOV32rm = true;
2422 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2424 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2426 if (NarrowToMOV32rm) {
2427 // If this is the special case where we use a MOV32rm to load a 32-bit
2428 // value and zero-extend the top bits. Change the destination register
2430 unsigned DstReg = NewMI->getOperand(0).getReg();
2431 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2432 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2435 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
2442 if (PrintFailedFusing)
2443 dbgs() << "We failed to fuse operand " << i << " in " << *MI;
2448 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2450 const SmallVectorImpl<unsigned> &Ops,
2451 int FrameIndex) const {
2452 // Check switch flag
2453 if (NoFusing) return NULL;
2455 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2456 switch (MI->getOpcode()) {
2457 case X86::CVTSD2SSrr:
2458 case X86::Int_CVTSD2SSrr:
2459 case X86::CVTSS2SDrr:
2460 case X86::Int_CVTSS2SDrr:
2462 case X86::RCPSSr_Int:
2463 case X86::ROUNDSDr_Int:
2464 case X86::ROUNDSSr_Int:
2466 case X86::RSQRTSSr_Int:
2468 case X86::SQRTSSr_Int:
2472 const MachineFrameInfo *MFI = MF.getFrameInfo();
2473 unsigned Size = MFI->getObjectSize(FrameIndex);
2474 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2475 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2476 unsigned NewOpc = 0;
2477 unsigned RCSize = 0;
2478 switch (MI->getOpcode()) {
2479 default: return NULL;
2480 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
2481 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
2482 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
2483 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
2485 // Check if it's safe to fold the load. If the size of the object is
2486 // narrower than the load width, then it's not.
2489 // Change to CMPXXri r, 0 first.
2490 MI->setDesc(get(NewOpc));
2491 MI->getOperand(1).ChangeToImmediate(0);
2492 } else if (Ops.size() != 1)
2495 SmallVector<MachineOperand,4> MOs;
2496 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2497 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2500 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2502 const SmallVectorImpl<unsigned> &Ops,
2503 MachineInstr *LoadMI) const {
2504 // Check switch flag
2505 if (NoFusing) return NULL;
2507 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2508 switch (MI->getOpcode()) {
2509 case X86::CVTSD2SSrr:
2510 case X86::Int_CVTSD2SSrr:
2511 case X86::CVTSS2SDrr:
2512 case X86::Int_CVTSS2SDrr:
2514 case X86::RCPSSr_Int:
2515 case X86::ROUNDSDr_Int:
2516 case X86::ROUNDSSr_Int:
2518 case X86::RSQRTSSr_Int:
2520 case X86::SQRTSSr_Int:
2524 // Determine the alignment of the load.
2525 unsigned Alignment = 0;
2526 if (LoadMI->hasOneMemOperand())
2527 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
2529 switch (LoadMI->getOpcode()) {
2533 case X86::V_SETALLONES:
2543 llvm_unreachable("Don't know how to fold this instruction!");
2545 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2546 unsigned NewOpc = 0;
2547 switch (MI->getOpcode()) {
2548 default: return NULL;
2549 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2550 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
2551 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
2552 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
2554 // Change to CMPXXri r, 0 first.
2555 MI->setDesc(get(NewOpc));
2556 MI->getOperand(1).ChangeToImmediate(0);
2557 } else if (Ops.size() != 1)
2560 SmallVector<MachineOperand,X86AddrNumOperands> MOs;
2561 switch (LoadMI->getOpcode()) {
2565 case X86::V_SETALLONES:
2567 case X86::FsFLD0SS: {
2568 // Folding a V_SET0P? or V_SETALLONES as a load, to ease register pressure.
2569 // Create a constant-pool entry and operands to load from it.
2571 // Medium and large mode can't fold loads this way.
2572 if (TM.getCodeModel() != CodeModel::Small &&
2573 TM.getCodeModel() != CodeModel::Kernel)
2576 // x86-32 PIC requires a PIC base register for constant pools.
2577 unsigned PICBase = 0;
2578 if (TM.getRelocationModel() == Reloc::PIC_) {
2579 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2582 // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
2583 // This doesn't work for several reasons.
2584 // 1. GlobalBaseReg may have been spilled.
2585 // 2. It may not be live at MI.
2589 // Create a constant-pool entry.
2590 MachineConstantPool &MCP = *MF.getConstantPool();
2592 if (LoadMI->getOpcode() == X86::FsFLD0SS)
2593 Ty = Type::getFloatTy(MF.getFunction()->getContext());
2594 else if (LoadMI->getOpcode() == X86::FsFLD0SD)
2595 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
2597 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
2598 const Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ?
2599 Constant::getAllOnesValue(Ty) :
2600 Constant::getNullValue(Ty);
2601 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
2603 // Create operands to load from the constant pool entry.
2604 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2605 MOs.push_back(MachineOperand::CreateImm(1));
2606 MOs.push_back(MachineOperand::CreateReg(0, false));
2607 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2608 MOs.push_back(MachineOperand::CreateReg(0, false));
2612 // Folding a normal load. Just copy the load's address operands.
2613 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2614 for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i)
2615 MOs.push_back(LoadMI->getOperand(i));
2619 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
2623 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2624 const SmallVectorImpl<unsigned> &Ops) const {
2625 // Check switch flag
2626 if (NoFusing) return 0;
2628 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2629 switch (MI->getOpcode()) {
2630 default: return false;
2639 if (Ops.size() != 1)
2642 unsigned OpNum = Ops[0];
2643 unsigned Opc = MI->getOpcode();
2644 unsigned NumOps = MI->getDesc().getNumOperands();
2645 bool isTwoAddr = NumOps > 1 &&
2646 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2648 // Folding a memory location into the two-address part of a two-address
2649 // instruction is different than folding it other places. It requires
2650 // replacing the *two* registers with the memory location.
2651 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2652 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2653 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2654 } else if (OpNum == 0) { // If operand 0
2663 OpcodeTablePtr = &RegOp2MemOpTable0;
2664 } else if (OpNum == 1) {
2665 OpcodeTablePtr = &RegOp2MemOpTable1;
2666 } else if (OpNum == 2) {
2667 OpcodeTablePtr = &RegOp2MemOpTable2;
2670 if (OpcodeTablePtr) {
2671 // Find the Opcode to fuse
2672 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2673 OpcodeTablePtr->find((unsigned*)Opc);
2674 if (I != OpcodeTablePtr->end())
2680 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2681 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2682 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2683 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2684 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2685 if (I == MemOp2RegOpTable.end())
2687 unsigned Opc = I->second.first;
2688 unsigned Index = I->second.second & 0xf;
2689 bool FoldedLoad = I->second.second & (1 << 4);
2690 bool FoldedStore = I->second.second & (1 << 5);
2691 if (UnfoldLoad && !FoldedLoad)
2693 UnfoldLoad &= FoldedLoad;
2694 if (UnfoldStore && !FoldedStore)
2696 UnfoldStore &= FoldedStore;
2698 const TargetInstrDesc &TID = get(Opc);
2699 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2700 const TargetRegisterClass *RC = TOI.getRegClass(&RI);
2701 if (!MI->hasOneMemOperand() &&
2702 RC == &X86::VR128RegClass &&
2703 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
2704 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
2705 // conservatively assume the address is unaligned. That's bad for
2708 SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
2709 SmallVector<MachineOperand,2> BeforeOps;
2710 SmallVector<MachineOperand,2> AfterOps;
2711 SmallVector<MachineOperand,4> ImpOps;
2712 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2713 MachineOperand &Op = MI->getOperand(i);
2714 if (i >= Index && i < Index + X86AddrNumOperands)
2715 AddrOps.push_back(Op);
2716 else if (Op.isReg() && Op.isImplicit())
2717 ImpOps.push_back(Op);
2719 BeforeOps.push_back(Op);
2721 AfterOps.push_back(Op);
2724 // Emit the load instruction.
2726 std::pair<MachineInstr::mmo_iterator,
2727 MachineInstr::mmo_iterator> MMOs =
2728 MF.extractLoadMemRefs(MI->memoperands_begin(),
2729 MI->memoperands_end());
2730 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
2732 // Address operands cannot be marked isKill.
2733 for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) {
2734 MachineOperand &MO = NewMIs[0]->getOperand(i);
2736 MO.setIsKill(false);
2741 // Emit the data processing instruction.
2742 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
2743 MachineInstrBuilder MIB(DataMI);
2746 MIB.addReg(Reg, RegState::Define);
2747 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2748 MIB.addOperand(BeforeOps[i]);
2751 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2752 MIB.addOperand(AfterOps[i]);
2753 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2754 MachineOperand &MO = ImpOps[i];
2755 MIB.addReg(MO.getReg(),
2756 getDefRegState(MO.isDef()) |
2757 RegState::Implicit |
2758 getKillRegState(MO.isKill()) |
2759 getDeadRegState(MO.isDead()) |
2760 getUndefRegState(MO.isUndef()));
2762 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2763 unsigned NewOpc = 0;
2764 switch (DataMI->getOpcode()) {
2766 case X86::CMP64ri32:
2773 MachineOperand &MO0 = DataMI->getOperand(0);
2774 MachineOperand &MO1 = DataMI->getOperand(1);
2775 if (MO1.getImm() == 0) {
2776 switch (DataMI->getOpcode()) {
2779 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2781 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2783 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2784 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2786 DataMI->setDesc(get(NewOpc));
2787 MO1.ChangeToRegister(MO0.getReg(), false);
2791 NewMIs.push_back(DataMI);
2793 // Emit the store instruction.
2795 const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI);
2796 std::pair<MachineInstr::mmo_iterator,
2797 MachineInstr::mmo_iterator> MMOs =
2798 MF.extractStoreMemRefs(MI->memoperands_begin(),
2799 MI->memoperands_end());
2800 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
2807 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2808 SmallVectorImpl<SDNode*> &NewNodes) const {
2809 if (!N->isMachineOpcode())
2812 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2813 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
2814 if (I == MemOp2RegOpTable.end())
2816 unsigned Opc = I->second.first;
2817 unsigned Index = I->second.second & 0xf;
2818 bool FoldedLoad = I->second.second & (1 << 4);
2819 bool FoldedStore = I->second.second & (1 << 5);
2820 const TargetInstrDesc &TID = get(Opc);
2821 const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI);
2822 unsigned NumDefs = TID.NumDefs;
2823 std::vector<SDValue> AddrOps;
2824 std::vector<SDValue> BeforeOps;
2825 std::vector<SDValue> AfterOps;
2826 DebugLoc dl = N->getDebugLoc();
2827 unsigned NumOps = N->getNumOperands();
2828 for (unsigned i = 0; i != NumOps-1; ++i) {
2829 SDValue Op = N->getOperand(i);
2830 if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands)
2831 AddrOps.push_back(Op);
2832 else if (i < Index-NumDefs)
2833 BeforeOps.push_back(Op);
2834 else if (i > Index-NumDefs)
2835 AfterOps.push_back(Op);
2837 SDValue Chain = N->getOperand(NumOps-1);
2838 AddrOps.push_back(Chain);
2840 // Emit the load instruction.
2842 MachineFunction &MF = DAG.getMachineFunction();
2844 EVT VT = *RC->vt_begin();
2845 std::pair<MachineInstr::mmo_iterator,
2846 MachineInstr::mmo_iterator> MMOs =
2847 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2848 cast<MachineSDNode>(N)->memoperands_end());
2849 if (!(*MMOs.first) &&
2850 RC == &X86::VR128RegClass &&
2851 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
2852 // Do not introduce a slow unaligned load.
2854 bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16;
2855 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2856 VT, MVT::Other, &AddrOps[0], AddrOps.size());
2857 NewNodes.push_back(Load);
2859 // Preserve memory reference information.
2860 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2863 // Emit the data processing instruction.
2864 std::vector<EVT> VTs;
2865 const TargetRegisterClass *DstRC = 0;
2866 if (TID.getNumDefs() > 0) {
2867 DstRC = TID.OpInfo[0].getRegClass(&RI);
2868 VTs.push_back(*DstRC->vt_begin());
2870 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2871 EVT VT = N->getValueType(i);
2872 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2876 BeforeOps.push_back(SDValue(Load, 0));
2877 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2878 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
2880 NewNodes.push_back(NewNode);
2882 // Emit the store instruction.
2885 AddrOps.push_back(SDValue(NewNode, 0));
2886 AddrOps.push_back(Chain);
2887 std::pair<MachineInstr::mmo_iterator,
2888 MachineInstr::mmo_iterator> MMOs =
2889 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2890 cast<MachineSDNode>(N)->memoperands_end());
2891 if (!(*MMOs.first) &&
2892 RC == &X86::VR128RegClass &&
2893 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
2894 // Do not introduce a slow unaligned store.
2896 bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16;
2897 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
2900 &AddrOps[0], AddrOps.size());
2901 NewNodes.push_back(Store);
2903 // Preserve memory reference information.
2904 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2910 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2911 bool UnfoldLoad, bool UnfoldStore,
2912 unsigned *LoadRegIndex) const {
2913 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2914 MemOp2RegOpTable.find((unsigned*)Opc);
2915 if (I == MemOp2RegOpTable.end())
2917 bool FoldedLoad = I->second.second & (1 << 4);
2918 bool FoldedStore = I->second.second & (1 << 5);
2919 if (UnfoldLoad && !FoldedLoad)
2921 if (UnfoldStore && !FoldedStore)
2924 *LoadRegIndex = I->second.second & 0xf;
2925 return I->second.first;
2929 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
2930 int64_t &Offset1, int64_t &Offset2) const {
2931 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
2933 unsigned Opc1 = Load1->getMachineOpcode();
2934 unsigned Opc2 = Load2->getMachineOpcode();
2936 default: return false;
2946 case X86::MMX_MOVD64rm:
2947 case X86::MMX_MOVQ64rm:
2948 case X86::FsMOVAPSrm:
2949 case X86::FsMOVAPDrm:
2952 case X86::MOVUPSrm_Int:
2956 case X86::MOVDQUrm_Int:
2960 default: return false;
2970 case X86::MMX_MOVD64rm:
2971 case X86::MMX_MOVQ64rm:
2972 case X86::FsMOVAPSrm:
2973 case X86::FsMOVAPDrm:
2976 case X86::MOVUPSrm_Int:
2980 case X86::MOVDQUrm_Int:
2984 // Check if chain operands and base addresses match.
2985 if (Load1->getOperand(0) != Load2->getOperand(0) ||
2986 Load1->getOperand(5) != Load2->getOperand(5))
2988 // Segment operands should match as well.
2989 if (Load1->getOperand(4) != Load2->getOperand(4))
2991 // Scale should be 1, Index should be Reg0.
2992 if (Load1->getOperand(1) == Load2->getOperand(1) &&
2993 Load1->getOperand(2) == Load2->getOperand(2)) {
2994 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
2997 // Now let's examine the displacements.
2998 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
2999 isa<ConstantSDNode>(Load2->getOperand(3))) {
3000 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
3001 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
3008 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
3009 int64_t Offset1, int64_t Offset2,
3010 unsigned NumLoads) const {
3011 assert(Offset2 > Offset1);
3012 if ((Offset2 - Offset1) / 8 > 64)
3015 unsigned Opc1 = Load1->getMachineOpcode();
3016 unsigned Opc2 = Load2->getMachineOpcode();
3018 return false; // FIXME: overly conservative?
3025 case X86::MMX_MOVD64rm:
3026 case X86::MMX_MOVQ64rm:
3030 EVT VT = Load1->getValueType(0);
3031 switch (VT.getSimpleVT().SimpleTy) {
3033 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
3034 // have 16 of them to play with.
3035 if (TM.getSubtargetImpl()->is64Bit()) {
3038 } else if (NumLoads) {
3058 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
3059 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
3060 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
3061 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
3063 Cond[0].setImm(GetOppositeBranchCondition(CC));
3068 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
3069 // FIXME: Return false for x87 stack register classes for now. We can't
3070 // allow any loads of these registers before FpGet_ST0_80.
3071 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
3072 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
3076 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher)
3077 /// register? e.g. r8, xmm8, xmm13, etc.
3078 bool X86InstrInfo::isX86_64ExtendedReg(unsigned RegNo) {
3081 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
3082 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
3083 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
3084 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
3085 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
3086 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
3087 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
3088 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
3089 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
3090 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
3097 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
3098 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
3099 /// size, and 3) use of X86-64 extended registers.
3100 unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
3102 const TargetInstrDesc &Desc = MI.getDesc();
3104 // Pseudo instructions do not need REX prefix byte.
3105 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
3107 if (Desc.TSFlags & X86II::REX_W)
3110 unsigned NumOps = Desc.getNumOperands();
3112 bool isTwoAddr = NumOps > 1 &&
3113 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
3115 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
3116 unsigned i = isTwoAddr ? 1 : 0;
3117 for (unsigned e = NumOps; i != e; ++i) {
3118 const MachineOperand& MO = MI.getOperand(i);
3120 unsigned Reg = MO.getReg();
3121 if (isX86_64NonExtLowByteReg(Reg))
3126 switch (Desc.TSFlags & X86II::FormMask) {
3127 case X86II::MRMInitReg:
3128 if (isX86_64ExtendedReg(MI.getOperand(0)))
3129 REX |= (1 << 0) | (1 << 2);
3131 case X86II::MRMSrcReg: {
3132 if (isX86_64ExtendedReg(MI.getOperand(0)))
3134 i = isTwoAddr ? 2 : 1;
3135 for (unsigned e = NumOps; i != e; ++i) {
3136 const MachineOperand& MO = MI.getOperand(i);
3137 if (isX86_64ExtendedReg(MO))
3142 case X86II::MRMSrcMem: {
3143 if (isX86_64ExtendedReg(MI.getOperand(0)))
3146 i = isTwoAddr ? 2 : 1;
3147 for (; i != NumOps; ++i) {
3148 const MachineOperand& MO = MI.getOperand(i);
3150 if (isX86_64ExtendedReg(MO))
3157 case X86II::MRM0m: case X86II::MRM1m:
3158 case X86II::MRM2m: case X86II::MRM3m:
3159 case X86II::MRM4m: case X86II::MRM5m:
3160 case X86II::MRM6m: case X86II::MRM7m:
3161 case X86II::MRMDestMem: {
3162 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
3163 i = isTwoAddr ? 1 : 0;
3164 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
3167 for (; i != e; ++i) {
3168 const MachineOperand& MO = MI.getOperand(i);
3170 if (isX86_64ExtendedReg(MO))
3178 if (isX86_64ExtendedReg(MI.getOperand(0)))
3180 i = isTwoAddr ? 2 : 1;
3181 for (unsigned e = NumOps; i != e; ++i) {
3182 const MachineOperand& MO = MI.getOperand(i);
3183 if (isX86_64ExtendedReg(MO))
3193 /// sizePCRelativeBlockAddress - This method returns the size of a PC
3194 /// relative block address instruction
3196 static unsigned sizePCRelativeBlockAddress() {
3200 /// sizeGlobalAddress - Give the size of the emission of this global address
3202 static unsigned sizeGlobalAddress(bool dword) {
3203 return dword ? 8 : 4;
3206 /// sizeConstPoolAddress - Give the size of the emission of this constant
3209 static unsigned sizeConstPoolAddress(bool dword) {
3210 return dword ? 8 : 4;
3213 /// sizeExternalSymbolAddress - Give the size of the emission of this external
3216 static unsigned sizeExternalSymbolAddress(bool dword) {
3217 return dword ? 8 : 4;
3220 /// sizeJumpTableAddress - Give the size of the emission of this jump
3223 static unsigned sizeJumpTableAddress(bool dword) {
3224 return dword ? 8 : 4;
3227 static unsigned sizeConstant(unsigned Size) {
3231 static unsigned sizeRegModRMByte(){
3235 static unsigned sizeSIBByte(){
3239 static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
3240 unsigned FinalSize = 0;
3241 // If this is a simple integer displacement that doesn't require a relocation.
3243 FinalSize += sizeConstant(4);
3247 // Otherwise, this is something that requires a relocation.
3248 if (RelocOp->isGlobal()) {
3249 FinalSize += sizeGlobalAddress(false);
3250 } else if (RelocOp->isCPI()) {
3251 FinalSize += sizeConstPoolAddress(false);
3252 } else if (RelocOp->isJTI()) {
3253 FinalSize += sizeJumpTableAddress(false);
3255 llvm_unreachable("Unknown value to relocate!");
3260 static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
3261 bool IsPIC, bool Is64BitMode) {
3262 const MachineOperand &Op3 = MI.getOperand(Op+3);
3264 const MachineOperand *DispForReloc = 0;
3265 unsigned FinalSize = 0;
3267 // Figure out what sort of displacement we have to handle here.
3268 if (Op3.isGlobal()) {
3269 DispForReloc = &Op3;
3270 } else if (Op3.isCPI()) {
3271 if (Is64BitMode || IsPIC) {
3272 DispForReloc = &Op3;
3276 } else if (Op3.isJTI()) {
3277 if (Is64BitMode || IsPIC) {
3278 DispForReloc = &Op3;
3286 const MachineOperand &Base = MI.getOperand(Op);
3287 const MachineOperand &IndexReg = MI.getOperand(Op+2);
3289 unsigned BaseReg = Base.getReg();
3291 // Is a SIB byte needed?
3292 if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
3293 IndexReg.getReg() == 0 &&
3294 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
3295 if (BaseReg == 0) { // Just a displacement?
3296 // Emit special case [disp32] encoding
3298 FinalSize += getDisplacementFieldSize(DispForReloc);
3300 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
3301 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
3302 // Emit simple indirect register encoding... [EAX] f.e.
3304 // Be pessimistic and assume it's a disp32, not a disp8
3306 // Emit the most general non-SIB encoding: [REG+disp32]
3308 FinalSize += getDisplacementFieldSize(DispForReloc);
3312 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
3313 assert(IndexReg.getReg() != X86::ESP &&
3314 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
3316 bool ForceDisp32 = false;
3317 if (BaseReg == 0 || DispForReloc) {
3318 // Emit the normal disp32 encoding.
3325 FinalSize += sizeSIBByte();
3327 // Do we need to output a displacement?
3328 if (DispVal != 0 || ForceDisp32) {
3329 FinalSize += getDisplacementFieldSize(DispForReloc);
3336 static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
3337 const TargetInstrDesc *Desc,
3338 bool IsPIC, bool Is64BitMode) {
3340 unsigned Opcode = Desc->Opcode;
3341 unsigned FinalSize = 0;
3343 // Emit the lock opcode prefix as needed.
3344 if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
3346 // Emit segment override opcode prefix as needed.
3347 switch (Desc->TSFlags & X86II::SegOvrMask) {
3352 default: llvm_unreachable("Invalid segment!");
3353 case 0: break; // No segment override!
3356 // Emit the repeat opcode prefix as needed.
3357 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
3359 // Emit the operand size opcode prefix as needed.
3360 if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
3362 // Emit the address size opcode prefix as needed.
3363 if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
3365 bool Need0FPrefix = false;
3366 switch (Desc->TSFlags & X86II::Op0Mask) {
3367 case X86II::TB: // Two-byte opcode prefix
3368 case X86II::T8: // 0F 38
3369 case X86II::TA: // 0F 3A
3370 Need0FPrefix = true;
3372 case X86II::TF: // F2 0F 38
3374 Need0FPrefix = true;
3376 case X86II::REP: break; // already handled.
3377 case X86II::XS: // F3 0F
3379 Need0FPrefix = true;
3381 case X86II::XD: // F2 0F
3383 Need0FPrefix = true;
3385 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
3386 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
3388 break; // Two-byte opcode prefix
3389 default: llvm_unreachable("Invalid prefix!");
3390 case 0: break; // No prefix!
3395 unsigned REX = X86InstrInfo::determineREX(MI);
3400 // 0x0F escape code must be emitted just before the opcode.
3404 switch (Desc->TSFlags & X86II::Op0Mask) {
3405 case X86II::T8: // 0F 38
3408 case X86II::TA: // 0F 3A
3411 case X86II::TF: // F2 0F 38
3416 // If this is a two-address instruction, skip one of the register operands.
3417 unsigned NumOps = Desc->getNumOperands();
3419 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
3421 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
3422 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
3425 switch (Desc->TSFlags & X86II::FormMask) {
3426 default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
3428 // Remember the current PC offset, this is the PIC relocation
3433 case TargetOpcode::INLINEASM: {
3434 const MachineFunction *MF = MI.getParent()->getParent();
3435 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
3436 FinalSize += TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
3437 *MF->getTarget().getMCAsmInfo());
3440 case TargetOpcode::DBG_LABEL:
3441 case TargetOpcode::EH_LABEL:
3442 case TargetOpcode::DBG_VALUE:
3444 case TargetOpcode::IMPLICIT_DEF:
3445 case TargetOpcode::KILL:
3446 case X86::FP_REG_KILL:
3448 case X86::MOVPC32r: {
3449 // This emits the "call" portion of this pseudo instruction.
3451 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3460 if (CurOp != NumOps) {
3461 const MachineOperand &MO = MI.getOperand(CurOp++);
3463 FinalSize += sizePCRelativeBlockAddress();
3464 } else if (MO.isGlobal()) {
3465 FinalSize += sizeGlobalAddress(false);
3466 } else if (MO.isSymbol()) {
3467 FinalSize += sizeExternalSymbolAddress(false);
3468 } else if (MO.isImm()) {
3469 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3471 llvm_unreachable("Unknown RawFrm operand!");
3476 case X86II::AddRegFrm:
3480 if (CurOp != NumOps) {
3481 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3482 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
3484 FinalSize += sizeConstant(Size);
3487 if (Opcode == X86::MOV64ri)
3489 if (MO1.isGlobal()) {
3490 FinalSize += sizeGlobalAddress(dword);
3491 } else if (MO1.isSymbol())
3492 FinalSize += sizeExternalSymbolAddress(dword);
3493 else if (MO1.isCPI())
3494 FinalSize += sizeConstPoolAddress(dword);
3495 else if (MO1.isJTI())
3496 FinalSize += sizeJumpTableAddress(dword);
3501 case X86II::MRMDestReg: {
3503 FinalSize += sizeRegModRMByte();
3505 if (CurOp != NumOps) {
3507 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3511 case X86II::MRMDestMem: {
3513 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3514 CurOp += X86AddrNumOperands + 1;
3515 if (CurOp != NumOps) {
3517 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3522 case X86II::MRMSrcReg:
3524 FinalSize += sizeRegModRMByte();
3526 if (CurOp != NumOps) {
3528 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3532 case X86II::MRMSrcMem: {
3534 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
3535 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
3536 AddrOperands = X86AddrNumOperands - 1; // No segment register
3538 AddrOperands = X86AddrNumOperands;
3541 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
3542 CurOp += AddrOperands + 1;
3543 if (CurOp != NumOps) {
3545 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3550 case X86II::MRM0r: case X86II::MRM1r:
3551 case X86II::MRM2r: case X86II::MRM3r:
3552 case X86II::MRM4r: case X86II::MRM5r:
3553 case X86II::MRM6r: case X86II::MRM7r:
3555 if (Desc->getOpcode() == X86::LFENCE ||
3556 Desc->getOpcode() == X86::MFENCE) {
3557 // Special handling of lfence and mfence;
3558 FinalSize += sizeRegModRMByte();
3559 } else if (Desc->getOpcode() == X86::MONITOR ||
3560 Desc->getOpcode() == X86::MWAIT) {
3561 // Special handling of monitor and mwait.
3562 FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode.
3565 FinalSize += sizeRegModRMByte();
3568 if (CurOp != NumOps) {
3569 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3570 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
3572 FinalSize += sizeConstant(Size);
3575 if (Opcode == X86::MOV64ri32)
3577 if (MO1.isGlobal()) {
3578 FinalSize += sizeGlobalAddress(dword);
3579 } else if (MO1.isSymbol())
3580 FinalSize += sizeExternalSymbolAddress(dword);
3581 else if (MO1.isCPI())
3582 FinalSize += sizeConstPoolAddress(dword);
3583 else if (MO1.isJTI())
3584 FinalSize += sizeJumpTableAddress(dword);
3589 case X86II::MRM0m: case X86II::MRM1m:
3590 case X86II::MRM2m: case X86II::MRM3m:
3591 case X86II::MRM4m: case X86II::MRM5m:
3592 case X86II::MRM6m: case X86II::MRM7m: {
3595 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3596 CurOp += X86AddrNumOperands;
3598 if (CurOp != NumOps) {
3599 const MachineOperand &MO = MI.getOperand(CurOp++);
3600 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
3602 FinalSize += sizeConstant(Size);
3605 if (Opcode == X86::MOV64mi32)
3607 if (MO.isGlobal()) {
3608 FinalSize += sizeGlobalAddress(dword);
3609 } else if (MO.isSymbol())
3610 FinalSize += sizeExternalSymbolAddress(dword);
3611 else if (MO.isCPI())
3612 FinalSize += sizeConstPoolAddress(dword);
3613 else if (MO.isJTI())
3614 FinalSize += sizeJumpTableAddress(dword);
3628 case X86II::MRMInitReg:
3630 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
3631 FinalSize += sizeRegModRMByte();
3636 if (!Desc->isVariadic() && CurOp != NumOps) {
3638 raw_string_ostream Msg(msg);
3639 Msg << "Cannot determine size: " << MI;
3640 report_fatal_error(Msg.str());
3648 unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
3649 const TargetInstrDesc &Desc = MI->getDesc();
3650 bool IsPIC = TM.getRelocationModel() == Reloc::PIC_;
3651 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
3652 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
3653 if (Desc.getOpcode() == X86::MOVPC32r)
3654 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
3658 /// getGlobalBaseReg - Return a virtual register initialized with the
3659 /// the global base register value. Output instructions required to
3660 /// initialize the register in the function entry block, if necessary.
3662 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3663 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3664 "X86-64 PIC uses RIP relative addressing");
3666 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3667 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3668 if (GlobalBaseReg != 0)
3669 return GlobalBaseReg;
3671 // Insert the set of GlobalBaseReg into the first MBB of the function
3672 MachineBasicBlock &FirstMBB = MF->front();
3673 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3674 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
3675 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3676 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3678 const TargetInstrInfo *TII = TM.getInstrInfo();
3679 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3680 // only used in JIT code emission as displacement to pc.
3681 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3683 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3684 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3685 if (TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3686 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3687 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3688 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3689 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3690 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3695 X86FI->setGlobalBaseReg(GlobalBaseReg);
3696 return GlobalBaseReg;
3699 // These are the replaceable SSE instructions. Some of these have Int variants
3700 // that we don't include here. We don't want to replace instructions selected
3702 static const unsigned ReplaceableInstrs[][3] = {
3703 //PackedInt PackedSingle PackedDouble
3704 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
3705 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
3706 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
3707 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
3708 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
3709 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
3710 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
3711 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
3712 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
3713 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
3714 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
3715 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
3716 { X86::V_SET0PS, X86::V_SET0PD, X86::V_SET0PI },
3717 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
3718 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
3721 // FIXME: Some shuffle and unpack instructions have equivalents in different
3722 // domains, but they require a bit more work than just switching opcodes.
3724 static const unsigned *lookup(unsigned opcode, unsigned domain) {
3725 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
3726 if (ReplaceableInstrs[i][domain-1] == opcode)
3727 return ReplaceableInstrs[i];
3731 std::pair<uint16_t, uint16_t>
3732 X86InstrInfo::GetSSEDomain(const MachineInstr *MI) const {
3733 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3734 return std::make_pair(domain,
3735 domain && lookup(MI->getOpcode(), domain) ? 0xe : 0);
3738 void X86InstrInfo::SetSSEDomain(MachineInstr *MI, unsigned Domain) const {
3739 assert(Domain>0 && Domain<4 && "Invalid execution domain");
3740 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3741 assert(dom && "Not an SSE instruction");
3742 const unsigned *table = lookup(MI->getOpcode(), dom);
3743 assert(table && "Cannot change domain");
3744 MI->setDesc(get(table[Domain-1]));
3747 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
3748 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
3749 NopInst.setOpcode(X86::NOOP);