1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/LLVMContext.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/MC/MCAsmInfo.h"
38 NoFusing("disable-spill-fusing",
39 cl::desc("Disable fusing of spill code into instructions"));
41 PrintFailedFusing("print-failed-fuse-candidates",
42 cl::desc("Print instructions that the allocator wants to"
43 " fuse, but the X86 backend currently can't"),
46 ReMatPICStubLoad("remat-pic-stub-load",
47 cl::desc("Re-materialize load from stub in PIC mode"),
48 cl::init(false), cl::Hidden);
50 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
51 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
52 TM(tm), RI(tm, *this) {
53 SmallVector<unsigned,16> AmbEntries;
54 static const unsigned OpTbl2Addr[][2] = {
55 { X86::ADC32ri, X86::ADC32mi },
56 { X86::ADC32ri8, X86::ADC32mi8 },
57 { X86::ADC32rr, X86::ADC32mr },
58 { X86::ADC64ri32, X86::ADC64mi32 },
59 { X86::ADC64ri8, X86::ADC64mi8 },
60 { X86::ADC64rr, X86::ADC64mr },
61 { X86::ADD16ri, X86::ADD16mi },
62 { X86::ADD16ri8, X86::ADD16mi8 },
63 { X86::ADD16rr, X86::ADD16mr },
64 { X86::ADD32ri, X86::ADD32mi },
65 { X86::ADD32ri8, X86::ADD32mi8 },
66 { X86::ADD32rr, X86::ADD32mr },
67 { X86::ADD64ri32, X86::ADD64mi32 },
68 { X86::ADD64ri8, X86::ADD64mi8 },
69 { X86::ADD64rr, X86::ADD64mr },
70 { X86::ADD8ri, X86::ADD8mi },
71 { X86::ADD8rr, X86::ADD8mr },
72 { X86::AND16ri, X86::AND16mi },
73 { X86::AND16ri8, X86::AND16mi8 },
74 { X86::AND16rr, X86::AND16mr },
75 { X86::AND32ri, X86::AND32mi },
76 { X86::AND32ri8, X86::AND32mi8 },
77 { X86::AND32rr, X86::AND32mr },
78 { X86::AND64ri32, X86::AND64mi32 },
79 { X86::AND64ri8, X86::AND64mi8 },
80 { X86::AND64rr, X86::AND64mr },
81 { X86::AND8ri, X86::AND8mi },
82 { X86::AND8rr, X86::AND8mr },
83 { X86::DEC16r, X86::DEC16m },
84 { X86::DEC32r, X86::DEC32m },
85 { X86::DEC64_16r, X86::DEC64_16m },
86 { X86::DEC64_32r, X86::DEC64_32m },
87 { X86::DEC64r, X86::DEC64m },
88 { X86::DEC8r, X86::DEC8m },
89 { X86::INC16r, X86::INC16m },
90 { X86::INC32r, X86::INC32m },
91 { X86::INC64_16r, X86::INC64_16m },
92 { X86::INC64_32r, X86::INC64_32m },
93 { X86::INC64r, X86::INC64m },
94 { X86::INC8r, X86::INC8m },
95 { X86::NEG16r, X86::NEG16m },
96 { X86::NEG32r, X86::NEG32m },
97 { X86::NEG64r, X86::NEG64m },
98 { X86::NEG8r, X86::NEG8m },
99 { X86::NOT16r, X86::NOT16m },
100 { X86::NOT32r, X86::NOT32m },
101 { X86::NOT64r, X86::NOT64m },
102 { X86::NOT8r, X86::NOT8m },
103 { X86::OR16ri, X86::OR16mi },
104 { X86::OR16ri8, X86::OR16mi8 },
105 { X86::OR16rr, X86::OR16mr },
106 { X86::OR32ri, X86::OR32mi },
107 { X86::OR32ri8, X86::OR32mi8 },
108 { X86::OR32rr, X86::OR32mr },
109 { X86::OR64ri32, X86::OR64mi32 },
110 { X86::OR64ri8, X86::OR64mi8 },
111 { X86::OR64rr, X86::OR64mr },
112 { X86::OR8ri, X86::OR8mi },
113 { X86::OR8rr, X86::OR8mr },
114 { X86::ROL16r1, X86::ROL16m1 },
115 { X86::ROL16rCL, X86::ROL16mCL },
116 { X86::ROL16ri, X86::ROL16mi },
117 { X86::ROL32r1, X86::ROL32m1 },
118 { X86::ROL32rCL, X86::ROL32mCL },
119 { X86::ROL32ri, X86::ROL32mi },
120 { X86::ROL64r1, X86::ROL64m1 },
121 { X86::ROL64rCL, X86::ROL64mCL },
122 { X86::ROL64ri, X86::ROL64mi },
123 { X86::ROL8r1, X86::ROL8m1 },
124 { X86::ROL8rCL, X86::ROL8mCL },
125 { X86::ROL8ri, X86::ROL8mi },
126 { X86::ROR16r1, X86::ROR16m1 },
127 { X86::ROR16rCL, X86::ROR16mCL },
128 { X86::ROR16ri, X86::ROR16mi },
129 { X86::ROR32r1, X86::ROR32m1 },
130 { X86::ROR32rCL, X86::ROR32mCL },
131 { X86::ROR32ri, X86::ROR32mi },
132 { X86::ROR64r1, X86::ROR64m1 },
133 { X86::ROR64rCL, X86::ROR64mCL },
134 { X86::ROR64ri, X86::ROR64mi },
135 { X86::ROR8r1, X86::ROR8m1 },
136 { X86::ROR8rCL, X86::ROR8mCL },
137 { X86::ROR8ri, X86::ROR8mi },
138 { X86::SAR16r1, X86::SAR16m1 },
139 { X86::SAR16rCL, X86::SAR16mCL },
140 { X86::SAR16ri, X86::SAR16mi },
141 { X86::SAR32r1, X86::SAR32m1 },
142 { X86::SAR32rCL, X86::SAR32mCL },
143 { X86::SAR32ri, X86::SAR32mi },
144 { X86::SAR64r1, X86::SAR64m1 },
145 { X86::SAR64rCL, X86::SAR64mCL },
146 { X86::SAR64ri, X86::SAR64mi },
147 { X86::SAR8r1, X86::SAR8m1 },
148 { X86::SAR8rCL, X86::SAR8mCL },
149 { X86::SAR8ri, X86::SAR8mi },
150 { X86::SBB32ri, X86::SBB32mi },
151 { X86::SBB32ri8, X86::SBB32mi8 },
152 { X86::SBB32rr, X86::SBB32mr },
153 { X86::SBB64ri32, X86::SBB64mi32 },
154 { X86::SBB64ri8, X86::SBB64mi8 },
155 { X86::SBB64rr, X86::SBB64mr },
156 { X86::SHL16rCL, X86::SHL16mCL },
157 { X86::SHL16ri, X86::SHL16mi },
158 { X86::SHL32rCL, X86::SHL32mCL },
159 { X86::SHL32ri, X86::SHL32mi },
160 { X86::SHL64rCL, X86::SHL64mCL },
161 { X86::SHL64ri, X86::SHL64mi },
162 { X86::SHL8rCL, X86::SHL8mCL },
163 { X86::SHL8ri, X86::SHL8mi },
164 { X86::SHLD16rrCL, X86::SHLD16mrCL },
165 { X86::SHLD16rri8, X86::SHLD16mri8 },
166 { X86::SHLD32rrCL, X86::SHLD32mrCL },
167 { X86::SHLD32rri8, X86::SHLD32mri8 },
168 { X86::SHLD64rrCL, X86::SHLD64mrCL },
169 { X86::SHLD64rri8, X86::SHLD64mri8 },
170 { X86::SHR16r1, X86::SHR16m1 },
171 { X86::SHR16rCL, X86::SHR16mCL },
172 { X86::SHR16ri, X86::SHR16mi },
173 { X86::SHR32r1, X86::SHR32m1 },
174 { X86::SHR32rCL, X86::SHR32mCL },
175 { X86::SHR32ri, X86::SHR32mi },
176 { X86::SHR64r1, X86::SHR64m1 },
177 { X86::SHR64rCL, X86::SHR64mCL },
178 { X86::SHR64ri, X86::SHR64mi },
179 { X86::SHR8r1, X86::SHR8m1 },
180 { X86::SHR8rCL, X86::SHR8mCL },
181 { X86::SHR8ri, X86::SHR8mi },
182 { X86::SHRD16rrCL, X86::SHRD16mrCL },
183 { X86::SHRD16rri8, X86::SHRD16mri8 },
184 { X86::SHRD32rrCL, X86::SHRD32mrCL },
185 { X86::SHRD32rri8, X86::SHRD32mri8 },
186 { X86::SHRD64rrCL, X86::SHRD64mrCL },
187 { X86::SHRD64rri8, X86::SHRD64mri8 },
188 { X86::SUB16ri, X86::SUB16mi },
189 { X86::SUB16ri8, X86::SUB16mi8 },
190 { X86::SUB16rr, X86::SUB16mr },
191 { X86::SUB32ri, X86::SUB32mi },
192 { X86::SUB32ri8, X86::SUB32mi8 },
193 { X86::SUB32rr, X86::SUB32mr },
194 { X86::SUB64ri32, X86::SUB64mi32 },
195 { X86::SUB64ri8, X86::SUB64mi8 },
196 { X86::SUB64rr, X86::SUB64mr },
197 { X86::SUB8ri, X86::SUB8mi },
198 { X86::SUB8rr, X86::SUB8mr },
199 { X86::XOR16ri, X86::XOR16mi },
200 { X86::XOR16ri8, X86::XOR16mi8 },
201 { X86::XOR16rr, X86::XOR16mr },
202 { X86::XOR32ri, X86::XOR32mi },
203 { X86::XOR32ri8, X86::XOR32mi8 },
204 { X86::XOR32rr, X86::XOR32mr },
205 { X86::XOR64ri32, X86::XOR64mi32 },
206 { X86::XOR64ri8, X86::XOR64mi8 },
207 { X86::XOR64rr, X86::XOR64mr },
208 { X86::XOR8ri, X86::XOR8mi },
209 { X86::XOR8rr, X86::XOR8mr }
212 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
213 unsigned RegOp = OpTbl2Addr[i][0];
214 unsigned MemOp = OpTbl2Addr[i][1];
215 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
216 std::make_pair(MemOp,0))).second)
217 assert(false && "Duplicated entries?");
218 // Index 0, folded load and store, no alignment requirement.
219 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
220 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
221 std::make_pair(RegOp,
223 AmbEntries.push_back(MemOp);
226 // If the third value is 1, then it's folding either a load or a store.
227 static const unsigned OpTbl0[][4] = {
228 { X86::BT16ri8, X86::BT16mi8, 1, 0 },
229 { X86::BT32ri8, X86::BT32mi8, 1, 0 },
230 { X86::BT64ri8, X86::BT64mi8, 1, 0 },
231 { X86::CALL32r, X86::CALL32m, 1, 0 },
232 { X86::CALL64r, X86::CALL64m, 1, 0 },
233 { X86::CMP16ri, X86::CMP16mi, 1, 0 },
234 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 },
235 { X86::CMP16rr, X86::CMP16mr, 1, 0 },
236 { X86::CMP32ri, X86::CMP32mi, 1, 0 },
237 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 },
238 { X86::CMP32rr, X86::CMP32mr, 1, 0 },
239 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 },
240 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 },
241 { X86::CMP64rr, X86::CMP64mr, 1, 0 },
242 { X86::CMP8ri, X86::CMP8mi, 1, 0 },
243 { X86::CMP8rr, X86::CMP8mr, 1, 0 },
244 { X86::DIV16r, X86::DIV16m, 1, 0 },
245 { X86::DIV32r, X86::DIV32m, 1, 0 },
246 { X86::DIV64r, X86::DIV64m, 1, 0 },
247 { X86::DIV8r, X86::DIV8m, 1, 0 },
248 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
249 { X86::FsMOVAPDrr, X86::MOVSDmr, 0, 0 },
250 { X86::FsMOVAPSrr, X86::MOVSSmr, 0, 0 },
251 { X86::IDIV16r, X86::IDIV16m, 1, 0 },
252 { X86::IDIV32r, X86::IDIV32m, 1, 0 },
253 { X86::IDIV64r, X86::IDIV64m, 1, 0 },
254 { X86::IDIV8r, X86::IDIV8m, 1, 0 },
255 { X86::IMUL16r, X86::IMUL16m, 1, 0 },
256 { X86::IMUL32r, X86::IMUL32m, 1, 0 },
257 { X86::IMUL64r, X86::IMUL64m, 1, 0 },
258 { X86::IMUL8r, X86::IMUL8m, 1, 0 },
259 { X86::JMP32r, X86::JMP32m, 1, 0 },
260 { X86::JMP64r, X86::JMP64m, 1, 0 },
261 { X86::MOV16ri, X86::MOV16mi, 0, 0 },
262 { X86::MOV16rr, X86::MOV16mr, 0, 0 },
263 { X86::MOV32ri, X86::MOV32mi, 0, 0 },
264 { X86::MOV32rr, X86::MOV32mr, 0, 0 },
265 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 },
266 { X86::MOV64rr, X86::MOV64mr, 0, 0 },
267 { X86::MOV8ri, X86::MOV8mi, 0, 0 },
268 { X86::MOV8rr, X86::MOV8mr, 0, 0 },
269 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 },
270 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 },
271 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 },
272 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 },
273 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
274 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
275 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0, 0 },
276 { X86::MOVSDrr, X86::MOVSDmr, 0, 0 },
277 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
278 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 },
279 { X86::MOVSSrr, X86::MOVSSmr, 0, 0 },
280 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 },
281 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 },
282 { X86::MUL16r, X86::MUL16m, 1, 0 },
283 { X86::MUL32r, X86::MUL32m, 1, 0 },
284 { X86::MUL64r, X86::MUL64m, 1, 0 },
285 { X86::MUL8r, X86::MUL8m, 1, 0 },
286 { X86::SETAEr, X86::SETAEm, 0, 0 },
287 { X86::SETAr, X86::SETAm, 0, 0 },
288 { X86::SETBEr, X86::SETBEm, 0, 0 },
289 { X86::SETBr, X86::SETBm, 0, 0 },
290 { X86::SETEr, X86::SETEm, 0, 0 },
291 { X86::SETGEr, X86::SETGEm, 0, 0 },
292 { X86::SETGr, X86::SETGm, 0, 0 },
293 { X86::SETLEr, X86::SETLEm, 0, 0 },
294 { X86::SETLr, X86::SETLm, 0, 0 },
295 { X86::SETNEr, X86::SETNEm, 0, 0 },
296 { X86::SETNOr, X86::SETNOm, 0, 0 },
297 { X86::SETNPr, X86::SETNPm, 0, 0 },
298 { X86::SETNSr, X86::SETNSm, 0, 0 },
299 { X86::SETOr, X86::SETOm, 0, 0 },
300 { X86::SETPr, X86::SETPm, 0, 0 },
301 { X86::SETSr, X86::SETSm, 0, 0 },
302 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 },
303 { X86::TEST16ri, X86::TEST16mi, 1, 0 },
304 { X86::TEST32ri, X86::TEST32mi, 1, 0 },
305 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 },
306 { X86::TEST8ri, X86::TEST8mi, 1, 0 }
309 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
310 unsigned RegOp = OpTbl0[i][0];
311 unsigned MemOp = OpTbl0[i][1];
312 unsigned Align = OpTbl0[i][3];
313 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
314 std::make_pair(MemOp,Align))).second)
315 assert(false && "Duplicated entries?");
316 unsigned FoldedLoad = OpTbl0[i][2];
317 // Index 0, folded load or store.
318 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
319 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
320 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
321 std::make_pair(RegOp, AuxInfo))).second)
322 AmbEntries.push_back(MemOp);
325 static const unsigned OpTbl1[][3] = {
326 { X86::CMP16rr, X86::CMP16rm, 0 },
327 { X86::CMP32rr, X86::CMP32rm, 0 },
328 { X86::CMP64rr, X86::CMP64rm, 0 },
329 { X86::CMP8rr, X86::CMP8rm, 0 },
330 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
331 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
332 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
333 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
334 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
335 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
336 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
337 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
338 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
339 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
340 { X86::FsMOVAPDrr, X86::MOVSDrm, 0 },
341 { X86::FsMOVAPSrr, X86::MOVSSrm, 0 },
342 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
343 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
344 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
345 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
346 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
347 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
348 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
349 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
350 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
351 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
352 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 },
353 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 },
354 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 },
355 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 },
356 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 },
357 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
358 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm, 0 },
359 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm, 0 },
360 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
361 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
362 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
363 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
364 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
365 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
366 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 },
367 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, 0 },
368 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, 16 },
369 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, 16 },
370 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
371 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
372 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
373 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
374 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
375 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
376 { X86::MOV16rr, X86::MOV16rm, 0 },
377 { X86::MOV32rr, X86::MOV32rm, 0 },
378 { X86::MOV64rr, X86::MOV64rm, 0 },
379 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
380 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
381 { X86::MOV8rr, X86::MOV8rm, 0 },
382 { X86::MOVAPDrr, X86::MOVAPDrm, 16 },
383 { X86::MOVAPSrr, X86::MOVAPSrm, 16 },
384 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
385 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
386 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
387 { X86::MOVDQArr, X86::MOVDQArm, 16 },
388 { X86::MOVSD2PDrr, X86::MOVSD2PDrm, 0 },
389 { X86::MOVSDrr, X86::MOVSDrm, 0 },
390 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 },
391 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 },
392 { X86::MOVSS2PSrr, X86::MOVSS2PSrm, 0 },
393 { X86::MOVSSrr, X86::MOVSSrm, 0 },
394 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
395 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
396 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
397 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
398 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
399 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
400 { X86::MOVUPDrr, X86::MOVUPDrm, 16 },
401 { X86::MOVUPSrr, X86::MOVUPSrm, 16 },
402 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
403 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
404 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
405 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
406 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
407 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
408 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
409 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
410 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
411 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
412 { X86::PSHUFDri, X86::PSHUFDmi, 16 },
413 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 },
414 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 },
415 { X86::RCPPSr, X86::RCPPSm, 16 },
416 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 },
417 { X86::RSQRTPSr, X86::RSQRTPSm, 16 },
418 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 },
419 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
420 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
421 { X86::SQRTPDr, X86::SQRTPDm, 16 },
422 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 },
423 { X86::SQRTPSr, X86::SQRTPSm, 16 },
424 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 },
425 { X86::SQRTSDr, X86::SQRTSDm, 0 },
426 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
427 { X86::SQRTSSr, X86::SQRTSSm, 0 },
428 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
429 { X86::TEST16rr, X86::TEST16rm, 0 },
430 { X86::TEST32rr, X86::TEST32rm, 0 },
431 { X86::TEST64rr, X86::TEST64rm, 0 },
432 { X86::TEST8rr, X86::TEST8rm, 0 },
433 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
434 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
435 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }
438 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
439 unsigned RegOp = OpTbl1[i][0];
440 unsigned MemOp = OpTbl1[i][1];
441 unsigned Align = OpTbl1[i][2];
442 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
443 std::make_pair(MemOp,Align))).second)
444 assert(false && "Duplicated entries?");
445 // Index 1, folded load
446 unsigned AuxInfo = 1 | (1 << 4);
447 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
448 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
449 std::make_pair(RegOp, AuxInfo))).second)
450 AmbEntries.push_back(MemOp);
453 static const unsigned OpTbl2[][3] = {
454 { X86::ADC32rr, X86::ADC32rm, 0 },
455 { X86::ADC64rr, X86::ADC64rm, 0 },
456 { X86::ADD16rr, X86::ADD16rm, 0 },
457 { X86::ADD32rr, X86::ADD32rm, 0 },
458 { X86::ADD64rr, X86::ADD64rm, 0 },
459 { X86::ADD8rr, X86::ADD8rm, 0 },
460 { X86::ADDPDrr, X86::ADDPDrm, 16 },
461 { X86::ADDPSrr, X86::ADDPSrm, 16 },
462 { X86::ADDSDrr, X86::ADDSDrm, 0 },
463 { X86::ADDSSrr, X86::ADDSSrm, 0 },
464 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 },
465 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 },
466 { X86::AND16rr, X86::AND16rm, 0 },
467 { X86::AND32rr, X86::AND32rm, 0 },
468 { X86::AND64rr, X86::AND64rm, 0 },
469 { X86::AND8rr, X86::AND8rm, 0 },
470 { X86::ANDNPDrr, X86::ANDNPDrm, 16 },
471 { X86::ANDNPSrr, X86::ANDNPSrm, 16 },
472 { X86::ANDPDrr, X86::ANDPDrm, 16 },
473 { X86::ANDPSrr, X86::ANDPSrm, 16 },
474 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
475 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
476 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
477 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
478 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
479 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
480 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
481 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
482 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
483 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
484 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
485 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
486 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
487 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
488 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
489 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
490 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
491 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
492 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
493 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
494 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
495 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
496 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
497 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
498 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
499 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
500 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
501 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
502 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
503 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
504 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
505 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
506 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
507 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
508 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
509 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
510 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
511 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
512 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
513 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
514 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
515 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
516 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
517 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
518 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
519 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
520 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
521 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
522 { X86::CMPPDrri, X86::CMPPDrmi, 16 },
523 { X86::CMPPSrri, X86::CMPPSrmi, 16 },
524 { X86::CMPSDrr, X86::CMPSDrm, 0 },
525 { X86::CMPSSrr, X86::CMPSSrm, 0 },
526 { X86::DIVPDrr, X86::DIVPDrm, 16 },
527 { X86::DIVPSrr, X86::DIVPSrm, 16 },
528 { X86::DIVSDrr, X86::DIVSDrm, 0 },
529 { X86::DIVSSrr, X86::DIVSSrm, 0 },
530 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 },
531 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 },
532 { X86::FsANDPDrr, X86::FsANDPDrm, 16 },
533 { X86::FsANDPSrr, X86::FsANDPSrm, 16 },
534 { X86::FsORPDrr, X86::FsORPDrm, 16 },
535 { X86::FsORPSrr, X86::FsORPSrm, 16 },
536 { X86::FsXORPDrr, X86::FsXORPDrm, 16 },
537 { X86::FsXORPSrr, X86::FsXORPSrm, 16 },
538 { X86::HADDPDrr, X86::HADDPDrm, 16 },
539 { X86::HADDPSrr, X86::HADDPSrm, 16 },
540 { X86::HSUBPDrr, X86::HSUBPDrm, 16 },
541 { X86::HSUBPSrr, X86::HSUBPSrm, 16 },
542 { X86::IMUL16rr, X86::IMUL16rm, 0 },
543 { X86::IMUL32rr, X86::IMUL32rm, 0 },
544 { X86::IMUL64rr, X86::IMUL64rm, 0 },
545 { X86::MAXPDrr, X86::MAXPDrm, 16 },
546 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 },
547 { X86::MAXPSrr, X86::MAXPSrm, 16 },
548 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 },
549 { X86::MAXSDrr, X86::MAXSDrm, 0 },
550 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
551 { X86::MAXSSrr, X86::MAXSSrm, 0 },
552 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
553 { X86::MINPDrr, X86::MINPDrm, 16 },
554 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 },
555 { X86::MINPSrr, X86::MINPSrm, 16 },
556 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 },
557 { X86::MINSDrr, X86::MINSDrm, 0 },
558 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
559 { X86::MINSSrr, X86::MINSSrm, 0 },
560 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
561 { X86::MULPDrr, X86::MULPDrm, 16 },
562 { X86::MULPSrr, X86::MULPSrm, 16 },
563 { X86::MULSDrr, X86::MULSDrm, 0 },
564 { X86::MULSSrr, X86::MULSSrm, 0 },
565 { X86::OR16rr, X86::OR16rm, 0 },
566 { X86::OR32rr, X86::OR32rm, 0 },
567 { X86::OR64rr, X86::OR64rm, 0 },
568 { X86::OR8rr, X86::OR8rm, 0 },
569 { X86::ORPDrr, X86::ORPDrm, 16 },
570 { X86::ORPSrr, X86::ORPSrm, 16 },
571 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 },
572 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 },
573 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 },
574 { X86::PADDBrr, X86::PADDBrm, 16 },
575 { X86::PADDDrr, X86::PADDDrm, 16 },
576 { X86::PADDQrr, X86::PADDQrm, 16 },
577 { X86::PADDSBrr, X86::PADDSBrm, 16 },
578 { X86::PADDSWrr, X86::PADDSWrm, 16 },
579 { X86::PADDWrr, X86::PADDWrm, 16 },
580 { X86::PANDNrr, X86::PANDNrm, 16 },
581 { X86::PANDrr, X86::PANDrm, 16 },
582 { X86::PAVGBrr, X86::PAVGBrm, 16 },
583 { X86::PAVGWrr, X86::PAVGWrm, 16 },
584 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 },
585 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 },
586 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 },
587 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 },
588 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 },
589 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 },
590 { X86::PINSRWrri, X86::PINSRWrmi, 16 },
591 { X86::PMADDWDrr, X86::PMADDWDrm, 16 },
592 { X86::PMAXSWrr, X86::PMAXSWrm, 16 },
593 { X86::PMAXUBrr, X86::PMAXUBrm, 16 },
594 { X86::PMINSWrr, X86::PMINSWrm, 16 },
595 { X86::PMINUBrr, X86::PMINUBrm, 16 },
596 { X86::PMULDQrr, X86::PMULDQrm, 16 },
597 { X86::PMULHUWrr, X86::PMULHUWrm, 16 },
598 { X86::PMULHWrr, X86::PMULHWrm, 16 },
599 { X86::PMULLDrr, X86::PMULLDrm, 16 },
600 { X86::PMULLDrr_int, X86::PMULLDrm_int, 16 },
601 { X86::PMULLWrr, X86::PMULLWrm, 16 },
602 { X86::PMULUDQrr, X86::PMULUDQrm, 16 },
603 { X86::PORrr, X86::PORrm, 16 },
604 { X86::PSADBWrr, X86::PSADBWrm, 16 },
605 { X86::PSLLDrr, X86::PSLLDrm, 16 },
606 { X86::PSLLQrr, X86::PSLLQrm, 16 },
607 { X86::PSLLWrr, X86::PSLLWrm, 16 },
608 { X86::PSRADrr, X86::PSRADrm, 16 },
609 { X86::PSRAWrr, X86::PSRAWrm, 16 },
610 { X86::PSRLDrr, X86::PSRLDrm, 16 },
611 { X86::PSRLQrr, X86::PSRLQrm, 16 },
612 { X86::PSRLWrr, X86::PSRLWrm, 16 },
613 { X86::PSUBBrr, X86::PSUBBrm, 16 },
614 { X86::PSUBDrr, X86::PSUBDrm, 16 },
615 { X86::PSUBSBrr, X86::PSUBSBrm, 16 },
616 { X86::PSUBSWrr, X86::PSUBSWrm, 16 },
617 { X86::PSUBWrr, X86::PSUBWrm, 16 },
618 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 },
619 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 },
620 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 },
621 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 },
622 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 },
623 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 },
624 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 },
625 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 },
626 { X86::PXORrr, X86::PXORrm, 16 },
627 { X86::SBB32rr, X86::SBB32rm, 0 },
628 { X86::SBB64rr, X86::SBB64rm, 0 },
629 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 },
630 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 },
631 { X86::SUB16rr, X86::SUB16rm, 0 },
632 { X86::SUB32rr, X86::SUB32rm, 0 },
633 { X86::SUB64rr, X86::SUB64rm, 0 },
634 { X86::SUB8rr, X86::SUB8rm, 0 },
635 { X86::SUBPDrr, X86::SUBPDrm, 16 },
636 { X86::SUBPSrr, X86::SUBPSrm, 16 },
637 { X86::SUBSDrr, X86::SUBSDrm, 0 },
638 { X86::SUBSSrr, X86::SUBSSrm, 0 },
639 // FIXME: TEST*rr -> swapped operand of TEST*mr.
640 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 },
641 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 },
642 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 },
643 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 },
644 { X86::XOR16rr, X86::XOR16rm, 0 },
645 { X86::XOR32rr, X86::XOR32rm, 0 },
646 { X86::XOR64rr, X86::XOR64rm, 0 },
647 { X86::XOR8rr, X86::XOR8rm, 0 },
648 { X86::XORPDrr, X86::XORPDrm, 16 },
649 { X86::XORPSrr, X86::XORPSrm, 16 }
652 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
653 unsigned RegOp = OpTbl2[i][0];
654 unsigned MemOp = OpTbl2[i][1];
655 unsigned Align = OpTbl2[i][2];
656 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
657 std::make_pair(MemOp,Align))).second)
658 assert(false && "Duplicated entries?");
659 // Index 2, folded load
660 unsigned AuxInfo = 2 | (1 << 4);
661 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
662 std::make_pair(RegOp, AuxInfo))).second)
663 AmbEntries.push_back(MemOp);
666 // Remove ambiguous entries.
667 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
670 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
671 unsigned &SrcReg, unsigned &DstReg,
672 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
673 switch (MI.getOpcode()) {
677 case X86::MOV8rr_NOREX:
684 // FP Stack register class copies
685 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
686 case X86::MOV_Fp3264: case X86::MOV_Fp3280:
687 case X86::MOV_Fp6432: case X86::MOV_Fp8032:
689 case X86::FsMOVAPSrr:
690 case X86::FsMOVAPDrr:
694 case X86::MOVSS2PSrr:
695 case X86::MOVSD2PDrr:
696 case X86::MOVPS2SSrr:
697 case X86::MOVPD2SDrr:
698 case X86::MMX_MOVQ64rr:
699 assert(MI.getNumOperands() >= 2 &&
700 MI.getOperand(0).isReg() &&
701 MI.getOperand(1).isReg() &&
702 "invalid register-register move instruction");
703 SrcReg = MI.getOperand(1).getReg();
704 DstReg = MI.getOperand(0).getReg();
705 SrcSubIdx = MI.getOperand(1).getSubReg();
706 DstSubIdx = MI.getOperand(0).getSubReg();
711 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
712 int &FrameIndex) const {
713 switch (MI->getOpcode()) {
725 case X86::MMX_MOVD64rm:
726 case X86::MMX_MOVQ64rm:
727 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
728 MI->getOperand(3).isReg() && MI->getOperand(4).isImm() &&
729 MI->getOperand(2).getImm() == 1 &&
730 MI->getOperand(3).getReg() == 0 &&
731 MI->getOperand(4).getImm() == 0) {
732 FrameIndex = MI->getOperand(1).getIndex();
733 return MI->getOperand(0).getReg();
740 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
741 int &FrameIndex) const {
742 switch (MI->getOpcode()) {
754 case X86::MMX_MOVD64mr:
755 case X86::MMX_MOVQ64mr:
756 case X86::MMX_MOVNTQmr:
757 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
758 MI->getOperand(2).isReg() && MI->getOperand(3).isImm() &&
759 MI->getOperand(1).getImm() == 1 &&
760 MI->getOperand(2).getReg() == 0 &&
761 MI->getOperand(3).getImm() == 0) {
762 FrameIndex = MI->getOperand(0).getIndex();
763 return MI->getOperand(X86AddrNumOperands).getReg();
770 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
772 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
773 bool isPICBase = false;
774 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
775 E = MRI.def_end(); I != E; ++I) {
776 MachineInstr *DefMI = I.getOperand().getParent();
777 if (DefMI->getOpcode() != X86::MOVPC32r)
779 assert(!isPICBase && "More than one PIC base?");
785 /// CanRematLoadWithDispOperand - Return true if a load with the specified
786 /// operand is a candidate for remat: for this to be true we need to know that
787 /// the load will always return the same value, even if moved.
788 static bool CanRematLoadWithDispOperand(const MachineOperand &MO,
789 X86TargetMachine &TM) {
790 // Loads from constant pool entries can be remat'd.
791 if (MO.isCPI()) return true;
793 // We can remat globals in some cases.
795 // If this is a load of a stub, not of the global, we can remat it. This
796 // access will always return the address of the global.
797 if (isGlobalStubReference(MO.getTargetFlags()))
800 // If the global itself is constant, we can remat the load.
801 if (GlobalVariable *GV = dyn_cast<GlobalVariable>(MO.getGlobal()))
802 if (GV->isConstant())
809 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
810 switch (MI->getOpcode()) {
822 case X86::MMX_MOVD64rm:
823 case X86::MMX_MOVQ64rm: {
824 // Loads from constant pools are trivially rematerializable.
825 if (MI->getOperand(1).isReg() &&
826 MI->getOperand(2).isImm() &&
827 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
828 CanRematLoadWithDispOperand(MI->getOperand(4), TM)) {
829 unsigned BaseReg = MI->getOperand(1).getReg();
830 if (BaseReg == 0 || BaseReg == X86::RIP)
832 // Allow re-materialization of PIC load.
833 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
835 const MachineFunction &MF = *MI->getParent()->getParent();
836 const MachineRegisterInfo &MRI = MF.getRegInfo();
837 bool isPICBase = false;
838 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
839 E = MRI.def_end(); I != E; ++I) {
840 MachineInstr *DefMI = I.getOperand().getParent();
841 if (DefMI->getOpcode() != X86::MOVPC32r)
843 assert(!isPICBase && "More than one PIC base?");
853 if (MI->getOperand(2).isImm() &&
854 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
855 !MI->getOperand(4).isReg()) {
856 // lea fi#, lea GV, etc. are all rematerializable.
857 if (!MI->getOperand(1).isReg())
859 unsigned BaseReg = MI->getOperand(1).getReg();
862 // Allow re-materialization of lea PICBase + x.
863 const MachineFunction &MF = *MI->getParent()->getParent();
864 const MachineRegisterInfo &MRI = MF.getRegInfo();
865 return regIsPICBase(BaseReg, MRI);
871 // All other instructions marked M_REMATERIALIZABLE are always trivially
876 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
877 /// would clobber the EFLAGS condition register. Note the result may be
878 /// conservative. If it cannot definitely determine the safety after visiting
879 /// two instructions it assumes it's not safe.
880 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
881 MachineBasicBlock::iterator I) {
882 // It's always safe to clobber EFLAGS at the end of a block.
886 // For compile time consideration, if we are not able to determine the
887 // safety after visiting 2 instructions, we will assume it's not safe.
888 for (unsigned i = 0; i < 2; ++i) {
889 bool SeenDef = false;
890 for (unsigned j = 0, e = I->getNumOperands(); j != e; ++j) {
891 MachineOperand &MO = I->getOperand(j);
894 if (MO.getReg() == X86::EFLAGS) {
902 // This instruction defines EFLAGS, no need to look any further.
906 // If we make it to the end of the block, it's safe to clobber EFLAGS.
911 // Conservative answer.
915 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
916 MachineBasicBlock::iterator I,
917 unsigned DestReg, unsigned SubIdx,
918 const MachineInstr *Orig) const {
919 DebugLoc DL = DebugLoc::getUnknownLoc();
920 if (I != MBB.end()) DL = I->getDebugLoc();
922 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
923 DestReg = RI.getSubReg(DestReg, SubIdx);
927 // MOV32r0 etc. are implemented with xor which clobbers condition code.
928 // Re-materialize them as movri instructions to avoid side effects.
930 unsigned Opc = Orig->getOpcode();
936 if (!isSafeToClobberEFLAGS(MBB, I)) {
939 case X86::MOV8r0: Opc = X86::MOV8ri; break;
940 case X86::MOV16r0: Opc = X86::MOV16ri; break;
941 case X86::MOV32r0: Opc = X86::MOV32ri; break;
950 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
951 MI->getOperand(0).setReg(DestReg);
954 BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0);
957 MachineInstr *NewMI = prior(I);
958 NewMI->getOperand(0).setSubReg(SubIdx);
961 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
962 /// is not marked dead.
963 static bool hasLiveCondCodeDef(MachineInstr *MI) {
964 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
965 MachineOperand &MO = MI->getOperand(i);
966 if (MO.isReg() && MO.isDef() &&
967 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
974 /// convertToThreeAddress - This method must be implemented by targets that
975 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
976 /// may be able to convert a two-address instruction into a true
977 /// three-address instruction on demand. This allows the X86 target (for
978 /// example) to convert ADD and SHL instructions into LEA instructions if they
979 /// would require register copies due to two-addressness.
981 /// This method returns a null pointer if the transformation cannot be
982 /// performed, otherwise it returns the new instruction.
985 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
986 MachineBasicBlock::iterator &MBBI,
987 LiveVariables *LV) const {
988 MachineInstr *MI = MBBI;
989 MachineFunction &MF = *MI->getParent()->getParent();
990 // All instructions input are two-addr instructions. Get the known operands.
991 unsigned Dest = MI->getOperand(0).getReg();
992 unsigned Src = MI->getOperand(1).getReg();
993 bool isDead = MI->getOperand(0).isDead();
994 bool isKill = MI->getOperand(1).isKill();
996 MachineInstr *NewMI = NULL;
997 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
998 // we have better subtarget support, enable the 16-bit LEA generation here.
999 bool DisableLEA16 = true;
1001 unsigned MIOpc = MI->getOpcode();
1003 case X86::SHUFPSrri: {
1004 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1005 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1007 unsigned B = MI->getOperand(1).getReg();
1008 unsigned C = MI->getOperand(2).getReg();
1009 if (B != C) return 0;
1010 unsigned A = MI->getOperand(0).getReg();
1011 unsigned M = MI->getOperand(3).getImm();
1012 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1013 .addReg(A, RegState::Define | getDeadRegState(isDead))
1014 .addReg(B, getKillRegState(isKill)).addImm(M);
1017 case X86::SHL64ri: {
1018 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1019 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1020 // the flags produced by a shift yet, so this is safe.
1021 unsigned ShAmt = MI->getOperand(2).getImm();
1022 if (ShAmt == 0 || ShAmt >= 4) return 0;
1024 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1025 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1026 .addReg(0).addImm(1 << ShAmt)
1027 .addReg(Src, getKillRegState(isKill))
1031 case X86::SHL32ri: {
1032 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1033 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1034 // the flags produced by a shift yet, so this is safe.
1035 unsigned ShAmt = MI->getOperand(2).getImm();
1036 if (ShAmt == 0 || ShAmt >= 4) return 0;
1038 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
1039 X86::LEA64_32r : X86::LEA32r;
1040 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1041 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1042 .addReg(0).addImm(1 << ShAmt)
1043 .addReg(Src, getKillRegState(isKill)).addImm(0);
1046 case X86::SHL16ri: {
1047 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1048 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1049 // the flags produced by a shift yet, so this is safe.
1050 unsigned ShAmt = MI->getOperand(2).getImm();
1051 if (ShAmt == 0 || ShAmt >= 4) return 0;
1054 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
1055 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1056 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1057 ? X86::LEA64_32r : X86::LEA32r;
1058 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1059 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1061 // Build and insert into an implicit UNDEF value. This is OK because
1062 // well be shifting and then extracting the lower 16-bits.
1063 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1064 MachineInstr *InsMI =
1065 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
1067 .addReg(Src, getKillRegState(isKill))
1068 .addImm(X86::SUBREG_16BIT);
1070 NewMI = BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(Opc), leaOutReg)
1071 .addReg(0).addImm(1 << ShAmt)
1072 .addReg(leaInReg, RegState::Kill)
1075 MachineInstr *ExtMI =
1076 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
1077 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1078 .addReg(leaOutReg, RegState::Kill)
1079 .addImm(X86::SUBREG_16BIT);
1082 // Update live variables
1083 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1084 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1086 LV->replaceKillInstruction(Src, MI, InsMI);
1088 LV->replaceKillInstruction(Dest, MI, ExtMI);
1092 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1093 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1094 .addReg(0).addImm(1 << ShAmt)
1095 .addReg(Src, getKillRegState(isKill))
1101 // The following opcodes also sets the condition code register(s). Only
1102 // convert them to equivalent lea if the condition code register def's
1104 if (hasLiveCondCodeDef(MI))
1107 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1112 case X86::INC64_32r: {
1113 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1114 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1115 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1116 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1117 .addReg(Dest, RegState::Define |
1118 getDeadRegState(isDead)),
1123 case X86::INC64_16r:
1124 if (DisableLEA16) return 0;
1125 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1126 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1127 .addReg(Dest, RegState::Define |
1128 getDeadRegState(isDead)),
1133 case X86::DEC64_32r: {
1134 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1135 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1136 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1137 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1138 .addReg(Dest, RegState::Define |
1139 getDeadRegState(isDead)),
1144 case X86::DEC64_16r:
1145 if (DisableLEA16) return 0;
1146 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1147 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1148 .addReg(Dest, RegState::Define |
1149 getDeadRegState(isDead)),
1153 case X86::ADD32rr: {
1154 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1155 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1156 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1157 unsigned Src2 = MI->getOperand(2).getReg();
1158 bool isKill2 = MI->getOperand(2).isKill();
1159 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1160 .addReg(Dest, RegState::Define |
1161 getDeadRegState(isDead)),
1162 Src, isKill, Src2, isKill2);
1164 LV->replaceKillInstruction(Src2, MI, NewMI);
1167 case X86::ADD16rr: {
1168 if (DisableLEA16) return 0;
1169 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1170 unsigned Src2 = MI->getOperand(2).getReg();
1171 bool isKill2 = MI->getOperand(2).isKill();
1172 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1173 .addReg(Dest, RegState::Define |
1174 getDeadRegState(isDead)),
1175 Src, isKill, Src2, isKill2);
1177 LV->replaceKillInstruction(Src2, MI, NewMI);
1180 case X86::ADD64ri32:
1182 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1183 if (MI->getOperand(2).isImm())
1184 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1185 .addReg(Dest, RegState::Define |
1186 getDeadRegState(isDead)),
1187 Src, isKill, MI->getOperand(2).getImm());
1191 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1192 if (MI->getOperand(2).isImm()) {
1193 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1194 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1195 .addReg(Dest, RegState::Define |
1196 getDeadRegState(isDead)),
1197 Src, isKill, MI->getOperand(2).getImm());
1202 if (DisableLEA16) return 0;
1203 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1204 if (MI->getOperand(2).isImm())
1205 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1206 .addReg(Dest, RegState::Define |
1207 getDeadRegState(isDead)),
1208 Src, isKill, MI->getOperand(2).getImm());
1211 if (DisableLEA16) return 0;
1213 case X86::SHL64ri: {
1214 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImm() &&
1215 "Unknown shl instruction!");
1216 unsigned ShAmt = MI->getOperand(2).getImm();
1217 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
1219 AM.Scale = 1 << ShAmt;
1221 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
1222 : (MIOpc == X86::SHL32ri
1223 ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
1224 NewMI = addFullAddress(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1225 .addReg(Dest, RegState::Define |
1226 getDeadRegState(isDead)), AM);
1228 NewMI->getOperand(3).setIsKill(true);
1236 if (!NewMI) return 0;
1238 if (LV) { // Update live variables
1240 LV->replaceKillInstruction(Src, MI, NewMI);
1242 LV->replaceKillInstruction(Dest, MI, NewMI);
1245 MFI->insert(MBBI, NewMI); // Insert the new inst
1249 /// commuteInstruction - We have a few instructions that must be hacked on to
1253 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1254 switch (MI->getOpcode()) {
1255 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1256 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1257 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1258 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1259 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1260 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1263 switch (MI->getOpcode()) {
1264 default: llvm_unreachable("Unreachable!");
1265 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1266 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1267 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1268 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1269 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1270 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1272 unsigned Amt = MI->getOperand(3).getImm();
1274 MachineFunction &MF = *MI->getParent()->getParent();
1275 MI = MF.CloneMachineInstr(MI);
1278 MI->setDesc(get(Opc));
1279 MI->getOperand(3).setImm(Size-Amt);
1280 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1282 case X86::CMOVB16rr:
1283 case X86::CMOVB32rr:
1284 case X86::CMOVB64rr:
1285 case X86::CMOVAE16rr:
1286 case X86::CMOVAE32rr:
1287 case X86::CMOVAE64rr:
1288 case X86::CMOVE16rr:
1289 case X86::CMOVE32rr:
1290 case X86::CMOVE64rr:
1291 case X86::CMOVNE16rr:
1292 case X86::CMOVNE32rr:
1293 case X86::CMOVNE64rr:
1294 case X86::CMOVBE16rr:
1295 case X86::CMOVBE32rr:
1296 case X86::CMOVBE64rr:
1297 case X86::CMOVA16rr:
1298 case X86::CMOVA32rr:
1299 case X86::CMOVA64rr:
1300 case X86::CMOVL16rr:
1301 case X86::CMOVL32rr:
1302 case X86::CMOVL64rr:
1303 case X86::CMOVGE16rr:
1304 case X86::CMOVGE32rr:
1305 case X86::CMOVGE64rr:
1306 case X86::CMOVLE16rr:
1307 case X86::CMOVLE32rr:
1308 case X86::CMOVLE64rr:
1309 case X86::CMOVG16rr:
1310 case X86::CMOVG32rr:
1311 case X86::CMOVG64rr:
1312 case X86::CMOVS16rr:
1313 case X86::CMOVS32rr:
1314 case X86::CMOVS64rr:
1315 case X86::CMOVNS16rr:
1316 case X86::CMOVNS32rr:
1317 case X86::CMOVNS64rr:
1318 case X86::CMOVP16rr:
1319 case X86::CMOVP32rr:
1320 case X86::CMOVP64rr:
1321 case X86::CMOVNP16rr:
1322 case X86::CMOVNP32rr:
1323 case X86::CMOVNP64rr:
1324 case X86::CMOVO16rr:
1325 case X86::CMOVO32rr:
1326 case X86::CMOVO64rr:
1327 case X86::CMOVNO16rr:
1328 case X86::CMOVNO32rr:
1329 case X86::CMOVNO64rr: {
1331 switch (MI->getOpcode()) {
1333 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1334 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1335 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1336 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1337 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1338 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1339 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1340 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1341 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1342 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1343 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1344 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1345 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1346 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1347 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1348 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1349 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1350 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1351 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1352 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1353 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1354 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1355 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1356 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1357 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1358 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1359 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1360 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1361 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1362 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1363 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1364 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1365 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1366 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1367 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1368 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1369 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1370 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1371 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1372 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1373 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1374 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1375 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1376 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1377 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1378 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1379 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1380 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1383 MachineFunction &MF = *MI->getParent()->getParent();
1384 MI = MF.CloneMachineInstr(MI);
1387 MI->setDesc(get(Opc));
1388 // Fallthrough intended.
1391 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1395 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1397 default: return X86::COND_INVALID;
1398 case X86::JE: return X86::COND_E;
1399 case X86::JNE: return X86::COND_NE;
1400 case X86::JL: return X86::COND_L;
1401 case X86::JLE: return X86::COND_LE;
1402 case X86::JG: return X86::COND_G;
1403 case X86::JGE: return X86::COND_GE;
1404 case X86::JB: return X86::COND_B;
1405 case X86::JBE: return X86::COND_BE;
1406 case X86::JA: return X86::COND_A;
1407 case X86::JAE: return X86::COND_AE;
1408 case X86::JS: return X86::COND_S;
1409 case X86::JNS: return X86::COND_NS;
1410 case X86::JP: return X86::COND_P;
1411 case X86::JNP: return X86::COND_NP;
1412 case X86::JO: return X86::COND_O;
1413 case X86::JNO: return X86::COND_NO;
1417 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1419 default: llvm_unreachable("Illegal condition code!");
1420 case X86::COND_E: return X86::JE;
1421 case X86::COND_NE: return X86::JNE;
1422 case X86::COND_L: return X86::JL;
1423 case X86::COND_LE: return X86::JLE;
1424 case X86::COND_G: return X86::JG;
1425 case X86::COND_GE: return X86::JGE;
1426 case X86::COND_B: return X86::JB;
1427 case X86::COND_BE: return X86::JBE;
1428 case X86::COND_A: return X86::JA;
1429 case X86::COND_AE: return X86::JAE;
1430 case X86::COND_S: return X86::JS;
1431 case X86::COND_NS: return X86::JNS;
1432 case X86::COND_P: return X86::JP;
1433 case X86::COND_NP: return X86::JNP;
1434 case X86::COND_O: return X86::JO;
1435 case X86::COND_NO: return X86::JNO;
1439 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1440 /// e.g. turning COND_E to COND_NE.
1441 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1443 default: llvm_unreachable("Illegal condition code!");
1444 case X86::COND_E: return X86::COND_NE;
1445 case X86::COND_NE: return X86::COND_E;
1446 case X86::COND_L: return X86::COND_GE;
1447 case X86::COND_LE: return X86::COND_G;
1448 case X86::COND_G: return X86::COND_LE;
1449 case X86::COND_GE: return X86::COND_L;
1450 case X86::COND_B: return X86::COND_AE;
1451 case X86::COND_BE: return X86::COND_A;
1452 case X86::COND_A: return X86::COND_BE;
1453 case X86::COND_AE: return X86::COND_B;
1454 case X86::COND_S: return X86::COND_NS;
1455 case X86::COND_NS: return X86::COND_S;
1456 case X86::COND_P: return X86::COND_NP;
1457 case X86::COND_NP: return X86::COND_P;
1458 case X86::COND_O: return X86::COND_NO;
1459 case X86::COND_NO: return X86::COND_O;
1463 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1464 const TargetInstrDesc &TID = MI->getDesc();
1465 if (!TID.isTerminator()) return false;
1467 // Conditional branch is a special case.
1468 if (TID.isBranch() && !TID.isBarrier())
1470 if (!TID.isPredicable())
1472 return !isPredicated(MI);
1475 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1476 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1477 const X86InstrInfo &TII) {
1478 if (MI->getOpcode() == X86::FP_REG_KILL)
1480 return TII.isUnpredicatedTerminator(MI);
1483 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1484 MachineBasicBlock *&TBB,
1485 MachineBasicBlock *&FBB,
1486 SmallVectorImpl<MachineOperand> &Cond,
1487 bool AllowModify) const {
1488 // Start from the bottom of the block and work up, examining the
1489 // terminator instructions.
1490 MachineBasicBlock::iterator I = MBB.end();
1491 while (I != MBB.begin()) {
1493 // Working from the bottom, when we see a non-terminator
1494 // instruction, we're done.
1495 if (!isBrAnalysisUnpredicatedTerminator(I, *this))
1497 // A terminator that isn't a branch can't easily be handled
1498 // by this analysis.
1499 if (!I->getDesc().isBranch())
1501 // Handle unconditional branches.
1502 if (I->getOpcode() == X86::JMP) {
1504 TBB = I->getOperand(0).getMBB();
1508 // If the block has any instructions after a JMP, delete them.
1509 while (next(I) != MBB.end())
1510 next(I)->eraseFromParent();
1513 // Delete the JMP if it's equivalent to a fall-through.
1514 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1516 I->eraseFromParent();
1520 // TBB is used to indicate the unconditinal destination.
1521 TBB = I->getOperand(0).getMBB();
1524 // Handle conditional branches.
1525 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1526 if (BranchCode == X86::COND_INVALID)
1527 return true; // Can't handle indirect branch.
1528 // Working from the bottom, handle the first conditional branch.
1531 TBB = I->getOperand(0).getMBB();
1532 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1535 // Handle subsequent conditional branches. Only handle the case
1536 // where all conditional branches branch to the same destination
1537 // and their condition opcodes fit one of the special
1538 // multi-branch idioms.
1539 assert(Cond.size() == 1);
1541 // Only handle the case where all conditional branches branch to
1542 // the same destination.
1543 if (TBB != I->getOperand(0).getMBB())
1545 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1546 // If the conditions are the same, we can leave them alone.
1547 if (OldBranchCode == BranchCode)
1549 // If they differ, see if they fit one of the known patterns.
1550 // Theoretically we could handle more patterns here, but
1551 // we shouldn't expect to see them if instruction selection
1552 // has done a reasonable job.
1553 if ((OldBranchCode == X86::COND_NP &&
1554 BranchCode == X86::COND_E) ||
1555 (OldBranchCode == X86::COND_E &&
1556 BranchCode == X86::COND_NP))
1557 BranchCode = X86::COND_NP_OR_E;
1558 else if ((OldBranchCode == X86::COND_P &&
1559 BranchCode == X86::COND_NE) ||
1560 (OldBranchCode == X86::COND_NE &&
1561 BranchCode == X86::COND_P))
1562 BranchCode = X86::COND_NE_OR_P;
1565 // Update the MachineOperand.
1566 Cond[0].setImm(BranchCode);
1572 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1573 MachineBasicBlock::iterator I = MBB.end();
1576 while (I != MBB.begin()) {
1578 if (I->getOpcode() != X86::JMP &&
1579 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1581 // Remove the branch.
1582 I->eraseFromParent();
1591 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1592 MachineBasicBlock *FBB,
1593 const SmallVectorImpl<MachineOperand> &Cond) const {
1594 // FIXME this should probably have a DebugLoc operand
1595 DebugLoc dl = DebugLoc::getUnknownLoc();
1596 // Shouldn't be a fall through.
1597 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1598 assert((Cond.size() == 1 || Cond.size() == 0) &&
1599 "X86 branch conditions have one component!");
1602 // Unconditional branch?
1603 assert(!FBB && "Unconditional branch with multiple successors!");
1604 BuildMI(&MBB, dl, get(X86::JMP)).addMBB(TBB);
1608 // Conditional branch.
1610 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1612 case X86::COND_NP_OR_E:
1613 // Synthesize NP_OR_E with two branches.
1614 BuildMI(&MBB, dl, get(X86::JNP)).addMBB(TBB);
1616 BuildMI(&MBB, dl, get(X86::JE)).addMBB(TBB);
1619 case X86::COND_NE_OR_P:
1620 // Synthesize NE_OR_P with two branches.
1621 BuildMI(&MBB, dl, get(X86::JNE)).addMBB(TBB);
1623 BuildMI(&MBB, dl, get(X86::JP)).addMBB(TBB);
1627 unsigned Opc = GetCondBranchFromCond(CC);
1628 BuildMI(&MBB, dl, get(Opc)).addMBB(TBB);
1633 // Two-way Conditional branch. Insert the second branch.
1634 BuildMI(&MBB, dl, get(X86::JMP)).addMBB(FBB);
1640 /// isHReg - Test if the given register is a physical h register.
1641 static bool isHReg(unsigned Reg) {
1642 return X86::GR8_ABCD_HRegClass.contains(Reg);
1645 bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1646 MachineBasicBlock::iterator MI,
1647 unsigned DestReg, unsigned SrcReg,
1648 const TargetRegisterClass *DestRC,
1649 const TargetRegisterClass *SrcRC) const {
1650 DebugLoc DL = DebugLoc::getUnknownLoc();
1651 if (MI != MBB.end()) DL = MI->getDebugLoc();
1653 // Determine if DstRC and SrcRC have a common superclass in common.
1654 const TargetRegisterClass *CommonRC = DestRC;
1655 if (DestRC == SrcRC)
1656 /* Source and destination have the same register class. */;
1657 else if (CommonRC->hasSuperClass(SrcRC))
1659 else if (!DestRC->hasSubClass(SrcRC)) {
1660 // Neither of GR64_NOREX or GR64_NOSP is a superclass of the other,
1661 // but we want to copy then as GR64. Similarly, for GR32_NOREX and
1662 // GR32_NOSP, copy as GR32.
1663 if (SrcRC->hasSuperClass(&X86::GR64RegClass) &&
1664 DestRC->hasSuperClass(&X86::GR64RegClass))
1665 CommonRC = &X86::GR64RegClass;
1666 else if (SrcRC->hasSuperClass(&X86::GR32RegClass) &&
1667 DestRC->hasSuperClass(&X86::GR32RegClass))
1668 CommonRC = &X86::GR32RegClass;
1675 if (CommonRC == &X86::GR64RegClass || CommonRC == &X86::GR64_NOSPRegClass) {
1677 } else if (CommonRC == &X86::GR32RegClass ||
1678 CommonRC == &X86::GR32_NOSPRegClass) {
1680 } else if (CommonRC == &X86::GR16RegClass) {
1682 } else if (CommonRC == &X86::GR8RegClass) {
1683 // Copying to or from a physical H register on x86-64 requires a NOREX
1684 // move. Otherwise use a normal move.
1685 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
1686 TM.getSubtarget<X86Subtarget>().is64Bit())
1687 Opc = X86::MOV8rr_NOREX;
1690 } else if (CommonRC == &X86::GR64_ABCDRegClass) {
1692 } else if (CommonRC == &X86::GR32_ABCDRegClass) {
1694 } else if (CommonRC == &X86::GR16_ABCDRegClass) {
1696 } else if (CommonRC == &X86::GR8_ABCD_LRegClass) {
1698 } else if (CommonRC == &X86::GR8_ABCD_HRegClass) {
1699 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1700 Opc = X86::MOV8rr_NOREX;
1703 } else if (CommonRC == &X86::GR64_NOREXRegClass ||
1704 CommonRC == &X86::GR64_NOREX_NOSPRegClass) {
1706 } else if (CommonRC == &X86::GR32_NOREXRegClass) {
1708 } else if (CommonRC == &X86::GR16_NOREXRegClass) {
1710 } else if (CommonRC == &X86::GR8_NOREXRegClass) {
1712 } else if (CommonRC == &X86::RFP32RegClass) {
1713 Opc = X86::MOV_Fp3232;
1714 } else if (CommonRC == &X86::RFP64RegClass || CommonRC == &X86::RSTRegClass) {
1715 Opc = X86::MOV_Fp6464;
1716 } else if (CommonRC == &X86::RFP80RegClass) {
1717 Opc = X86::MOV_Fp8080;
1718 } else if (CommonRC == &X86::FR32RegClass) {
1719 Opc = X86::FsMOVAPSrr;
1720 } else if (CommonRC == &X86::FR64RegClass) {
1721 Opc = X86::FsMOVAPDrr;
1722 } else if (CommonRC == &X86::VR128RegClass) {
1723 Opc = X86::MOVAPSrr;
1724 } else if (CommonRC == &X86::VR64RegClass) {
1725 Opc = X86::MMX_MOVQ64rr;
1729 BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg);
1733 // Moving EFLAGS to / from another register requires a push and a pop.
1734 if (SrcRC == &X86::CCRRegClass) {
1735 if (SrcReg != X86::EFLAGS)
1737 if (DestRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1738 BuildMI(MBB, MI, DL, get(X86::PUSHFQ));
1739 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1741 } else if (DestRC == &X86::GR32RegClass ||
1742 DestRC == &X86::GR32_NOSPRegClass) {
1743 BuildMI(MBB, MI, DL, get(X86::PUSHFD));
1744 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
1747 } else if (DestRC == &X86::CCRRegClass) {
1748 if (DestReg != X86::EFLAGS)
1750 if (SrcRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1751 BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
1752 BuildMI(MBB, MI, DL, get(X86::POPFQ));
1754 } else if (SrcRC == &X86::GR32RegClass ||
1755 DestRC == &X86::GR32_NOSPRegClass) {
1756 BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
1757 BuildMI(MBB, MI, DL, get(X86::POPFD));
1762 // Moving from ST(0) turns into FpGET_ST0_32 etc.
1763 if (SrcRC == &X86::RSTRegClass) {
1764 // Copying from ST(0)/ST(1).
1765 if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
1766 // Can only copy from ST(0)/ST(1) right now
1768 bool isST0 = SrcReg == X86::ST0;
1770 if (DestRC == &X86::RFP32RegClass)
1771 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
1772 else if (DestRC == &X86::RFP64RegClass)
1773 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
1775 if (DestRC != &X86::RFP80RegClass)
1777 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
1779 BuildMI(MBB, MI, DL, get(Opc), DestReg);
1783 // Moving to ST(0) turns into FpSET_ST0_32 etc.
1784 if (DestRC == &X86::RSTRegClass) {
1785 // Copying to ST(0) / ST(1).
1786 if (DestReg != X86::ST0 && DestReg != X86::ST1)
1787 // Can only copy to TOS right now
1789 bool isST0 = DestReg == X86::ST0;
1791 if (SrcRC == &X86::RFP32RegClass)
1792 Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32;
1793 else if (SrcRC == &X86::RFP64RegClass)
1794 Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64;
1796 if (SrcRC != &X86::RFP80RegClass)
1798 Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80;
1800 BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg);
1804 // Not yet supported!
1808 static unsigned getStoreRegOpcode(unsigned SrcReg,
1809 const TargetRegisterClass *RC,
1810 bool isStackAligned,
1811 TargetMachine &TM) {
1813 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
1815 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
1817 } else if (RC == &X86::GR16RegClass) {
1819 } else if (RC == &X86::GR8RegClass) {
1820 // Copying to or from a physical H register on x86-64 requires a NOREX
1821 // move. Otherwise use a normal move.
1822 if (isHReg(SrcReg) &&
1823 TM.getSubtarget<X86Subtarget>().is64Bit())
1824 Opc = X86::MOV8mr_NOREX;
1827 } else if (RC == &X86::GR64_ABCDRegClass) {
1829 } else if (RC == &X86::GR32_ABCDRegClass) {
1831 } else if (RC == &X86::GR16_ABCDRegClass) {
1833 } else if (RC == &X86::GR8_ABCD_LRegClass) {
1835 } else if (RC == &X86::GR8_ABCD_HRegClass) {
1836 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1837 Opc = X86::MOV8mr_NOREX;
1840 } else if (RC == &X86::GR64_NOREXRegClass ||
1841 RC == &X86::GR64_NOREX_NOSPRegClass) {
1843 } else if (RC == &X86::GR32_NOREXRegClass) {
1845 } else if (RC == &X86::GR16_NOREXRegClass) {
1847 } else if (RC == &X86::GR8_NOREXRegClass) {
1849 } else if (RC == &X86::RFP80RegClass) {
1850 Opc = X86::ST_FpP80m; // pops
1851 } else if (RC == &X86::RFP64RegClass) {
1852 Opc = X86::ST_Fp64m;
1853 } else if (RC == &X86::RFP32RegClass) {
1854 Opc = X86::ST_Fp32m;
1855 } else if (RC == &X86::FR32RegClass) {
1857 } else if (RC == &X86::FR64RegClass) {
1859 } else if (RC == &X86::VR128RegClass) {
1860 // If stack is realigned we can use aligned stores.
1861 Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr;
1862 } else if (RC == &X86::VR64RegClass) {
1863 Opc = X86::MMX_MOVQ64mr;
1865 llvm_unreachable("Unknown regclass");
1871 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1872 MachineBasicBlock::iterator MI,
1873 unsigned SrcReg, bool isKill, int FrameIdx,
1874 const TargetRegisterClass *RC) const {
1875 const MachineFunction &MF = *MBB.getParent();
1876 bool isAligned = (RI.getStackAlignment() >= 16) ||
1877 RI.needsStackRealignment(MF);
1878 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
1879 DebugLoc DL = DebugLoc::getUnknownLoc();
1880 if (MI != MBB.end()) DL = MI->getDebugLoc();
1881 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
1882 .addReg(SrcReg, getKillRegState(isKill));
1885 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
1887 SmallVectorImpl<MachineOperand> &Addr,
1888 const TargetRegisterClass *RC,
1889 MachineInstr::mmo_iterator MMOBegin,
1890 MachineInstr::mmo_iterator MMOEnd,
1891 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1892 bool isAligned = (RI.getStackAlignment() >= 16) ||
1893 RI.needsStackRealignment(MF);
1894 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
1895 DebugLoc DL = DebugLoc::getUnknownLoc();
1896 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
1897 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1898 MIB.addOperand(Addr[i]);
1899 MIB.addReg(SrcReg, getKillRegState(isKill));
1900 (*MIB).setMemRefs(MMOBegin, MMOEnd);
1901 NewMIs.push_back(MIB);
1904 static unsigned getLoadRegOpcode(unsigned DestReg,
1905 const TargetRegisterClass *RC,
1906 bool isStackAligned,
1907 const TargetMachine &TM) {
1909 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
1911 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
1913 } else if (RC == &X86::GR16RegClass) {
1915 } else if (RC == &X86::GR8RegClass) {
1916 // Copying to or from a physical H register on x86-64 requires a NOREX
1917 // move. Otherwise use a normal move.
1918 if (isHReg(DestReg) &&
1919 TM.getSubtarget<X86Subtarget>().is64Bit())
1920 Opc = X86::MOV8rm_NOREX;
1923 } else if (RC == &X86::GR64_ABCDRegClass) {
1925 } else if (RC == &X86::GR32_ABCDRegClass) {
1927 } else if (RC == &X86::GR16_ABCDRegClass) {
1929 } else if (RC == &X86::GR8_ABCD_LRegClass) {
1931 } else if (RC == &X86::GR8_ABCD_HRegClass) {
1932 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1933 Opc = X86::MOV8rm_NOREX;
1936 } else if (RC == &X86::GR64_NOREXRegClass ||
1937 RC == &X86::GR64_NOREX_NOSPRegClass) {
1939 } else if (RC == &X86::GR32_NOREXRegClass) {
1941 } else if (RC == &X86::GR16_NOREXRegClass) {
1943 } else if (RC == &X86::GR8_NOREXRegClass) {
1945 } else if (RC == &X86::RFP80RegClass) {
1946 Opc = X86::LD_Fp80m;
1947 } else if (RC == &X86::RFP64RegClass) {
1948 Opc = X86::LD_Fp64m;
1949 } else if (RC == &X86::RFP32RegClass) {
1950 Opc = X86::LD_Fp32m;
1951 } else if (RC == &X86::FR32RegClass) {
1953 } else if (RC == &X86::FR64RegClass) {
1955 } else if (RC == &X86::VR128RegClass) {
1956 // If stack is realigned we can use aligned loads.
1957 Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm;
1958 } else if (RC == &X86::VR64RegClass) {
1959 Opc = X86::MMX_MOVQ64rm;
1961 llvm_unreachable("Unknown regclass");
1967 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1968 MachineBasicBlock::iterator MI,
1969 unsigned DestReg, int FrameIdx,
1970 const TargetRegisterClass *RC) const{
1971 const MachineFunction &MF = *MBB.getParent();
1972 bool isAligned = (RI.getStackAlignment() >= 16) ||
1973 RI.needsStackRealignment(MF);
1974 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
1975 DebugLoc DL = DebugLoc::getUnknownLoc();
1976 if (MI != MBB.end()) DL = MI->getDebugLoc();
1977 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
1980 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
1981 SmallVectorImpl<MachineOperand> &Addr,
1982 const TargetRegisterClass *RC,
1983 MachineInstr::mmo_iterator MMOBegin,
1984 MachineInstr::mmo_iterator MMOEnd,
1985 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1986 bool isAligned = (RI.getStackAlignment() >= 16) ||
1987 RI.needsStackRealignment(MF);
1988 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
1989 DebugLoc DL = DebugLoc::getUnknownLoc();
1990 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
1991 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1992 MIB.addOperand(Addr[i]);
1993 (*MIB).setMemRefs(MMOBegin, MMOEnd);
1994 NewMIs.push_back(MIB);
1997 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1998 MachineBasicBlock::iterator MI,
1999 const std::vector<CalleeSavedInfo> &CSI) const {
2003 DebugLoc DL = DebugLoc::getUnknownLoc();
2004 if (MI != MBB.end()) DL = MI->getDebugLoc();
2006 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2007 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2008 unsigned SlotSize = is64Bit ? 8 : 4;
2010 MachineFunction &MF = *MBB.getParent();
2011 unsigned FPReg = RI.getFrameRegister(MF);
2012 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2013 unsigned CalleeFrameSize = 0;
2015 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
2016 for (unsigned i = CSI.size(); i != 0; --i) {
2017 unsigned Reg = CSI[i-1].getReg();
2018 const TargetRegisterClass *RegClass = CSI[i-1].getRegClass();
2019 // Add the callee-saved register as live-in. It's killed at the spill.
2022 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
2024 if (RegClass != &X86::VR128RegClass && !isWin64) {
2025 CalleeFrameSize += SlotSize;
2026 BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
2028 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass);
2032 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
2036 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
2037 MachineBasicBlock::iterator MI,
2038 const std::vector<CalleeSavedInfo> &CSI) const {
2042 DebugLoc DL = DebugLoc::getUnknownLoc();
2043 if (MI != MBB.end()) DL = MI->getDebugLoc();
2045 MachineFunction &MF = *MBB.getParent();
2046 unsigned FPReg = RI.getFrameRegister(MF);
2047 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2048 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2049 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
2050 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2051 unsigned Reg = CSI[i].getReg();
2053 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
2055 const TargetRegisterClass *RegClass = CSI[i].getRegClass();
2056 if (RegClass != &X86::VR128RegClass && !isWin64) {
2057 BuildMI(MBB, MI, DL, get(Opc), Reg);
2059 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
2065 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2066 const SmallVectorImpl<MachineOperand> &MOs,
2068 const TargetInstrInfo &TII) {
2069 // Create the base instruction with the memory operand as the first part.
2070 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2071 MI->getDebugLoc(), true);
2072 MachineInstrBuilder MIB(NewMI);
2073 unsigned NumAddrOps = MOs.size();
2074 for (unsigned i = 0; i != NumAddrOps; ++i)
2075 MIB.addOperand(MOs[i]);
2076 if (NumAddrOps < 4) // FrameIndex only
2079 // Loop over the rest of the ri operands, converting them over.
2080 unsigned NumOps = MI->getDesc().getNumOperands()-2;
2081 for (unsigned i = 0; i != NumOps; ++i) {
2082 MachineOperand &MO = MI->getOperand(i+2);
2085 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2086 MachineOperand &MO = MI->getOperand(i);
2092 static MachineInstr *FuseInst(MachineFunction &MF,
2093 unsigned Opcode, unsigned OpNo,
2094 const SmallVectorImpl<MachineOperand> &MOs,
2095 MachineInstr *MI, const TargetInstrInfo &TII) {
2096 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2097 MI->getDebugLoc(), true);
2098 MachineInstrBuilder MIB(NewMI);
2100 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2101 MachineOperand &MO = MI->getOperand(i);
2103 assert(MO.isReg() && "Expected to fold into reg operand!");
2104 unsigned NumAddrOps = MOs.size();
2105 for (unsigned i = 0; i != NumAddrOps; ++i)
2106 MIB.addOperand(MOs[i]);
2107 if (NumAddrOps < 4) // FrameIndex only
2116 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2117 const SmallVectorImpl<MachineOperand> &MOs,
2119 MachineFunction &MF = *MI->getParent()->getParent();
2120 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2122 unsigned NumAddrOps = MOs.size();
2123 for (unsigned i = 0; i != NumAddrOps; ++i)
2124 MIB.addOperand(MOs[i]);
2125 if (NumAddrOps < 4) // FrameIndex only
2127 return MIB.addImm(0);
2131 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2132 MachineInstr *MI, unsigned i,
2133 const SmallVectorImpl<MachineOperand> &MOs,
2134 unsigned Size, unsigned Align) const {
2135 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2136 bool isTwoAddrFold = false;
2137 unsigned NumOps = MI->getDesc().getNumOperands();
2138 bool isTwoAddr = NumOps > 1 &&
2139 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2141 MachineInstr *NewMI = NULL;
2142 // Folding a memory location into the two-address part of a two-address
2143 // instruction is different than folding it other places. It requires
2144 // replacing the *two* registers with the memory location.
2145 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2146 MI->getOperand(0).isReg() &&
2147 MI->getOperand(1).isReg() &&
2148 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2149 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2150 isTwoAddrFold = true;
2151 } else if (i == 0) { // If operand 0
2152 if (MI->getOpcode() == X86::MOV16r0)
2153 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2154 else if (MI->getOpcode() == X86::MOV32r0)
2155 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2156 else if (MI->getOpcode() == X86::MOV8r0)
2157 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2161 OpcodeTablePtr = &RegOp2MemOpTable0;
2162 } else if (i == 1) {
2163 OpcodeTablePtr = &RegOp2MemOpTable1;
2164 } else if (i == 2) {
2165 OpcodeTablePtr = &RegOp2MemOpTable2;
2168 // If table selected...
2169 if (OpcodeTablePtr) {
2170 // Find the Opcode to fuse
2171 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2172 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
2173 if (I != OpcodeTablePtr->end()) {
2174 unsigned Opcode = I->second.first;
2175 unsigned MinAlign = I->second.second;
2176 if (Align < MinAlign)
2178 bool NarrowToMOV32rm = false;
2180 unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize();
2181 if (Size < RCSize) {
2182 // Check if it's safe to fold the load. If the size of the object is
2183 // narrower than the load width, then it's not.
2184 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2186 // If this is a 64-bit load, but the spill slot is 32, then we can do
2187 // a 32-bit load which is implicitly zero-extended. This likely is due
2188 // to liveintervalanalysis remat'ing a load from stack slot.
2189 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2191 Opcode = X86::MOV32rm;
2192 NarrowToMOV32rm = true;
2197 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2199 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2201 if (NarrowToMOV32rm) {
2202 // If this is the special case where we use a MOV32rm to load a 32-bit
2203 // value and zero-extend the top bits. Change the destination register
2205 unsigned DstReg = NewMI->getOperand(0).getReg();
2206 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2207 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2208 4/*x86_subreg_32bit*/));
2210 NewMI->getOperand(0).setSubReg(4/*x86_subreg_32bit*/);
2217 if (PrintFailedFusing)
2218 errs() << "We failed to fuse operand " << i << " in " << *MI;
2223 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2225 const SmallVectorImpl<unsigned> &Ops,
2226 int FrameIndex) const {
2227 // Check switch flag
2228 if (NoFusing) return NULL;
2230 const MachineFrameInfo *MFI = MF.getFrameInfo();
2231 unsigned Size = MFI->getObjectSize(FrameIndex);
2232 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2233 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2234 unsigned NewOpc = 0;
2235 unsigned RCSize = 0;
2236 switch (MI->getOpcode()) {
2237 default: return NULL;
2238 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
2239 case X86::TEST16rr: NewOpc = X86::CMP16ri; RCSize = 2; break;
2240 case X86::TEST32rr: NewOpc = X86::CMP32ri; RCSize = 4; break;
2241 case X86::TEST64rr: NewOpc = X86::CMP64ri32; RCSize = 8; break;
2243 // Check if it's safe to fold the load. If the size of the object is
2244 // narrower than the load width, then it's not.
2247 // Change to CMPXXri r, 0 first.
2248 MI->setDesc(get(NewOpc));
2249 MI->getOperand(1).ChangeToImmediate(0);
2250 } else if (Ops.size() != 1)
2253 SmallVector<MachineOperand,4> MOs;
2254 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2255 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2258 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2260 const SmallVectorImpl<unsigned> &Ops,
2261 MachineInstr *LoadMI) const {
2262 // Check switch flag
2263 if (NoFusing) return NULL;
2265 // Determine the alignment of the load.
2266 unsigned Alignment = 0;
2267 if (LoadMI->hasOneMemOperand())
2268 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
2270 switch (LoadMI->getOpcode()) {
2272 case X86::V_SETALLONES:
2282 llvm_unreachable("Don't know how to fold this instruction!");
2284 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2285 unsigned NewOpc = 0;
2286 switch (MI->getOpcode()) {
2287 default: return NULL;
2288 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2289 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2290 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2291 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2293 // Change to CMPXXri r, 0 first.
2294 MI->setDesc(get(NewOpc));
2295 MI->getOperand(1).ChangeToImmediate(0);
2296 } else if (Ops.size() != 1)
2299 SmallVector<MachineOperand,X86AddrNumOperands> MOs;
2300 switch (LoadMI->getOpcode()) {
2302 case X86::V_SETALLONES:
2304 case X86::FsFLD0SS: {
2305 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
2306 // Create a constant-pool entry and operands to load from it.
2308 // x86-32 PIC requires a PIC base register for constant pools.
2309 unsigned PICBase = 0;
2310 if (TM.getRelocationModel() == Reloc::PIC_) {
2311 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2314 // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
2315 // This doesn't work for several reasons.
2316 // 1. GlobalBaseReg may have been spilled.
2317 // 2. It may not be live at MI.
2321 // Create a constant-pool entry.
2322 MachineConstantPool &MCP = *MF.getConstantPool();
2324 if (LoadMI->getOpcode() == X86::FsFLD0SS)
2325 Ty = Type::getFloatTy(MF.getFunction()->getContext());
2326 else if (LoadMI->getOpcode() == X86::FsFLD0SD)
2327 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
2329 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
2330 Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ?
2331 Constant::getAllOnesValue(Ty) :
2332 Constant::getNullValue(Ty);
2333 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
2335 // Create operands to load from the constant pool entry.
2336 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2337 MOs.push_back(MachineOperand::CreateImm(1));
2338 MOs.push_back(MachineOperand::CreateReg(0, false));
2339 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2340 MOs.push_back(MachineOperand::CreateReg(0, false));
2344 // Folding a normal load. Just copy the load's address operands.
2345 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2346 for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i)
2347 MOs.push_back(LoadMI->getOperand(i));
2351 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
2355 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2356 const SmallVectorImpl<unsigned> &Ops) const {
2357 // Check switch flag
2358 if (NoFusing) return 0;
2360 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2361 switch (MI->getOpcode()) {
2362 default: return false;
2371 if (Ops.size() != 1)
2374 unsigned OpNum = Ops[0];
2375 unsigned Opc = MI->getOpcode();
2376 unsigned NumOps = MI->getDesc().getNumOperands();
2377 bool isTwoAddr = NumOps > 1 &&
2378 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2380 // Folding a memory location into the two-address part of a two-address
2381 // instruction is different than folding it other places. It requires
2382 // replacing the *two* registers with the memory location.
2383 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2384 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2385 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2386 } else if (OpNum == 0) { // If operand 0
2394 OpcodeTablePtr = &RegOp2MemOpTable0;
2395 } else if (OpNum == 1) {
2396 OpcodeTablePtr = &RegOp2MemOpTable1;
2397 } else if (OpNum == 2) {
2398 OpcodeTablePtr = &RegOp2MemOpTable2;
2401 if (OpcodeTablePtr) {
2402 // Find the Opcode to fuse
2403 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2404 OpcodeTablePtr->find((unsigned*)Opc);
2405 if (I != OpcodeTablePtr->end())
2411 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2412 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2413 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2414 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2415 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2416 if (I == MemOp2RegOpTable.end())
2418 DebugLoc dl = MI->getDebugLoc();
2419 unsigned Opc = I->second.first;
2420 unsigned Index = I->second.second & 0xf;
2421 bool FoldedLoad = I->second.second & (1 << 4);
2422 bool FoldedStore = I->second.second & (1 << 5);
2423 if (UnfoldLoad && !FoldedLoad)
2425 UnfoldLoad &= FoldedLoad;
2426 if (UnfoldStore && !FoldedStore)
2428 UnfoldStore &= FoldedStore;
2430 const TargetInstrDesc &TID = get(Opc);
2431 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2432 const TargetRegisterClass *RC = TOI.getRegClass(&RI);
2433 SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
2434 SmallVector<MachineOperand,2> BeforeOps;
2435 SmallVector<MachineOperand,2> AfterOps;
2436 SmallVector<MachineOperand,4> ImpOps;
2437 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2438 MachineOperand &Op = MI->getOperand(i);
2439 if (i >= Index && i < Index + X86AddrNumOperands)
2440 AddrOps.push_back(Op);
2441 else if (Op.isReg() && Op.isImplicit())
2442 ImpOps.push_back(Op);
2444 BeforeOps.push_back(Op);
2446 AfterOps.push_back(Op);
2449 // Emit the load instruction.
2451 std::pair<MachineInstr::mmo_iterator,
2452 MachineInstr::mmo_iterator> MMOs =
2453 MF.extractLoadMemRefs(MI->memoperands_begin(),
2454 MI->memoperands_end());
2455 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
2457 // Address operands cannot be marked isKill.
2458 for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) {
2459 MachineOperand &MO = NewMIs[0]->getOperand(i);
2461 MO.setIsKill(false);
2466 // Emit the data processing instruction.
2467 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
2468 MachineInstrBuilder MIB(DataMI);
2471 MIB.addReg(Reg, RegState::Define);
2472 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2473 MIB.addOperand(BeforeOps[i]);
2476 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2477 MIB.addOperand(AfterOps[i]);
2478 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2479 MachineOperand &MO = ImpOps[i];
2480 MIB.addReg(MO.getReg(),
2481 getDefRegState(MO.isDef()) |
2482 RegState::Implicit |
2483 getKillRegState(MO.isKill()) |
2484 getDeadRegState(MO.isDead()) |
2485 getUndefRegState(MO.isUndef()));
2487 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2488 unsigned NewOpc = 0;
2489 switch (DataMI->getOpcode()) {
2491 case X86::CMP64ri32:
2495 MachineOperand &MO0 = DataMI->getOperand(0);
2496 MachineOperand &MO1 = DataMI->getOperand(1);
2497 if (MO1.getImm() == 0) {
2498 switch (DataMI->getOpcode()) {
2500 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2501 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2502 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2503 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2505 DataMI->setDesc(get(NewOpc));
2506 MO1.ChangeToRegister(MO0.getReg(), false);
2510 NewMIs.push_back(DataMI);
2512 // Emit the store instruction.
2514 const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI);
2515 std::pair<MachineInstr::mmo_iterator,
2516 MachineInstr::mmo_iterator> MMOs =
2517 MF.extractStoreMemRefs(MI->memoperands_begin(),
2518 MI->memoperands_end());
2519 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
2526 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2527 SmallVectorImpl<SDNode*> &NewNodes) const {
2528 if (!N->isMachineOpcode())
2531 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2532 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
2533 if (I == MemOp2RegOpTable.end())
2535 unsigned Opc = I->second.first;
2536 unsigned Index = I->second.second & 0xf;
2537 bool FoldedLoad = I->second.second & (1 << 4);
2538 bool FoldedStore = I->second.second & (1 << 5);
2539 const TargetInstrDesc &TID = get(Opc);
2540 const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI);
2541 unsigned NumDefs = TID.NumDefs;
2542 std::vector<SDValue> AddrOps;
2543 std::vector<SDValue> BeforeOps;
2544 std::vector<SDValue> AfterOps;
2545 DebugLoc dl = N->getDebugLoc();
2546 unsigned NumOps = N->getNumOperands();
2547 for (unsigned i = 0; i != NumOps-1; ++i) {
2548 SDValue Op = N->getOperand(i);
2549 if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands)
2550 AddrOps.push_back(Op);
2551 else if (i < Index-NumDefs)
2552 BeforeOps.push_back(Op);
2553 else if (i > Index-NumDefs)
2554 AfterOps.push_back(Op);
2556 SDValue Chain = N->getOperand(NumOps-1);
2557 AddrOps.push_back(Chain);
2559 // Emit the load instruction.
2561 MachineFunction &MF = DAG.getMachineFunction();
2563 EVT VT = *RC->vt_begin();
2564 bool isAligned = (RI.getStackAlignment() >= 16) ||
2565 RI.needsStackRealignment(MF);
2566 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2567 VT, MVT::Other, &AddrOps[0], AddrOps.size());
2568 NewNodes.push_back(Load);
2570 // Preserve memory reference information.
2571 std::pair<MachineInstr::mmo_iterator,
2572 MachineInstr::mmo_iterator> MMOs =
2573 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2574 cast<MachineSDNode>(N)->memoperands_end());
2575 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2578 // Emit the data processing instruction.
2579 std::vector<EVT> VTs;
2580 const TargetRegisterClass *DstRC = 0;
2581 if (TID.getNumDefs() > 0) {
2582 DstRC = TID.OpInfo[0].getRegClass(&RI);
2583 VTs.push_back(*DstRC->vt_begin());
2585 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2586 EVT VT = N->getValueType(i);
2587 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2591 BeforeOps.push_back(SDValue(Load, 0));
2592 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2593 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
2595 NewNodes.push_back(NewNode);
2597 // Emit the store instruction.
2600 AddrOps.push_back(SDValue(NewNode, 0));
2601 AddrOps.push_back(Chain);
2602 bool isAligned = (RI.getStackAlignment() >= 16) ||
2603 RI.needsStackRealignment(MF);
2604 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
2607 &AddrOps[0], AddrOps.size());
2608 NewNodes.push_back(Store);
2610 // Preserve memory reference information.
2611 std::pair<MachineInstr::mmo_iterator,
2612 MachineInstr::mmo_iterator> MMOs =
2613 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2614 cast<MachineSDNode>(N)->memoperands_end());
2615 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2621 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2622 bool UnfoldLoad, bool UnfoldStore) const {
2623 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2624 MemOp2RegOpTable.find((unsigned*)Opc);
2625 if (I == MemOp2RegOpTable.end())
2627 bool FoldedLoad = I->second.second & (1 << 4);
2628 bool FoldedStore = I->second.second & (1 << 5);
2629 if (UnfoldLoad && !FoldedLoad)
2631 if (UnfoldStore && !FoldedStore)
2633 return I->second.first;
2636 bool X86InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
2637 if (MBB.empty()) return false;
2639 switch (MBB.back().getOpcode()) {
2640 case X86::TCRETURNri:
2641 case X86::TCRETURNdi:
2642 case X86::RET: // Return.
2647 case X86::JMP: // Uncond branch.
2648 case X86::JMP32r: // Indirect branch.
2649 case X86::JMP64r: // Indirect branch (64-bit).
2650 case X86::JMP32m: // Indirect branch through mem.
2651 case X86::JMP64m: // Indirect branch through mem (64-bit).
2653 default: return false;
2658 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2659 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2660 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
2661 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
2663 Cond[0].setImm(GetOppositeBranchCondition(CC));
2668 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
2669 // FIXME: Return false for x87 stack register classes for now. We can't
2670 // allow any loads of these registers before FpGet_ST0_80.
2671 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
2672 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
2675 unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
2676 switch (Desc->TSFlags & X86II::ImmMask) {
2677 case X86II::Imm8: return 1;
2678 case X86II::Imm16: return 2;
2679 case X86II::Imm32: return 4;
2680 case X86II::Imm64: return 8;
2681 default: llvm_unreachable("Immediate size not set!");
2686 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
2687 /// e.g. r8, xmm8, etc.
2688 bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) {
2689 if (!MO.isReg()) return false;
2690 switch (MO.getReg()) {
2692 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
2693 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
2694 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
2695 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
2696 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
2697 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
2698 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
2699 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
2700 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
2701 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
2708 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
2709 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
2710 /// size, and 3) use of X86-64 extended registers.
2711 unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
2713 const TargetInstrDesc &Desc = MI.getDesc();
2715 // Pseudo instructions do not need REX prefix byte.
2716 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
2718 if (Desc.TSFlags & X86II::REX_W)
2721 unsigned NumOps = Desc.getNumOperands();
2723 bool isTwoAddr = NumOps > 1 &&
2724 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
2726 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
2727 unsigned i = isTwoAddr ? 1 : 0;
2728 for (unsigned e = NumOps; i != e; ++i) {
2729 const MachineOperand& MO = MI.getOperand(i);
2731 unsigned Reg = MO.getReg();
2732 if (isX86_64NonExtLowByteReg(Reg))
2737 switch (Desc.TSFlags & X86II::FormMask) {
2738 case X86II::MRMInitReg:
2739 if (isX86_64ExtendedReg(MI.getOperand(0)))
2740 REX |= (1 << 0) | (1 << 2);
2742 case X86II::MRMSrcReg: {
2743 if (isX86_64ExtendedReg(MI.getOperand(0)))
2745 i = isTwoAddr ? 2 : 1;
2746 for (unsigned e = NumOps; i != e; ++i) {
2747 const MachineOperand& MO = MI.getOperand(i);
2748 if (isX86_64ExtendedReg(MO))
2753 case X86II::MRMSrcMem: {
2754 if (isX86_64ExtendedReg(MI.getOperand(0)))
2757 i = isTwoAddr ? 2 : 1;
2758 for (; i != NumOps; ++i) {
2759 const MachineOperand& MO = MI.getOperand(i);
2761 if (isX86_64ExtendedReg(MO))
2768 case X86II::MRM0m: case X86II::MRM1m:
2769 case X86II::MRM2m: case X86II::MRM3m:
2770 case X86II::MRM4m: case X86II::MRM5m:
2771 case X86II::MRM6m: case X86II::MRM7m:
2772 case X86II::MRMDestMem: {
2773 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
2774 i = isTwoAddr ? 1 : 0;
2775 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
2778 for (; i != e; ++i) {
2779 const MachineOperand& MO = MI.getOperand(i);
2781 if (isX86_64ExtendedReg(MO))
2789 if (isX86_64ExtendedReg(MI.getOperand(0)))
2791 i = isTwoAddr ? 2 : 1;
2792 for (unsigned e = NumOps; i != e; ++i) {
2793 const MachineOperand& MO = MI.getOperand(i);
2794 if (isX86_64ExtendedReg(MO))
2804 /// sizePCRelativeBlockAddress - This method returns the size of a PC
2805 /// relative block address instruction
2807 static unsigned sizePCRelativeBlockAddress() {
2811 /// sizeGlobalAddress - Give the size of the emission of this global address
2813 static unsigned sizeGlobalAddress(bool dword) {
2814 return dword ? 8 : 4;
2817 /// sizeConstPoolAddress - Give the size of the emission of this constant
2820 static unsigned sizeConstPoolAddress(bool dword) {
2821 return dword ? 8 : 4;
2824 /// sizeExternalSymbolAddress - Give the size of the emission of this external
2827 static unsigned sizeExternalSymbolAddress(bool dword) {
2828 return dword ? 8 : 4;
2831 /// sizeJumpTableAddress - Give the size of the emission of this jump
2834 static unsigned sizeJumpTableAddress(bool dword) {
2835 return dword ? 8 : 4;
2838 static unsigned sizeConstant(unsigned Size) {
2842 static unsigned sizeRegModRMByte(){
2846 static unsigned sizeSIBByte(){
2850 static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
2851 unsigned FinalSize = 0;
2852 // If this is a simple integer displacement that doesn't require a relocation.
2854 FinalSize += sizeConstant(4);
2858 // Otherwise, this is something that requires a relocation.
2859 if (RelocOp->isGlobal()) {
2860 FinalSize += sizeGlobalAddress(false);
2861 } else if (RelocOp->isCPI()) {
2862 FinalSize += sizeConstPoolAddress(false);
2863 } else if (RelocOp->isJTI()) {
2864 FinalSize += sizeJumpTableAddress(false);
2866 llvm_unreachable("Unknown value to relocate!");
2871 static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
2872 bool IsPIC, bool Is64BitMode) {
2873 const MachineOperand &Op3 = MI.getOperand(Op+3);
2875 const MachineOperand *DispForReloc = 0;
2876 unsigned FinalSize = 0;
2878 // Figure out what sort of displacement we have to handle here.
2879 if (Op3.isGlobal()) {
2880 DispForReloc = &Op3;
2881 } else if (Op3.isCPI()) {
2882 if (Is64BitMode || IsPIC) {
2883 DispForReloc = &Op3;
2887 } else if (Op3.isJTI()) {
2888 if (Is64BitMode || IsPIC) {
2889 DispForReloc = &Op3;
2897 const MachineOperand &Base = MI.getOperand(Op);
2898 const MachineOperand &IndexReg = MI.getOperand(Op+2);
2900 unsigned BaseReg = Base.getReg();
2902 // Is a SIB byte needed?
2903 if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
2904 IndexReg.getReg() == 0 &&
2905 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
2906 if (BaseReg == 0) { // Just a displacement?
2907 // Emit special case [disp32] encoding
2909 FinalSize += getDisplacementFieldSize(DispForReloc);
2911 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
2912 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
2913 // Emit simple indirect register encoding... [EAX] f.e.
2915 // Be pessimistic and assume it's a disp32, not a disp8
2917 // Emit the most general non-SIB encoding: [REG+disp32]
2919 FinalSize += getDisplacementFieldSize(DispForReloc);
2923 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
2924 assert(IndexReg.getReg() != X86::ESP &&
2925 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
2927 bool ForceDisp32 = false;
2928 if (BaseReg == 0 || DispForReloc) {
2929 // Emit the normal disp32 encoding.
2936 FinalSize += sizeSIBByte();
2938 // Do we need to output a displacement?
2939 if (DispVal != 0 || ForceDisp32) {
2940 FinalSize += getDisplacementFieldSize(DispForReloc);
2947 static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
2948 const TargetInstrDesc *Desc,
2949 bool IsPIC, bool Is64BitMode) {
2951 unsigned Opcode = Desc->Opcode;
2952 unsigned FinalSize = 0;
2954 // Emit the lock opcode prefix as needed.
2955 if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
2957 // Emit segment override opcode prefix as needed.
2958 switch (Desc->TSFlags & X86II::SegOvrMask) {
2963 default: llvm_unreachable("Invalid segment!");
2964 case 0: break; // No segment override!
2967 // Emit the repeat opcode prefix as needed.
2968 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
2970 // Emit the operand size opcode prefix as needed.
2971 if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
2973 // Emit the address size opcode prefix as needed.
2974 if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
2976 bool Need0FPrefix = false;
2977 switch (Desc->TSFlags & X86II::Op0Mask) {
2978 case X86II::TB: // Two-byte opcode prefix
2979 case X86II::T8: // 0F 38
2980 case X86II::TA: // 0F 3A
2981 Need0FPrefix = true;
2983 case X86II::TF: // F2 0F 38
2985 Need0FPrefix = true;
2987 case X86II::REP: break; // already handled.
2988 case X86II::XS: // F3 0F
2990 Need0FPrefix = true;
2992 case X86II::XD: // F2 0F
2994 Need0FPrefix = true;
2996 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
2997 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
2999 break; // Two-byte opcode prefix
3000 default: llvm_unreachable("Invalid prefix!");
3001 case 0: break; // No prefix!
3006 unsigned REX = X86InstrInfo::determineREX(MI);
3011 // 0x0F escape code must be emitted just before the opcode.
3015 switch (Desc->TSFlags & X86II::Op0Mask) {
3016 case X86II::T8: // 0F 38
3019 case X86II::TA: // 0F 3A
3022 case X86II::TF: // F2 0F 38
3027 // If this is a two-address instruction, skip one of the register operands.
3028 unsigned NumOps = Desc->getNumOperands();
3030 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
3032 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
3033 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
3036 switch (Desc->TSFlags & X86II::FormMask) {
3037 default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
3039 // Remember the current PC offset, this is the PIC relocation
3044 case TargetInstrInfo::INLINEASM: {
3045 const MachineFunction *MF = MI.getParent()->getParent();
3046 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
3047 FinalSize += TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
3048 *MF->getTarget().getMCAsmInfo());
3051 case TargetInstrInfo::DBG_LABEL:
3052 case TargetInstrInfo::EH_LABEL:
3054 case TargetInstrInfo::IMPLICIT_DEF:
3055 case TargetInstrInfo::KILL:
3056 case X86::DWARF_LOC:
3057 case X86::FP_REG_KILL:
3059 case X86::MOVPC32r: {
3060 // This emits the "call" portion of this pseudo instruction.
3062 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3071 if (CurOp != NumOps) {
3072 const MachineOperand &MO = MI.getOperand(CurOp++);
3074 FinalSize += sizePCRelativeBlockAddress();
3075 } else if (MO.isGlobal()) {
3076 FinalSize += sizeGlobalAddress(false);
3077 } else if (MO.isSymbol()) {
3078 FinalSize += sizeExternalSymbolAddress(false);
3079 } else if (MO.isImm()) {
3080 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3082 llvm_unreachable("Unknown RawFrm operand!");
3087 case X86II::AddRegFrm:
3091 if (CurOp != NumOps) {
3092 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3093 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3095 FinalSize += sizeConstant(Size);
3098 if (Opcode == X86::MOV64ri)
3100 if (MO1.isGlobal()) {
3101 FinalSize += sizeGlobalAddress(dword);
3102 } else if (MO1.isSymbol())
3103 FinalSize += sizeExternalSymbolAddress(dword);
3104 else if (MO1.isCPI())
3105 FinalSize += sizeConstPoolAddress(dword);
3106 else if (MO1.isJTI())
3107 FinalSize += sizeJumpTableAddress(dword);
3112 case X86II::MRMDestReg: {
3114 FinalSize += sizeRegModRMByte();
3116 if (CurOp != NumOps) {
3118 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3122 case X86II::MRMDestMem: {
3124 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3125 CurOp += X86AddrNumOperands + 1;
3126 if (CurOp != NumOps) {
3128 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3133 case X86II::MRMSrcReg:
3135 FinalSize += sizeRegModRMByte();
3137 if (CurOp != NumOps) {
3139 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3143 case X86II::MRMSrcMem: {
3145 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
3146 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
3147 AddrOperands = X86AddrNumOperands - 1; // No segment register
3149 AddrOperands = X86AddrNumOperands;
3152 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
3153 CurOp += AddrOperands + 1;
3154 if (CurOp != NumOps) {
3156 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3161 case X86II::MRM0r: case X86II::MRM1r:
3162 case X86II::MRM2r: case X86II::MRM3r:
3163 case X86II::MRM4r: case X86II::MRM5r:
3164 case X86II::MRM6r: case X86II::MRM7r:
3166 if (Desc->getOpcode() == X86::LFENCE ||
3167 Desc->getOpcode() == X86::MFENCE) {
3168 // Special handling of lfence and mfence;
3169 FinalSize += sizeRegModRMByte();
3170 } else if (Desc->getOpcode() == X86::MONITOR ||
3171 Desc->getOpcode() == X86::MWAIT) {
3172 // Special handling of monitor and mwait.
3173 FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode.
3176 FinalSize += sizeRegModRMByte();
3179 if (CurOp != NumOps) {
3180 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3181 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3183 FinalSize += sizeConstant(Size);
3186 if (Opcode == X86::MOV64ri32)
3188 if (MO1.isGlobal()) {
3189 FinalSize += sizeGlobalAddress(dword);
3190 } else if (MO1.isSymbol())
3191 FinalSize += sizeExternalSymbolAddress(dword);
3192 else if (MO1.isCPI())
3193 FinalSize += sizeConstPoolAddress(dword);
3194 else if (MO1.isJTI())
3195 FinalSize += sizeJumpTableAddress(dword);
3200 case X86II::MRM0m: case X86II::MRM1m:
3201 case X86II::MRM2m: case X86II::MRM3m:
3202 case X86II::MRM4m: case X86II::MRM5m:
3203 case X86II::MRM6m: case X86II::MRM7m: {
3206 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3207 CurOp += X86AddrNumOperands;
3209 if (CurOp != NumOps) {
3210 const MachineOperand &MO = MI.getOperand(CurOp++);
3211 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3213 FinalSize += sizeConstant(Size);
3216 if (Opcode == X86::MOV64mi32)
3218 if (MO.isGlobal()) {
3219 FinalSize += sizeGlobalAddress(dword);
3220 } else if (MO.isSymbol())
3221 FinalSize += sizeExternalSymbolAddress(dword);
3222 else if (MO.isCPI())
3223 FinalSize += sizeConstPoolAddress(dword);
3224 else if (MO.isJTI())
3225 FinalSize += sizeJumpTableAddress(dword);
3231 case X86II::MRMInitReg:
3233 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
3234 FinalSize += sizeRegModRMByte();
3239 if (!Desc->isVariadic() && CurOp != NumOps) {
3241 raw_string_ostream Msg(msg);
3242 Msg << "Cannot determine size: " << MI;
3243 llvm_report_error(Msg.str());
3251 unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
3252 const TargetInstrDesc &Desc = MI->getDesc();
3253 bool IsPIC = TM.getRelocationModel() == Reloc::PIC_;
3254 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
3255 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
3256 if (Desc.getOpcode() == X86::MOVPC32r)
3257 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
3261 /// getGlobalBaseReg - Return a virtual register initialized with the
3262 /// the global base register value. Output instructions required to
3263 /// initialize the register in the function entry block, if necessary.
3265 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3266 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3267 "X86-64 PIC uses RIP relative addressing");
3269 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3270 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3271 if (GlobalBaseReg != 0)
3272 return GlobalBaseReg;
3274 // Insert the set of GlobalBaseReg into the first MBB of the function
3275 MachineBasicBlock &FirstMBB = MF->front();
3276 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3277 DebugLoc DL = DebugLoc::getUnknownLoc();
3278 if (MBBI != FirstMBB.end()) DL = MBBI->getDebugLoc();
3279 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3280 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3282 const TargetInstrInfo *TII = TM.getInstrInfo();
3283 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3284 // only used in JIT code emission as displacement to pc.
3285 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3287 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3288 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3289 if (TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3290 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3291 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3292 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3293 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3294 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3299 X86FI->setGlobalBaseReg(GlobalBaseReg);
3300 return GlobalBaseReg;