1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "X86InstrInfo.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/LiveVariables.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Target/TargetAsmInfo.h"
34 NoFusing("disable-spill-fusing",
35 cl::desc("Disable fusing of spill code into instructions"));
37 PrintFailedFusing("print-failed-fuse-candidates",
38 cl::desc("Print instructions that the allocator wants to"
39 " fuse, but the X86 backend currently can't"),
42 ReMatPICStubLoad("remat-pic-stub-load",
43 cl::desc("Re-materialize load from stub in PIC mode"),
44 cl::init(false), cl::Hidden);
47 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
48 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
49 TM(tm), RI(tm, *this) {
50 SmallVector<unsigned,16> AmbEntries;
51 static const unsigned OpTbl2Addr[][2] = {
52 { X86::ADC32ri, X86::ADC32mi },
53 { X86::ADC32ri8, X86::ADC32mi8 },
54 { X86::ADC32rr, X86::ADC32mr },
55 { X86::ADC64ri32, X86::ADC64mi32 },
56 { X86::ADC64ri8, X86::ADC64mi8 },
57 { X86::ADC64rr, X86::ADC64mr },
58 { X86::ADD16ri, X86::ADD16mi },
59 { X86::ADD16ri8, X86::ADD16mi8 },
60 { X86::ADD16rr, X86::ADD16mr },
61 { X86::ADD32ri, X86::ADD32mi },
62 { X86::ADD32ri8, X86::ADD32mi8 },
63 { X86::ADD32rr, X86::ADD32mr },
64 { X86::ADD64ri32, X86::ADD64mi32 },
65 { X86::ADD64ri8, X86::ADD64mi8 },
66 { X86::ADD64rr, X86::ADD64mr },
67 { X86::ADD8ri, X86::ADD8mi },
68 { X86::ADD8rr, X86::ADD8mr },
69 { X86::AND16ri, X86::AND16mi },
70 { X86::AND16ri8, X86::AND16mi8 },
71 { X86::AND16rr, X86::AND16mr },
72 { X86::AND32ri, X86::AND32mi },
73 { X86::AND32ri8, X86::AND32mi8 },
74 { X86::AND32rr, X86::AND32mr },
75 { X86::AND64ri32, X86::AND64mi32 },
76 { X86::AND64ri8, X86::AND64mi8 },
77 { X86::AND64rr, X86::AND64mr },
78 { X86::AND8ri, X86::AND8mi },
79 { X86::AND8rr, X86::AND8mr },
80 { X86::DEC16r, X86::DEC16m },
81 { X86::DEC32r, X86::DEC32m },
82 { X86::DEC64_16r, X86::DEC64_16m },
83 { X86::DEC64_32r, X86::DEC64_32m },
84 { X86::DEC64r, X86::DEC64m },
85 { X86::DEC8r, X86::DEC8m },
86 { X86::INC16r, X86::INC16m },
87 { X86::INC32r, X86::INC32m },
88 { X86::INC64_16r, X86::INC64_16m },
89 { X86::INC64_32r, X86::INC64_32m },
90 { X86::INC64r, X86::INC64m },
91 { X86::INC8r, X86::INC8m },
92 { X86::NEG16r, X86::NEG16m },
93 { X86::NEG32r, X86::NEG32m },
94 { X86::NEG64r, X86::NEG64m },
95 { X86::NEG8r, X86::NEG8m },
96 { X86::NOT16r, X86::NOT16m },
97 { X86::NOT32r, X86::NOT32m },
98 { X86::NOT64r, X86::NOT64m },
99 { X86::NOT8r, X86::NOT8m },
100 { X86::OR16ri, X86::OR16mi },
101 { X86::OR16ri8, X86::OR16mi8 },
102 { X86::OR16rr, X86::OR16mr },
103 { X86::OR32ri, X86::OR32mi },
104 { X86::OR32ri8, X86::OR32mi8 },
105 { X86::OR32rr, X86::OR32mr },
106 { X86::OR64ri32, X86::OR64mi32 },
107 { X86::OR64ri8, X86::OR64mi8 },
108 { X86::OR64rr, X86::OR64mr },
109 { X86::OR8ri, X86::OR8mi },
110 { X86::OR8rr, X86::OR8mr },
111 { X86::ROL16r1, X86::ROL16m1 },
112 { X86::ROL16rCL, X86::ROL16mCL },
113 { X86::ROL16ri, X86::ROL16mi },
114 { X86::ROL32r1, X86::ROL32m1 },
115 { X86::ROL32rCL, X86::ROL32mCL },
116 { X86::ROL32ri, X86::ROL32mi },
117 { X86::ROL64r1, X86::ROL64m1 },
118 { X86::ROL64rCL, X86::ROL64mCL },
119 { X86::ROL64ri, X86::ROL64mi },
120 { X86::ROL8r1, X86::ROL8m1 },
121 { X86::ROL8rCL, X86::ROL8mCL },
122 { X86::ROL8ri, X86::ROL8mi },
123 { X86::ROR16r1, X86::ROR16m1 },
124 { X86::ROR16rCL, X86::ROR16mCL },
125 { X86::ROR16ri, X86::ROR16mi },
126 { X86::ROR32r1, X86::ROR32m1 },
127 { X86::ROR32rCL, X86::ROR32mCL },
128 { X86::ROR32ri, X86::ROR32mi },
129 { X86::ROR64r1, X86::ROR64m1 },
130 { X86::ROR64rCL, X86::ROR64mCL },
131 { X86::ROR64ri, X86::ROR64mi },
132 { X86::ROR8r1, X86::ROR8m1 },
133 { X86::ROR8rCL, X86::ROR8mCL },
134 { X86::ROR8ri, X86::ROR8mi },
135 { X86::SAR16r1, X86::SAR16m1 },
136 { X86::SAR16rCL, X86::SAR16mCL },
137 { X86::SAR16ri, X86::SAR16mi },
138 { X86::SAR32r1, X86::SAR32m1 },
139 { X86::SAR32rCL, X86::SAR32mCL },
140 { X86::SAR32ri, X86::SAR32mi },
141 { X86::SAR64r1, X86::SAR64m1 },
142 { X86::SAR64rCL, X86::SAR64mCL },
143 { X86::SAR64ri, X86::SAR64mi },
144 { X86::SAR8r1, X86::SAR8m1 },
145 { X86::SAR8rCL, X86::SAR8mCL },
146 { X86::SAR8ri, X86::SAR8mi },
147 { X86::SBB32ri, X86::SBB32mi },
148 { X86::SBB32ri8, X86::SBB32mi8 },
149 { X86::SBB32rr, X86::SBB32mr },
150 { X86::SBB64ri32, X86::SBB64mi32 },
151 { X86::SBB64ri8, X86::SBB64mi8 },
152 { X86::SBB64rr, X86::SBB64mr },
153 { X86::SHL16rCL, X86::SHL16mCL },
154 { X86::SHL16ri, X86::SHL16mi },
155 { X86::SHL32rCL, X86::SHL32mCL },
156 { X86::SHL32ri, X86::SHL32mi },
157 { X86::SHL64rCL, X86::SHL64mCL },
158 { X86::SHL64ri, X86::SHL64mi },
159 { X86::SHL8rCL, X86::SHL8mCL },
160 { X86::SHL8ri, X86::SHL8mi },
161 { X86::SHLD16rrCL, X86::SHLD16mrCL },
162 { X86::SHLD16rri8, X86::SHLD16mri8 },
163 { X86::SHLD32rrCL, X86::SHLD32mrCL },
164 { X86::SHLD32rri8, X86::SHLD32mri8 },
165 { X86::SHLD64rrCL, X86::SHLD64mrCL },
166 { X86::SHLD64rri8, X86::SHLD64mri8 },
167 { X86::SHR16r1, X86::SHR16m1 },
168 { X86::SHR16rCL, X86::SHR16mCL },
169 { X86::SHR16ri, X86::SHR16mi },
170 { X86::SHR32r1, X86::SHR32m1 },
171 { X86::SHR32rCL, X86::SHR32mCL },
172 { X86::SHR32ri, X86::SHR32mi },
173 { X86::SHR64r1, X86::SHR64m1 },
174 { X86::SHR64rCL, X86::SHR64mCL },
175 { X86::SHR64ri, X86::SHR64mi },
176 { X86::SHR8r1, X86::SHR8m1 },
177 { X86::SHR8rCL, X86::SHR8mCL },
178 { X86::SHR8ri, X86::SHR8mi },
179 { X86::SHRD16rrCL, X86::SHRD16mrCL },
180 { X86::SHRD16rri8, X86::SHRD16mri8 },
181 { X86::SHRD32rrCL, X86::SHRD32mrCL },
182 { X86::SHRD32rri8, X86::SHRD32mri8 },
183 { X86::SHRD64rrCL, X86::SHRD64mrCL },
184 { X86::SHRD64rri8, X86::SHRD64mri8 },
185 { X86::SUB16ri, X86::SUB16mi },
186 { X86::SUB16ri8, X86::SUB16mi8 },
187 { X86::SUB16rr, X86::SUB16mr },
188 { X86::SUB32ri, X86::SUB32mi },
189 { X86::SUB32ri8, X86::SUB32mi8 },
190 { X86::SUB32rr, X86::SUB32mr },
191 { X86::SUB64ri32, X86::SUB64mi32 },
192 { X86::SUB64ri8, X86::SUB64mi8 },
193 { X86::SUB64rr, X86::SUB64mr },
194 { X86::SUB8ri, X86::SUB8mi },
195 { X86::SUB8rr, X86::SUB8mr },
196 { X86::XOR16ri, X86::XOR16mi },
197 { X86::XOR16ri8, X86::XOR16mi8 },
198 { X86::XOR16rr, X86::XOR16mr },
199 { X86::XOR32ri, X86::XOR32mi },
200 { X86::XOR32ri8, X86::XOR32mi8 },
201 { X86::XOR32rr, X86::XOR32mr },
202 { X86::XOR64ri32, X86::XOR64mi32 },
203 { X86::XOR64ri8, X86::XOR64mi8 },
204 { X86::XOR64rr, X86::XOR64mr },
205 { X86::XOR8ri, X86::XOR8mi },
206 { X86::XOR8rr, X86::XOR8mr }
209 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
210 unsigned RegOp = OpTbl2Addr[i][0];
211 unsigned MemOp = OpTbl2Addr[i][1];
212 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
214 assert(false && "Duplicated entries?");
215 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); // Index 0,folded load and store
216 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
217 std::make_pair(RegOp,
219 AmbEntries.push_back(MemOp);
222 // If the third value is 1, then it's folding either a load or a store.
223 static const unsigned OpTbl0[][3] = {
224 { X86::CALL32r, X86::CALL32m, 1 },
225 { X86::CALL64r, X86::CALL64m, 1 },
226 { X86::CMP16ri, X86::CMP16mi, 1 },
227 { X86::CMP16ri8, X86::CMP16mi8, 1 },
228 { X86::CMP16rr, X86::CMP16mr, 1 },
229 { X86::CMP32ri, X86::CMP32mi, 1 },
230 { X86::CMP32ri8, X86::CMP32mi8, 1 },
231 { X86::CMP32rr, X86::CMP32mr, 1 },
232 { X86::CMP64ri32, X86::CMP64mi32, 1 },
233 { X86::CMP64ri8, X86::CMP64mi8, 1 },
234 { X86::CMP64rr, X86::CMP64mr, 1 },
235 { X86::CMP8ri, X86::CMP8mi, 1 },
236 { X86::CMP8rr, X86::CMP8mr, 1 },
237 { X86::DIV16r, X86::DIV16m, 1 },
238 { X86::DIV32r, X86::DIV32m, 1 },
239 { X86::DIV64r, X86::DIV64m, 1 },
240 { X86::DIV8r, X86::DIV8m, 1 },
241 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0 },
242 { X86::FsMOVAPDrr, X86::MOVSDmr, 0 },
243 { X86::FsMOVAPSrr, X86::MOVSSmr, 0 },
244 { X86::IDIV16r, X86::IDIV16m, 1 },
245 { X86::IDIV32r, X86::IDIV32m, 1 },
246 { X86::IDIV64r, X86::IDIV64m, 1 },
247 { X86::IDIV8r, X86::IDIV8m, 1 },
248 { X86::IMUL16r, X86::IMUL16m, 1 },
249 { X86::IMUL32r, X86::IMUL32m, 1 },
250 { X86::IMUL64r, X86::IMUL64m, 1 },
251 { X86::IMUL8r, X86::IMUL8m, 1 },
252 { X86::JMP32r, X86::JMP32m, 1 },
253 { X86::JMP64r, X86::JMP64m, 1 },
254 { X86::MOV16ri, X86::MOV16mi, 0 },
255 { X86::MOV16rr, X86::MOV16mr, 0 },
256 { X86::MOV16to16_, X86::MOV16_mr, 0 },
257 { X86::MOV32ri, X86::MOV32mi, 0 },
258 { X86::MOV32rr, X86::MOV32mr, 0 },
259 { X86::MOV32to32_, X86::MOV32_mr, 0 },
260 { X86::MOV64ri32, X86::MOV64mi32, 0 },
261 { X86::MOV64rr, X86::MOV64mr, 0 },
262 { X86::MOV8ri, X86::MOV8mi, 0 },
263 { X86::MOV8rr, X86::MOV8mr, 0 },
264 { X86::MOVAPDrr, X86::MOVAPDmr, 0 },
265 { X86::MOVAPSrr, X86::MOVAPSmr, 0 },
266 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0 },
267 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0 },
268 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0 },
269 { X86::MOVSDrr, X86::MOVSDmr, 0 },
270 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0 },
271 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0 },
272 { X86::MOVSSrr, X86::MOVSSmr, 0 },
273 { X86::MOVUPDrr, X86::MOVUPDmr, 0 },
274 { X86::MOVUPSrr, X86::MOVUPSmr, 0 },
275 { X86::MUL16r, X86::MUL16m, 1 },
276 { X86::MUL32r, X86::MUL32m, 1 },
277 { X86::MUL64r, X86::MUL64m, 1 },
278 { X86::MUL8r, X86::MUL8m, 1 },
279 { X86::SETAEr, X86::SETAEm, 0 },
280 { X86::SETAr, X86::SETAm, 0 },
281 { X86::SETBEr, X86::SETBEm, 0 },
282 { X86::SETBr, X86::SETBm, 0 },
283 { X86::SETEr, X86::SETEm, 0 },
284 { X86::SETGEr, X86::SETGEm, 0 },
285 { X86::SETGr, X86::SETGm, 0 },
286 { X86::SETLEr, X86::SETLEm, 0 },
287 { X86::SETLr, X86::SETLm, 0 },
288 { X86::SETNEr, X86::SETNEm, 0 },
289 { X86::SETNPr, X86::SETNPm, 0 },
290 { X86::SETNSr, X86::SETNSm, 0 },
291 { X86::SETPr, X86::SETPm, 0 },
292 { X86::SETSr, X86::SETSm, 0 },
293 { X86::TAILJMPr, X86::TAILJMPm, 1 },
294 { X86::TEST16ri, X86::TEST16mi, 1 },
295 { X86::TEST32ri, X86::TEST32mi, 1 },
296 { X86::TEST64ri32, X86::TEST64mi32, 1 },
297 { X86::TEST8ri, X86::TEST8mi, 1 }
300 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
301 unsigned RegOp = OpTbl0[i][0];
302 unsigned MemOp = OpTbl0[i][1];
303 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
305 assert(false && "Duplicated entries?");
306 unsigned FoldedLoad = OpTbl0[i][2];
307 // Index 0, folded load or store.
308 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
309 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
310 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
311 std::make_pair(RegOp, AuxInfo))).second)
312 AmbEntries.push_back(MemOp);
315 static const unsigned OpTbl1[][2] = {
316 { X86::CMP16rr, X86::CMP16rm },
317 { X86::CMP32rr, X86::CMP32rm },
318 { X86::CMP64rr, X86::CMP64rm },
319 { X86::CMP8rr, X86::CMP8rm },
320 { X86::CVTSD2SSrr, X86::CVTSD2SSrm },
321 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm },
322 { X86::CVTSI2SDrr, X86::CVTSI2SDrm },
323 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm },
324 { X86::CVTSI2SSrr, X86::CVTSI2SSrm },
325 { X86::CVTSS2SDrr, X86::CVTSS2SDrm },
326 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm },
327 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm },
328 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm },
329 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm },
330 { X86::FsMOVAPDrr, X86::MOVSDrm },
331 { X86::FsMOVAPSrr, X86::MOVSSrm },
332 { X86::IMUL16rri, X86::IMUL16rmi },
333 { X86::IMUL16rri8, X86::IMUL16rmi8 },
334 { X86::IMUL32rri, X86::IMUL32rmi },
335 { X86::IMUL32rri8, X86::IMUL32rmi8 },
336 { X86::IMUL64rri32, X86::IMUL64rmi32 },
337 { X86::IMUL64rri8, X86::IMUL64rmi8 },
338 { X86::Int_CMPSDrr, X86::Int_CMPSDrm },
339 { X86::Int_CMPSSrr, X86::Int_CMPSSrm },
340 { X86::Int_COMISDrr, X86::Int_COMISDrm },
341 { X86::Int_COMISSrr, X86::Int_COMISSrm },
342 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm },
343 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm },
344 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm },
345 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm },
346 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm },
347 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm },
348 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm },
349 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm },
350 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm },
351 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm },
352 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm },
353 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm },
354 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm },
355 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm },
356 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm },
357 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm },
358 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
359 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
360 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm },
361 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
362 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm },
363 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
364 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm },
365 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm },
366 { X86::MOV16rr, X86::MOV16rm },
367 { X86::MOV16to16_, X86::MOV16_rm },
368 { X86::MOV32rr, X86::MOV32rm },
369 { X86::MOV32to32_, X86::MOV32_rm },
370 { X86::MOV64rr, X86::MOV64rm },
371 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm },
372 { X86::MOV64toSDrr, X86::MOV64toSDrm },
373 { X86::MOV8rr, X86::MOV8rm },
374 { X86::MOVAPDrr, X86::MOVAPDrm },
375 { X86::MOVAPSrr, X86::MOVAPSrm },
376 { X86::MOVDDUPrr, X86::MOVDDUPrm },
377 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm },
378 { X86::MOVDI2SSrr, X86::MOVDI2SSrm },
379 { X86::MOVSD2PDrr, X86::MOVSD2PDrm },
380 { X86::MOVSDrr, X86::MOVSDrm },
381 { X86::MOVSHDUPrr, X86::MOVSHDUPrm },
382 { X86::MOVSLDUPrr, X86::MOVSLDUPrm },
383 { X86::MOVSS2PSrr, X86::MOVSS2PSrm },
384 { X86::MOVSSrr, X86::MOVSSrm },
385 { X86::MOVSX16rr8, X86::MOVSX16rm8 },
386 { X86::MOVSX32rr16, X86::MOVSX32rm16 },
387 { X86::MOVSX32rr8, X86::MOVSX32rm8 },
388 { X86::MOVSX64rr16, X86::MOVSX64rm16 },
389 { X86::MOVSX64rr32, X86::MOVSX64rm32 },
390 { X86::MOVSX64rr8, X86::MOVSX64rm8 },
391 { X86::MOVUPDrr, X86::MOVUPDrm },
392 { X86::MOVUPSrr, X86::MOVUPSrm },
393 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm },
394 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm },
395 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm },
396 { X86::MOVZX16rr8, X86::MOVZX16rm8 },
397 { X86::MOVZX32rr16, X86::MOVZX32rm16 },
398 { X86::MOVZX32rr8, X86::MOVZX32rm8 },
399 { X86::MOVZX64rr16, X86::MOVZX64rm16 },
400 { X86::MOVZX64rr32, X86::MOVZX64rm32 },
401 { X86::MOVZX64rr8, X86::MOVZX64rm8 },
402 { X86::PSHUFDri, X86::PSHUFDmi },
403 { X86::PSHUFHWri, X86::PSHUFHWmi },
404 { X86::PSHUFLWri, X86::PSHUFLWmi },
405 { X86::RCPPSr, X86::RCPPSm },
406 { X86::RCPPSr_Int, X86::RCPPSm_Int },
407 { X86::RSQRTPSr, X86::RSQRTPSm },
408 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int },
409 { X86::RSQRTSSr, X86::RSQRTSSm },
410 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int },
411 { X86::SQRTPDr, X86::SQRTPDm },
412 { X86::SQRTPDr_Int, X86::SQRTPDm_Int },
413 { X86::SQRTPSr, X86::SQRTPSm },
414 { X86::SQRTPSr_Int, X86::SQRTPSm_Int },
415 { X86::SQRTSDr, X86::SQRTSDm },
416 { X86::SQRTSDr_Int, X86::SQRTSDm_Int },
417 { X86::SQRTSSr, X86::SQRTSSm },
418 { X86::SQRTSSr_Int, X86::SQRTSSm_Int },
419 { X86::TEST16rr, X86::TEST16rm },
420 { X86::TEST32rr, X86::TEST32rm },
421 { X86::TEST64rr, X86::TEST64rm },
422 { X86::TEST8rr, X86::TEST8rm },
423 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
424 { X86::UCOMISDrr, X86::UCOMISDrm },
425 { X86::UCOMISSrr, X86::UCOMISSrm }
428 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
429 unsigned RegOp = OpTbl1[i][0];
430 unsigned MemOp = OpTbl1[i][1];
431 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
433 assert(false && "Duplicated entries?");
434 unsigned AuxInfo = 1 | (1 << 4); // Index 1, folded load
435 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
436 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
437 std::make_pair(RegOp, AuxInfo))).second)
438 AmbEntries.push_back(MemOp);
441 static const unsigned OpTbl2[][2] = {
442 { X86::ADC32rr, X86::ADC32rm },
443 { X86::ADC64rr, X86::ADC64rm },
444 { X86::ADD16rr, X86::ADD16rm },
445 { X86::ADD32rr, X86::ADD32rm },
446 { X86::ADD64rr, X86::ADD64rm },
447 { X86::ADD8rr, X86::ADD8rm },
448 { X86::ADDPDrr, X86::ADDPDrm },
449 { X86::ADDPSrr, X86::ADDPSrm },
450 { X86::ADDSDrr, X86::ADDSDrm },
451 { X86::ADDSSrr, X86::ADDSSrm },
452 { X86::ADDSUBPDrr, X86::ADDSUBPDrm },
453 { X86::ADDSUBPSrr, X86::ADDSUBPSrm },
454 { X86::AND16rr, X86::AND16rm },
455 { X86::AND32rr, X86::AND32rm },
456 { X86::AND64rr, X86::AND64rm },
457 { X86::AND8rr, X86::AND8rm },
458 { X86::ANDNPDrr, X86::ANDNPDrm },
459 { X86::ANDNPSrr, X86::ANDNPSrm },
460 { X86::ANDPDrr, X86::ANDPDrm },
461 { X86::ANDPSrr, X86::ANDPSrm },
462 { X86::CMOVA16rr, X86::CMOVA16rm },
463 { X86::CMOVA32rr, X86::CMOVA32rm },
464 { X86::CMOVA64rr, X86::CMOVA64rm },
465 { X86::CMOVAE16rr, X86::CMOVAE16rm },
466 { X86::CMOVAE32rr, X86::CMOVAE32rm },
467 { X86::CMOVAE64rr, X86::CMOVAE64rm },
468 { X86::CMOVB16rr, X86::CMOVB16rm },
469 { X86::CMOVB32rr, X86::CMOVB32rm },
470 { X86::CMOVB64rr, X86::CMOVB64rm },
471 { X86::CMOVBE16rr, X86::CMOVBE16rm },
472 { X86::CMOVBE32rr, X86::CMOVBE32rm },
473 { X86::CMOVBE64rr, X86::CMOVBE64rm },
474 { X86::CMOVE16rr, X86::CMOVE16rm },
475 { X86::CMOVE32rr, X86::CMOVE32rm },
476 { X86::CMOVE64rr, X86::CMOVE64rm },
477 { X86::CMOVG16rr, X86::CMOVG16rm },
478 { X86::CMOVG32rr, X86::CMOVG32rm },
479 { X86::CMOVG64rr, X86::CMOVG64rm },
480 { X86::CMOVGE16rr, X86::CMOVGE16rm },
481 { X86::CMOVGE32rr, X86::CMOVGE32rm },
482 { X86::CMOVGE64rr, X86::CMOVGE64rm },
483 { X86::CMOVL16rr, X86::CMOVL16rm },
484 { X86::CMOVL32rr, X86::CMOVL32rm },
485 { X86::CMOVL64rr, X86::CMOVL64rm },
486 { X86::CMOVLE16rr, X86::CMOVLE16rm },
487 { X86::CMOVLE32rr, X86::CMOVLE32rm },
488 { X86::CMOVLE64rr, X86::CMOVLE64rm },
489 { X86::CMOVNE16rr, X86::CMOVNE16rm },
490 { X86::CMOVNE32rr, X86::CMOVNE32rm },
491 { X86::CMOVNE64rr, X86::CMOVNE64rm },
492 { X86::CMOVNP16rr, X86::CMOVNP16rm },
493 { X86::CMOVNP32rr, X86::CMOVNP32rm },
494 { X86::CMOVNP64rr, X86::CMOVNP64rm },
495 { X86::CMOVNS16rr, X86::CMOVNS16rm },
496 { X86::CMOVNS32rr, X86::CMOVNS32rm },
497 { X86::CMOVNS64rr, X86::CMOVNS64rm },
498 { X86::CMOVP16rr, X86::CMOVP16rm },
499 { X86::CMOVP32rr, X86::CMOVP32rm },
500 { X86::CMOVP64rr, X86::CMOVP64rm },
501 { X86::CMOVS16rr, X86::CMOVS16rm },
502 { X86::CMOVS32rr, X86::CMOVS32rm },
503 { X86::CMOVS64rr, X86::CMOVS64rm },
504 { X86::CMPPDrri, X86::CMPPDrmi },
505 { X86::CMPPSrri, X86::CMPPSrmi },
506 { X86::CMPSDrr, X86::CMPSDrm },
507 { X86::CMPSSrr, X86::CMPSSrm },
508 { X86::DIVPDrr, X86::DIVPDrm },
509 { X86::DIVPSrr, X86::DIVPSrm },
510 { X86::DIVSDrr, X86::DIVSDrm },
511 { X86::DIVSSrr, X86::DIVSSrm },
512 { X86::FsANDNPDrr, X86::FsANDNPDrm },
513 { X86::FsANDNPSrr, X86::FsANDNPSrm },
514 { X86::FsANDPDrr, X86::FsANDPDrm },
515 { X86::FsANDPSrr, X86::FsANDPSrm },
516 { X86::FsORPDrr, X86::FsORPDrm },
517 { X86::FsORPSrr, X86::FsORPSrm },
518 { X86::FsXORPDrr, X86::FsXORPDrm },
519 { X86::FsXORPSrr, X86::FsXORPSrm },
520 { X86::HADDPDrr, X86::HADDPDrm },
521 { X86::HADDPSrr, X86::HADDPSrm },
522 { X86::HSUBPDrr, X86::HSUBPDrm },
523 { X86::HSUBPSrr, X86::HSUBPSrm },
524 { X86::IMUL16rr, X86::IMUL16rm },
525 { X86::IMUL32rr, X86::IMUL32rm },
526 { X86::IMUL64rr, X86::IMUL64rm },
527 { X86::MAXPDrr, X86::MAXPDrm },
528 { X86::MAXPDrr_Int, X86::MAXPDrm_Int },
529 { X86::MAXPSrr, X86::MAXPSrm },
530 { X86::MAXPSrr_Int, X86::MAXPSrm_Int },
531 { X86::MAXSDrr, X86::MAXSDrm },
532 { X86::MAXSDrr_Int, X86::MAXSDrm_Int },
533 { X86::MAXSSrr, X86::MAXSSrm },
534 { X86::MAXSSrr_Int, X86::MAXSSrm_Int },
535 { X86::MINPDrr, X86::MINPDrm },
536 { X86::MINPDrr_Int, X86::MINPDrm_Int },
537 { X86::MINPSrr, X86::MINPSrm },
538 { X86::MINPSrr_Int, X86::MINPSrm_Int },
539 { X86::MINSDrr, X86::MINSDrm },
540 { X86::MINSDrr_Int, X86::MINSDrm_Int },
541 { X86::MINSSrr, X86::MINSSrm },
542 { X86::MINSSrr_Int, X86::MINSSrm_Int },
543 { X86::MULPDrr, X86::MULPDrm },
544 { X86::MULPSrr, X86::MULPSrm },
545 { X86::MULSDrr, X86::MULSDrm },
546 { X86::MULSSrr, X86::MULSSrm },
547 { X86::OR16rr, X86::OR16rm },
548 { X86::OR32rr, X86::OR32rm },
549 { X86::OR64rr, X86::OR64rm },
550 { X86::OR8rr, X86::OR8rm },
551 { X86::ORPDrr, X86::ORPDrm },
552 { X86::ORPSrr, X86::ORPSrm },
553 { X86::PACKSSDWrr, X86::PACKSSDWrm },
554 { X86::PACKSSWBrr, X86::PACKSSWBrm },
555 { X86::PACKUSWBrr, X86::PACKUSWBrm },
556 { X86::PADDBrr, X86::PADDBrm },
557 { X86::PADDDrr, X86::PADDDrm },
558 { X86::PADDQrr, X86::PADDQrm },
559 { X86::PADDSBrr, X86::PADDSBrm },
560 { X86::PADDSWrr, X86::PADDSWrm },
561 { X86::PADDWrr, X86::PADDWrm },
562 { X86::PANDNrr, X86::PANDNrm },
563 { X86::PANDrr, X86::PANDrm },
564 { X86::PAVGBrr, X86::PAVGBrm },
565 { X86::PAVGWrr, X86::PAVGWrm },
566 { X86::PCMPEQBrr, X86::PCMPEQBrm },
567 { X86::PCMPEQDrr, X86::PCMPEQDrm },
568 { X86::PCMPEQWrr, X86::PCMPEQWrm },
569 { X86::PCMPGTBrr, X86::PCMPGTBrm },
570 { X86::PCMPGTDrr, X86::PCMPGTDrm },
571 { X86::PCMPGTWrr, X86::PCMPGTWrm },
572 { X86::PINSRWrri, X86::PINSRWrmi },
573 { X86::PMADDWDrr, X86::PMADDWDrm },
574 { X86::PMAXSWrr, X86::PMAXSWrm },
575 { X86::PMAXUBrr, X86::PMAXUBrm },
576 { X86::PMINSWrr, X86::PMINSWrm },
577 { X86::PMINUBrr, X86::PMINUBrm },
578 { X86::PMULDQrr, X86::PMULDQrm },
579 { X86::PMULDQrr_int, X86::PMULDQrm_int },
580 { X86::PMULHUWrr, X86::PMULHUWrm },
581 { X86::PMULHWrr, X86::PMULHWrm },
582 { X86::PMULLDrr, X86::PMULLDrm },
583 { X86::PMULLDrr_int, X86::PMULLDrm_int },
584 { X86::PMULLWrr, X86::PMULLWrm },
585 { X86::PMULUDQrr, X86::PMULUDQrm },
586 { X86::PORrr, X86::PORrm },
587 { X86::PSADBWrr, X86::PSADBWrm },
588 { X86::PSLLDrr, X86::PSLLDrm },
589 { X86::PSLLQrr, X86::PSLLQrm },
590 { X86::PSLLWrr, X86::PSLLWrm },
591 { X86::PSRADrr, X86::PSRADrm },
592 { X86::PSRAWrr, X86::PSRAWrm },
593 { X86::PSRLDrr, X86::PSRLDrm },
594 { X86::PSRLQrr, X86::PSRLQrm },
595 { X86::PSRLWrr, X86::PSRLWrm },
596 { X86::PSUBBrr, X86::PSUBBrm },
597 { X86::PSUBDrr, X86::PSUBDrm },
598 { X86::PSUBSBrr, X86::PSUBSBrm },
599 { X86::PSUBSWrr, X86::PSUBSWrm },
600 { X86::PSUBWrr, X86::PSUBWrm },
601 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm },
602 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm },
603 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm },
604 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm },
605 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm },
606 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm },
607 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm },
608 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm },
609 { X86::PXORrr, X86::PXORrm },
610 { X86::SBB32rr, X86::SBB32rm },
611 { X86::SBB64rr, X86::SBB64rm },
612 { X86::SHUFPDrri, X86::SHUFPDrmi },
613 { X86::SHUFPSrri, X86::SHUFPSrmi },
614 { X86::SUB16rr, X86::SUB16rm },
615 { X86::SUB32rr, X86::SUB32rm },
616 { X86::SUB64rr, X86::SUB64rm },
617 { X86::SUB8rr, X86::SUB8rm },
618 { X86::SUBPDrr, X86::SUBPDrm },
619 { X86::SUBPSrr, X86::SUBPSrm },
620 { X86::SUBSDrr, X86::SUBSDrm },
621 { X86::SUBSSrr, X86::SUBSSrm },
622 // FIXME: TEST*rr -> swapped operand of TEST*mr.
623 { X86::UNPCKHPDrr, X86::UNPCKHPDrm },
624 { X86::UNPCKHPSrr, X86::UNPCKHPSrm },
625 { X86::UNPCKLPDrr, X86::UNPCKLPDrm },
626 { X86::UNPCKLPSrr, X86::UNPCKLPSrm },
627 { X86::XOR16rr, X86::XOR16rm },
628 { X86::XOR32rr, X86::XOR32rm },
629 { X86::XOR64rr, X86::XOR64rm },
630 { X86::XOR8rr, X86::XOR8rm },
631 { X86::XORPDrr, X86::XORPDrm },
632 { X86::XORPSrr, X86::XORPSrm }
635 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
636 unsigned RegOp = OpTbl2[i][0];
637 unsigned MemOp = OpTbl2[i][1];
638 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
640 assert(false && "Duplicated entries?");
641 unsigned AuxInfo = 2 | (1 << 4); // Index 1, folded load
642 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
643 std::make_pair(RegOp, AuxInfo))).second)
644 AmbEntries.push_back(MemOp);
647 // Remove ambiguous entries.
648 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
651 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
653 unsigned& destReg) const {
654 switch (MI.getOpcode()) {
661 case X86::MOV16to16_:
662 case X86::MOV32to32_:
666 // FP Stack register class copies
667 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
668 case X86::MOV_Fp3264: case X86::MOV_Fp3280:
669 case X86::MOV_Fp6432: case X86::MOV_Fp8032:
671 case X86::FsMOVAPSrr:
672 case X86::FsMOVAPDrr:
675 case X86::MOVSS2PSrr:
676 case X86::MOVSD2PDrr:
677 case X86::MOVPS2SSrr:
678 case X86::MOVPD2SDrr:
679 case X86::MMX_MOVD64rr:
680 case X86::MMX_MOVQ64rr:
681 assert(MI.getNumOperands() >= 2 &&
682 MI.getOperand(0).isRegister() &&
683 MI.getOperand(1).isRegister() &&
684 "invalid register-register move instruction");
685 sourceReg = MI.getOperand(1).getReg();
686 destReg = MI.getOperand(0).getReg();
691 unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
692 int &FrameIndex) const {
693 switch (MI->getOpcode()) {
706 case X86::MMX_MOVD64rm:
707 case X86::MMX_MOVQ64rm:
708 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
709 MI->getOperand(3).isReg() && MI->getOperand(4).isImm() &&
710 MI->getOperand(2).getImm() == 1 &&
711 MI->getOperand(3).getReg() == 0 &&
712 MI->getOperand(4).getImm() == 0) {
713 FrameIndex = MI->getOperand(1).getIndex();
714 return MI->getOperand(0).getReg();
721 unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
722 int &FrameIndex) const {
723 switch (MI->getOpcode()) {
736 case X86::MMX_MOVD64mr:
737 case X86::MMX_MOVQ64mr:
738 case X86::MMX_MOVNTQmr:
739 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
740 MI->getOperand(2).isReg() && MI->getOperand(3).isImm() &&
741 MI->getOperand(1).getImm() == 1 &&
742 MI->getOperand(2).getReg() == 0 &&
743 MI->getOperand(3).getImm() == 0) {
744 FrameIndex = MI->getOperand(0).getIndex();
745 return MI->getOperand(4).getReg();
753 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
755 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
756 bool isPICBase = false;
757 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
758 E = MRI.def_end(); I != E; ++I) {
759 MachineInstr *DefMI = I.getOperand().getParent();
760 if (DefMI->getOpcode() != X86::MOVPC32r)
762 assert(!isPICBase && "More than one PIC base?");
768 /// isGVStub - Return true if the GV requires an extra load to get the
770 static inline bool isGVStub(GlobalValue *GV, X86TargetMachine &TM) {
771 return TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false);
775 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
776 switch (MI->getOpcode()) {
789 case X86::MMX_MOVD64rm:
790 case X86::MMX_MOVQ64rm: {
791 // Loads from constant pools are trivially rematerializable.
792 if (MI->getOperand(1).isReg() &&
793 MI->getOperand(2).isImm() &&
794 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
795 (MI->getOperand(4).isCPI() ||
796 (MI->getOperand(4).isGlobal() &&
797 isGVStub(MI->getOperand(4).getGlobal(), TM)))) {
798 unsigned BaseReg = MI->getOperand(1).getReg();
801 // Allow re-materialization of PIC load.
802 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
804 const MachineFunction &MF = *MI->getParent()->getParent();
805 const MachineRegisterInfo &MRI = MF.getRegInfo();
806 bool isPICBase = false;
807 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
808 E = MRI.def_end(); I != E; ++I) {
809 MachineInstr *DefMI = I.getOperand().getParent();
810 if (DefMI->getOpcode() != X86::MOVPC32r)
812 assert(!isPICBase && "More than one PIC base?");
822 if (MI->getOperand(1).isReg() &&
823 MI->getOperand(2).isImm() &&
824 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
825 !MI->getOperand(4).isReg()) {
826 // lea fi#, lea GV, etc. are all rematerializable.
827 unsigned BaseReg = MI->getOperand(1).getReg();
830 // Allow re-materialization of lea PICBase + x.
831 const MachineFunction &MF = *MI->getParent()->getParent();
832 const MachineRegisterInfo &MRI = MF.getRegInfo();
833 return regIsPICBase(BaseReg, MRI);
839 // All other instructions marked M_REMATERIALIZABLE are always trivially
844 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
845 /// would clobber the EFLAGS condition register. Note the result may be
846 /// conservative. If it cannot definitely determine the safety after visiting
847 /// two instructions it assumes it's not safe.
848 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
849 MachineBasicBlock::iterator I) {
850 // For compile time consideration, if we are not able to determine the
851 // safety after visiting 2 instructions, we will assume it's not safe.
852 for (unsigned i = 0; i < 2; ++i) {
854 // Reached end of block, it's safe.
856 bool SeenDef = false;
857 for (unsigned j = 0, e = I->getNumOperands(); j != e; ++j) {
858 MachineOperand &MO = I->getOperand(j);
859 if (!MO.isRegister())
861 if (MO.getReg() == X86::EFLAGS) {
869 // This instruction defines EFLAGS, no need to look any further.
874 // Conservative answer.
878 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
879 MachineBasicBlock::iterator I,
881 const MachineInstr *Orig) const {
882 unsigned SubIdx = Orig->getOperand(0).isReg()
883 ? Orig->getOperand(0).getSubReg() : 0;
884 bool ChangeSubIdx = SubIdx != 0;
885 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
886 DestReg = RI.getSubReg(DestReg, SubIdx);
890 // MOV32r0 etc. are implemented with xor which clobbers condition code.
891 // Re-materialize them as movri instructions to avoid side effects.
892 bool Emitted = false;
893 switch (Orig->getOpcode()) {
899 if (!isSafeToClobberEFLAGS(MBB, I)) {
901 switch (Orig->getOpcode()) {
903 case X86::MOV8r0: Opc = X86::MOV8ri; break;
904 case X86::MOV16r0: Opc = X86::MOV16ri; break;
905 case X86::MOV32r0: Opc = X86::MOV32ri; break;
906 case X86::MOV64r0: Opc = X86::MOV64ri32; break;
908 BuildMI(MBB, I, get(Opc), DestReg).addImm(0);
916 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
917 MI->getOperand(0).setReg(DestReg);
922 MachineInstr *NewMI = prior(I);
923 NewMI->getOperand(0).setSubReg(SubIdx);
927 /// isInvariantLoad - Return true if the specified instruction (which is marked
928 /// mayLoad) is loading from a location whose value is invariant across the
929 /// function. For example, loading a value from the constant pool or from
930 /// from the argument area of a function if it does not change. This should
931 /// only return true of *all* loads the instruction does are invariant (if it
932 /// does multiple loads).
933 bool X86InstrInfo::isInvariantLoad(MachineInstr *MI) const {
934 // This code cares about loads from three cases: constant pool entries,
935 // invariant argument slots, and global stubs. In order to handle these cases
936 // for all of the myriad of X86 instructions, we just scan for a CP/FI/GV
937 // operand and base our analysis on it. This is safe because the address of
938 // none of these three cases is ever used as anything other than a load base
939 // and X86 doesn't have any instructions that load from multiple places.
941 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
942 const MachineOperand &MO = MI->getOperand(i);
943 // Loads from constant pools are trivially invariant.
948 return isGVStub(MO.getGlobal(), TM);
950 // If this is a load from an invariant stack slot, the load is a constant.
952 const MachineFrameInfo &MFI =
953 *MI->getParent()->getParent()->getFrameInfo();
954 int Idx = MO.getIndex();
955 return MFI.isFixedObjectIndex(Idx) && MFI.isImmutableObjectIndex(Idx);
959 // All other instances of these instructions are presumed to have other
964 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
965 /// is not marked dead.
966 static bool hasLiveCondCodeDef(MachineInstr *MI) {
967 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
968 MachineOperand &MO = MI->getOperand(i);
969 if (MO.isRegister() && MO.isDef() &&
970 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
977 /// convertToThreeAddress - This method must be implemented by targets that
978 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
979 /// may be able to convert a two-address instruction into a true
980 /// three-address instruction on demand. This allows the X86 target (for
981 /// example) to convert ADD and SHL instructions into LEA instructions if they
982 /// would require register copies due to two-addressness.
984 /// This method returns a null pointer if the transformation cannot be
985 /// performed, otherwise it returns the new instruction.
988 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
989 MachineBasicBlock::iterator &MBBI,
990 LiveVariables *LV) const {
991 MachineInstr *MI = MBBI;
992 MachineFunction &MF = *MI->getParent()->getParent();
993 // All instructions input are two-addr instructions. Get the known operands.
994 unsigned Dest = MI->getOperand(0).getReg();
995 unsigned Src = MI->getOperand(1).getReg();
996 bool isDead = MI->getOperand(0).isDead();
997 bool isKill = MI->getOperand(1).isKill();
999 MachineInstr *NewMI = NULL;
1000 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1001 // we have better subtarget support, enable the 16-bit LEA generation here.
1002 bool DisableLEA16 = true;
1004 unsigned MIOpc = MI->getOpcode();
1006 case X86::SHUFPSrri: {
1007 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1008 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1010 unsigned B = MI->getOperand(1).getReg();
1011 unsigned C = MI->getOperand(2).getReg();
1012 if (B != C) return 0;
1013 unsigned A = MI->getOperand(0).getReg();
1014 unsigned M = MI->getOperand(3).getImm();
1015 NewMI = BuildMI(MF, get(X86::PSHUFDri)).addReg(A, true, false, false, isDead)
1016 .addReg(B, false, false, isKill).addImm(M);
1019 case X86::SHL64ri: {
1020 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1021 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1022 // the flags produced by a shift yet, so this is safe.
1023 unsigned ShAmt = MI->getOperand(2).getImm();
1024 if (ShAmt == 0 || ShAmt >= 4) return 0;
1026 NewMI = BuildMI(MF, get(X86::LEA64r)).addReg(Dest, true, false, false, isDead)
1027 .addReg(0).addImm(1 << ShAmt).addReg(Src, false, false, isKill).addImm(0);
1030 case X86::SHL32ri: {
1031 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1032 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1033 // the flags produced by a shift yet, so this is safe.
1034 unsigned ShAmt = MI->getOperand(2).getImm();
1035 if (ShAmt == 0 || ShAmt >= 4) return 0;
1037 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
1038 X86::LEA64_32r : X86::LEA32r;
1039 NewMI = BuildMI(MF, get(Opc)).addReg(Dest, true, false, false, isDead)
1040 .addReg(0).addImm(1 << ShAmt)
1041 .addReg(Src, false, false, isKill).addImm(0);
1044 case X86::SHL16ri: {
1045 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1046 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1047 // the flags produced by a shift yet, so this is safe.
1048 unsigned ShAmt = MI->getOperand(2).getImm();
1049 if (ShAmt == 0 || ShAmt >= 4) return 0;
1052 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
1053 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1054 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1055 ? X86::LEA64_32r : X86::LEA32r;
1056 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1057 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1059 // Build and insert into an implicit UNDEF value. This is OK because
1060 // well be shifting and then extracting the lower 16-bits.
1061 BuildMI(*MFI, MBBI, get(X86::IMPLICIT_DEF), leaInReg);
1062 MachineInstr *InsMI = BuildMI(*MFI, MBBI, get(X86::INSERT_SUBREG),leaInReg)
1063 .addReg(leaInReg).addReg(Src, false, false, isKill)
1064 .addImm(X86::SUBREG_16BIT);
1066 NewMI = BuildMI(*MFI, MBBI, get(Opc), leaOutReg).addReg(0).addImm(1 << ShAmt)
1067 .addReg(leaInReg, false, false, true).addImm(0);
1069 MachineInstr *ExtMI = BuildMI(*MFI, MBBI, get(X86::EXTRACT_SUBREG))
1070 .addReg(Dest, true, false, false, isDead)
1071 .addReg(leaOutReg, false, false, true).addImm(X86::SUBREG_16BIT);
1073 // Update live variables
1074 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1075 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1077 LV->replaceKillInstruction(Src, MI, InsMI);
1079 LV->replaceKillInstruction(Dest, MI, ExtMI);
1083 NewMI = BuildMI(MF, get(X86::LEA16r)).addReg(Dest, true, false, false, isDead)
1084 .addReg(0).addImm(1 << ShAmt)
1085 .addReg(Src, false, false, isKill).addImm(0);
1090 // The following opcodes also sets the condition code register(s). Only
1091 // convert them to equivalent lea if the condition code register def's
1093 if (hasLiveCondCodeDef(MI))
1096 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1101 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1102 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1103 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1104 NewMI = addRegOffset(BuildMI(MF, get(Opc))
1105 .addReg(Dest, true, false, false, isDead),
1110 case X86::INC64_16r:
1111 if (DisableLEA16) return 0;
1112 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1113 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r))
1114 .addReg(Dest, true, false, false, isDead),
1119 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1120 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1121 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1122 NewMI = addRegOffset(BuildMI(MF, get(Opc))
1123 .addReg(Dest, true, false, false, isDead),
1128 case X86::DEC64_16r:
1129 if (DisableLEA16) return 0;
1130 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1131 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r))
1132 .addReg(Dest, true, false, false, isDead),
1136 case X86::ADD32rr: {
1137 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1138 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1139 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1140 unsigned Src2 = MI->getOperand(2).getReg();
1141 bool isKill2 = MI->getOperand(2).isKill();
1142 NewMI = addRegReg(BuildMI(MF, get(Opc))
1143 .addReg(Dest, true, false, false, isDead),
1144 Src, isKill, Src2, isKill2);
1146 LV->replaceKillInstruction(Src2, MI, NewMI);
1149 case X86::ADD16rr: {
1150 if (DisableLEA16) return 0;
1151 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1152 unsigned Src2 = MI->getOperand(2).getReg();
1153 bool isKill2 = MI->getOperand(2).isKill();
1154 NewMI = addRegReg(BuildMI(MF, get(X86::LEA16r))
1155 .addReg(Dest, true, false, false, isDead),
1156 Src, isKill, Src2, isKill2);
1158 LV->replaceKillInstruction(Src2, MI, NewMI);
1161 case X86::ADD64ri32:
1163 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1164 if (MI->getOperand(2).isImmediate())
1165 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA64r))
1166 .addReg(Dest, true, false, false, isDead),
1167 Src, isKill, MI->getOperand(2).getImm());
1171 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1172 if (MI->getOperand(2).isImmediate()) {
1173 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1174 NewMI = addRegOffset(BuildMI(MF, get(Opc))
1175 .addReg(Dest, true, false, false, isDead),
1176 Src, isKill, MI->getOperand(2).getImm());
1181 if (DisableLEA16) return 0;
1182 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1183 if (MI->getOperand(2).isImmediate())
1184 NewMI = addRegOffset(BuildMI(MF, get(X86::LEA16r))
1185 .addReg(Dest, true, false, false, isDead),
1186 Src, isKill, MI->getOperand(2).getImm());
1189 if (DisableLEA16) return 0;
1191 case X86::SHL64ri: {
1192 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImmediate() &&
1193 "Unknown shl instruction!");
1194 unsigned ShAmt = MI->getOperand(2).getImm();
1195 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
1197 AM.Scale = 1 << ShAmt;
1199 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
1200 : (MIOpc == X86::SHL32ri
1201 ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
1202 NewMI = addFullAddress(BuildMI(MF, get(Opc))
1203 .addReg(Dest, true, false, false, isDead), AM);
1205 NewMI->getOperand(3).setIsKill(true);
1213 if (!NewMI) return 0;
1215 if (LV) { // Update live variables
1217 LV->replaceKillInstruction(Src, MI, NewMI);
1219 LV->replaceKillInstruction(Dest, MI, NewMI);
1222 MFI->insert(MBBI, NewMI); // Insert the new inst
1226 /// commuteInstruction - We have a few instructions that must be hacked on to
1230 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1231 switch (MI->getOpcode()) {
1232 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1233 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1234 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1235 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1236 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1237 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1240 switch (MI->getOpcode()) {
1241 default: assert(0 && "Unreachable!");
1242 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1243 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1244 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1245 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1246 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1247 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1249 unsigned Amt = MI->getOperand(3).getImm();
1250 unsigned A = MI->getOperand(0).getReg();
1251 unsigned B = MI->getOperand(1).getReg();
1252 unsigned C = MI->getOperand(2).getReg();
1253 bool AisDead = MI->getOperand(0).isDead();
1254 bool BisKill = MI->getOperand(1).isKill();
1255 bool CisKill = MI->getOperand(2).isKill();
1256 // If machine instrs are no longer in two-address forms, update
1257 // destination register as well.
1259 // Must be two address instruction!
1260 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
1261 "Expecting a two-address instruction!");
1265 MachineFunction &MF = *MI->getParent()->getParent();
1266 return BuildMI(MF, get(Opc))
1267 .addReg(A, true, false, false, AisDead)
1268 .addReg(C, false, false, CisKill)
1269 .addReg(B, false, false, BisKill).addImm(Size-Amt);
1271 case X86::CMOVB16rr:
1272 case X86::CMOVB32rr:
1273 case X86::CMOVB64rr:
1274 case X86::CMOVAE16rr:
1275 case X86::CMOVAE32rr:
1276 case X86::CMOVAE64rr:
1277 case X86::CMOVE16rr:
1278 case X86::CMOVE32rr:
1279 case X86::CMOVE64rr:
1280 case X86::CMOVNE16rr:
1281 case X86::CMOVNE32rr:
1282 case X86::CMOVNE64rr:
1283 case X86::CMOVBE16rr:
1284 case X86::CMOVBE32rr:
1285 case X86::CMOVBE64rr:
1286 case X86::CMOVA16rr:
1287 case X86::CMOVA32rr:
1288 case X86::CMOVA64rr:
1289 case X86::CMOVL16rr:
1290 case X86::CMOVL32rr:
1291 case X86::CMOVL64rr:
1292 case X86::CMOVGE16rr:
1293 case X86::CMOVGE32rr:
1294 case X86::CMOVGE64rr:
1295 case X86::CMOVLE16rr:
1296 case X86::CMOVLE32rr:
1297 case X86::CMOVLE64rr:
1298 case X86::CMOVG16rr:
1299 case X86::CMOVG32rr:
1300 case X86::CMOVG64rr:
1301 case X86::CMOVS16rr:
1302 case X86::CMOVS32rr:
1303 case X86::CMOVS64rr:
1304 case X86::CMOVNS16rr:
1305 case X86::CMOVNS32rr:
1306 case X86::CMOVNS64rr:
1307 case X86::CMOVP16rr:
1308 case X86::CMOVP32rr:
1309 case X86::CMOVP64rr:
1310 case X86::CMOVNP16rr:
1311 case X86::CMOVNP32rr:
1312 case X86::CMOVNP64rr: {
1314 switch (MI->getOpcode()) {
1316 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1317 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1318 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1319 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1320 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1321 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1322 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1323 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1324 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1325 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1326 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1327 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1328 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1329 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1330 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1331 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1332 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1333 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1334 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1335 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1336 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1337 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1338 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1339 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1340 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1341 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1342 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1343 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1344 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1345 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1346 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1347 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1348 case X86::CMOVS64rr: Opc = X86::CMOVNS32rr; break;
1349 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1350 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1351 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1352 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1353 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1354 case X86::CMOVP64rr: Opc = X86::CMOVNP32rr; break;
1355 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1356 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1357 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1360 MI->setDesc(get(Opc));
1361 // Fallthrough intended.
1364 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1368 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1370 default: return X86::COND_INVALID;
1371 case X86::JE: return X86::COND_E;
1372 case X86::JNE: return X86::COND_NE;
1373 case X86::JL: return X86::COND_L;
1374 case X86::JLE: return X86::COND_LE;
1375 case X86::JG: return X86::COND_G;
1376 case X86::JGE: return X86::COND_GE;
1377 case X86::JB: return X86::COND_B;
1378 case X86::JBE: return X86::COND_BE;
1379 case X86::JA: return X86::COND_A;
1380 case X86::JAE: return X86::COND_AE;
1381 case X86::JS: return X86::COND_S;
1382 case X86::JNS: return X86::COND_NS;
1383 case X86::JP: return X86::COND_P;
1384 case X86::JNP: return X86::COND_NP;
1385 case X86::JO: return X86::COND_O;
1386 case X86::JNO: return X86::COND_NO;
1390 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1392 default: assert(0 && "Illegal condition code!");
1393 case X86::COND_E: return X86::JE;
1394 case X86::COND_NE: return X86::JNE;
1395 case X86::COND_L: return X86::JL;
1396 case X86::COND_LE: return X86::JLE;
1397 case X86::COND_G: return X86::JG;
1398 case X86::COND_GE: return X86::JGE;
1399 case X86::COND_B: return X86::JB;
1400 case X86::COND_BE: return X86::JBE;
1401 case X86::COND_A: return X86::JA;
1402 case X86::COND_AE: return X86::JAE;
1403 case X86::COND_S: return X86::JS;
1404 case X86::COND_NS: return X86::JNS;
1405 case X86::COND_P: return X86::JP;
1406 case X86::COND_NP: return X86::JNP;
1407 case X86::COND_O: return X86::JO;
1408 case X86::COND_NO: return X86::JNO;
1412 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1413 /// e.g. turning COND_E to COND_NE.
1414 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1416 default: assert(0 && "Illegal condition code!");
1417 case X86::COND_E: return X86::COND_NE;
1418 case X86::COND_NE: return X86::COND_E;
1419 case X86::COND_L: return X86::COND_GE;
1420 case X86::COND_LE: return X86::COND_G;
1421 case X86::COND_G: return X86::COND_LE;
1422 case X86::COND_GE: return X86::COND_L;
1423 case X86::COND_B: return X86::COND_AE;
1424 case X86::COND_BE: return X86::COND_A;
1425 case X86::COND_A: return X86::COND_BE;
1426 case X86::COND_AE: return X86::COND_B;
1427 case X86::COND_S: return X86::COND_NS;
1428 case X86::COND_NS: return X86::COND_S;
1429 case X86::COND_P: return X86::COND_NP;
1430 case X86::COND_NP: return X86::COND_P;
1431 case X86::COND_O: return X86::COND_NO;
1432 case X86::COND_NO: return X86::COND_O;
1436 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1437 const TargetInstrDesc &TID = MI->getDesc();
1438 if (!TID.isTerminator()) return false;
1440 // Conditional branch is a special case.
1441 if (TID.isBranch() && !TID.isBarrier())
1443 if (!TID.isPredicable())
1445 return !isPredicated(MI);
1448 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1449 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1450 const X86InstrInfo &TII) {
1451 if (MI->getOpcode() == X86::FP_REG_KILL)
1453 return TII.isUnpredicatedTerminator(MI);
1456 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1457 MachineBasicBlock *&TBB,
1458 MachineBasicBlock *&FBB,
1459 SmallVectorImpl<MachineOperand> &Cond) const {
1460 // If the block has no terminators, it just falls into the block after it.
1461 MachineBasicBlock::iterator I = MBB.end();
1462 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this))
1465 // Get the last instruction in the block.
1466 MachineInstr *LastInst = I;
1468 // If there is only one terminator instruction, process it.
1469 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) {
1470 if (!LastInst->getDesc().isBranch())
1473 // If the block ends with a branch there are 3 possibilities:
1474 // it's an unconditional, conditional, or indirect branch.
1476 if (LastInst->getOpcode() == X86::JMP) {
1477 TBB = LastInst->getOperand(0).getMBB();
1480 X86::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
1481 if (BranchCode == X86::COND_INVALID)
1482 return true; // Can't handle indirect branch.
1484 // Otherwise, block ends with fall-through condbranch.
1485 TBB = LastInst->getOperand(0).getMBB();
1486 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1490 // Get the instruction before it if it's a terminator.
1491 MachineInstr *SecondLastInst = I;
1493 // If there are three terminators, we don't know what sort of block this is.
1494 if (SecondLastInst && I != MBB.begin() &&
1495 isBrAnalysisUnpredicatedTerminator(--I, *this))
1498 // If the block ends with X86::JMP and a conditional branch, handle it.
1499 X86::CondCode BranchCode = GetCondFromBranchOpc(SecondLastInst->getOpcode());
1500 if (BranchCode != X86::COND_INVALID && LastInst->getOpcode() == X86::JMP) {
1501 TBB = SecondLastInst->getOperand(0).getMBB();
1502 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1503 FBB = LastInst->getOperand(0).getMBB();
1507 // If the block ends with two X86::JMPs, handle it. The second one is not
1508 // executed, so remove it.
1509 if (SecondLastInst->getOpcode() == X86::JMP &&
1510 LastInst->getOpcode() == X86::JMP) {
1511 TBB = SecondLastInst->getOperand(0).getMBB();
1513 I->eraseFromParent();
1517 // Otherwise, can't handle this.
1521 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1522 MachineBasicBlock::iterator I = MBB.end();
1523 if (I == MBB.begin()) return 0;
1525 if (I->getOpcode() != X86::JMP &&
1526 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1529 // Remove the branch.
1530 I->eraseFromParent();
1534 if (I == MBB.begin()) return 1;
1536 if (GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1539 // Remove the branch.
1540 I->eraseFromParent();
1544 static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
1545 MachineOperand &MO) {
1546 if (MO.isRegister())
1547 MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(),
1548 MO.isKill(), MO.isDead(), MO.getSubReg());
1549 else if (MO.isImmediate())
1550 MIB = MIB.addImm(MO.getImm());
1551 else if (MO.isFrameIndex())
1552 MIB = MIB.addFrameIndex(MO.getIndex());
1553 else if (MO.isGlobalAddress())
1554 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
1555 else if (MO.isConstantPoolIndex())
1556 MIB = MIB.addConstantPoolIndex(MO.getIndex(), MO.getOffset());
1557 else if (MO.isJumpTableIndex())
1558 MIB = MIB.addJumpTableIndex(MO.getIndex());
1559 else if (MO.isExternalSymbol())
1560 MIB = MIB.addExternalSymbol(MO.getSymbolName());
1562 assert(0 && "Unknown operand for X86InstrAddOperand!");
1568 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1569 MachineBasicBlock *FBB,
1570 const SmallVectorImpl<MachineOperand> &Cond) const {
1571 // Shouldn't be a fall through.
1572 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1573 assert((Cond.size() == 1 || Cond.size() == 0) &&
1574 "X86 branch conditions have one component!");
1576 if (FBB == 0) { // One way branch.
1578 // Unconditional branch?
1579 BuildMI(&MBB, get(X86::JMP)).addMBB(TBB);
1581 // Conditional branch.
1582 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
1583 BuildMI(&MBB, get(Opc)).addMBB(TBB);
1588 // Two-way Conditional branch.
1589 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
1590 BuildMI(&MBB, get(Opc)).addMBB(TBB);
1591 BuildMI(&MBB, get(X86::JMP)).addMBB(FBB);
1595 bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1596 MachineBasicBlock::iterator MI,
1597 unsigned DestReg, unsigned SrcReg,
1598 const TargetRegisterClass *DestRC,
1599 const TargetRegisterClass *SrcRC) const {
1600 if (DestRC == SrcRC) {
1602 if (DestRC == &X86::GR64RegClass) {
1604 } else if (DestRC == &X86::GR32RegClass) {
1606 } else if (DestRC == &X86::GR16RegClass) {
1608 } else if (DestRC == &X86::GR8RegClass) {
1610 } else if (DestRC == &X86::GR32_RegClass) {
1611 Opc = X86::MOV32_rr;
1612 } else if (DestRC == &X86::GR16_RegClass) {
1613 Opc = X86::MOV16_rr;
1614 } else if (DestRC == &X86::RFP32RegClass) {
1615 Opc = X86::MOV_Fp3232;
1616 } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) {
1617 Opc = X86::MOV_Fp6464;
1618 } else if (DestRC == &X86::RFP80RegClass) {
1619 Opc = X86::MOV_Fp8080;
1620 } else if (DestRC == &X86::FR32RegClass) {
1621 Opc = X86::FsMOVAPSrr;
1622 } else if (DestRC == &X86::FR64RegClass) {
1623 Opc = X86::FsMOVAPDrr;
1624 } else if (DestRC == &X86::VR128RegClass) {
1625 Opc = X86::MOVAPSrr;
1626 } else if (DestRC == &X86::VR64RegClass) {
1627 Opc = X86::MMX_MOVQ64rr;
1631 BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
1635 // Moving EFLAGS to / from another register requires a push and a pop.
1636 if (SrcRC == &X86::CCRRegClass) {
1637 assert(SrcReg == X86::EFLAGS);
1638 if (DestRC == &X86::GR64RegClass) {
1639 BuildMI(MBB, MI, get(X86::PUSHFQ));
1640 BuildMI(MBB, MI, get(X86::POP64r), DestReg);
1642 } else if (DestRC == &X86::GR32RegClass) {
1643 BuildMI(MBB, MI, get(X86::PUSHFD));
1644 BuildMI(MBB, MI, get(X86::POP32r), DestReg);
1647 } else if (DestRC == &X86::CCRRegClass) {
1648 assert(DestReg == X86::EFLAGS);
1649 if (SrcRC == &X86::GR64RegClass) {
1650 BuildMI(MBB, MI, get(X86::PUSH64r)).addReg(SrcReg);
1651 BuildMI(MBB, MI, get(X86::POPFQ));
1653 } else if (SrcRC == &X86::GR32RegClass) {
1654 BuildMI(MBB, MI, get(X86::PUSH32r)).addReg(SrcReg);
1655 BuildMI(MBB, MI, get(X86::POPFD));
1660 // Moving from ST(0) turns into FpGET_ST0_32 etc.
1661 if (SrcRC == &X86::RSTRegClass) {
1662 // Copying from ST(0)/ST(1).
1663 if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
1664 // Can only copy from ST(0)/ST(1) right now
1666 bool isST0 = SrcReg == X86::ST0;
1668 if (DestRC == &X86::RFP32RegClass)
1669 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
1670 else if (DestRC == &X86::RFP64RegClass)
1671 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
1673 assert(DestRC == &X86::RFP80RegClass);
1674 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
1676 BuildMI(MBB, MI, get(Opc), DestReg);
1680 // Moving to ST(0) turns into FpSET_ST0_32 etc.
1681 if (DestRC == &X86::RSTRegClass) {
1682 // Copying to ST(0). FIXME: handle ST(1) also
1683 if (DestReg != X86::ST0)
1684 // Can only copy to TOS right now
1687 if (SrcRC == &X86::RFP32RegClass)
1688 Opc = X86::FpSET_ST0_32;
1689 else if (SrcRC == &X86::RFP64RegClass)
1690 Opc = X86::FpSET_ST0_64;
1692 assert(SrcRC == &X86::RFP80RegClass);
1693 Opc = X86::FpSET_ST0_80;
1695 BuildMI(MBB, MI, get(Opc)).addReg(SrcReg);
1699 // Not yet supported!
1703 static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
1704 bool isStackAligned) {
1706 if (RC == &X86::GR64RegClass) {
1708 } else if (RC == &X86::GR32RegClass) {
1710 } else if (RC == &X86::GR16RegClass) {
1712 } else if (RC == &X86::GR8RegClass) {
1714 } else if (RC == &X86::GR32_RegClass) {
1715 Opc = X86::MOV32_mr;
1716 } else if (RC == &X86::GR16_RegClass) {
1717 Opc = X86::MOV16_mr;
1718 } else if (RC == &X86::RFP80RegClass) {
1719 Opc = X86::ST_FpP80m; // pops
1720 } else if (RC == &X86::RFP64RegClass) {
1721 Opc = X86::ST_Fp64m;
1722 } else if (RC == &X86::RFP32RegClass) {
1723 Opc = X86::ST_Fp32m;
1724 } else if (RC == &X86::FR32RegClass) {
1726 } else if (RC == &X86::FR64RegClass) {
1728 } else if (RC == &X86::VR128RegClass) {
1729 // If stack is realigned we can use aligned stores.
1730 Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr;
1731 } else if (RC == &X86::VR64RegClass) {
1732 Opc = X86::MMX_MOVQ64mr;
1734 assert(0 && "Unknown regclass");
1741 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1742 MachineBasicBlock::iterator MI,
1743 unsigned SrcReg, bool isKill, int FrameIdx,
1744 const TargetRegisterClass *RC) const {
1745 const MachineFunction &MF = *MBB.getParent();
1746 bool isAligned = (RI.getStackAlignment() >= 16) ||
1747 RI.needsStackRealignment(MF);
1748 unsigned Opc = getStoreRegOpcode(RC, isAligned);
1749 addFrameReference(BuildMI(MBB, MI, get(Opc)), FrameIdx)
1750 .addReg(SrcReg, false, false, isKill);
1753 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
1755 SmallVectorImpl<MachineOperand> &Addr,
1756 const TargetRegisterClass *RC,
1757 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1758 bool isAligned = (RI.getStackAlignment() >= 16) ||
1759 RI.needsStackRealignment(MF);
1760 unsigned Opc = getStoreRegOpcode(RC, isAligned);
1761 MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
1762 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1763 MIB = X86InstrAddOperand(MIB, Addr[i]);
1764 MIB.addReg(SrcReg, false, false, isKill);
1765 NewMIs.push_back(MIB);
1768 static unsigned getLoadRegOpcode(const TargetRegisterClass *RC,
1769 bool isStackAligned) {
1771 if (RC == &X86::GR64RegClass) {
1773 } else if (RC == &X86::GR32RegClass) {
1775 } else if (RC == &X86::GR16RegClass) {
1777 } else if (RC == &X86::GR8RegClass) {
1779 } else if (RC == &X86::GR32_RegClass) {
1780 Opc = X86::MOV32_rm;
1781 } else if (RC == &X86::GR16_RegClass) {
1782 Opc = X86::MOV16_rm;
1783 } else if (RC == &X86::RFP80RegClass) {
1784 Opc = X86::LD_Fp80m;
1785 } else if (RC == &X86::RFP64RegClass) {
1786 Opc = X86::LD_Fp64m;
1787 } else if (RC == &X86::RFP32RegClass) {
1788 Opc = X86::LD_Fp32m;
1789 } else if (RC == &X86::FR32RegClass) {
1791 } else if (RC == &X86::FR64RegClass) {
1793 } else if (RC == &X86::VR128RegClass) {
1794 // If stack is realigned we can use aligned loads.
1795 Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm;
1796 } else if (RC == &X86::VR64RegClass) {
1797 Opc = X86::MMX_MOVQ64rm;
1799 assert(0 && "Unknown regclass");
1806 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1807 MachineBasicBlock::iterator MI,
1808 unsigned DestReg, int FrameIdx,
1809 const TargetRegisterClass *RC) const{
1810 const MachineFunction &MF = *MBB.getParent();
1811 bool isAligned = (RI.getStackAlignment() >= 16) ||
1812 RI.needsStackRealignment(MF);
1813 unsigned Opc = getLoadRegOpcode(RC, isAligned);
1814 addFrameReference(BuildMI(MBB, MI, get(Opc), DestReg), FrameIdx);
1817 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
1818 SmallVectorImpl<MachineOperand> &Addr,
1819 const TargetRegisterClass *RC,
1820 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1821 bool isAligned = (RI.getStackAlignment() >= 16) ||
1822 RI.needsStackRealignment(MF);
1823 unsigned Opc = getLoadRegOpcode(RC, isAligned);
1824 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
1825 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1826 MIB = X86InstrAddOperand(MIB, Addr[i]);
1827 NewMIs.push_back(MIB);
1830 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1831 MachineBasicBlock::iterator MI,
1832 const std::vector<CalleeSavedInfo> &CSI) const {
1836 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1837 unsigned SlotSize = is64Bit ? 8 : 4;
1839 MachineFunction &MF = *MBB.getParent();
1840 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1841 X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize);
1843 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
1844 for (unsigned i = CSI.size(); i != 0; --i) {
1845 unsigned Reg = CSI[i-1].getReg();
1846 // Add the callee-saved register as live-in. It's killed at the spill.
1848 BuildMI(MBB, MI, get(Opc)).addReg(Reg);
1853 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1854 MachineBasicBlock::iterator MI,
1855 const std::vector<CalleeSavedInfo> &CSI) const {
1859 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1861 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
1862 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1863 unsigned Reg = CSI[i].getReg();
1864 BuildMI(MBB, MI, get(Opc), Reg);
1869 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
1870 SmallVector<MachineOperand,4> &MOs,
1871 MachineInstr *MI, const TargetInstrInfo &TII) {
1872 // Create the base instruction with the memory operand as the first part.
1873 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true);
1874 MachineInstrBuilder MIB(NewMI);
1875 unsigned NumAddrOps = MOs.size();
1876 for (unsigned i = 0; i != NumAddrOps; ++i)
1877 MIB = X86InstrAddOperand(MIB, MOs[i]);
1878 if (NumAddrOps < 4) // FrameIndex only
1879 MIB.addImm(1).addReg(0).addImm(0);
1881 // Loop over the rest of the ri operands, converting them over.
1882 unsigned NumOps = MI->getDesc().getNumOperands()-2;
1883 for (unsigned i = 0; i != NumOps; ++i) {
1884 MachineOperand &MO = MI->getOperand(i+2);
1885 MIB = X86InstrAddOperand(MIB, MO);
1887 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
1888 MachineOperand &MO = MI->getOperand(i);
1889 MIB = X86InstrAddOperand(MIB, MO);
1894 static MachineInstr *FuseInst(MachineFunction &MF,
1895 unsigned Opcode, unsigned OpNo,
1896 SmallVector<MachineOperand,4> &MOs,
1897 MachineInstr *MI, const TargetInstrInfo &TII) {
1898 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), true);
1899 MachineInstrBuilder MIB(NewMI);
1901 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1902 MachineOperand &MO = MI->getOperand(i);
1904 assert(MO.isRegister() && "Expected to fold into reg operand!");
1905 unsigned NumAddrOps = MOs.size();
1906 for (unsigned i = 0; i != NumAddrOps; ++i)
1907 MIB = X86InstrAddOperand(MIB, MOs[i]);
1908 if (NumAddrOps < 4) // FrameIndex only
1909 MIB.addImm(1).addReg(0).addImm(0);
1911 MIB = X86InstrAddOperand(MIB, MO);
1917 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
1918 SmallVector<MachineOperand,4> &MOs,
1920 MachineFunction &MF = *MI->getParent()->getParent();
1921 MachineInstrBuilder MIB = BuildMI(MF, TII.get(Opcode));
1923 unsigned NumAddrOps = MOs.size();
1924 for (unsigned i = 0; i != NumAddrOps; ++i)
1925 MIB = X86InstrAddOperand(MIB, MOs[i]);
1926 if (NumAddrOps < 4) // FrameIndex only
1927 MIB.addImm(1).addReg(0).addImm(0);
1928 return MIB.addImm(0);
1932 X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
1933 MachineInstr *MI, unsigned i,
1934 SmallVector<MachineOperand,4> &MOs) const {
1935 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
1936 bool isTwoAddrFold = false;
1937 unsigned NumOps = MI->getDesc().getNumOperands();
1938 bool isTwoAddr = NumOps > 1 &&
1939 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
1941 MachineInstr *NewMI = NULL;
1942 // Folding a memory location into the two-address part of a two-address
1943 // instruction is different than folding it other places. It requires
1944 // replacing the *two* registers with the memory location.
1945 if (isTwoAddr && NumOps >= 2 && i < 2 &&
1946 MI->getOperand(0).isRegister() &&
1947 MI->getOperand(1).isRegister() &&
1948 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
1949 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
1950 isTwoAddrFold = true;
1951 } else if (i == 0) { // If operand 0
1952 if (MI->getOpcode() == X86::MOV16r0)
1953 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
1954 else if (MI->getOpcode() == X86::MOV32r0)
1955 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
1956 else if (MI->getOpcode() == X86::MOV64r0)
1957 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
1958 else if (MI->getOpcode() == X86::MOV8r0)
1959 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
1963 OpcodeTablePtr = &RegOp2MemOpTable0;
1964 } else if (i == 1) {
1965 OpcodeTablePtr = &RegOp2MemOpTable1;
1966 } else if (i == 2) {
1967 OpcodeTablePtr = &RegOp2MemOpTable2;
1970 // If table selected...
1971 if (OpcodeTablePtr) {
1972 // Find the Opcode to fuse
1973 DenseMap<unsigned*, unsigned>::iterator I =
1974 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
1975 if (I != OpcodeTablePtr->end()) {
1977 NewMI = FuseTwoAddrInst(MF, I->second, MOs, MI, *this);
1979 NewMI = FuseInst(MF, I->second, i, MOs, MI, *this);
1985 if (PrintFailedFusing)
1986 cerr << "We failed to fuse operand " << i << *MI;
1991 MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
1993 SmallVectorImpl<unsigned> &Ops,
1994 int FrameIndex) const {
1995 // Check switch flag
1996 if (NoFusing) return NULL;
1998 const MachineFrameInfo *MFI = MF.getFrameInfo();
1999 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2000 // FIXME: Move alignment requirement into tables?
2001 if (Alignment < 16) {
2002 switch (MI->getOpcode()) {
2004 // Not always safe to fold movsd into these instructions since their load
2005 // folding variants expects the address to be 16 byte aligned.
2006 case X86::FsANDNPDrr:
2007 case X86::FsANDNPSrr:
2008 case X86::FsANDPDrr:
2009 case X86::FsANDPSrr:
2012 case X86::FsXORPDrr:
2013 case X86::FsXORPSrr:
2018 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2019 unsigned NewOpc = 0;
2020 switch (MI->getOpcode()) {
2021 default: return NULL;
2022 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2023 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2024 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2025 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2027 // Change to CMPXXri r, 0 first.
2028 MI->setDesc(get(NewOpc));
2029 MI->getOperand(1).ChangeToImmediate(0);
2030 } else if (Ops.size() != 1)
2033 SmallVector<MachineOperand,4> MOs;
2034 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2035 return foldMemoryOperand(MF, MI, Ops[0], MOs);
2038 MachineInstr* X86InstrInfo::foldMemoryOperand(MachineFunction &MF,
2040 SmallVectorImpl<unsigned> &Ops,
2041 MachineInstr *LoadMI) const {
2042 // Check switch flag
2043 if (NoFusing) return NULL;
2045 // Determine the alignment of the load.
2046 unsigned Alignment = 0;
2047 if (LoadMI->hasOneMemOperand())
2048 Alignment = LoadMI->memoperands_begin()->getAlignment();
2050 // FIXME: Move alignment requirement into tables?
2051 if (Alignment < 16) {
2052 switch (MI->getOpcode()) {
2054 // Not always safe to fold movsd into these instructions since their load
2055 // folding variants expects the address to be 16 byte aligned.
2056 case X86::FsANDNPDrr:
2057 case X86::FsANDNPSrr:
2058 case X86::FsANDPDrr:
2059 case X86::FsANDPSrr:
2062 case X86::FsXORPDrr:
2063 case X86::FsXORPSrr:
2068 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2069 unsigned NewOpc = 0;
2070 switch (MI->getOpcode()) {
2071 default: return NULL;
2072 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2073 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2074 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2075 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2077 // Change to CMPXXri r, 0 first.
2078 MI->setDesc(get(NewOpc));
2079 MI->getOperand(1).ChangeToImmediate(0);
2080 } else if (Ops.size() != 1)
2083 SmallVector<MachineOperand,4> MOs;
2084 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2085 for (unsigned i = NumOps - 4; i != NumOps; ++i)
2086 MOs.push_back(LoadMI->getOperand(i));
2087 return foldMemoryOperand(MF, MI, Ops[0], MOs);
2091 bool X86InstrInfo::canFoldMemoryOperand(MachineInstr *MI,
2092 SmallVectorImpl<unsigned> &Ops) const {
2093 // Check switch flag
2094 if (NoFusing) return 0;
2096 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2097 switch (MI->getOpcode()) {
2098 default: return false;
2107 if (Ops.size() != 1)
2110 unsigned OpNum = Ops[0];
2111 unsigned Opc = MI->getOpcode();
2112 unsigned NumOps = MI->getDesc().getNumOperands();
2113 bool isTwoAddr = NumOps > 1 &&
2114 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2116 // Folding a memory location into the two-address part of a two-address
2117 // instruction is different than folding it other places. It requires
2118 // replacing the *two* registers with the memory location.
2119 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
2120 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2121 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2122 } else if (OpNum == 0) { // If operand 0
2131 OpcodeTablePtr = &RegOp2MemOpTable0;
2132 } else if (OpNum == 1) {
2133 OpcodeTablePtr = &RegOp2MemOpTable1;
2134 } else if (OpNum == 2) {
2135 OpcodeTablePtr = &RegOp2MemOpTable2;
2138 if (OpcodeTablePtr) {
2139 // Find the Opcode to fuse
2140 DenseMap<unsigned*, unsigned>::iterator I =
2141 OpcodeTablePtr->find((unsigned*)Opc);
2142 if (I != OpcodeTablePtr->end())
2148 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2149 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2150 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2151 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2152 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2153 if (I == MemOp2RegOpTable.end())
2155 unsigned Opc = I->second.first;
2156 unsigned Index = I->second.second & 0xf;
2157 bool FoldedLoad = I->second.second & (1 << 4);
2158 bool FoldedStore = I->second.second & (1 << 5);
2159 if (UnfoldLoad && !FoldedLoad)
2161 UnfoldLoad &= FoldedLoad;
2162 if (UnfoldStore && !FoldedStore)
2164 UnfoldStore &= FoldedStore;
2166 const TargetInstrDesc &TID = get(Opc);
2167 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2168 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
2169 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
2170 SmallVector<MachineOperand,4> AddrOps;
2171 SmallVector<MachineOperand,2> BeforeOps;
2172 SmallVector<MachineOperand,2> AfterOps;
2173 SmallVector<MachineOperand,4> ImpOps;
2174 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2175 MachineOperand &Op = MI->getOperand(i);
2176 if (i >= Index && i < Index+4)
2177 AddrOps.push_back(Op);
2178 else if (Op.isRegister() && Op.isImplicit())
2179 ImpOps.push_back(Op);
2181 BeforeOps.push_back(Op);
2183 AfterOps.push_back(Op);
2186 // Emit the load instruction.
2188 loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
2190 // Address operands cannot be marked isKill.
2191 for (unsigned i = 1; i != 5; ++i) {
2192 MachineOperand &MO = NewMIs[0]->getOperand(i);
2193 if (MO.isRegister())
2194 MO.setIsKill(false);
2199 // Emit the data processing instruction.
2200 MachineInstr *DataMI = MF.CreateMachineInstr(TID, true);
2201 MachineInstrBuilder MIB(DataMI);
2204 MIB.addReg(Reg, true);
2205 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2206 MIB = X86InstrAddOperand(MIB, BeforeOps[i]);
2209 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2210 MIB = X86InstrAddOperand(MIB, AfterOps[i]);
2211 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2212 MachineOperand &MO = ImpOps[i];
2213 MIB.addReg(MO.getReg(), MO.isDef(), true, MO.isKill(), MO.isDead());
2215 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2216 unsigned NewOpc = 0;
2217 switch (DataMI->getOpcode()) {
2219 case X86::CMP64ri32:
2223 MachineOperand &MO0 = DataMI->getOperand(0);
2224 MachineOperand &MO1 = DataMI->getOperand(1);
2225 if (MO1.getImm() == 0) {
2226 switch (DataMI->getOpcode()) {
2228 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2229 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2230 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2231 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2233 DataMI->setDesc(get(NewOpc));
2234 MO1.ChangeToRegister(MO0.getReg(), false);
2238 NewMIs.push_back(DataMI);
2240 // Emit the store instruction.
2242 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
2243 const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass()
2244 ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
2245 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
2252 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2253 SmallVectorImpl<SDNode*> &NewNodes) const {
2254 if (!N->isMachineOpcode())
2257 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2258 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
2259 if (I == MemOp2RegOpTable.end())
2261 unsigned Opc = I->second.first;
2262 unsigned Index = I->second.second & 0xf;
2263 bool FoldedLoad = I->second.second & (1 << 4);
2264 bool FoldedStore = I->second.second & (1 << 5);
2265 const TargetInstrDesc &TID = get(Opc);
2266 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2267 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
2268 ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
2269 std::vector<SDValue> AddrOps;
2270 std::vector<SDValue> BeforeOps;
2271 std::vector<SDValue> AfterOps;
2272 unsigned NumOps = N->getNumOperands();
2273 for (unsigned i = 0; i != NumOps-1; ++i) {
2274 SDValue Op = N->getOperand(i);
2275 if (i >= Index && i < Index+4)
2276 AddrOps.push_back(Op);
2278 BeforeOps.push_back(Op);
2280 AfterOps.push_back(Op);
2282 SDValue Chain = N->getOperand(NumOps-1);
2283 AddrOps.push_back(Chain);
2285 // Emit the load instruction.
2287 const MachineFunction &MF = DAG.getMachineFunction();
2289 MVT VT = *RC->vt_begin();
2290 bool isAligned = (RI.getStackAlignment() >= 16) ||
2291 RI.needsStackRealignment(MF);
2292 Load = DAG.getTargetNode(getLoadRegOpcode(RC, isAligned),
2294 &AddrOps[0], AddrOps.size());
2295 NewNodes.push_back(Load);
2298 // Emit the data processing instruction.
2299 std::vector<MVT> VTs;
2300 const TargetRegisterClass *DstRC = 0;
2301 if (TID.getNumDefs() > 0) {
2302 const TargetOperandInfo &DstTOI = TID.OpInfo[0];
2303 DstRC = DstTOI.isLookupPtrRegClass()
2304 ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
2305 VTs.push_back(*DstRC->vt_begin());
2307 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2308 MVT VT = N->getValueType(i);
2309 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2313 BeforeOps.push_back(SDValue(Load, 0));
2314 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2315 SDNode *NewNode= DAG.getTargetNode(Opc, VTs, &BeforeOps[0], BeforeOps.size());
2316 NewNodes.push_back(NewNode);
2318 // Emit the store instruction.
2321 AddrOps.push_back(SDValue(NewNode, 0));
2322 AddrOps.push_back(Chain);
2323 bool isAligned = (RI.getStackAlignment() >= 16) ||
2324 RI.needsStackRealignment(MF);
2325 SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, isAligned),
2326 MVT::Other, &AddrOps[0], AddrOps.size());
2327 NewNodes.push_back(Store);
2333 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2334 bool UnfoldLoad, bool UnfoldStore) const {
2335 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2336 MemOp2RegOpTable.find((unsigned*)Opc);
2337 if (I == MemOp2RegOpTable.end())
2339 bool FoldedLoad = I->second.second & (1 << 4);
2340 bool FoldedStore = I->second.second & (1 << 5);
2341 if (UnfoldLoad && !FoldedLoad)
2343 if (UnfoldStore && !FoldedStore)
2345 return I->second.first;
2348 bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
2349 if (MBB.empty()) return false;
2351 switch (MBB.back().getOpcode()) {
2352 case X86::TCRETURNri:
2353 case X86::TCRETURNdi:
2354 case X86::RET: // Return.
2359 case X86::JMP: // Uncond branch.
2360 case X86::JMP32r: // Indirect branch.
2361 case X86::JMP64r: // Indirect branch (64-bit).
2362 case X86::JMP32m: // Indirect branch through mem.
2363 case X86::JMP64m: // Indirect branch through mem (64-bit).
2365 default: return false;
2370 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2371 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2372 Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm()));
2376 const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
2377 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
2378 if (Subtarget->is64Bit())
2379 return &X86::GR64RegClass;
2381 return &X86::GR32RegClass;
2384 unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
2385 switch (Desc->TSFlags & X86II::ImmMask) {
2386 case X86II::Imm8: return 1;
2387 case X86II::Imm16: return 2;
2388 case X86II::Imm32: return 4;
2389 case X86II::Imm64: return 8;
2390 default: assert(0 && "Immediate size not set!");
2395 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
2396 /// e.g. r8, xmm8, etc.
2397 bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) {
2398 if (!MO.isRegister()) return false;
2399 switch (MO.getReg()) {
2401 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
2402 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
2403 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
2404 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
2405 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
2406 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
2407 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
2408 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
2409 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
2410 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
2417 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
2418 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
2419 /// size, and 3) use of X86-64 extended registers.
2420 unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
2422 const TargetInstrDesc &Desc = MI.getDesc();
2424 // Pseudo instructions do not need REX prefix byte.
2425 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
2427 if (Desc.TSFlags & X86II::REX_W)
2430 unsigned NumOps = Desc.getNumOperands();
2432 bool isTwoAddr = NumOps > 1 &&
2433 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
2435 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
2436 unsigned i = isTwoAddr ? 1 : 0;
2437 for (unsigned e = NumOps; i != e; ++i) {
2438 const MachineOperand& MO = MI.getOperand(i);
2439 if (MO.isRegister()) {
2440 unsigned Reg = MO.getReg();
2441 if (isX86_64NonExtLowByteReg(Reg))
2446 switch (Desc.TSFlags & X86II::FormMask) {
2447 case X86II::MRMInitReg:
2448 if (isX86_64ExtendedReg(MI.getOperand(0)))
2449 REX |= (1 << 0) | (1 << 2);
2451 case X86II::MRMSrcReg: {
2452 if (isX86_64ExtendedReg(MI.getOperand(0)))
2454 i = isTwoAddr ? 2 : 1;
2455 for (unsigned e = NumOps; i != e; ++i) {
2456 const MachineOperand& MO = MI.getOperand(i);
2457 if (isX86_64ExtendedReg(MO))
2462 case X86II::MRMSrcMem: {
2463 if (isX86_64ExtendedReg(MI.getOperand(0)))
2466 i = isTwoAddr ? 2 : 1;
2467 for (; i != NumOps; ++i) {
2468 const MachineOperand& MO = MI.getOperand(i);
2469 if (MO.isRegister()) {
2470 if (isX86_64ExtendedReg(MO))
2477 case X86II::MRM0m: case X86II::MRM1m:
2478 case X86II::MRM2m: case X86II::MRM3m:
2479 case X86II::MRM4m: case X86II::MRM5m:
2480 case X86II::MRM6m: case X86II::MRM7m:
2481 case X86II::MRMDestMem: {
2482 unsigned e = isTwoAddr ? 5 : 4;
2483 i = isTwoAddr ? 1 : 0;
2484 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
2487 for (; i != e; ++i) {
2488 const MachineOperand& MO = MI.getOperand(i);
2489 if (MO.isRegister()) {
2490 if (isX86_64ExtendedReg(MO))
2498 if (isX86_64ExtendedReg(MI.getOperand(0)))
2500 i = isTwoAddr ? 2 : 1;
2501 for (unsigned e = NumOps; i != e; ++i) {
2502 const MachineOperand& MO = MI.getOperand(i);
2503 if (isX86_64ExtendedReg(MO))
2513 /// sizePCRelativeBlockAddress - This method returns the size of a PC
2514 /// relative block address instruction
2516 static unsigned sizePCRelativeBlockAddress() {
2520 /// sizeGlobalAddress - Give the size of the emission of this global address
2522 static unsigned sizeGlobalAddress(bool dword) {
2523 return dword ? 8 : 4;
2526 /// sizeConstPoolAddress - Give the size of the emission of this constant
2529 static unsigned sizeConstPoolAddress(bool dword) {
2530 return dword ? 8 : 4;
2533 /// sizeExternalSymbolAddress - Give the size of the emission of this external
2536 static unsigned sizeExternalSymbolAddress(bool dword) {
2537 return dword ? 8 : 4;
2540 /// sizeJumpTableAddress - Give the size of the emission of this jump
2543 static unsigned sizeJumpTableAddress(bool dword) {
2544 return dword ? 8 : 4;
2547 static unsigned sizeConstant(unsigned Size) {
2551 static unsigned sizeRegModRMByte(){
2555 static unsigned sizeSIBByte(){
2559 static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
2560 unsigned FinalSize = 0;
2561 // If this is a simple integer displacement that doesn't require a relocation.
2563 FinalSize += sizeConstant(4);
2567 // Otherwise, this is something that requires a relocation.
2568 if (RelocOp->isGlobalAddress()) {
2569 FinalSize += sizeGlobalAddress(false);
2570 } else if (RelocOp->isConstantPoolIndex()) {
2571 FinalSize += sizeConstPoolAddress(false);
2572 } else if (RelocOp->isJumpTableIndex()) {
2573 FinalSize += sizeJumpTableAddress(false);
2575 assert(0 && "Unknown value to relocate!");
2580 static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
2581 bool IsPIC, bool Is64BitMode) {
2582 const MachineOperand &Op3 = MI.getOperand(Op+3);
2584 const MachineOperand *DispForReloc = 0;
2585 unsigned FinalSize = 0;
2587 // Figure out what sort of displacement we have to handle here.
2588 if (Op3.isGlobalAddress()) {
2589 DispForReloc = &Op3;
2590 } else if (Op3.isConstantPoolIndex()) {
2591 if (Is64BitMode || IsPIC) {
2592 DispForReloc = &Op3;
2596 } else if (Op3.isJumpTableIndex()) {
2597 if (Is64BitMode || IsPIC) {
2598 DispForReloc = &Op3;
2606 const MachineOperand &Base = MI.getOperand(Op);
2607 const MachineOperand &IndexReg = MI.getOperand(Op+2);
2609 unsigned BaseReg = Base.getReg();
2611 // Is a SIB byte needed?
2612 if (IndexReg.getReg() == 0 &&
2613 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
2614 if (BaseReg == 0) { // Just a displacement?
2615 // Emit special case [disp32] encoding
2617 FinalSize += getDisplacementFieldSize(DispForReloc);
2619 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
2620 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
2621 // Emit simple indirect register encoding... [EAX] f.e.
2623 // Be pessimistic and assume it's a disp32, not a disp8
2625 // Emit the most general non-SIB encoding: [REG+disp32]
2627 FinalSize += getDisplacementFieldSize(DispForReloc);
2631 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
2632 assert(IndexReg.getReg() != X86::ESP &&
2633 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
2635 bool ForceDisp32 = false;
2636 if (BaseReg == 0 || DispForReloc) {
2637 // Emit the normal disp32 encoding.
2644 FinalSize += sizeSIBByte();
2646 // Do we need to output a displacement?
2647 if (DispVal != 0 || ForceDisp32) {
2648 FinalSize += getDisplacementFieldSize(DispForReloc);
2655 static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
2656 const TargetInstrDesc *Desc,
2657 bool IsPIC, bool Is64BitMode) {
2659 unsigned Opcode = Desc->Opcode;
2660 unsigned FinalSize = 0;
2662 // Emit the lock opcode prefix as needed.
2663 if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
2665 // Emit the repeat opcode prefix as needed.
2666 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
2668 // Emit the operand size opcode prefix as needed.
2669 if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
2671 // Emit the address size opcode prefix as needed.
2672 if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
2674 bool Need0FPrefix = false;
2675 switch (Desc->TSFlags & X86II::Op0Mask) {
2676 case X86II::TB: // Two-byte opcode prefix
2677 case X86II::T8: // 0F 38
2678 case X86II::TA: // 0F 3A
2679 Need0FPrefix = true;
2681 case X86II::REP: break; // already handled.
2682 case X86II::XS: // F3 0F
2684 Need0FPrefix = true;
2686 case X86II::XD: // F2 0F
2688 Need0FPrefix = true;
2690 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
2691 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
2693 break; // Two-byte opcode prefix
2694 default: assert(0 && "Invalid prefix!");
2695 case 0: break; // No prefix!
2700 unsigned REX = X86InstrInfo::determineREX(MI);
2705 // 0x0F escape code must be emitted just before the opcode.
2709 switch (Desc->TSFlags & X86II::Op0Mask) {
2710 case X86II::T8: // 0F 38
2713 case X86II::TA: // 0F 3A
2718 // If this is a two-address instruction, skip one of the register operands.
2719 unsigned NumOps = Desc->getNumOperands();
2721 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
2724 switch (Desc->TSFlags & X86II::FormMask) {
2725 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
2727 // Remember the current PC offset, this is the PIC relocation
2732 case TargetInstrInfo::INLINEASM: {
2733 const MachineFunction *MF = MI.getParent()->getParent();
2734 const char *AsmStr = MI.getOperand(0).getSymbolName();
2735 const TargetAsmInfo* AI = MF->getTarget().getTargetAsmInfo();
2736 FinalSize += AI->getInlineAsmLength(AsmStr);
2739 case TargetInstrInfo::DBG_LABEL:
2740 case TargetInstrInfo::EH_LABEL:
2742 case TargetInstrInfo::IMPLICIT_DEF:
2743 case TargetInstrInfo::DECLARE:
2744 case X86::DWARF_LOC:
2745 case X86::FP_REG_KILL:
2747 case X86::MOVPC32r: {
2748 // This emits the "call" portion of this pseudo instruction.
2750 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2759 if (CurOp != NumOps) {
2760 const MachineOperand &MO = MI.getOperand(CurOp++);
2761 if (MO.isMachineBasicBlock()) {
2762 FinalSize += sizePCRelativeBlockAddress();
2763 } else if (MO.isGlobalAddress()) {
2764 FinalSize += sizeGlobalAddress(false);
2765 } else if (MO.isExternalSymbol()) {
2766 FinalSize += sizeExternalSymbolAddress(false);
2767 } else if (MO.isImmediate()) {
2768 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2770 assert(0 && "Unknown RawFrm operand!");
2775 case X86II::AddRegFrm:
2779 if (CurOp != NumOps) {
2780 const MachineOperand &MO1 = MI.getOperand(CurOp++);
2781 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
2782 if (MO1.isImmediate())
2783 FinalSize += sizeConstant(Size);
2786 if (Opcode == X86::MOV64ri)
2788 if (MO1.isGlobalAddress()) {
2789 FinalSize += sizeGlobalAddress(dword);
2790 } else if (MO1.isExternalSymbol())
2791 FinalSize += sizeExternalSymbolAddress(dword);
2792 else if (MO1.isConstantPoolIndex())
2793 FinalSize += sizeConstPoolAddress(dword);
2794 else if (MO1.isJumpTableIndex())
2795 FinalSize += sizeJumpTableAddress(dword);
2800 case X86II::MRMDestReg: {
2802 FinalSize += sizeRegModRMByte();
2804 if (CurOp != NumOps) {
2806 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2810 case X86II::MRMDestMem: {
2812 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
2814 if (CurOp != NumOps) {
2816 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2821 case X86II::MRMSrcReg:
2823 FinalSize += sizeRegModRMByte();
2825 if (CurOp != NumOps) {
2827 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2831 case X86II::MRMSrcMem: {
2834 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
2836 if (CurOp != NumOps) {
2838 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
2843 case X86II::MRM0r: case X86II::MRM1r:
2844 case X86II::MRM2r: case X86II::MRM3r:
2845 case X86II::MRM4r: case X86II::MRM5r:
2846 case X86II::MRM6r: case X86II::MRM7r:
2849 FinalSize += sizeRegModRMByte();
2851 if (CurOp != NumOps) {
2852 const MachineOperand &MO1 = MI.getOperand(CurOp++);
2853 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
2854 if (MO1.isImmediate())
2855 FinalSize += sizeConstant(Size);
2858 if (Opcode == X86::MOV64ri32)
2860 if (MO1.isGlobalAddress()) {
2861 FinalSize += sizeGlobalAddress(dword);
2862 } else if (MO1.isExternalSymbol())
2863 FinalSize += sizeExternalSymbolAddress(dword);
2864 else if (MO1.isConstantPoolIndex())
2865 FinalSize += sizeConstPoolAddress(dword);
2866 else if (MO1.isJumpTableIndex())
2867 FinalSize += sizeJumpTableAddress(dword);
2872 case X86II::MRM0m: case X86II::MRM1m:
2873 case X86II::MRM2m: case X86II::MRM3m:
2874 case X86II::MRM4m: case X86II::MRM5m:
2875 case X86II::MRM6m: case X86II::MRM7m: {
2878 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
2881 if (CurOp != NumOps) {
2882 const MachineOperand &MO = MI.getOperand(CurOp++);
2883 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
2884 if (MO.isImmediate())
2885 FinalSize += sizeConstant(Size);
2888 if (Opcode == X86::MOV64mi32)
2890 if (MO.isGlobalAddress()) {
2891 FinalSize += sizeGlobalAddress(dword);
2892 } else if (MO.isExternalSymbol())
2893 FinalSize += sizeExternalSymbolAddress(dword);
2894 else if (MO.isConstantPoolIndex())
2895 FinalSize += sizeConstPoolAddress(dword);
2896 else if (MO.isJumpTableIndex())
2897 FinalSize += sizeJumpTableAddress(dword);
2903 case X86II::MRMInitReg:
2905 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
2906 FinalSize += sizeRegModRMByte();
2911 if (!Desc->isVariadic() && CurOp != NumOps) {
2912 cerr << "Cannot determine size: ";
2923 unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
2924 const TargetInstrDesc &Desc = MI->getDesc();
2925 bool IsPIC = (TM.getRelocationModel() == Reloc::PIC_);
2926 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
2927 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
2928 if (Desc.getOpcode() == X86::MOVPC32r) {
2929 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);