1 //======- X86InstrFragmentsSIMD.td - x86 ISA -------------*- tablegen -*-=====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX Pattern Fragments
16 //===----------------------------------------------------------------------===//
18 def load_mmx : PatFrag<(ops node:$ptr), (v1i64 (load node:$ptr))>;
20 def bc_v8i8 : PatFrag<(ops node:$in), (v8i8 (bitconvert node:$in))>;
21 def bc_v4i16 : PatFrag<(ops node:$in), (v4i16 (bitconvert node:$in))>;
22 def bc_v2i32 : PatFrag<(ops node:$in), (v2i32 (bitconvert node:$in))>;
23 def bc_v1i64 : PatFrag<(ops node:$in), (v1i64 (bitconvert node:$in))>;
25 //===----------------------------------------------------------------------===//
27 //===----------------------------------------------------------------------===//
29 // MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
31 def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
32 return getI8Imm(X86::getShuffleSHUFImmediate(N));
35 // Patterns for: vector_shuffle v1, v2, <2, 6, 3, 7, ...>
36 def mmx_unpckh : PatFrag<(ops node:$lhs, node:$rhs),
37 (vector_shuffle node:$lhs, node:$rhs), [{
38 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
41 // Patterns for: vector_shuffle v1, v2, <0, 4, 2, 5, ...>
42 def mmx_unpckl : PatFrag<(ops node:$lhs, node:$rhs),
43 (vector_shuffle node:$lhs, node:$rhs), [{
44 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
47 // Patterns for: vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
48 def mmx_unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
49 (vector_shuffle node:$lhs, node:$rhs), [{
50 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
53 // Patterns for: vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
54 def mmx_unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
55 (vector_shuffle node:$lhs, node:$rhs), [{
56 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
59 def mmx_pshufw : PatFrag<(ops node:$lhs, node:$rhs),
60 (vector_shuffle node:$lhs, node:$rhs), [{
61 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
62 }], MMX_SHUFFLE_get_shuf_imm>;
64 //===----------------------------------------------------------------------===//
65 // SSE specific DAG Nodes.
66 //===----------------------------------------------------------------------===//
68 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
69 SDTCisFP<0>, SDTCisInt<2> ]>;
70 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
71 SDTCisFP<1>, SDTCisVT<3, i8>]>;
73 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
74 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
75 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
76 [SDNPCommutative, SDNPAssociative]>;
77 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
78 [SDNPCommutative, SDNPAssociative]>;
79 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
80 [SDNPCommutative, SDNPAssociative]>;
81 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
82 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
83 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
84 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
85 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
86 def X86pshufb : SDNode<"X86ISD::PSHUFB",
87 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
89 def X86pextrb : SDNode<"X86ISD::PEXTRB",
90 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
91 def X86pextrw : SDNode<"X86ISD::PEXTRW",
92 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
93 def X86pinsrb : SDNode<"X86ISD::PINSRB",
94 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
95 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
96 def X86pinsrw : SDNode<"X86ISD::PINSRW",
97 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
98 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
99 def X86insrtps : SDNode<"X86ISD::INSERTPS",
100 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
101 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
102 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
103 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
104 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
105 [SDNPHasChain, SDNPMayLoad]>;
106 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
107 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
108 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
109 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
110 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
111 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
112 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
113 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
114 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
115 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
116 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
117 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
119 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
121 SDTCisVT<2, v4f32>]>;
122 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
124 //===----------------------------------------------------------------------===//
125 // SSE Complex Patterns
126 //===----------------------------------------------------------------------===//
128 // These are 'extloads' from a scalar to the low element of a vector, zeroing
129 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
131 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
132 [SDNPHasChain, SDNPMayLoad]>;
133 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
134 [SDNPHasChain, SDNPMayLoad]>;
136 def ssmem : Operand<v4f32> {
137 let PrintMethod = "printf32mem";
138 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
139 let ParserMatchClass = X86MemAsmOperand;
141 def sdmem : Operand<v2f64> {
142 let PrintMethod = "printf64mem";
143 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
144 let ParserMatchClass = X86MemAsmOperand;
147 //===----------------------------------------------------------------------===//
148 // SSE pattern fragments
149 //===----------------------------------------------------------------------===//
151 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
152 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
153 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
154 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
156 // FIXME: move this to a more appropriate place after all AVX is done.
157 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
158 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
159 def loadv8i32 : PatFrag<(ops node:$ptr), (v8i32 (load node:$ptr))>;
160 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
162 // Like 'store', but always requires vector alignment.
163 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
164 (store node:$val, node:$ptr), [{
165 return cast<StoreSDNode>(N)->getAlignment() >= 16;
168 // Like 'load', but always requires vector alignment.
169 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
170 return cast<LoadSDNode>(N)->getAlignment() >= 16;
173 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
174 (f32 (alignedload node:$ptr))>;
175 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
176 (f64 (alignedload node:$ptr))>;
177 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
178 (v4f32 (alignedload node:$ptr))>;
179 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
180 (v2f64 (alignedload node:$ptr))>;
181 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
182 (v4i32 (alignedload node:$ptr))>;
183 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
184 (v2i64 (alignedload node:$ptr))>;
186 // FIXME: move this to a more appropriate place after all AVX is done.
187 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
188 (v8f32 (alignedload node:$ptr))>;
189 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
190 (v4f64 (alignedload node:$ptr))>;
191 def alignedloadv8i32 : PatFrag<(ops node:$ptr),
192 (v8i32 (alignedload node:$ptr))>;
193 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
194 (v4i64 (alignedload node:$ptr))>;
196 // Like 'load', but uses special alignment checks suitable for use in
197 // memory operands in most SSE instructions, which are required to
198 // be naturally aligned on some targets but not on others. If the subtarget
199 // allows unaligned accesses, match any load, though this may require
200 // setting a feature bit in the processor (on startup, for example).
201 // Opteron 10h and later implement such a feature.
202 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
203 return Subtarget->hasVectorUAMem()
204 || cast<LoadSDNode>(N)->getAlignment() >= 16;
207 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
208 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
209 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
210 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
211 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
212 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
213 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
215 // FIXME: move this to a more appropriate place after all AVX is done.
216 def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>;
217 def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>;
219 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
221 // FIXME: 8 byte alignment for mmx reads is not required
222 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
223 return cast<LoadSDNode>(N)->getAlignment() >= 8;
226 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
227 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
228 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
229 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
232 // Like 'store', but requires the non-temporal bit to be set
233 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
234 (st node:$val, node:$ptr), [{
235 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
236 return ST->isNonTemporal();
240 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
241 (st node:$val, node:$ptr), [{
242 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
243 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
244 ST->getAddressingMode() == ISD::UNINDEXED &&
245 ST->getAlignment() >= 16;
249 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
250 (st node:$val, node:$ptr), [{
251 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
252 return ST->isNonTemporal() &&
253 ST->getAlignment() < 16;
257 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
258 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
259 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
260 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
261 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
262 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
264 def vzmovl_v2i64 : PatFrag<(ops node:$src),
265 (bitconvert (v2i64 (X86vzmovl
266 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
267 def vzmovl_v4i32 : PatFrag<(ops node:$src),
268 (bitconvert (v4i32 (X86vzmovl
269 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
271 def vzload_v2i64 : PatFrag<(ops node:$src),
272 (bitconvert (v2i64 (X86vzload node:$src)))>;
275 def fp32imm0 : PatLeaf<(f32 fpimm), [{
276 return N->isExactlyValue(+0.0);
279 // BYTE_imm - Transform bit immediates into byte immediates.
280 def BYTE_imm : SDNodeXForm<imm, [{
281 // Transformation function: imm >> 3
282 return getI32Imm(N->getZExtValue() >> 3);
285 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
287 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
288 return getI8Imm(X86::getShuffleSHUFImmediate(N));
291 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
293 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
294 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
297 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
299 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
300 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
303 // SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
305 def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
306 return getI8Imm(X86::getShufflePALIGNRImmediate(N));
309 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
310 (vector_shuffle node:$lhs, node:$rhs), [{
311 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
312 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
315 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
316 (vector_shuffle node:$lhs, node:$rhs), [{
317 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
320 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
321 (vector_shuffle node:$lhs, node:$rhs), [{
322 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
325 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
326 (vector_shuffle node:$lhs, node:$rhs), [{
327 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
330 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
331 (vector_shuffle node:$lhs, node:$rhs), [{
332 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
335 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
336 (vector_shuffle node:$lhs, node:$rhs), [{
337 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
340 def movl : PatFrag<(ops node:$lhs, node:$rhs),
341 (vector_shuffle node:$lhs, node:$rhs), [{
342 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
345 def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
346 (vector_shuffle node:$lhs, node:$rhs), [{
347 return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
350 def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
351 (vector_shuffle node:$lhs, node:$rhs), [{
352 return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
355 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
356 (vector_shuffle node:$lhs, node:$rhs), [{
357 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
360 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
361 (vector_shuffle node:$lhs, node:$rhs), [{
362 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
365 def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
366 (vector_shuffle node:$lhs, node:$rhs), [{
367 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
370 def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
371 (vector_shuffle node:$lhs, node:$rhs), [{
372 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
375 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
376 (vector_shuffle node:$lhs, node:$rhs), [{
377 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
378 }], SHUFFLE_get_shuf_imm>;
380 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
381 (vector_shuffle node:$lhs, node:$rhs), [{
382 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
383 }], SHUFFLE_get_shuf_imm>;
385 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
386 (vector_shuffle node:$lhs, node:$rhs), [{
387 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
388 }], SHUFFLE_get_pshufhw_imm>;
390 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
391 (vector_shuffle node:$lhs, node:$rhs), [{
392 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
393 }], SHUFFLE_get_pshuflw_imm>;
395 def palign : PatFrag<(ops node:$lhs, node:$rhs),
396 (vector_shuffle node:$lhs, node:$rhs), [{
397 return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
398 }], SHUFFLE_get_palign_imm>;