1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // Low word of MMX to GPR.
19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
21 // GPR to low word of MMX.
22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
25 //===----------------------------------------------------------------------===//
26 // MMX Pattern Fragments
27 //===----------------------------------------------------------------------===//
29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
30 def load_mvmmx : PatFrag<(ops node:$ptr),
31 (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
32 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
34 //===----------------------------------------------------------------------===//
35 // SSE specific DAG Nodes.
36 //===----------------------------------------------------------------------===//
38 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
39 SDTCisFP<1>, SDTCisVT<3, i8>,
42 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
43 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
45 // Commutative and Associative FMIN and FMAX.
46 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
47 [SDNPCommutative, SDNPAssociative]>;
48 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
49 [SDNPCommutative, SDNPAssociative]>;
51 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
52 [SDNPCommutative, SDNPAssociative]>;
53 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
54 [SDNPCommutative, SDNPAssociative]>;
55 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
56 [SDNPCommutative, SDNPAssociative]>;
57 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
58 [SDNPCommutative, SDNPAssociative]>;
59 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
60 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
61 def X86frsqrt14s: SDNode<"X86ISD::FRSQRT", SDTFPBinOp>;
62 def X86frcp14s : SDNode<"X86ISD::FRCP", SDTFPBinOp>;
63 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
64 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
65 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
66 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
67 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
68 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
69 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
70 def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
71 //def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
72 def X86cvtdq2pd: SDNode<"X86ISD::CVTDQ2PD",
73 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
74 SDTCisVT<1, v4i32>]>>;
75 def X86cvtudq2pd: SDNode<"X86ISD::CVTUDQ2PD",
76 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
77 SDTCisVT<1, v4i32>]>>;
78 def X86pshufb : SDNode<"X86ISD::PSHUFB",
79 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
81 def X86psadbw : SDNode<"X86ISD::PSADBW",
82 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
84 def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
85 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
86 SDTCisSameAs<1,2>, SDTCisInt<3>]>>;
87 def X86andnp : SDNode<"X86ISD::ANDNP",
88 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
90 def X86psign : SDNode<"X86ISD::PSIGN",
91 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
93 def X86pextrb : SDNode<"X86ISD::PEXTRB",
94 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
95 def X86pextrw : SDNode<"X86ISD::PEXTRW",
96 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
97 def X86pinsrb : SDNode<"X86ISD::PINSRB",
98 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
99 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
100 def X86pinsrw : SDNode<"X86ISD::PINSRW",
101 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
102 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
103 def X86insertps : SDNode<"X86ISD::INSERTPS",
104 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
105 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
106 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
107 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
109 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
110 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
112 def X86vzext : SDNode<"X86ISD::VZEXT",
113 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
114 SDTCisInt<0>, SDTCisInt<1>,
115 SDTCisOpSmallerThanOp<1, 0>]>>;
117 def X86vsext : SDNode<"X86ISD::VSEXT",
118 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
119 SDTCisInt<0>, SDTCisInt<1>,
120 SDTCisOpSmallerThanOp<1, 0>]>>;
122 def SDTVtrunc : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
123 SDTCisInt<0>, SDTCisInt<1>,
124 SDTCisOpSmallerThanOp<0, 1>]>;
126 def X86vtrunc : SDNode<"X86ISD::VTRUNC", SDTVtrunc>;
127 def X86vtruncs : SDNode<"X86ISD::VTRUNCS", SDTVtrunc>;
128 def X86vtruncus : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
130 def X86trunc : SDNode<"X86ISD::TRUNC",
131 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
132 SDTCisOpSmallerThanOp<0, 1>]>>;
133 def X86vfpext : SDNode<"X86ISD::VFPEXT",
134 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
135 SDTCisFP<0>, SDTCisFP<1>,
136 SDTCisOpSmallerThanOp<1, 0>]>>;
137 def X86vfpround: SDNode<"X86ISD::VFPROUND",
138 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
139 SDTCisFP<0>, SDTCisFP<1>,
140 SDTCisOpSmallerThanOp<0, 1>]>>;
142 def X86fround: SDNode<"X86ISD::VFPROUND",
143 SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
144 SDTCVecEltisVT<0, f32>,
145 SDTCVecEltisVT<1, f64>,
146 SDTCVecEltisVT<2, f64>,
147 SDTCisOpSmallerThanOp<0, 1>]>>;
148 def X86froundRnd: SDNode<"X86ISD::VFPROUND",
149 SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
150 SDTCVecEltisVT<0, f32>,
151 SDTCVecEltisVT<1, f64>,
152 SDTCVecEltisVT<2, f64>,
153 SDTCisOpSmallerThanOp<0, 1>,
156 def X86fpext : SDNode<"X86ISD::VFPEXT",
157 SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
158 SDTCVecEltisVT<0, f64>,
159 SDTCVecEltisVT<1, f32>,
160 SDTCVecEltisVT<2, f32>,
161 SDTCisOpSmallerThanOp<1, 0>]>>;
163 def X86fpextRnd : SDNode<"X86ISD::VFPEXT",
164 SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
165 SDTCVecEltisVT<0, f64>,
166 SDTCVecEltisVT<1, f32>,
167 SDTCVecEltisVT<2, f32>,
168 SDTCisOpSmallerThanOp<1, 0>,
171 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
172 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
173 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
174 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
175 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
177 def X86IntCmpMask : SDTypeProfile<1, 2,
178 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
179 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
180 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
183 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
184 SDTCisVec<1>, SDTCisSameAs<2, 1>,
185 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
186 def X86CmpMaskCCRound :
187 SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
188 SDTCisVec<1>, SDTCisSameAs<2, 1>,
189 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
191 def X86CmpMaskCCScalar :
192 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
194 def X86CmpMaskCCScalarRound :
195 SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>,
198 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
199 def X86cmpmRnd : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
200 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
201 def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
202 def X86cmpmsRnd : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalarRound>;
204 def X86vshl : SDNode<"X86ISD::VSHL",
205 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
207 def X86vsrl : SDNode<"X86ISD::VSRL",
208 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
210 def X86vsra : SDNode<"X86ISD::VSRA",
211 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
214 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
215 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
216 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
218 def X86vpshl : SDNode<"X86ISD::VPSHL",
219 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
221 def X86vpsha : SDNode<"X86ISD::VPSHA",
222 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
225 def X86vpcom : SDNode<"X86ISD::VPCOM",
226 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
227 SDTCisVec<2>, SDTCisVT<3, i8>]>>;
228 def X86vpcomu : SDNode<"X86ISD::VPCOMU",
229 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
230 SDTCisVec<2>, SDTCisVT<3, i8>]>>;
232 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
234 SDTCisSameAs<2, 1>]>;
235 def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
236 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
237 def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
238 def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
239 def X86mulhrs : SDNode<"X86ISD::MULHRS" , SDTIntBinOp>;
240 def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp>;
241 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
242 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
243 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
244 def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
245 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
246 SDTCisVec<1>, SDTCisSameAs<2, 1>,
247 SDTCVecEltisVT<0, i1>,
248 SDTCisSameNumEltsAs<0, 1>]>>;
249 def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
250 SDTCisVec<1>, SDTCisSameAs<2, 1>,
251 SDTCVecEltisVT<0, i1>,
252 SDTCisSameNumEltsAs<0, 1>]>>;
253 def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
255 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
256 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
257 SDTCisSameAs<1,2>]>>;
258 def X86pmuldq : SDNode<"X86ISD::PMULDQ",
259 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
260 SDTCisSameAs<1,2>]>>;
262 def X86extrqi : SDNode<"X86ISD::EXTRQI",
263 SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
264 SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
265 def X86insertqi : SDNode<"X86ISD::INSERTQI",
266 SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
267 SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
270 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
271 // translated into one of the target nodes below during lowering.
272 // Note: this is a work in progress...
273 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
274 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
276 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
277 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
279 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
281 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
282 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
283 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
284 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
285 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
286 SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
287 def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
288 SDTCisInt<2>, SDTCisInt<3>]>;
290 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
291 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
293 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
294 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
296 def SDTTernlog : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
297 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>,
300 def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
301 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
303 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc.
304 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]>;
306 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
307 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
308 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
309 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
310 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
311 SDTCisVec<0>, SDTCisInt<2>]>;
312 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
313 SDTCisVec<0>, SDTCisInt<3>]>;
314 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
315 SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
317 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
318 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
320 def X86Abs : SDNode<"X86ISD::ABS", SDTIntUnaryOp>;
321 def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>;
323 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
324 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
325 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
327 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
328 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
330 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
331 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
332 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
334 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
335 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
337 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
338 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
339 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
341 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
342 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
344 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
345 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
346 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
348 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
349 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
351 def X86vpmaddubsw : SDNode<"X86ISD::VPMADDUBSW" , SDTPack>;
352 def X86vpmaddwd : SDNode<"X86ISD::VPMADDWD" , SDTPack>;
354 def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
355 def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
356 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
357 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
358 def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
359 def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
360 def X86vpternlog : SDNode<"X86ISD::VPTERNLOG", SDTTernlog>;
362 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
364 def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
365 def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImmRound>;
366 def X86VReduce : SDNode<"X86ISD::VREDUCE", SDTFPUnaryOpImmRound>;
367 def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;
368 def X86VGetMant : SDNode<"X86ISD::VGETMANT", SDTFPUnaryOpImmRound>;
369 def X86Vfpclass : SDNode<"X86ISD::VFPCLASS",
370 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
371 SDTCisVec<1>, SDTCisInt<2>]>, []>;
373 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
374 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
375 SDTCisSubVecOfVec<1, 0>]>, []>;
376 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
377 def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
378 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
379 def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
380 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
382 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
384 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
386 def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
387 def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
388 def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
389 def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
390 def X86fmaxRnd : SDNode<"X86ISD::FMAX_RND", SDTFPBinOpRound>;
391 def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOpRound>;
392 def X86fminRnd : SDNode<"X86ISD::FMIN_RND", SDTFPBinOpRound>;
393 def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>;
394 def X86fsqrtRnds : SDNode<"X86ISD::FSQRT_RND", STDFp2SrcRm>;
395 def X86fgetexpRnd : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
396 def X86fgetexpRnds : SDNode<"X86ISD::FGETEXP_RND", STDFp2SrcRm>;
398 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
399 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
400 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
401 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
402 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
403 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
405 def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
406 def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
407 def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
408 def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
409 def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
410 def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
412 def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
413 def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
414 def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
416 def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
417 def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
418 def X86RndScales : SDNode<"X86ISD::VRNDSCALE", STDFp3SrcRm>;
419 def X86Reduces : SDNode<"X86ISD::VREDUCE", STDFp3SrcRm>;
420 def X86GetMants : SDNode<"X86ISD::VGETMANT", STDFp3SrcRm>;
422 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
423 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
425 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
426 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
427 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
430 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
431 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
433 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
434 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
435 def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
436 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
438 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
439 SDTCisSameAs<0,1>, SDTCisInt<2>, SDTCisInt<3>]>;
441 def SDTDoubleToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
442 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
443 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
444 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
446 def SDTDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
447 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
448 def SDTSDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>,SDTCisFP<1>,
449 SDTCVecEltisVT<1, f64>, SDTCisInt<2>]>;
450 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
451 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
452 def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
453 SDTCVecEltisVT<1, f32>, SDTCisInt<2>]>;
454 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
455 SDTCisFP<0>, SDTCVecEltisVT<1, i32>,
457 def SDTVlongToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
458 SDTCisFP<0>, SDTCVecEltisVT<1, i64>,
461 def SDTVFPToIntRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
462 SDTCisFP<1>, SDTCVecEltisVT<0, i32>,
464 def SDTVFPToLongRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
465 SDTCisFP<1>, SDTCVecEltisVT<0, i64>,
469 def X86SintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTintToFPRound>;
470 def X86UintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTintToFPRound>;
472 def X86cvttss2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTSFloatToIntRnd>;
473 def X86cvttss2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTSFloatToIntRnd>;
474 def X86cvttsd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTSDoubleToIntRnd>;
475 def X86cvttsd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTSDoubleToIntRnd>;
476 // Vector with rounding mode
478 // cvtt fp-to-int staff
479 def X86VFpToSintRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToIntRound>;
480 def X86VFpToUintRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToIntRound>;
481 def X86VFpToSlongRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToLongRound>;
482 def X86VFpToUlongRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToLongRound>;
484 def X86VSintToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVintToFPRound>;
485 def X86VUintToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVintToFPRound>;
486 def X86VSlongToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVlongToFPRound>;
487 def X86VUlongToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVlongToFPRound>;
489 // cvt fp-to-int staff
490 def X86cvtps2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToIntRnd>;
491 def X86cvtps2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToIntRnd>;
492 def X86cvtpd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToIntRnd>;
493 def X86cvtpd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToIntRnd>;
495 // Vector without rounding mode
496 def X86cvtps2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToInt>;
497 def X86cvtps2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToInt>;
498 def X86cvtpd2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToInt>;
499 def X86cvtpd2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToInt>;
501 def X86vfpextRnd : SDNode<"X86ISD::VFPEXT",
502 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
503 SDTCisFP<0>, SDTCisFP<1>,
504 SDTCisOpSmallerThanOp<1, 0>,
506 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND",
507 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
508 SDTCisFP<0>, SDTCisFP<1>,
509 SDTCVecEltisVT<0, f32>,
510 SDTCVecEltisVT<1, f64>,
513 //===----------------------------------------------------------------------===//
514 // SSE Complex Patterns
515 //===----------------------------------------------------------------------===//
517 // These are 'extloads' from a scalar to the low element of a vector, zeroing
518 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
520 def sse_load_f32 : ComplexPattern<v4f32, 5, "selectScalarSSELoad", [],
521 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
523 def sse_load_f64 : ComplexPattern<v2f64, 5, "selectScalarSSELoad", [],
524 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
527 def ssmem : Operand<v4f32> {
528 let PrintMethod = "printf32mem";
529 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
530 let ParserMatchClass = X86Mem32AsmOperand;
531 let OperandType = "OPERAND_MEMORY";
533 def sdmem : Operand<v2f64> {
534 let PrintMethod = "printf64mem";
535 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
536 let ParserMatchClass = X86Mem64AsmOperand;
537 let OperandType = "OPERAND_MEMORY";
540 //===----------------------------------------------------------------------===//
541 // SSE pattern fragments
542 //===----------------------------------------------------------------------===//
544 // 128-bit load pattern fragments
545 // NOTE: all 128-bit integer vector loads are promoted to v2i64
546 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
547 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
548 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
550 // 256-bit load pattern fragments
551 // NOTE: all 256-bit integer vector loads are promoted to v4i64
552 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
553 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
554 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
556 // 512-bit load pattern fragments
557 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
558 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
559 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
560 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
561 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
562 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
564 // 128-/256-/512-bit extload pattern fragments
565 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
566 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
567 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
569 // These are needed to match a scalar load that is used in a vector-only
570 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
571 // The memory operand is required to be a 128-bit load, so it must be converted
572 // from a vector to a scalar.
573 def loadf32_128 : PatFrag<(ops node:$ptr),
574 (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
575 def loadf64_128 : PatFrag<(ops node:$ptr),
576 (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
578 // Like 'store', but always requires 128-bit vector alignment.
579 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
580 (store node:$val, node:$ptr), [{
581 return cast<StoreSDNode>(N)->getAlignment() >= 16;
584 // Like 'store', but always requires 256-bit vector alignment.
585 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
586 (store node:$val, node:$ptr), [{
587 return cast<StoreSDNode>(N)->getAlignment() >= 32;
590 // Like 'store', but always requires 512-bit vector alignment.
591 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
592 (store node:$val, node:$ptr), [{
593 return cast<StoreSDNode>(N)->getAlignment() >= 64;
596 // Like 'load', but always requires 128-bit vector alignment.
597 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
598 return cast<LoadSDNode>(N)->getAlignment() >= 16;
601 // Like 'X86vzload', but always requires 128-bit vector alignment.
602 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
603 return cast<MemSDNode>(N)->getAlignment() >= 16;
606 // Like 'load', but always requires 256-bit vector alignment.
607 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
608 return cast<LoadSDNode>(N)->getAlignment() >= 32;
611 // Like 'load', but always requires 512-bit vector alignment.
612 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
613 return cast<LoadSDNode>(N)->getAlignment() >= 64;
616 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
617 (f32 (alignedload node:$ptr))>;
618 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
619 (f64 (alignedload node:$ptr))>;
621 // 128-bit aligned load pattern fragments
622 // NOTE: all 128-bit integer vector loads are promoted to v2i64
623 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
624 (v4f32 (alignedload node:$ptr))>;
625 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
626 (v2f64 (alignedload node:$ptr))>;
627 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
628 (v2i64 (alignedload node:$ptr))>;
630 // 256-bit aligned load pattern fragments
631 // NOTE: all 256-bit integer vector loads are promoted to v4i64
632 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
633 (v8f32 (alignedload256 node:$ptr))>;
634 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
635 (v4f64 (alignedload256 node:$ptr))>;
636 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
637 (v4i64 (alignedload256 node:$ptr))>;
639 // 512-bit aligned load pattern fragments
640 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
641 (v16f32 (alignedload512 node:$ptr))>;
642 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
643 (v16i32 (alignedload512 node:$ptr))>;
644 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
645 (v8f64 (alignedload512 node:$ptr))>;
646 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
647 (v8i64 (alignedload512 node:$ptr))>;
649 // Like 'load', but uses special alignment checks suitable for use in
650 // memory operands in most SSE instructions, which are required to
651 // be naturally aligned on some targets but not on others. If the subtarget
652 // allows unaligned accesses, match any load, though this may require
653 // setting a feature bit in the processor (on startup, for example).
654 // Opteron 10h and later implement such a feature.
655 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
656 return Subtarget->hasSSEUnalignedMem()
657 || cast<LoadSDNode>(N)->getAlignment() >= 16;
660 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
661 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
663 // 128-bit memop pattern fragments
664 // NOTE: all 128-bit integer vector loads are promoted to v2i64
665 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
666 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
667 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
669 // These are needed to match a scalar memop that is used in a vector-only
670 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
671 // The memory operand is required to be a 128-bit load, so it must be converted
672 // from a vector to a scalar.
673 def memopfsf32_128 : PatFrag<(ops node:$ptr),
674 (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
675 def memopfsf64_128 : PatFrag<(ops node:$ptr),
676 (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
679 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
681 // FIXME: 8 byte alignment for mmx reads is not required
682 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
683 return cast<LoadSDNode>(N)->getAlignment() >= 8;
686 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
688 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
689 (masked_gather node:$src1, node:$src2, node:$src3) , [{
690 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
691 return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
692 Mgt->getBasePtr().getValueType() == MVT::v4i32);
696 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
697 (masked_gather node:$src1, node:$src2, node:$src3) , [{
698 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
699 return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
700 Mgt->getBasePtr().getValueType() == MVT::v8i32);
704 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
705 (masked_gather node:$src1, node:$src2, node:$src3) , [{
706 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
707 return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
708 Mgt->getBasePtr().getValueType() == MVT::v2i64);
711 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
712 (masked_gather node:$src1, node:$src2, node:$src3) , [{
713 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
714 return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
715 Mgt->getBasePtr().getValueType() == MVT::v4i64);
718 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
719 (masked_gather node:$src1, node:$src2, node:$src3) , [{
720 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
721 return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
722 Mgt->getBasePtr().getValueType() == MVT::v8i64);
725 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
726 (masked_gather node:$src1, node:$src2, node:$src3) , [{
727 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
728 return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
729 Mgt->getBasePtr().getValueType() == MVT::v16i32);
733 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
734 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
735 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
736 return (Sc->getIndex().getValueType() == MVT::v2i64 ||
737 Sc->getBasePtr().getValueType() == MVT::v2i64);
741 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
742 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
743 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
744 return (Sc->getIndex().getValueType() == MVT::v4i32 ||
745 Sc->getBasePtr().getValueType() == MVT::v4i32);
749 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
750 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
751 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
752 return (Sc->getIndex().getValueType() == MVT::v4i64 ||
753 Sc->getBasePtr().getValueType() == MVT::v4i64);
757 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
758 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
759 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
760 return (Sc->getIndex().getValueType() == MVT::v8i32 ||
761 Sc->getBasePtr().getValueType() == MVT::v8i32);
765 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
766 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
767 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
768 return (Sc->getIndex().getValueType() == MVT::v8i64 ||
769 Sc->getBasePtr().getValueType() == MVT::v8i64);
772 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
773 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
774 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
775 return (Sc->getIndex().getValueType() == MVT::v16i32 ||
776 Sc->getBasePtr().getValueType() == MVT::v16i32);
780 // 128-bit bitconvert pattern fragments
781 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
782 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
783 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
784 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
785 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
786 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
788 // 256-bit bitconvert pattern fragments
789 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
790 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
791 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
792 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
793 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
795 // 512-bit bitconvert pattern fragments
796 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
797 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
798 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
799 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
801 def vzmovl_v2i64 : PatFrag<(ops node:$src),
802 (bitconvert (v2i64 (X86vzmovl
803 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
804 def vzmovl_v4i32 : PatFrag<(ops node:$src),
805 (bitconvert (v4i32 (X86vzmovl
806 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
808 def vzload_v2i64 : PatFrag<(ops node:$src),
809 (bitconvert (v2i64 (X86vzload node:$src)))>;
812 def fp32imm0 : PatLeaf<(f32 fpimm), [{
813 return N->isExactlyValue(+0.0);
816 def I8Imm : SDNodeXForm<imm, [{
817 // Transformation function: get the low 8 bits.
818 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
821 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
822 def FROUND_CURRENT : ImmLeaf<i32, [{
823 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
826 // BYTE_imm - Transform bit immediates into byte immediates.
827 def BYTE_imm : SDNodeXForm<imm, [{
828 // Transformation function: imm >> 3
829 return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
832 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
833 // to VEXTRACTF128/VEXTRACTI128 imm.
834 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
835 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
838 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
839 // VINSERTF128/VINSERTI128 imm.
840 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
841 return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
844 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
845 // to VEXTRACTF64x4 imm.
846 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
847 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
850 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
852 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
853 return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
856 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
857 (extract_subvector node:$bigvec,
859 return X86::isVEXTRACT128Index(N);
860 }], EXTRACT_get_vextract128_imm>;
862 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
864 (insert_subvector node:$bigvec, node:$smallvec,
866 return X86::isVINSERT128Index(N);
867 }], INSERT_get_vinsert128_imm>;
870 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
871 (extract_subvector node:$bigvec,
873 return X86::isVEXTRACT256Index(N);
874 }], EXTRACT_get_vextract256_imm>;
876 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
878 (insert_subvector node:$bigvec, node:$smallvec,
880 return X86::isVINSERT256Index(N);
881 }], INSERT_get_vinsert256_imm>;
883 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
884 (masked_load node:$src1, node:$src2, node:$src3), [{
885 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
886 return Load->getAlignment() >= 16;
890 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
891 (masked_load node:$src1, node:$src2, node:$src3), [{
892 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
893 return Load->getAlignment() >= 32;
897 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
898 (masked_load node:$src1, node:$src2, node:$src3), [{
899 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
900 return Load->getAlignment() >= 64;
904 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
905 (masked_load node:$src1, node:$src2, node:$src3), [{
906 return isa<MaskedLoadSDNode>(N);
909 // masked store fragments.
910 // X86mstore can't be implemented in core DAG files because some targets
911 // doesn't support vector type ( llvm-tblgen will fail)
912 def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
913 (masked_store node:$src1, node:$src2, node:$src3), [{
914 return !cast<MaskedStoreSDNode>(N)->isTruncatingStore();
917 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
918 (X86mstore node:$src1, node:$src2, node:$src3), [{
919 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
920 return Store->getAlignment() >= 16;
924 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
925 (X86mstore node:$src1, node:$src2, node:$src3), [{
926 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
927 return Store->getAlignment() >= 32;
931 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
932 (X86mstore node:$src1, node:$src2, node:$src3), [{
933 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
934 return Store->getAlignment() >= 64;
938 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
939 (X86mstore node:$src1, node:$src2, node:$src3), [{
940 return isa<MaskedStoreSDNode>(N);
943 // masked truncstore fragments
944 // X86mtruncstore can't be implemented in core DAG files because some targets
945 // doesn't support vector type ( llvm-tblgen will fail)
946 def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
947 (masked_store node:$src1, node:$src2, node:$src3), [{
948 return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
950 def masked_truncstorevi8 :
951 PatFrag<(ops node:$src1, node:$src2, node:$src3),
952 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
953 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
955 def masked_truncstorevi16 :
956 PatFrag<(ops node:$src1, node:$src2, node:$src3),
957 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
958 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
960 def masked_truncstorevi32 :
961 PatFrag<(ops node:$src1, node:$src2, node:$src3),
962 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
963 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;