1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // Low word of MMX to GPR.
19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
22 //===----------------------------------------------------------------------===//
23 // MMX Pattern Fragments
24 //===----------------------------------------------------------------------===//
26 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
27 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
29 //===----------------------------------------------------------------------===//
30 // SSE specific DAG Nodes.
31 //===----------------------------------------------------------------------===//
33 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
34 SDTCisFP<0>, SDTCisInt<2> ]>;
35 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
36 SDTCisFP<1>, SDTCisVT<3, i8>,
39 def X86umin : SDNode<"X86ISD::UMIN", SDTIntBinOp>;
40 def X86umax : SDNode<"X86ISD::UMAX", SDTIntBinOp>;
41 def X86smin : SDNode<"X86ISD::SMIN", SDTIntBinOp>;
42 def X86smax : SDNode<"X86ISD::SMAX", SDTIntBinOp>;
44 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
45 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
47 // Commutative and Associative FMIN and FMAX.
48 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
49 [SDNPCommutative, SDNPAssociative]>;
50 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
51 [SDNPCommutative, SDNPAssociative]>;
53 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
54 [SDNPCommutative, SDNPAssociative]>;
55 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
56 [SDNPCommutative, SDNPAssociative]>;
57 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
58 [SDNPCommutative, SDNPAssociative]>;
59 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
60 [SDNPCommutative, SDNPAssociative]>;
61 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
62 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
63 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
64 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
65 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
66 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
67 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
68 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
69 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
70 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
71 def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
72 //def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
73 def X86pshufb : SDNode<"X86ISD::PSHUFB",
74 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
76 def X86andnp : SDNode<"X86ISD::ANDNP",
77 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
79 def X86psign : SDNode<"X86ISD::PSIGN",
80 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
82 def X86pextrb : SDNode<"X86ISD::PEXTRB",
83 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
84 def X86pextrw : SDNode<"X86ISD::PEXTRW",
85 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
86 def X86pinsrb : SDNode<"X86ISD::PINSRB",
87 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
88 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
89 def X86pinsrw : SDNode<"X86ISD::PINSRW",
90 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
91 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
92 def X86insertps : SDNode<"X86ISD::INSERTPS",
93 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
94 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
95 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
96 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
98 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
99 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
101 def X86vzext : SDNode<"X86ISD::VZEXT",
102 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
103 SDTCisInt<0>, SDTCisInt<1>,
104 SDTCisOpSmallerThanOp<1, 0>]>>;
106 def X86vsext : SDNode<"X86ISD::VSEXT",
107 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
108 SDTCisInt<0>, SDTCisInt<1>,
109 SDTCisOpSmallerThanOp<1, 0>]>>;
111 def X86vtrunc : SDNode<"X86ISD::VTRUNC",
112 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
113 SDTCisInt<0>, SDTCisInt<1>,
114 SDTCisOpSmallerThanOp<0, 1>]>>;
115 def X86trunc : SDNode<"X86ISD::TRUNC",
116 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
117 SDTCisOpSmallerThanOp<0, 1>]>>;
119 def X86vtruncm : SDNode<"X86ISD::VTRUNCM",
120 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
121 SDTCisInt<0>, SDTCisInt<1>,
122 SDTCisVec<2>, SDTCisInt<2>,
123 SDTCisOpSmallerThanOp<0, 2>]>>;
124 def X86vfpext : SDNode<"X86ISD::VFPEXT",
125 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
126 SDTCisFP<0>, SDTCisFP<1>,
127 SDTCisOpSmallerThanOp<1, 0>]>>;
128 def X86vfpround: SDNode<"X86ISD::VFPROUND",
129 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
130 SDTCisFP<0>, SDTCisFP<1>,
131 SDTCisOpSmallerThanOp<0, 1>]>>;
133 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
134 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
135 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
136 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
137 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
139 def X86IntCmpMask : SDTypeProfile<1, 2,
140 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
141 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
142 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
145 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<0>, SDTCisVec<1>,
146 SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
147 def X86CmpMaskCCScalar :
148 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
150 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
151 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
152 def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
154 def X86vshl : SDNode<"X86ISD::VSHL",
155 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
157 def X86vsrl : SDNode<"X86ISD::VSRL",
158 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
160 def X86vsra : SDNode<"X86ISD::VSRA",
161 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
164 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
165 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
166 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
168 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
170 SDTCisSameAs<2, 1>]>;
171 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
172 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
173 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
174 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
175 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
177 SDTCisSameAs<2, 1>]>>;
178 def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
180 SDTCisSameAs<2, 1>]>>;
181 def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
183 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
184 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
185 SDTCisSameAs<1,2>]>>;
186 def X86pmuldq : SDNode<"X86ISD::PMULDQ",
187 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
188 SDTCisSameAs<1,2>]>>;
190 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
191 // translated into one of the target nodes below during lowering.
192 // Note: this is a work in progress...
193 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
194 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
196 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
197 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
199 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
201 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
202 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
203 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
204 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
206 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
207 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
209 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
210 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
212 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
213 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
214 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
215 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
216 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
217 SDTCisVec<0>, SDTCisInt<2>]>;
218 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
219 SDTCisVec<0>, SDTCisInt<3>]>;
221 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
222 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
224 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
225 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
226 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
228 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
230 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
231 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
232 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
234 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
235 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
237 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
238 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
239 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
241 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
242 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
244 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
245 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
246 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
248 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
249 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
251 def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
252 def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
253 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
254 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
255 def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
256 def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
258 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
260 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
261 def X86VBroadcastm : SDNode<"X86ISD::VBROADCASTM", SDTVBroadcastm>;
262 def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
263 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
264 def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
265 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
267 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
269 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
271 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
272 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
273 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
274 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
275 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
276 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
278 def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
279 def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
280 def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
281 def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
282 def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
283 def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
285 def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
286 def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
287 def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
289 def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
290 def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
292 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
293 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
295 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
296 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
297 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
300 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
301 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
303 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 3,
304 [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
305 SDTCisVec<3>, SDTCisVec<1>, SDTCisInt<1>]>, []>;
306 def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 3,
308 SDTCisVec<3>, SDTCisVec<1>, SDTCisInt<1>]>, []>;
310 //===----------------------------------------------------------------------===//
311 // SSE Complex Patterns
312 //===----------------------------------------------------------------------===//
314 // These are 'extloads' from a scalar to the low element of a vector, zeroing
315 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
317 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
318 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
320 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
321 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
324 def ssmem : Operand<v4f32> {
325 let PrintMethod = "printf32mem";
326 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
327 let ParserMatchClass = X86Mem32AsmOperand;
328 let OperandType = "OPERAND_MEMORY";
330 def sdmem : Operand<v2f64> {
331 let PrintMethod = "printf64mem";
332 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
333 let ParserMatchClass = X86Mem64AsmOperand;
334 let OperandType = "OPERAND_MEMORY";
337 //===----------------------------------------------------------------------===//
338 // SSE pattern fragments
339 //===----------------------------------------------------------------------===//
341 // 128-bit load pattern fragments
342 // NOTE: all 128-bit integer vector loads are promoted to v2i64
343 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
344 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
345 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
347 // 256-bit load pattern fragments
348 // NOTE: all 256-bit integer vector loads are promoted to v4i64
349 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
350 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
351 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
353 // 512-bit load pattern fragments
354 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
355 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
356 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
357 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
358 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
359 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
361 // 128-/256-/512-bit extload pattern fragments
362 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
363 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
364 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
366 // Like 'store', but always requires 128-bit vector alignment.
367 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
368 (store node:$val, node:$ptr), [{
369 return cast<StoreSDNode>(N)->getAlignment() >= 16;
372 // Like 'store', but always requires 256-bit vector alignment.
373 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
374 (store node:$val, node:$ptr), [{
375 return cast<StoreSDNode>(N)->getAlignment() >= 32;
378 // Like 'store', but always requires 512-bit vector alignment.
379 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
380 (store node:$val, node:$ptr), [{
381 return cast<StoreSDNode>(N)->getAlignment() >= 64;
384 // Like 'load', but always requires 128-bit vector alignment.
385 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
386 return cast<LoadSDNode>(N)->getAlignment() >= 16;
389 // Like 'X86vzload', but always requires 128-bit vector alignment.
390 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
391 return cast<MemSDNode>(N)->getAlignment() >= 16;
394 // Like 'load', but always requires 256-bit vector alignment.
395 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
396 return cast<LoadSDNode>(N)->getAlignment() >= 32;
399 // Like 'load', but always requires 512-bit vector alignment.
400 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
401 return cast<LoadSDNode>(N)->getAlignment() >= 64;
404 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
405 (f32 (alignedload node:$ptr))>;
406 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
407 (f64 (alignedload node:$ptr))>;
409 // 128-bit aligned load pattern fragments
410 // NOTE: all 128-bit integer vector loads are promoted to v2i64
411 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
412 (v4f32 (alignedload node:$ptr))>;
413 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
414 (v2f64 (alignedload node:$ptr))>;
415 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
416 (v2i64 (alignedload node:$ptr))>;
418 // 256-bit aligned load pattern fragments
419 // NOTE: all 256-bit integer vector loads are promoted to v4i64
420 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
421 (v8f32 (alignedload256 node:$ptr))>;
422 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
423 (v4f64 (alignedload256 node:$ptr))>;
424 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
425 (v4i64 (alignedload256 node:$ptr))>;
427 // 512-bit aligned load pattern fragments
428 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
429 (v16f32 (alignedload512 node:$ptr))>;
430 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
431 (v16i32 (alignedload512 node:$ptr))>;
432 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
433 (v8f64 (alignedload512 node:$ptr))>;
434 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
435 (v8i64 (alignedload512 node:$ptr))>;
437 // Like 'load', but uses special alignment checks suitable for use in
438 // memory operands in most SSE instructions, which are required to
439 // be naturally aligned on some targets but not on others. If the subtarget
440 // allows unaligned accesses, match any load, though this may require
441 // setting a feature bit in the processor (on startup, for example).
442 // Opteron 10h and later implement such a feature.
443 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
444 return Subtarget->hasSSEUnalignedMem()
445 || cast<LoadSDNode>(N)->getAlignment() >= 16;
448 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
449 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
451 // 128-bit memop pattern fragments
452 // NOTE: all 128-bit integer vector loads are promoted to v2i64
453 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
454 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
455 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
457 // 256-bit memop pattern fragments
458 // NOTE: all 256-bit integer vector loads are promoted to v4i64
459 def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>;
460 def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>;
461 def memopv4i64 : PatFrag<(ops node:$ptr), (v4i64 (memop node:$ptr))>;
463 // 512-bit memop pattern fragments
464 def memopv16f32 : PatFrag<(ops node:$ptr), (v16f32 (memop node:$ptr))>;
465 def memopv8f64 : PatFrag<(ops node:$ptr), (v8f64 (memop node:$ptr))>;
466 def memopv16i32 : PatFrag<(ops node:$ptr), (v16i32 (memop node:$ptr))>;
467 def memopv8i64 : PatFrag<(ops node:$ptr), (v8i64 (memop node:$ptr))>;
469 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
471 // FIXME: 8 byte alignment for mmx reads is not required
472 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
473 return cast<LoadSDNode>(N)->getAlignment() >= 8;
476 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
479 // Like 'store', but requires the non-temporal bit to be set
480 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
481 (st node:$val, node:$ptr), [{
482 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
483 return ST->isNonTemporal();
487 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
488 (st node:$val, node:$ptr), [{
489 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
490 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
491 ST->getAddressingMode() == ISD::UNINDEXED &&
492 ST->getAlignment() >= 16;
496 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
497 (st node:$val, node:$ptr), [{
498 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
499 return ST->isNonTemporal() &&
500 ST->getAlignment() < 16;
504 // 128-bit bitconvert pattern fragments
505 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
506 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
507 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
508 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
509 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
510 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
512 // 256-bit bitconvert pattern fragments
513 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
514 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
515 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
516 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
517 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
519 // 512-bit bitconvert pattern fragments
520 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
521 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
522 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
523 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
525 def vzmovl_v2i64 : PatFrag<(ops node:$src),
526 (bitconvert (v2i64 (X86vzmovl
527 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
528 def vzmovl_v4i32 : PatFrag<(ops node:$src),
529 (bitconvert (v4i32 (X86vzmovl
530 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
532 def vzload_v2i64 : PatFrag<(ops node:$src),
533 (bitconvert (v2i64 (X86vzload node:$src)))>;
536 def fp32imm0 : PatLeaf<(f32 fpimm), [{
537 return N->isExactlyValue(+0.0);
540 def I8Imm : SDNodeXForm<imm, [{
541 // Transformation function: get the low 8 bits.
542 return getI8Imm((uint8_t)N->getZExtValue());
545 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
546 def FROUND_CURRENT : ImmLeaf<i32, [{
547 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
550 // BYTE_imm - Transform bit immediates into byte immediates.
551 def BYTE_imm : SDNodeXForm<imm, [{
552 // Transformation function: imm >> 3
553 return getI32Imm(N->getZExtValue() >> 3);
556 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
557 // to VEXTRACTF128/VEXTRACTI128 imm.
558 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
559 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N));
562 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
563 // VINSERTF128/VINSERTI128 imm.
564 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
565 return getI8Imm(X86::getInsertVINSERT128Immediate(N));
568 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
569 // to VEXTRACTF64x4 imm.
570 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
571 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N));
574 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
576 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
577 return getI8Imm(X86::getInsertVINSERT256Immediate(N));
580 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
581 (extract_subvector node:$bigvec,
583 return X86::isVEXTRACT128Index(N);
584 }], EXTRACT_get_vextract128_imm>;
586 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
588 (insert_subvector node:$bigvec, node:$smallvec,
590 return X86::isVINSERT128Index(N);
591 }], INSERT_get_vinsert128_imm>;
594 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
595 (extract_subvector node:$bigvec,
597 return X86::isVEXTRACT256Index(N);
598 }], EXTRACT_get_vextract256_imm>;
600 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
602 (insert_subvector node:$bigvec, node:$smallvec,
604 return X86::isVINSERT256Index(N);
605 }], INSERT_get_vinsert256_imm>;