1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // Low word of MMX to GPR.
19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
21 // GPR to low word of MMX.
22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
25 //===----------------------------------------------------------------------===//
26 // MMX Pattern Fragments
27 //===----------------------------------------------------------------------===//
29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
30 def load_mvmmx : PatFrag<(ops node:$ptr),
31 (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
32 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
34 //===----------------------------------------------------------------------===//
35 // SSE specific DAG Nodes.
36 //===----------------------------------------------------------------------===//
38 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
39 SDTCisFP<1>, SDTCisVT<3, i8>,
42 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
43 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
45 // Commutative and Associative FMIN and FMAX.
46 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
47 [SDNPCommutative, SDNPAssociative]>;
48 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
49 [SDNPCommutative, SDNPAssociative]>;
51 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
52 [SDNPCommutative, SDNPAssociative]>;
53 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
54 [SDNPCommutative, SDNPAssociative]>;
55 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
56 [SDNPCommutative, SDNPAssociative]>;
57 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
58 [SDNPCommutative, SDNPAssociative]>;
59 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
60 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
61 def X86frsqrt14s: SDNode<"X86ISD::FRSQRT", SDTFPBinOp>;
62 def X86frcp14s : SDNode<"X86ISD::FRCP", SDTFPBinOp>;
63 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
64 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
65 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
66 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
67 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
68 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
69 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
70 def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
71 //def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
72 def X86cvtdq2pd: SDNode<"X86ISD::CVTDQ2PD",
73 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
74 SDTCisVT<1, v4i32>]>>;
75 def X86cvtudq2pd: SDNode<"X86ISD::CVTUDQ2PD",
76 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
77 SDTCisVT<1, v4i32>]>>;
78 def X86pshufb : SDNode<"X86ISD::PSHUFB",
79 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
81 def X86psadbw : SDNode<"X86ISD::PSADBW",
82 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
84 def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
85 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
86 SDTCisSameAs<1,2>, SDTCisInt<3>]>>;
87 def X86andnp : SDNode<"X86ISD::ANDNP",
88 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
90 def X86psign : SDNode<"X86ISD::PSIGN",
91 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
93 def X86pextrb : SDNode<"X86ISD::PEXTRB",
94 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
95 def X86pextrw : SDNode<"X86ISD::PEXTRW",
96 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
97 def X86pinsrb : SDNode<"X86ISD::PINSRB",
98 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
99 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
100 def X86pinsrw : SDNode<"X86ISD::PINSRW",
101 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
102 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
103 def X86insertps : SDNode<"X86ISD::INSERTPS",
104 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
105 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
106 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
107 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
109 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
110 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
112 def X86vzext : SDNode<"X86ISD::VZEXT",
113 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
114 SDTCisInt<0>, SDTCisInt<1>,
115 SDTCisOpSmallerThanOp<1, 0>]>>;
117 def X86vsext : SDNode<"X86ISD::VSEXT",
118 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
119 SDTCisInt<0>, SDTCisInt<1>,
120 SDTCisOpSmallerThanOp<1, 0>]>>;
122 def SDTVtrunc : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
123 SDTCisInt<0>, SDTCisInt<1>,
124 SDTCisOpSmallerThanOp<0, 1>]>;
126 def X86vtrunc : SDNode<"X86ISD::VTRUNC", SDTVtrunc>;
127 def X86vtruncs : SDNode<"X86ISD::VTRUNCS", SDTVtrunc>;
128 def X86vtruncus : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
130 def X86trunc : SDNode<"X86ISD::TRUNC",
131 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
132 SDTCisOpSmallerThanOp<0, 1>]>>;
133 def X86vfpext : SDNode<"X86ISD::VFPEXT",
134 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
135 SDTCisFP<0>, SDTCisFP<1>,
136 SDTCisOpSmallerThanOp<1, 0>]>>;
137 def X86vfpround: SDNode<"X86ISD::VFPROUND",
138 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
139 SDTCisFP<0>, SDTCisFP<1>,
140 SDTCisOpSmallerThanOp<0, 1>]>>;
142 def X86fround: SDNode<"X86ISD::VFPROUND",
143 SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
144 SDTCVecEltisVT<0, f32>,
145 SDTCVecEltisVT<1, f64>,
146 SDTCVecEltisVT<2, f64>,
147 SDTCisOpSmallerThanOp<0, 1>]>>;
148 def X86froundRnd: SDNode<"X86ISD::VFPROUND",
149 SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
150 SDTCVecEltisVT<0, f32>,
151 SDTCVecEltisVT<1, f64>,
152 SDTCVecEltisVT<2, f64>,
153 SDTCisOpSmallerThanOp<0, 1>,
156 def X86fpext : SDNode<"X86ISD::VFPEXT",
157 SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
158 SDTCVecEltisVT<0, f64>,
159 SDTCVecEltisVT<1, f32>,
160 SDTCVecEltisVT<2, f32>,
161 SDTCisOpSmallerThanOp<1, 0>]>>;
163 def X86fpextRnd : SDNode<"X86ISD::VFPEXT",
164 SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
165 SDTCVecEltisVT<0, f64>,
166 SDTCVecEltisVT<1, f32>,
167 SDTCVecEltisVT<2, f32>,
168 SDTCisOpSmallerThanOp<1, 0>,
171 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
172 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
173 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
174 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
175 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
177 def X86IntCmpMask : SDTypeProfile<1, 2,
178 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
179 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
180 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
183 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
184 SDTCisVec<1>, SDTCisSameAs<2, 1>,
185 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
186 def X86CmpMaskCCRound :
187 SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
188 SDTCisVec<1>, SDTCisSameAs<2, 1>,
189 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
191 def X86CmpMaskCCScalar :
192 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
194 def X86CmpMaskCCScalarRound :
195 SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>,
198 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
199 def X86cmpmRnd : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
200 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
201 def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
202 def X86cmpmsRnd : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalarRound>;
204 def X86vshl : SDNode<"X86ISD::VSHL",
205 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
207 def X86vsrl : SDNode<"X86ISD::VSRL",
208 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
210 def X86vsra : SDNode<"X86ISD::VSRA",
211 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
214 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
215 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
216 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
218 def X86vpshl : SDNode<"X86ISD::VPSHL",
219 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
221 def X86vpsha : SDNode<"X86ISD::VPSHA",
222 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
225 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
227 SDTCisSameAs<2, 1>]>;
228 def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
229 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
230 def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
231 def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
232 def X86mulhrs : SDNode<"X86ISD::MULHRS" , SDTIntBinOp>;
233 def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp>;
234 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
235 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
236 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
237 def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
238 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
239 SDTCisVec<1>, SDTCisSameAs<2, 1>,
240 SDTCVecEltisVT<0, i1>,
241 SDTCisSameNumEltsAs<0, 1>]>>;
242 def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
243 SDTCisVec<1>, SDTCisSameAs<2, 1>,
244 SDTCVecEltisVT<0, i1>,
245 SDTCisSameNumEltsAs<0, 1>]>>;
246 def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
248 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
249 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
250 SDTCisSameAs<1,2>]>>;
251 def X86pmuldq : SDNode<"X86ISD::PMULDQ",
252 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
253 SDTCisSameAs<1,2>]>>;
255 def X86extrqi : SDNode<"X86ISD::EXTRQI",
256 SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
257 SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
258 def X86insertqi : SDNode<"X86ISD::INSERTQI",
259 SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
260 SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
263 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
264 // translated into one of the target nodes below during lowering.
265 // Note: this is a work in progress...
266 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
267 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
269 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
270 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
272 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
274 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
275 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
276 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
277 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
278 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
279 SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
280 def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
281 SDTCisInt<2>, SDTCisInt<3>]>;
283 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
284 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
286 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
287 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
289 def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
290 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
292 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc.
293 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]>;
295 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
296 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
297 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
298 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
299 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
300 SDTCisVec<0>, SDTCisInt<2>]>;
301 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
302 SDTCisVec<0>, SDTCisInt<3>]>;
303 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
304 SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
306 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
307 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
309 def X86Abs : SDNode<"X86ISD::ABS", SDTIntUnaryOp>;
310 def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>;
312 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
313 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
314 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
316 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
317 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
319 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
320 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
321 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
323 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
324 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
326 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
327 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
328 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
330 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
331 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
333 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
334 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
335 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
337 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
338 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
340 def X86vpmaddubsw : SDNode<"X86ISD::VPMADDUBSW" , SDTPack>;
341 def X86vpmaddwd : SDNode<"X86ISD::VPMADDWD" , SDTPack>;
343 def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
344 def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
345 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
346 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
347 def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
348 def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
350 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
352 def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
353 def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImmRound>;
354 def X86VReduce : SDNode<"X86ISD::VREDUCE", SDTFPUnaryOpImmRound>;
355 def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;
356 def X86VGetMant : SDNode<"X86ISD::VGETMANT", SDTFPUnaryOpImmRound>;
357 def X86Vfpclass : SDNode<"X86ISD::VFPCLASS",
358 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
359 SDTCisVec<1>, SDTCisInt<2>]>, []>;
361 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
362 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
363 SDTCisSubVecOfVec<1, 0>]>, []>;
364 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
365 def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
366 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
367 def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
368 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
370 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
372 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
374 def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
375 def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
376 def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
377 def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
378 def X86fmaxRnd : SDNode<"X86ISD::FMAX_RND", SDTFPBinOpRound>;
379 def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOpRound>;
380 def X86fminRnd : SDNode<"X86ISD::FMIN_RND", SDTFPBinOpRound>;
381 def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>;
382 def X86fsqrtRnds : SDNode<"X86ISD::FSQRT_RND", STDFp2SrcRm>;
383 def X86fgetexpRnd : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
384 def X86fgetexpRnds : SDNode<"X86ISD::FGETEXP_RND", STDFp2SrcRm>;
386 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
387 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
388 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
389 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
390 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
391 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
393 def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
394 def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
395 def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
396 def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
397 def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
398 def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
400 def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
401 def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
402 def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
404 def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
405 def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
406 def X86RndScales : SDNode<"X86ISD::VRNDSCALE", STDFp3SrcRm>;
407 def X86Reduces : SDNode<"X86ISD::VREDUCE", STDFp3SrcRm>;
408 def X86GetMants : SDNode<"X86ISD::VGETMANT", STDFp3SrcRm>;
410 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
411 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
413 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
414 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
415 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
418 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
419 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
421 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
422 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
423 def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
424 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
426 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
427 SDTCisSameAs<0,1>, SDTCisInt<2>, SDTCisInt<3>]>;
429 def SDTDoubleToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
430 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
431 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
432 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
434 def SDTDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
435 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
436 def SDTSDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>,SDTCisFP<1>,
437 SDTCVecEltisVT<1, f64>, SDTCisInt<2>]>;
438 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
439 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
440 def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
441 SDTCVecEltisVT<1, f32>, SDTCisInt<2>]>;
442 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
443 SDTCisFP<0>, SDTCVecEltisVT<1, i32>,
445 def SDTVlongToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
446 SDTCisFP<0>, SDTCVecEltisVT<1, i64>,
449 def SDTVFPToIntRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
450 SDTCisFP<1>, SDTCVecEltisVT<0, i32>,
452 def SDTVFPToLongRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
453 SDTCisFP<1>, SDTCVecEltisVT<0, i64>,
457 def X86SintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTintToFPRound>;
458 def X86UintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTintToFPRound>;
460 def X86cvttss2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTSFloatToIntRnd>;
461 def X86cvttss2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTSFloatToIntRnd>;
462 def X86cvttsd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTSDoubleToIntRnd>;
463 def X86cvttsd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTSDoubleToIntRnd>;
464 // Vector with rounding mode
466 // cvtt fp-to-int staff
467 def X86VFpToSintRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToIntRound>;
468 def X86VFpToUintRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToIntRound>;
469 def X86VFpToSlongRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToLongRound>;
470 def X86VFpToUlongRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToLongRound>;
472 def X86VSintToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVintToFPRound>;
473 def X86VUintToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVintToFPRound>;
474 def X86VSlongToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVlongToFPRound>;
475 def X86VUlongToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVlongToFPRound>;
477 // cvt fp-to-int staff
478 def X86cvtps2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToIntRnd>;
479 def X86cvtps2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToIntRnd>;
480 def X86cvtpd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToIntRnd>;
481 def X86cvtpd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToIntRnd>;
483 // Vector without rounding mode
484 def X86cvtps2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToInt>;
485 def X86cvtps2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToInt>;
486 def X86cvtpd2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToInt>;
487 def X86cvtpd2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToInt>;
489 def X86vfpextRnd : SDNode<"X86ISD::VFPEXT",
490 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
491 SDTCisFP<0>, SDTCisFP<1>,
492 SDTCisOpSmallerThanOp<1, 0>,
494 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND",
495 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
496 SDTCisFP<0>, SDTCisFP<1>,
497 SDTCVecEltisVT<0, f32>,
498 SDTCVecEltisVT<1, f64>,
501 //===----------------------------------------------------------------------===//
502 // SSE Complex Patterns
503 //===----------------------------------------------------------------------===//
505 // These are 'extloads' from a scalar to the low element of a vector, zeroing
506 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
508 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
509 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
511 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
512 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
515 def ssmem : Operand<v4f32> {
516 let PrintMethod = "printf32mem";
517 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
518 let ParserMatchClass = X86Mem32AsmOperand;
519 let OperandType = "OPERAND_MEMORY";
521 def sdmem : Operand<v2f64> {
522 let PrintMethod = "printf64mem";
523 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
524 let ParserMatchClass = X86Mem64AsmOperand;
525 let OperandType = "OPERAND_MEMORY";
528 //===----------------------------------------------------------------------===//
529 // SSE pattern fragments
530 //===----------------------------------------------------------------------===//
532 // 128-bit load pattern fragments
533 // NOTE: all 128-bit integer vector loads are promoted to v2i64
534 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
535 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
536 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
538 // 256-bit load pattern fragments
539 // NOTE: all 256-bit integer vector loads are promoted to v4i64
540 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
541 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
542 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
544 // 512-bit load pattern fragments
545 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
546 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
547 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
548 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
549 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
550 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
552 // 128-/256-/512-bit extload pattern fragments
553 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
554 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
555 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
557 // These are needed to match a scalar load that is used in a vector-only
558 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
559 // The memory operand is required to be a 128-bit load, so it must be converted
560 // from a vector to a scalar.
561 def loadf32_128 : PatFrag<(ops node:$ptr),
562 (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
563 def loadf64_128 : PatFrag<(ops node:$ptr),
564 (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
566 // Like 'store', but always requires 128-bit vector alignment.
567 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
568 (store node:$val, node:$ptr), [{
569 return cast<StoreSDNode>(N)->getAlignment() >= 16;
572 // Like 'store', but always requires 256-bit vector alignment.
573 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
574 (store node:$val, node:$ptr), [{
575 return cast<StoreSDNode>(N)->getAlignment() >= 32;
578 // Like 'store', but always requires 512-bit vector alignment.
579 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
580 (store node:$val, node:$ptr), [{
581 return cast<StoreSDNode>(N)->getAlignment() >= 64;
584 // Like 'load', but always requires 128-bit vector alignment.
585 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
586 return cast<LoadSDNode>(N)->getAlignment() >= 16;
589 // Like 'X86vzload', but always requires 128-bit vector alignment.
590 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
591 return cast<MemSDNode>(N)->getAlignment() >= 16;
594 // Like 'load', but always requires 256-bit vector alignment.
595 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
596 return cast<LoadSDNode>(N)->getAlignment() >= 32;
599 // Like 'load', but always requires 512-bit vector alignment.
600 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
601 return cast<LoadSDNode>(N)->getAlignment() >= 64;
604 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
605 (f32 (alignedload node:$ptr))>;
606 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
607 (f64 (alignedload node:$ptr))>;
609 // 128-bit aligned load pattern fragments
610 // NOTE: all 128-bit integer vector loads are promoted to v2i64
611 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
612 (v4f32 (alignedload node:$ptr))>;
613 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
614 (v2f64 (alignedload node:$ptr))>;
615 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
616 (v2i64 (alignedload node:$ptr))>;
618 // 256-bit aligned load pattern fragments
619 // NOTE: all 256-bit integer vector loads are promoted to v4i64
620 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
621 (v8f32 (alignedload256 node:$ptr))>;
622 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
623 (v4f64 (alignedload256 node:$ptr))>;
624 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
625 (v4i64 (alignedload256 node:$ptr))>;
627 // 512-bit aligned load pattern fragments
628 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
629 (v16f32 (alignedload512 node:$ptr))>;
630 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
631 (v16i32 (alignedload512 node:$ptr))>;
632 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
633 (v8f64 (alignedload512 node:$ptr))>;
634 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
635 (v8i64 (alignedload512 node:$ptr))>;
637 // Like 'load', but uses special alignment checks suitable for use in
638 // memory operands in most SSE instructions, which are required to
639 // be naturally aligned on some targets but not on others. If the subtarget
640 // allows unaligned accesses, match any load, though this may require
641 // setting a feature bit in the processor (on startup, for example).
642 // Opteron 10h and later implement such a feature.
643 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
644 return Subtarget->hasSSEUnalignedMem()
645 || cast<LoadSDNode>(N)->getAlignment() >= 16;
648 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
649 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
651 // 128-bit memop pattern fragments
652 // NOTE: all 128-bit integer vector loads are promoted to v2i64
653 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
654 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
655 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
657 // These are needed to match a scalar memop that is used in a vector-only
658 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
659 // The memory operand is required to be a 128-bit load, so it must be converted
660 // from a vector to a scalar.
661 def memopfsf32_128 : PatFrag<(ops node:$ptr),
662 (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
663 def memopfsf64_128 : PatFrag<(ops node:$ptr),
664 (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
667 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
669 // FIXME: 8 byte alignment for mmx reads is not required
670 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
671 return cast<LoadSDNode>(N)->getAlignment() >= 8;
674 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
676 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
677 (masked_gather node:$src1, node:$src2, node:$src3) , [{
678 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
679 return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
680 Mgt->getBasePtr().getValueType() == MVT::v4i32);
684 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
685 (masked_gather node:$src1, node:$src2, node:$src3) , [{
686 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
687 return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
688 Mgt->getBasePtr().getValueType() == MVT::v8i32);
692 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
693 (masked_gather node:$src1, node:$src2, node:$src3) , [{
694 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
695 return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
696 Mgt->getBasePtr().getValueType() == MVT::v2i64);
699 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
700 (masked_gather node:$src1, node:$src2, node:$src3) , [{
701 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
702 return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
703 Mgt->getBasePtr().getValueType() == MVT::v4i64);
706 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
707 (masked_gather node:$src1, node:$src2, node:$src3) , [{
708 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
709 return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
710 Mgt->getBasePtr().getValueType() == MVT::v8i64);
713 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
714 (masked_gather node:$src1, node:$src2, node:$src3) , [{
715 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
716 return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
717 Mgt->getBasePtr().getValueType() == MVT::v16i32);
721 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
722 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
723 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
724 return (Sc->getIndex().getValueType() == MVT::v2i64 ||
725 Sc->getBasePtr().getValueType() == MVT::v2i64);
729 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
730 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
731 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
732 return (Sc->getIndex().getValueType() == MVT::v4i32 ||
733 Sc->getBasePtr().getValueType() == MVT::v4i32);
737 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
738 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
739 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
740 return (Sc->getIndex().getValueType() == MVT::v4i64 ||
741 Sc->getBasePtr().getValueType() == MVT::v4i64);
745 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
746 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
747 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
748 return (Sc->getIndex().getValueType() == MVT::v8i32 ||
749 Sc->getBasePtr().getValueType() == MVT::v8i32);
753 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
754 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
755 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
756 return (Sc->getIndex().getValueType() == MVT::v8i64 ||
757 Sc->getBasePtr().getValueType() == MVT::v8i64);
760 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
761 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
762 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
763 return (Sc->getIndex().getValueType() == MVT::v16i32 ||
764 Sc->getBasePtr().getValueType() == MVT::v16i32);
768 // 128-bit bitconvert pattern fragments
769 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
770 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
771 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
772 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
773 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
774 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
776 // 256-bit bitconvert pattern fragments
777 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
778 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
779 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
780 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
781 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
783 // 512-bit bitconvert pattern fragments
784 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
785 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
786 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
787 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
789 def vzmovl_v2i64 : PatFrag<(ops node:$src),
790 (bitconvert (v2i64 (X86vzmovl
791 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
792 def vzmovl_v4i32 : PatFrag<(ops node:$src),
793 (bitconvert (v4i32 (X86vzmovl
794 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
796 def vzload_v2i64 : PatFrag<(ops node:$src),
797 (bitconvert (v2i64 (X86vzload node:$src)))>;
800 def fp32imm0 : PatLeaf<(f32 fpimm), [{
801 return N->isExactlyValue(+0.0);
804 def I8Imm : SDNodeXForm<imm, [{
805 // Transformation function: get the low 8 bits.
806 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
809 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
810 def FROUND_CURRENT : ImmLeaf<i32, [{
811 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
814 // BYTE_imm - Transform bit immediates into byte immediates.
815 def BYTE_imm : SDNodeXForm<imm, [{
816 // Transformation function: imm >> 3
817 return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
820 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
821 // to VEXTRACTF128/VEXTRACTI128 imm.
822 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
823 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
826 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
827 // VINSERTF128/VINSERTI128 imm.
828 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
829 return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
832 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
833 // to VEXTRACTF64x4 imm.
834 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
835 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
838 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
840 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
841 return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
844 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
845 (extract_subvector node:$bigvec,
847 return X86::isVEXTRACT128Index(N);
848 }], EXTRACT_get_vextract128_imm>;
850 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
852 (insert_subvector node:$bigvec, node:$smallvec,
854 return X86::isVINSERT128Index(N);
855 }], INSERT_get_vinsert128_imm>;
858 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
859 (extract_subvector node:$bigvec,
861 return X86::isVEXTRACT256Index(N);
862 }], EXTRACT_get_vextract256_imm>;
864 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
866 (insert_subvector node:$bigvec, node:$smallvec,
868 return X86::isVINSERT256Index(N);
869 }], INSERT_get_vinsert256_imm>;
871 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
872 (masked_load node:$src1, node:$src2, node:$src3), [{
873 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
874 return Load->getAlignment() >= 16;
878 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
879 (masked_load node:$src1, node:$src2, node:$src3), [{
880 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
881 return Load->getAlignment() >= 32;
885 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
886 (masked_load node:$src1, node:$src2, node:$src3), [{
887 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
888 return Load->getAlignment() >= 64;
892 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
893 (masked_load node:$src1, node:$src2, node:$src3), [{
894 return isa<MaskedLoadSDNode>(N);
897 // masked store fragments.
898 // X86mstore can't be implemented in core DAG files because some targets
899 // doesn't support vector type ( llvm-tblgen will fail)
900 def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
901 (masked_store node:$src1, node:$src2, node:$src3), [{
902 return !cast<MaskedStoreSDNode>(N)->isTruncatingStore();
905 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
906 (X86mstore node:$src1, node:$src2, node:$src3), [{
907 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
908 return Store->getAlignment() >= 16;
912 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
913 (X86mstore node:$src1, node:$src2, node:$src3), [{
914 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
915 return Store->getAlignment() >= 32;
919 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
920 (X86mstore node:$src1, node:$src2, node:$src3), [{
921 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
922 return Store->getAlignment() >= 64;
926 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
927 (X86mstore node:$src1, node:$src2, node:$src3), [{
928 return isa<MaskedStoreSDNode>(N);
931 // masked truncstore fragments
932 // X86mtruncstore can't be implemented in core DAG files because some targets
933 // doesn't support vector type ( llvm-tblgen will fail)
934 def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
935 (masked_store node:$src1, node:$src2, node:$src3), [{
936 return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
938 def masked_truncstorevi8 :
939 PatFrag<(ops node:$src1, node:$src2, node:$src3),
940 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
941 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
943 def masked_truncstorevi16 :
944 PatFrag<(ops node:$src1, node:$src2, node:$src3),
945 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
946 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
948 def masked_truncstorevi32 :
949 PatFrag<(ops node:$src1, node:$src2, node:$src3),
950 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
951 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;