1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // Low word of MMX to GPR.
19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
21 // GPR to low word of MMX.
22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
25 //===----------------------------------------------------------------------===//
26 // MMX Pattern Fragments
27 //===----------------------------------------------------------------------===//
29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
30 def load_mvmmx : PatFrag<(ops node:$ptr),
31 (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
32 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
34 //===----------------------------------------------------------------------===//
35 // SSE specific DAG Nodes.
36 //===----------------------------------------------------------------------===//
38 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
39 SDTCisFP<1>, SDTCisVT<3, i8>,
42 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
43 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
45 // Commutative and Associative FMIN and FMAX.
46 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
47 [SDNPCommutative, SDNPAssociative]>;
48 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
49 [SDNPCommutative, SDNPAssociative]>;
51 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
52 [SDNPCommutative, SDNPAssociative]>;
53 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
54 [SDNPCommutative, SDNPAssociative]>;
55 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
56 [SDNPCommutative, SDNPAssociative]>;
57 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
58 [SDNPCommutative, SDNPAssociative]>;
59 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
60 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
61 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
62 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
63 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
64 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
65 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
66 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
67 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
68 def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
69 //def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
70 def X86cvtdq2pd: SDNode<"X86ISD::CVTDQ2PD",
71 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
72 SDTCisVT<1, v4i32>]>>;
73 def X86cvtudq2pd: SDNode<"X86ISD::CVTUDQ2PD",
74 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
75 SDTCisVT<1, v4i32>]>>;
76 def X86pshufb : SDNode<"X86ISD::PSHUFB",
77 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
79 def X86psadbw : SDNode<"X86ISD::PSADBW",
80 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
82 def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
83 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
84 SDTCisSameAs<1,2>, SDTCisInt<3>]>>;
85 def X86andnp : SDNode<"X86ISD::ANDNP",
86 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
88 def X86psign : SDNode<"X86ISD::PSIGN",
89 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
91 def X86pextrb : SDNode<"X86ISD::PEXTRB",
92 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
93 def X86pextrw : SDNode<"X86ISD::PEXTRW",
94 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
95 def X86pinsrb : SDNode<"X86ISD::PINSRB",
96 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
97 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
98 def X86pinsrw : SDNode<"X86ISD::PINSRW",
99 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
100 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
101 def X86insertps : SDNode<"X86ISD::INSERTPS",
102 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
103 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
104 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
105 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
107 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
108 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
110 def X86vzext : SDNode<"X86ISD::VZEXT",
111 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
112 SDTCisInt<0>, SDTCisInt<1>,
113 SDTCisOpSmallerThanOp<1, 0>]>>;
115 def X86vsext : SDNode<"X86ISD::VSEXT",
116 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
117 SDTCisInt<0>, SDTCisInt<1>,
118 SDTCisOpSmallerThanOp<1, 0>]>>;
120 def SDTVtrunc : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
121 SDTCisInt<0>, SDTCisInt<1>,
122 SDTCisOpSmallerThanOp<0, 1>]>;
124 def X86vtrunc : SDNode<"X86ISD::VTRUNC", SDTVtrunc>;
125 def X86vtruncs : SDNode<"X86ISD::VTRUNCS", SDTVtrunc>;
126 def X86vtruncus : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
128 def X86trunc : SDNode<"X86ISD::TRUNC",
129 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
130 SDTCisOpSmallerThanOp<0, 1>]>>;
131 def X86vfpext : SDNode<"X86ISD::VFPEXT",
132 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
133 SDTCisFP<0>, SDTCisFP<1>,
134 SDTCisOpSmallerThanOp<1, 0>]>>;
135 def X86vfpround: SDNode<"X86ISD::VFPROUND",
136 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
137 SDTCisFP<0>, SDTCisFP<1>,
138 SDTCisOpSmallerThanOp<0, 1>]>>;
140 def X86fround: SDNode<"X86ISD::VFPROUND",
141 SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
142 SDTCVecEltisVT<0, f32>,
143 SDTCVecEltisVT<1, f64>,
144 SDTCVecEltisVT<2, f64>,
145 SDTCisOpSmallerThanOp<0, 1>]>>;
146 def X86froundRnd: SDNode<"X86ISD::VFPROUND",
147 SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
148 SDTCVecEltisVT<0, f32>,
149 SDTCVecEltisVT<1, f64>,
150 SDTCVecEltisVT<2, f64>,
151 SDTCisOpSmallerThanOp<0, 1>,
154 def X86fpext : SDNode<"X86ISD::VFPEXT",
155 SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
156 SDTCVecEltisVT<0, f64>,
157 SDTCVecEltisVT<1, f32>,
158 SDTCVecEltisVT<2, f32>,
159 SDTCisOpSmallerThanOp<1, 0>]>>;
161 def X86fpextRnd : SDNode<"X86ISD::VFPEXT",
162 SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisFP<1>,SDTCisFP<2>,
163 SDTCVecEltisVT<0, f64>,
164 SDTCVecEltisVT<1, f32>,
165 SDTCVecEltisVT<2, f32>,
166 SDTCisOpSmallerThanOp<1, 0>,
169 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
170 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
171 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
172 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
173 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
175 def X86IntCmpMask : SDTypeProfile<1, 2,
176 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
177 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
178 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
181 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
182 SDTCisVec<1>, SDTCisSameAs<2, 1>,
183 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
184 def X86CmpMaskCCRound :
185 SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
186 SDTCisVec<1>, SDTCisSameAs<2, 1>,
187 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
189 def X86CmpMaskCCScalar :
190 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
192 def X86CmpMaskCCScalarRound :
193 SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>,
196 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
197 def X86cmpmRnd : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
198 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
199 def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
200 def X86cmpmsRnd : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalarRound>;
202 def X86vshl : SDNode<"X86ISD::VSHL",
203 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
205 def X86vsrl : SDNode<"X86ISD::VSRL",
206 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
208 def X86vsra : SDNode<"X86ISD::VSRA",
209 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
212 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
213 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
214 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
216 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
218 SDTCisSameAs<2, 1>]>;
219 def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
220 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
221 def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
222 def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
223 def X86mulhrs : SDNode<"X86ISD::MULHRS" , SDTIntBinOp>;
224 def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp>;
225 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
226 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
227 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
228 def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
229 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
230 SDTCisVec<1>, SDTCisSameAs<2, 1>,
231 SDTCVecEltisVT<0, i1>,
232 SDTCisSameNumEltsAs<0, 1>]>>;
233 def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
234 SDTCisVec<1>, SDTCisSameAs<2, 1>,
235 SDTCVecEltisVT<0, i1>,
236 SDTCisSameNumEltsAs<0, 1>]>>;
237 def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
239 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
240 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
241 SDTCisSameAs<1,2>]>>;
242 def X86pmuldq : SDNode<"X86ISD::PMULDQ",
243 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
244 SDTCisSameAs<1,2>]>>;
246 def X86extrqi : SDNode<"X86ISD::EXTRQI",
247 SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
248 SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
249 def X86insertqi : SDNode<"X86ISD::INSERTQI",
250 SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
251 SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
254 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
255 // translated into one of the target nodes below during lowering.
256 // Note: this is a work in progress...
257 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
258 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
260 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
261 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
263 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
265 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
266 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
267 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
268 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
269 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
270 SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
271 def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
272 SDTCisInt<2>, SDTCisInt<3>]>;
274 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
275 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
277 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
278 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
280 def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
281 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
283 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc.
284 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]>;
286 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
287 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
288 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
289 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
290 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
291 SDTCisVec<0>, SDTCisInt<2>]>;
292 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
293 SDTCisVec<0>, SDTCisInt<3>]>;
294 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
295 SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
297 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
298 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
300 def X86Abs : SDNode<"X86ISD::ABS", SDTIntUnaryOp>;
301 def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>;
303 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
304 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
305 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
307 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
308 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
310 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
311 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
312 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
314 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
315 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
317 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
318 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
319 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
321 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
322 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
324 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
325 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
326 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
328 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
329 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
331 def X86vpmaddubsw : SDNode<"X86ISD::VPMADDUBSW" , SDTPack>;
332 def X86vpmaddwd : SDNode<"X86ISD::VPMADDWD" , SDTPack>;
334 def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
335 def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
336 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
337 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
338 def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
339 def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
341 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
343 def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
344 def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImmRound>;
345 def X86VReduce : SDNode<"X86ISD::VREDUCE", SDTFPUnaryOpImmRound>;
346 def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;
347 def X86VGetMant : SDNode<"X86ISD::VGETMANT", SDTFPUnaryOpImmRound>;
348 def X86Vfpclass : SDNode<"X86ISD::VFPCLASS",
349 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
350 SDTCisVec<1>, SDTCisInt<2>]>, []>;
352 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
353 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
354 SDTCisSubVecOfVec<1, 0>]>, []>;
355 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
356 def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
357 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
358 def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
359 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
361 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
363 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
365 def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
366 def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
367 def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
368 def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
369 def X86fmaxRnd : SDNode<"X86ISD::FMAX_RND", SDTFPBinOpRound>;
370 def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOpRound>;
371 def X86fminRnd : SDNode<"X86ISD::FMIN_RND", SDTFPBinOpRound>;
372 def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>;
373 def X86fsqrtRnds : SDNode<"X86ISD::FSQRT_RND", STDFp2SrcRm>;
374 def X86fgetexpRnd : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
375 def X86fgetexpRnds : SDNode<"X86ISD::FGETEXP_RND", STDFp2SrcRm>;
377 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
378 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
379 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
380 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
381 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
382 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
384 def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
385 def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
386 def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
387 def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
388 def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
389 def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
391 def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
392 def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
393 def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
395 def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
396 def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
397 def X86RndScales : SDNode<"X86ISD::VRNDSCALE", STDFp3SrcRm>;
398 def X86Reduces : SDNode<"X86ISD::VREDUCE", STDFp3SrcRm>;
399 def X86GetMants : SDNode<"X86ISD::VGETMANT", STDFp3SrcRm>;
401 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
402 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
404 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
405 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
406 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
409 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
410 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
412 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
413 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
414 def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
415 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
417 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
418 SDTCisSameAs<0,1>, SDTCisInt<2>, SDTCisInt<3>]>;
420 def SDTDoubleToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
421 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
422 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
423 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
425 def SDTDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
426 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
427 def SDTSDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>,SDTCisFP<1>,
428 SDTCVecEltisVT<1, f64>, SDTCisInt<2>]>;
429 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
430 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
431 def SDTSFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisFP<1>,
432 SDTCVecEltisVT<1, f32>, SDTCisInt<2>]>;
433 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
434 SDTCisFP<0>, SDTCVecEltisVT<1, i32>,
436 def SDTVlongToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
437 SDTCisFP<0>, SDTCVecEltisVT<1, i64>,
440 def SDTVFPToIntRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
441 SDTCisFP<1>, SDTCVecEltisVT<0, i32>,
443 def SDTVFPToLongRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
444 SDTCisFP<1>, SDTCVecEltisVT<0, i64>,
448 def X86SintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTintToFPRound>;
449 def X86UintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTintToFPRound>;
451 def X86cvttss2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTSFloatToIntRnd>;
452 def X86cvttss2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTSFloatToIntRnd>;
453 def X86cvttsd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTSDoubleToIntRnd>;
454 def X86cvttsd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTSDoubleToIntRnd>;
455 // Vector with rounding mode
457 // cvtt fp-to-int staff
458 def X86VFpToSintRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToIntRound>;
459 def X86VFpToUintRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToIntRound>;
460 def X86VFpToSlongRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToLongRound>;
461 def X86VFpToUlongRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToLongRound>;
463 def X86VSintToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVintToFPRound>;
464 def X86VUintToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVintToFPRound>;
465 def X86VSlongToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVlongToFPRound>;
466 def X86VUlongToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVlongToFPRound>;
468 // cvt fp-to-int staff
469 def X86cvtps2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToIntRnd>;
470 def X86cvtps2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToIntRnd>;
471 def X86cvtpd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToIntRnd>;
472 def X86cvtpd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToIntRnd>;
474 // Vector without rounding mode
475 def X86cvtps2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToInt>;
476 def X86cvtps2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToInt>;
477 def X86cvtpd2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToInt>;
478 def X86cvtpd2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToInt>;
480 def X86vfpextRnd : SDNode<"X86ISD::VFPEXT",
481 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
482 SDTCisFP<0>, SDTCisFP<1>,
483 SDTCisOpSmallerThanOp<1, 0>,
485 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND",
486 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
487 SDTCisFP<0>, SDTCisFP<1>,
488 SDTCVecEltisVT<0, f32>,
489 SDTCVecEltisVT<1, f64>,
492 //===----------------------------------------------------------------------===//
493 // SSE Complex Patterns
494 //===----------------------------------------------------------------------===//
496 // These are 'extloads' from a scalar to the low element of a vector, zeroing
497 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
499 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
500 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
502 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
503 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
506 def ssmem : Operand<v4f32> {
507 let PrintMethod = "printf32mem";
508 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
509 let ParserMatchClass = X86Mem32AsmOperand;
510 let OperandType = "OPERAND_MEMORY";
512 def sdmem : Operand<v2f64> {
513 let PrintMethod = "printf64mem";
514 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
515 let ParserMatchClass = X86Mem64AsmOperand;
516 let OperandType = "OPERAND_MEMORY";
519 //===----------------------------------------------------------------------===//
520 // SSE pattern fragments
521 //===----------------------------------------------------------------------===//
523 // 128-bit load pattern fragments
524 // NOTE: all 128-bit integer vector loads are promoted to v2i64
525 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
526 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
527 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
529 // 256-bit load pattern fragments
530 // NOTE: all 256-bit integer vector loads are promoted to v4i64
531 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
532 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
533 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
535 // 512-bit load pattern fragments
536 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
537 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
538 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
539 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
540 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
541 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
543 // 128-/256-/512-bit extload pattern fragments
544 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
545 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
546 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
548 // These are needed to match a scalar load that is used in a vector-only
549 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
550 // The memory operand is required to be a 128-bit load, so it must be converted
551 // from a vector to a scalar.
552 def loadf32_128 : PatFrag<(ops node:$ptr),
553 (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
554 def loadf64_128 : PatFrag<(ops node:$ptr),
555 (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
557 // Like 'store', but always requires 128-bit vector alignment.
558 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
559 (store node:$val, node:$ptr), [{
560 return cast<StoreSDNode>(N)->getAlignment() >= 16;
563 // Like 'store', but always requires 256-bit vector alignment.
564 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
565 (store node:$val, node:$ptr), [{
566 return cast<StoreSDNode>(N)->getAlignment() >= 32;
569 // Like 'store', but always requires 512-bit vector alignment.
570 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
571 (store node:$val, node:$ptr), [{
572 return cast<StoreSDNode>(N)->getAlignment() >= 64;
575 // Like 'load', but always requires 128-bit vector alignment.
576 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
577 return cast<LoadSDNode>(N)->getAlignment() >= 16;
580 // Like 'X86vzload', but always requires 128-bit vector alignment.
581 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
582 return cast<MemSDNode>(N)->getAlignment() >= 16;
585 // Like 'load', but always requires 256-bit vector alignment.
586 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
587 return cast<LoadSDNode>(N)->getAlignment() >= 32;
590 // Like 'load', but always requires 512-bit vector alignment.
591 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
592 return cast<LoadSDNode>(N)->getAlignment() >= 64;
595 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
596 (f32 (alignedload node:$ptr))>;
597 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
598 (f64 (alignedload node:$ptr))>;
600 // 128-bit aligned load pattern fragments
601 // NOTE: all 128-bit integer vector loads are promoted to v2i64
602 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
603 (v4f32 (alignedload node:$ptr))>;
604 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
605 (v2f64 (alignedload node:$ptr))>;
606 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
607 (v2i64 (alignedload node:$ptr))>;
609 // 256-bit aligned load pattern fragments
610 // NOTE: all 256-bit integer vector loads are promoted to v4i64
611 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
612 (v8f32 (alignedload256 node:$ptr))>;
613 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
614 (v4f64 (alignedload256 node:$ptr))>;
615 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
616 (v4i64 (alignedload256 node:$ptr))>;
618 // 512-bit aligned load pattern fragments
619 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
620 (v16f32 (alignedload512 node:$ptr))>;
621 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
622 (v16i32 (alignedload512 node:$ptr))>;
623 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
624 (v8f64 (alignedload512 node:$ptr))>;
625 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
626 (v8i64 (alignedload512 node:$ptr))>;
628 // Like 'load', but uses special alignment checks suitable for use in
629 // memory operands in most SSE instructions, which are required to
630 // be naturally aligned on some targets but not on others. If the subtarget
631 // allows unaligned accesses, match any load, though this may require
632 // setting a feature bit in the processor (on startup, for example).
633 // Opteron 10h and later implement such a feature.
634 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
635 return Subtarget->hasSSEUnalignedMem()
636 || cast<LoadSDNode>(N)->getAlignment() >= 16;
639 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
640 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
642 // 128-bit memop pattern fragments
643 // NOTE: all 128-bit integer vector loads are promoted to v2i64
644 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
645 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
646 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
648 // These are needed to match a scalar memop that is used in a vector-only
649 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
650 // The memory operand is required to be a 128-bit load, so it must be converted
651 // from a vector to a scalar.
652 def memopfsf32_128 : PatFrag<(ops node:$ptr),
653 (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
654 def memopfsf64_128 : PatFrag<(ops node:$ptr),
655 (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
658 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
660 // FIXME: 8 byte alignment for mmx reads is not required
661 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
662 return cast<LoadSDNode>(N)->getAlignment() >= 8;
665 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
667 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
668 (masked_gather node:$src1, node:$src2, node:$src3) , [{
669 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
670 return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
671 Mgt->getBasePtr().getValueType() == MVT::v4i32);
675 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
676 (masked_gather node:$src1, node:$src2, node:$src3) , [{
677 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
678 return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
679 Mgt->getBasePtr().getValueType() == MVT::v8i32);
683 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
684 (masked_gather node:$src1, node:$src2, node:$src3) , [{
685 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
686 return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
687 Mgt->getBasePtr().getValueType() == MVT::v2i64);
690 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
691 (masked_gather node:$src1, node:$src2, node:$src3) , [{
692 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
693 return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
694 Mgt->getBasePtr().getValueType() == MVT::v4i64);
697 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
698 (masked_gather node:$src1, node:$src2, node:$src3) , [{
699 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
700 return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
701 Mgt->getBasePtr().getValueType() == MVT::v8i64);
704 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
705 (masked_gather node:$src1, node:$src2, node:$src3) , [{
706 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
707 return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
708 Mgt->getBasePtr().getValueType() == MVT::v16i32);
712 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
713 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
714 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
715 return (Sc->getIndex().getValueType() == MVT::v2i64 ||
716 Sc->getBasePtr().getValueType() == MVT::v2i64);
720 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
721 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
722 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
723 return (Sc->getIndex().getValueType() == MVT::v4i32 ||
724 Sc->getBasePtr().getValueType() == MVT::v4i32);
728 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
729 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
730 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
731 return (Sc->getIndex().getValueType() == MVT::v4i64 ||
732 Sc->getBasePtr().getValueType() == MVT::v4i64);
736 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
737 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
738 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
739 return (Sc->getIndex().getValueType() == MVT::v8i32 ||
740 Sc->getBasePtr().getValueType() == MVT::v8i32);
744 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
745 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
746 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
747 return (Sc->getIndex().getValueType() == MVT::v8i64 ||
748 Sc->getBasePtr().getValueType() == MVT::v8i64);
751 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
752 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
753 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
754 return (Sc->getIndex().getValueType() == MVT::v16i32 ||
755 Sc->getBasePtr().getValueType() == MVT::v16i32);
759 // 128-bit bitconvert pattern fragments
760 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
761 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
762 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
763 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
764 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
765 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
767 // 256-bit bitconvert pattern fragments
768 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
769 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
770 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
771 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
772 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
774 // 512-bit bitconvert pattern fragments
775 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
776 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
777 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
778 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
780 def vzmovl_v2i64 : PatFrag<(ops node:$src),
781 (bitconvert (v2i64 (X86vzmovl
782 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
783 def vzmovl_v4i32 : PatFrag<(ops node:$src),
784 (bitconvert (v4i32 (X86vzmovl
785 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
787 def vzload_v2i64 : PatFrag<(ops node:$src),
788 (bitconvert (v2i64 (X86vzload node:$src)))>;
791 def fp32imm0 : PatLeaf<(f32 fpimm), [{
792 return N->isExactlyValue(+0.0);
795 def I8Imm : SDNodeXForm<imm, [{
796 // Transformation function: get the low 8 bits.
797 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
800 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
801 def FROUND_CURRENT : ImmLeaf<i32, [{
802 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
805 // BYTE_imm - Transform bit immediates into byte immediates.
806 def BYTE_imm : SDNodeXForm<imm, [{
807 // Transformation function: imm >> 3
808 return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
811 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
812 // to VEXTRACTF128/VEXTRACTI128 imm.
813 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
814 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
817 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
818 // VINSERTF128/VINSERTI128 imm.
819 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
820 return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
823 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
824 // to VEXTRACTF64x4 imm.
825 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
826 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
829 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
831 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
832 return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
835 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
836 (extract_subvector node:$bigvec,
838 return X86::isVEXTRACT128Index(N);
839 }], EXTRACT_get_vextract128_imm>;
841 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
843 (insert_subvector node:$bigvec, node:$smallvec,
845 return X86::isVINSERT128Index(N);
846 }], INSERT_get_vinsert128_imm>;
849 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
850 (extract_subvector node:$bigvec,
852 return X86::isVEXTRACT256Index(N);
853 }], EXTRACT_get_vextract256_imm>;
855 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
857 (insert_subvector node:$bigvec, node:$smallvec,
859 return X86::isVINSERT256Index(N);
860 }], INSERT_get_vinsert256_imm>;
862 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
863 (masked_load node:$src1, node:$src2, node:$src3), [{
864 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
865 return Load->getAlignment() >= 16;
869 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
870 (masked_load node:$src1, node:$src2, node:$src3), [{
871 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
872 return Load->getAlignment() >= 32;
876 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
877 (masked_load node:$src1, node:$src2, node:$src3), [{
878 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
879 return Load->getAlignment() >= 64;
883 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
884 (masked_load node:$src1, node:$src2, node:$src3), [{
885 return isa<MaskedLoadSDNode>(N);
888 // masked store fragments.
889 // X86mstore can't be implemented in core DAG files because some targets
890 // doesn't support vector type ( llvm-tblgen will fail)
891 def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
892 (masked_store node:$src1, node:$src2, node:$src3), [{
893 return !cast<MaskedStoreSDNode>(N)->isTruncatingStore();
896 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
897 (X86mstore node:$src1, node:$src2, node:$src3), [{
898 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
899 return Store->getAlignment() >= 16;
903 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
904 (X86mstore node:$src1, node:$src2, node:$src3), [{
905 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
906 return Store->getAlignment() >= 32;
910 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
911 (X86mstore node:$src1, node:$src2, node:$src3), [{
912 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
913 return Store->getAlignment() >= 64;
917 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
918 (X86mstore node:$src1, node:$src2, node:$src3), [{
919 return isa<MaskedStoreSDNode>(N);
922 // masked truncstore fragments
923 // X86mtruncstore can't be implemented in core DAG files because some targets
924 // doesn't support vector type ( llvm-tblgen will fail)
925 def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
926 (masked_store node:$src1, node:$src2, node:$src3), [{
927 return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
929 def masked_truncstorevi8 :
930 PatFrag<(ops node:$src1, node:$src2, node:$src3),
931 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
932 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
934 def masked_truncstorevi16 :
935 PatFrag<(ops node:$src1, node:$src2, node:$src3),
936 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
937 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
939 def masked_truncstorevi32 :
940 PatFrag<(ops node:$src1, node:$src2, node:$src3),
941 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
942 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;