1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // Low word of MMX to GPR.
19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
21 // GPR to low word of MMX.
22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
25 //===----------------------------------------------------------------------===//
26 // MMX Pattern Fragments
27 //===----------------------------------------------------------------------===//
29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
30 def load_mvmmx : PatFrag<(ops node:$ptr),
31 (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
32 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
34 //===----------------------------------------------------------------------===//
35 // SSE specific DAG Nodes.
36 //===----------------------------------------------------------------------===//
38 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
39 SDTCisFP<1>, SDTCisVT<3, i8>,
42 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
43 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
45 // Commutative and Associative FMIN and FMAX.
46 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
47 [SDNPCommutative, SDNPAssociative]>;
48 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
49 [SDNPCommutative, SDNPAssociative]>;
51 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
52 [SDNPCommutative, SDNPAssociative]>;
53 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
54 [SDNPCommutative, SDNPAssociative]>;
55 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
56 [SDNPCommutative, SDNPAssociative]>;
57 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
58 [SDNPCommutative, SDNPAssociative]>;
59 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
60 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
61 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
62 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
63 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
64 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
65 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
66 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
67 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
68 def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
69 //def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
70 def X86cvtdq2pd: SDNode<"X86ISD::CVTDQ2PD",
71 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
72 SDTCisVT<1, v4i32>]>>;
73 def X86pshufb : SDNode<"X86ISD::PSHUFB",
74 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
76 def X86psadbw : SDNode<"X86ISD::PSADBW",
77 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
79 def X86andnp : SDNode<"X86ISD::ANDNP",
80 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
82 def X86psign : SDNode<"X86ISD::PSIGN",
83 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
85 def X86pextrb : SDNode<"X86ISD::PEXTRB",
86 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
87 def X86pextrw : SDNode<"X86ISD::PEXTRW",
88 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
89 def X86pinsrb : SDNode<"X86ISD::PINSRB",
90 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
91 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
92 def X86pinsrw : SDNode<"X86ISD::PINSRW",
93 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
94 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
95 def X86insertps : SDNode<"X86ISD::INSERTPS",
96 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
97 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
98 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
99 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
101 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
102 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
104 def X86vzext : SDNode<"X86ISD::VZEXT",
105 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
106 SDTCisInt<0>, SDTCisInt<1>,
107 SDTCisOpSmallerThanOp<1, 0>]>>;
109 def X86vsext : SDNode<"X86ISD::VSEXT",
110 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
111 SDTCisInt<0>, SDTCisInt<1>,
112 SDTCisOpSmallerThanOp<1, 0>]>>;
114 def X86vtrunc : SDNode<"X86ISD::VTRUNC",
115 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
116 SDTCisInt<0>, SDTCisInt<1>,
117 SDTCisOpSmallerThanOp<0, 1>]>>;
118 def X86trunc : SDNode<"X86ISD::TRUNC",
119 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
120 SDTCisOpSmallerThanOp<0, 1>]>>;
122 def X86vtruncm : SDNode<"X86ISD::VTRUNCM",
123 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
124 SDTCisInt<0>, SDTCisInt<1>,
125 SDTCisVec<2>, SDTCisInt<2>,
126 SDTCisOpSmallerThanOp<0, 2>]>>;
127 def X86vfpext : SDNode<"X86ISD::VFPEXT",
128 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
129 SDTCisFP<0>, SDTCisFP<1>,
130 SDTCisOpSmallerThanOp<1, 0>]>>;
131 def X86vfpround: SDNode<"X86ISD::VFPROUND",
132 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
133 SDTCisFP<0>, SDTCisFP<1>,
134 SDTCisOpSmallerThanOp<0, 1>]>>;
136 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
137 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
138 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
139 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
140 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
142 def X86IntCmpMask : SDTypeProfile<1, 2,
143 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
144 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
145 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
148 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
149 SDTCisVec<1>, SDTCisSameAs<2, 1>,
150 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
151 def X86CmpMaskCCRound :
152 SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
153 SDTCisVec<1>, SDTCisSameAs<2, 1>,
154 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
156 def X86CmpMaskCCScalar :
157 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
159 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
160 def X86cmpmRnd : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
161 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
162 def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
164 def X86vshl : SDNode<"X86ISD::VSHL",
165 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
167 def X86vsrl : SDNode<"X86ISD::VSRL",
168 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
170 def X86vsra : SDNode<"X86ISD::VSRA",
171 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
174 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
175 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
176 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
178 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
180 SDTCisSameAs<2, 1>]>;
181 def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
182 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
183 def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
184 def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
185 def X86mulhrs : SDNode<"X86ISD::MULHRS" , SDTIntBinOp>;
186 def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp>;
187 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
188 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
189 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
190 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
191 SDTCisVec<1>, SDTCisSameAs<2, 1>,
192 SDTCVecEltisVT<0, i1>,
193 SDTCisSameNumEltsAs<0, 1>]>>;
194 def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
195 SDTCisVec<1>, SDTCisSameAs<2, 1>,
196 SDTCVecEltisVT<0, i1>,
197 SDTCisSameNumEltsAs<0, 1>]>>;
198 def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
200 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
201 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
202 SDTCisSameAs<1,2>]>>;
203 def X86pmuldq : SDNode<"X86ISD::PMULDQ",
204 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
205 SDTCisSameAs<1,2>]>>;
207 def X86extrqi : SDNode<"X86ISD::EXTRQI",
208 SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
209 SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
210 def X86insertqi : SDNode<"X86ISD::INSERTQI",
211 SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
212 SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
215 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
216 // translated into one of the target nodes below during lowering.
217 // Note: this is a work in progress...
218 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
219 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
221 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
222 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
224 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
226 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
227 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
228 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
229 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
230 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
231 SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
233 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
234 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
236 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
237 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
239 def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
240 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
242 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc.
243 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]>;
245 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
246 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
247 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
248 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
249 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
250 SDTCisVec<0>, SDTCisInt<2>]>;
251 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
252 SDTCisVec<0>, SDTCisInt<3>]>;
253 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
254 SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
256 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
257 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
258 def X86Abs : SDNode<"X86ISD::ABS", SDTIntUnaryOp>;
260 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
261 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
262 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
264 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
265 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
267 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
268 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
269 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
271 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
272 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
274 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
275 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
276 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
278 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
279 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
281 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
282 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
283 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
285 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
286 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
288 def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
289 def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
290 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
291 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
292 def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
293 def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
295 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
297 def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
298 def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImmRound>;
300 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
301 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
302 SDTCisSubVecOfVec<1, 0>]>, []>;
303 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
304 def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
305 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
306 def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
307 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
309 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
311 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
313 def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
314 def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
315 def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
316 def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
317 def X86fmaxRnd : SDNode<"X86ISD::FMAX_RND", SDTFPBinOpRound>;
318 def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOpRound>;
319 def X86fminRnd : SDNode<"X86ISD::FMIN_RND", SDTFPBinOpRound>;
320 def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>;
321 def X86fgetexpRnd : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
323 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
324 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
325 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
326 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
327 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
328 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
330 def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
331 def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
332 def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
333 def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
334 def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
335 def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
337 def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
338 def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
339 def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
341 def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
342 def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
343 def X86RndScale : SDNode<"X86ISD::RNDSCALE", STDFp3SrcRm>;
345 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
346 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
348 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
349 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
350 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
353 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
354 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
356 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
357 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
358 def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
359 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
361 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
362 SDTCisSameAs<0,1>, SDTCisInt<2>, SDTCisInt<3>]>;
364 def X86SintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTintToFPRound>;
365 def X86SuintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTintToFPRound>;
367 //===----------------------------------------------------------------------===//
368 // SSE Complex Patterns
369 //===----------------------------------------------------------------------===//
371 // These are 'extloads' from a scalar to the low element of a vector, zeroing
372 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
374 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
375 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
377 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
378 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
381 def ssmem : Operand<v4f32> {
382 let PrintMethod = "printf32mem";
383 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
384 let ParserMatchClass = X86Mem32AsmOperand;
385 let OperandType = "OPERAND_MEMORY";
387 def sdmem : Operand<v2f64> {
388 let PrintMethod = "printf64mem";
389 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
390 let ParserMatchClass = X86Mem64AsmOperand;
391 let OperandType = "OPERAND_MEMORY";
394 //===----------------------------------------------------------------------===//
395 // SSE pattern fragments
396 //===----------------------------------------------------------------------===//
398 // 128-bit load pattern fragments
399 // NOTE: all 128-bit integer vector loads are promoted to v2i64
400 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
401 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
402 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
404 // 256-bit load pattern fragments
405 // NOTE: all 256-bit integer vector loads are promoted to v4i64
406 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
407 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
408 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
410 // 512-bit load pattern fragments
411 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
412 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
413 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
414 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
415 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
416 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
418 // 128-/256-/512-bit extload pattern fragments
419 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
420 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
421 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
423 // These are needed to match a scalar load that is used in a vector-only
424 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
425 // The memory operand is required to be a 128-bit load, so it must be converted
426 // from a vector to a scalar.
427 def loadf32_128 : PatFrag<(ops node:$ptr),
428 (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
429 def loadf64_128 : PatFrag<(ops node:$ptr),
430 (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
432 // Like 'store', but always requires 128-bit vector alignment.
433 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
434 (store node:$val, node:$ptr), [{
435 return cast<StoreSDNode>(N)->getAlignment() >= 16;
438 // Like 'store', but always requires 256-bit vector alignment.
439 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
440 (store node:$val, node:$ptr), [{
441 return cast<StoreSDNode>(N)->getAlignment() >= 32;
444 // Like 'store', but always requires 512-bit vector alignment.
445 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
446 (store node:$val, node:$ptr), [{
447 return cast<StoreSDNode>(N)->getAlignment() >= 64;
450 // Like 'load', but always requires 128-bit vector alignment.
451 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
452 return cast<LoadSDNode>(N)->getAlignment() >= 16;
455 // Like 'X86vzload', but always requires 128-bit vector alignment.
456 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
457 return cast<MemSDNode>(N)->getAlignment() >= 16;
460 // Like 'load', but always requires 256-bit vector alignment.
461 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
462 return cast<LoadSDNode>(N)->getAlignment() >= 32;
465 // Like 'load', but always requires 512-bit vector alignment.
466 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
467 return cast<LoadSDNode>(N)->getAlignment() >= 64;
470 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
471 (f32 (alignedload node:$ptr))>;
472 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
473 (f64 (alignedload node:$ptr))>;
475 // 128-bit aligned load pattern fragments
476 // NOTE: all 128-bit integer vector loads are promoted to v2i64
477 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
478 (v4f32 (alignedload node:$ptr))>;
479 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
480 (v2f64 (alignedload node:$ptr))>;
481 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
482 (v2i64 (alignedload node:$ptr))>;
484 // 256-bit aligned load pattern fragments
485 // NOTE: all 256-bit integer vector loads are promoted to v4i64
486 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
487 (v8f32 (alignedload256 node:$ptr))>;
488 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
489 (v4f64 (alignedload256 node:$ptr))>;
490 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
491 (v4i64 (alignedload256 node:$ptr))>;
493 // 512-bit aligned load pattern fragments
494 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
495 (v16f32 (alignedload512 node:$ptr))>;
496 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
497 (v16i32 (alignedload512 node:$ptr))>;
498 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
499 (v8f64 (alignedload512 node:$ptr))>;
500 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
501 (v8i64 (alignedload512 node:$ptr))>;
503 // Like 'load', but uses special alignment checks suitable for use in
504 // memory operands in most SSE instructions, which are required to
505 // be naturally aligned on some targets but not on others. If the subtarget
506 // allows unaligned accesses, match any load, though this may require
507 // setting a feature bit in the processor (on startup, for example).
508 // Opteron 10h and later implement such a feature.
509 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
510 return Subtarget->hasSSEUnalignedMem()
511 || cast<LoadSDNode>(N)->getAlignment() >= 16;
514 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
515 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
517 // 128-bit memop pattern fragments
518 // NOTE: all 128-bit integer vector loads are promoted to v2i64
519 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
520 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
521 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
523 // These are needed to match a scalar memop that is used in a vector-only
524 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
525 // The memory operand is required to be a 128-bit load, so it must be converted
526 // from a vector to a scalar.
527 def memopfsf32_128 : PatFrag<(ops node:$ptr),
528 (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
529 def memopfsf64_128 : PatFrag<(ops node:$ptr),
530 (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
533 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
535 // FIXME: 8 byte alignment for mmx reads is not required
536 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
537 return cast<LoadSDNode>(N)->getAlignment() >= 8;
540 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
543 // Like 'store', but requires the non-temporal bit to be set
544 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
545 (st node:$val, node:$ptr), [{
546 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
547 return ST->isNonTemporal();
551 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
552 (st node:$val, node:$ptr), [{
553 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
554 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
555 ST->getAddressingMode() == ISD::UNINDEXED &&
556 ST->getAlignment() >= 16;
560 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
561 (st node:$val, node:$ptr), [{
562 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
563 return ST->isNonTemporal() &&
564 ST->getAlignment() < 16;
568 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
569 (masked_gather node:$src1, node:$src2, node:$src3) , [{
570 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
571 return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
572 Mgt->getBasePtr().getValueType() == MVT::v4i32);
576 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
577 (masked_gather node:$src1, node:$src2, node:$src3) , [{
578 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
579 return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
580 Mgt->getBasePtr().getValueType() == MVT::v8i32);
584 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
585 (masked_gather node:$src1, node:$src2, node:$src3) , [{
586 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
587 return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
588 Mgt->getBasePtr().getValueType() == MVT::v2i64);
591 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
592 (masked_gather node:$src1, node:$src2, node:$src3) , [{
593 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
594 return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
595 Mgt->getBasePtr().getValueType() == MVT::v4i64);
598 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
599 (masked_gather node:$src1, node:$src2, node:$src3) , [{
600 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
601 return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
602 Mgt->getBasePtr().getValueType() == MVT::v8i64);
605 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
606 (masked_gather node:$src1, node:$src2, node:$src3) , [{
607 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
608 return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
609 Mgt->getBasePtr().getValueType() == MVT::v16i32);
613 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
614 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
615 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
616 return (Sc->getIndex().getValueType() == MVT::v2i64 ||
617 Sc->getBasePtr().getValueType() == MVT::v2i64);
621 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
622 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
623 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
624 return (Sc->getIndex().getValueType() == MVT::v4i32 ||
625 Sc->getBasePtr().getValueType() == MVT::v4i32);
629 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
630 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
631 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
632 return (Sc->getIndex().getValueType() == MVT::v4i64 ||
633 Sc->getBasePtr().getValueType() == MVT::v4i64);
637 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
638 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
639 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
640 return (Sc->getIndex().getValueType() == MVT::v8i32 ||
641 Sc->getBasePtr().getValueType() == MVT::v8i32);
645 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
646 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
647 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
648 return (Sc->getIndex().getValueType() == MVT::v8i64 ||
649 Sc->getBasePtr().getValueType() == MVT::v8i64);
652 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
653 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
654 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
655 return (Sc->getIndex().getValueType() == MVT::v16i32 ||
656 Sc->getBasePtr().getValueType() == MVT::v16i32);
660 // 128-bit bitconvert pattern fragments
661 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
662 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
663 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
664 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
665 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
666 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
668 // 256-bit bitconvert pattern fragments
669 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
670 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
671 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
672 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
673 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
675 // 512-bit bitconvert pattern fragments
676 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
677 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
678 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
679 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
681 def vzmovl_v2i64 : PatFrag<(ops node:$src),
682 (bitconvert (v2i64 (X86vzmovl
683 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
684 def vzmovl_v4i32 : PatFrag<(ops node:$src),
685 (bitconvert (v4i32 (X86vzmovl
686 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
688 def vzload_v2i64 : PatFrag<(ops node:$src),
689 (bitconvert (v2i64 (X86vzload node:$src)))>;
692 def fp32imm0 : PatLeaf<(f32 fpimm), [{
693 return N->isExactlyValue(+0.0);
696 def I8Imm : SDNodeXForm<imm, [{
697 // Transformation function: get the low 8 bits.
698 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
701 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
702 def FROUND_CURRENT : ImmLeaf<i32, [{
703 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
706 // BYTE_imm - Transform bit immediates into byte immediates.
707 def BYTE_imm : SDNodeXForm<imm, [{
708 // Transformation function: imm >> 3
709 return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
712 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
713 // to VEXTRACTF128/VEXTRACTI128 imm.
714 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
715 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
718 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
719 // VINSERTF128/VINSERTI128 imm.
720 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
721 return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
724 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
725 // to VEXTRACTF64x4 imm.
726 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
727 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
730 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
732 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
733 return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
736 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
737 (extract_subvector node:$bigvec,
739 return X86::isVEXTRACT128Index(N);
740 }], EXTRACT_get_vextract128_imm>;
742 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
744 (insert_subvector node:$bigvec, node:$smallvec,
746 return X86::isVINSERT128Index(N);
747 }], INSERT_get_vinsert128_imm>;
750 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
751 (extract_subvector node:$bigvec,
753 return X86::isVEXTRACT256Index(N);
754 }], EXTRACT_get_vextract256_imm>;
756 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
758 (insert_subvector node:$bigvec, node:$smallvec,
760 return X86::isVINSERT256Index(N);
761 }], INSERT_get_vinsert256_imm>;
763 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
764 (masked_load node:$src1, node:$src2, node:$src3), [{
765 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
766 return Load->getAlignment() >= 16;
770 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
771 (masked_load node:$src1, node:$src2, node:$src3), [{
772 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
773 return Load->getAlignment() >= 32;
777 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
778 (masked_load node:$src1, node:$src2, node:$src3), [{
779 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
780 return Load->getAlignment() >= 64;
784 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
785 (masked_load node:$src1, node:$src2, node:$src3), [{
786 return isa<MaskedLoadSDNode>(N);
789 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
790 (masked_store node:$src1, node:$src2, node:$src3), [{
791 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
792 return Store->getAlignment() >= 16;
796 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
797 (masked_store node:$src1, node:$src2, node:$src3), [{
798 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
799 return Store->getAlignment() >= 32;
803 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
804 (masked_store node:$src1, node:$src2, node:$src3), [{
805 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
806 return Store->getAlignment() >= 64;
810 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
811 (masked_store node:$src1, node:$src2, node:$src3), [{
812 return isa<MaskedStoreSDNode>(N);