1 //======- X86InstrFragmentsSIMD.td - x86 ISA -------------*- tablegen -*-=====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX Pattern Fragments
16 //===----------------------------------------------------------------------===//
18 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
19 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
21 //===----------------------------------------------------------------------===//
22 // SSE specific DAG Nodes.
23 //===----------------------------------------------------------------------===//
25 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
26 SDTCisFP<0>, SDTCisInt<2> ]>;
27 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
28 SDTCisFP<1>, SDTCisVT<3, i8>]>;
30 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
31 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
32 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
35 [SDNPCommutative, SDNPAssociative]>;
36 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
37 [SDNPCommutative, SDNPAssociative]>;
38 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
39 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
40 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
41 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
42 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
43 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
44 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
45 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
46 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
47 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
48 def X86cmpss : SDNode<"X86ISD::FSETCCss", SDTX86Cmpss>;
49 def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
50 def X86pshufb : SDNode<"X86ISD::PSHUFB",
51 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
53 def X86andnp : SDNode<"X86ISD::ANDNP",
54 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
56 def X86psign : SDNode<"X86ISD::PSIGN",
57 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
59 def X86pextrb : SDNode<"X86ISD::PEXTRB",
60 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
61 def X86pextrw : SDNode<"X86ISD::PEXTRW",
62 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
63 def X86pinsrb : SDNode<"X86ISD::PINSRB",
64 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
65 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
66 def X86pinsrw : SDNode<"X86ISD::PINSRW",
67 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
68 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
69 def X86insrtps : SDNode<"X86ISD::INSERTPS",
70 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
71 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
72 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
73 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
74 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
75 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
76 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
77 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
78 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
79 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
80 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
81 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
82 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
83 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
84 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
85 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
86 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
87 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
89 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
92 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
93 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
95 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
96 // translated into one of the target nodes below during lowering.
97 // Note: this is a work in progress...
98 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
99 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
102 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
103 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
104 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
105 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
107 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
109 def X86PAlign : SDNode<"X86ISD::PALIGN", SDTShuff3OpI>;
111 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
112 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
113 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
115 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
117 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
118 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
119 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
121 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
122 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
124 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
125 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
126 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
128 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
129 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
131 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
132 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
134 def X86VPermilp : SDNode<"X86ISD::VPERMILP", SDTShuff2OpI>;
136 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
138 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
140 //===----------------------------------------------------------------------===//
141 // SSE Complex Patterns
142 //===----------------------------------------------------------------------===//
144 // These are 'extloads' from a scalar to the low element of a vector, zeroing
145 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
147 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
148 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
150 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
151 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
154 def ssmem : Operand<v4f32> {
155 let PrintMethod = "printf32mem";
156 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
157 let ParserMatchClass = X86MemAsmOperand;
158 let OperandType = "OPERAND_MEMORY";
160 def sdmem : Operand<v2f64> {
161 let PrintMethod = "printf64mem";
162 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
163 let ParserMatchClass = X86MemAsmOperand;
164 let OperandType = "OPERAND_MEMORY";
167 //===----------------------------------------------------------------------===//
168 // SSE pattern fragments
169 //===----------------------------------------------------------------------===//
171 // 128-bit load pattern fragments
172 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
173 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
174 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
175 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
177 // 256-bit load pattern fragments
178 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
179 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
180 def loadv8i32 : PatFrag<(ops node:$ptr), (v8i32 (load node:$ptr))>;
181 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
183 // Like 'store', but always requires 128-bit vector alignment.
184 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
185 (store node:$val, node:$ptr), [{
186 return cast<StoreSDNode>(N)->getAlignment() >= 16;
189 // Like 'store', but always requires 256-bit vector alignment.
190 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
191 (store node:$val, node:$ptr), [{
192 return cast<StoreSDNode>(N)->getAlignment() >= 32;
195 // Like 'load', but always requires 128-bit vector alignment.
196 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
197 return cast<LoadSDNode>(N)->getAlignment() >= 16;
200 // Like 'load', but always requires 256-bit vector alignment.
201 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
202 return cast<LoadSDNode>(N)->getAlignment() >= 32;
205 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
206 (f32 (alignedload node:$ptr))>;
207 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
208 (f64 (alignedload node:$ptr))>;
210 // 128-bit aligned load pattern fragments
211 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
212 (v4f32 (alignedload node:$ptr))>;
213 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
214 (v2f64 (alignedload node:$ptr))>;
215 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
216 (v4i32 (alignedload node:$ptr))>;
217 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
218 (v2i64 (alignedload node:$ptr))>;
220 // 256-bit aligned load pattern fragments
221 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
222 (v8f32 (alignedload256 node:$ptr))>;
223 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
224 (v4f64 (alignedload256 node:$ptr))>;
225 def alignedloadv8i32 : PatFrag<(ops node:$ptr),
226 (v8i32 (alignedload256 node:$ptr))>;
227 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
228 (v4i64 (alignedload256 node:$ptr))>;
230 // Like 'load', but uses special alignment checks suitable for use in
231 // memory operands in most SSE instructions, which are required to
232 // be naturally aligned on some targets but not on others. If the subtarget
233 // allows unaligned accesses, match any load, though this may require
234 // setting a feature bit in the processor (on startup, for example).
235 // Opteron 10h and later implement such a feature.
236 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
237 return Subtarget->hasVectorUAMem()
238 || cast<LoadSDNode>(N)->getAlignment() >= 16;
241 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
242 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
244 // 128-bit memop pattern fragments
245 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
246 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
247 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
248 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
249 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop node:$ptr))>;
250 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
252 // 256-bit memop pattern fragments
253 def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>;
254 def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>;
255 def memopv4i64 : PatFrag<(ops node:$ptr), (v4i64 (memop node:$ptr))>;
256 def memopv8i32 : PatFrag<(ops node:$ptr), (v8i32 (memop node:$ptr))>;
257 def memopv16i16 : PatFrag<(ops node:$ptr), (v16i16 (memop node:$ptr))>;
258 def memopv32i8 : PatFrag<(ops node:$ptr), (v32i8 (memop node:$ptr))>;
260 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
262 // FIXME: 8 byte alignment for mmx reads is not required
263 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
264 return cast<LoadSDNode>(N)->getAlignment() >= 8;
267 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
270 // Like 'store', but requires the non-temporal bit to be set
271 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
272 (st node:$val, node:$ptr), [{
273 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
274 return ST->isNonTemporal();
278 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
279 (st node:$val, node:$ptr), [{
280 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
281 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
282 ST->getAddressingMode() == ISD::UNINDEXED &&
283 ST->getAlignment() >= 16;
287 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
288 (st node:$val, node:$ptr), [{
289 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
290 return ST->isNonTemporal() &&
291 ST->getAlignment() < 16;
295 // 128-bit bitconvert pattern fragments
296 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
297 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
298 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
299 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
300 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
301 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
303 // 256-bit bitconvert pattern fragments
304 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
305 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
306 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
307 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
309 def vzmovl_v2i64 : PatFrag<(ops node:$src),
310 (bitconvert (v2i64 (X86vzmovl
311 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
312 def vzmovl_v4i32 : PatFrag<(ops node:$src),
313 (bitconvert (v4i32 (X86vzmovl
314 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
316 def vzload_v2i64 : PatFrag<(ops node:$src),
317 (bitconvert (v2i64 (X86vzload node:$src)))>;
320 def fp32imm0 : PatLeaf<(f32 fpimm), [{
321 return N->isExactlyValue(+0.0);
324 // BYTE_imm - Transform bit immediates into byte immediates.
325 def BYTE_imm : SDNodeXForm<imm, [{
326 // Transformation function: imm >> 3
327 return getI32Imm(N->getZExtValue() >> 3);
330 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
332 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
333 return getI8Imm(X86::getShuffleSHUFImmediate(N));
336 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
338 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
339 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
342 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
344 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
345 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
348 // EXTRACT_get_vextractf128_imm xform function: convert extract_subvector index
349 // to VEXTRACTF128 imm.
350 def EXTRACT_get_vextractf128_imm : SDNodeXForm<extract_subvector, [{
351 return getI8Imm(X86::getExtractVEXTRACTF128Immediate(N));
354 // INSERT_get_vinsertf128_imm xform function: convert insert_subvector index to
356 def INSERT_get_vinsertf128_imm : SDNodeXForm<insert_subvector, [{
357 return getI8Imm(X86::getInsertVINSERTF128Immediate(N));
360 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
361 (vector_shuffle node:$lhs, node:$rhs), [{
362 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
363 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
366 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
367 (vector_shuffle node:$lhs, node:$rhs), [{
368 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
371 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
372 (vector_shuffle node:$lhs, node:$rhs), [{
373 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
376 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
377 (vector_shuffle node:$lhs, node:$rhs), [{
378 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
381 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
382 (vector_shuffle node:$lhs, node:$rhs), [{
383 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
386 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
387 (vector_shuffle node:$lhs, node:$rhs), [{
388 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
391 def movl : PatFrag<(ops node:$lhs, node:$rhs),
392 (vector_shuffle node:$lhs, node:$rhs), [{
393 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
396 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
397 (vector_shuffle node:$lhs, node:$rhs), [{
398 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N), Subtarget->hasAVX2());
401 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
402 (vector_shuffle node:$lhs, node:$rhs), [{
403 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N), Subtarget->hasAVX2());
406 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
407 (vector_shuffle node:$lhs, node:$rhs), [{
408 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
409 }], SHUFFLE_get_shuf_imm>;
411 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
412 (vector_shuffle node:$lhs, node:$rhs), [{
413 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
414 }], SHUFFLE_get_shuf_imm>;
416 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
417 (vector_shuffle node:$lhs, node:$rhs), [{
418 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
419 }], SHUFFLE_get_pshufhw_imm>;
421 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
422 (vector_shuffle node:$lhs, node:$rhs), [{
423 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
424 }], SHUFFLE_get_pshuflw_imm>;
426 def vextractf128_extract : PatFrag<(ops node:$bigvec, node:$index),
427 (extract_subvector node:$bigvec,
429 return X86::isVEXTRACTF128Index(N);
430 }], EXTRACT_get_vextractf128_imm>;
432 def vinsertf128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
434 (insert_subvector node:$bigvec, node:$smallvec,
436 return X86::isVINSERTF128Index(N);
437 }], INSERT_get_vinsertf128_imm>;