1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // Low word of MMX to GPR.
19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
21 // GPR to low word of MMX.
22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
25 //===----------------------------------------------------------------------===//
26 // MMX Pattern Fragments
27 //===----------------------------------------------------------------------===//
29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
30 def load_mvmmx : PatFrag<(ops node:$ptr),
31 (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
32 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
34 //===----------------------------------------------------------------------===//
35 // SSE specific DAG Nodes.
36 //===----------------------------------------------------------------------===//
38 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
39 SDTCisFP<1>, SDTCisVT<3, i8>,
42 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
43 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
45 // Commutative and Associative FMIN and FMAX.
46 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
47 [SDNPCommutative, SDNPAssociative]>;
48 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
49 [SDNPCommutative, SDNPAssociative]>;
51 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
52 [SDNPCommutative, SDNPAssociative]>;
53 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
54 [SDNPCommutative, SDNPAssociative]>;
55 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
56 [SDNPCommutative, SDNPAssociative]>;
57 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
58 [SDNPCommutative, SDNPAssociative]>;
59 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
60 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
61 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
62 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
63 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
64 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
65 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
66 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
67 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
68 def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
69 //def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
70 def X86cvtdq2pd: SDNode<"X86ISD::CVTDQ2PD",
71 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
72 SDTCisVT<1, v4i32>]>>;
73 def X86cvtudq2pd: SDNode<"X86ISD::CVTUDQ2PD",
74 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
75 SDTCisVT<1, v4i32>]>>;
76 def X86pshufb : SDNode<"X86ISD::PSHUFB",
77 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
79 def X86psadbw : SDNode<"X86ISD::PSADBW",
80 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
82 def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
83 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
84 SDTCisSameAs<1,2>, SDTCisInt<3>]>>;
85 def X86andnp : SDNode<"X86ISD::ANDNP",
86 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
88 def X86psign : SDNode<"X86ISD::PSIGN",
89 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
91 def X86pextrb : SDNode<"X86ISD::PEXTRB",
92 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
93 def X86pextrw : SDNode<"X86ISD::PEXTRW",
94 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
95 def X86pinsrb : SDNode<"X86ISD::PINSRB",
96 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
97 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
98 def X86pinsrw : SDNode<"X86ISD::PINSRW",
99 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
100 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
101 def X86insertps : SDNode<"X86ISD::INSERTPS",
102 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
103 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
104 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
105 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
107 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
108 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
110 def X86vzext : SDNode<"X86ISD::VZEXT",
111 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
112 SDTCisInt<0>, SDTCisInt<1>,
113 SDTCisOpSmallerThanOp<1, 0>]>>;
115 def X86vsext : SDNode<"X86ISD::VSEXT",
116 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
117 SDTCisInt<0>, SDTCisInt<1>,
118 SDTCisOpSmallerThanOp<1, 0>]>>;
120 def SDTVtrunc : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
121 SDTCisInt<0>, SDTCisInt<1>,
122 SDTCisOpSmallerThanOp<0, 1>]>;
124 def X86vtrunc : SDNode<"X86ISD::VTRUNC", SDTVtrunc>;
125 def X86vtruncs : SDNode<"X86ISD::VTRUNCS", SDTVtrunc>;
126 def X86vtruncus : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
128 def X86trunc : SDNode<"X86ISD::TRUNC",
129 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
130 SDTCisOpSmallerThanOp<0, 1>]>>;
131 def X86vfpext : SDNode<"X86ISD::VFPEXT",
132 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
133 SDTCisFP<0>, SDTCisFP<1>,
134 SDTCisOpSmallerThanOp<1, 0>]>>;
135 def X86vfpround: SDNode<"X86ISD::VFPROUND",
136 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
137 SDTCisFP<0>, SDTCisFP<1>,
138 SDTCisOpSmallerThanOp<0, 1>]>>;
140 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
141 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
142 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
143 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
144 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
146 def X86IntCmpMask : SDTypeProfile<1, 2,
147 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
148 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
149 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
152 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
153 SDTCisVec<1>, SDTCisSameAs<2, 1>,
154 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
155 def X86CmpMaskCCRound :
156 SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
157 SDTCisVec<1>, SDTCisSameAs<2, 1>,
158 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
160 def X86CmpMaskCCScalar :
161 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
163 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
164 def X86cmpmRnd : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
165 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
166 def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
168 def X86vshl : SDNode<"X86ISD::VSHL",
169 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
171 def X86vsrl : SDNode<"X86ISD::VSRL",
172 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
174 def X86vsra : SDNode<"X86ISD::VSRA",
175 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
178 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
179 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
180 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
182 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
184 SDTCisSameAs<2, 1>]>;
185 def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
186 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
187 def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
188 def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
189 def X86mulhrs : SDNode<"X86ISD::MULHRS" , SDTIntBinOp>;
190 def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp>;
191 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
192 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
193 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
194 def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
195 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
196 SDTCisVec<1>, SDTCisSameAs<2, 1>,
197 SDTCVecEltisVT<0, i1>,
198 SDTCisSameNumEltsAs<0, 1>]>>;
199 def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
200 SDTCisVec<1>, SDTCisSameAs<2, 1>,
201 SDTCVecEltisVT<0, i1>,
202 SDTCisSameNumEltsAs<0, 1>]>>;
203 def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
205 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
206 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
207 SDTCisSameAs<1,2>]>>;
208 def X86pmuldq : SDNode<"X86ISD::PMULDQ",
209 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
210 SDTCisSameAs<1,2>]>>;
212 def X86extrqi : SDNode<"X86ISD::EXTRQI",
213 SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
214 SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
215 def X86insertqi : SDNode<"X86ISD::INSERTQI",
216 SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
217 SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
220 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
221 // translated into one of the target nodes below during lowering.
222 // Note: this is a work in progress...
223 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
224 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
226 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
227 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
229 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
231 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
232 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
233 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
234 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
235 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
236 SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
237 def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
238 SDTCisInt<2>, SDTCisInt<3>]>;
240 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
241 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
243 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
244 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
246 def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
247 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
249 def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc.
250 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]>;
252 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
253 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
254 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
255 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
256 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
257 SDTCisVec<0>, SDTCisInt<2>]>;
258 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
259 SDTCisVec<0>, SDTCisInt<3>]>;
260 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
261 SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
263 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
264 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
266 def X86Abs : SDNode<"X86ISD::ABS", SDTIntUnaryOp>;
267 def X86Conflict : SDNode<"X86ISD::CONFLICT", SDTIntUnaryOp>;
269 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
270 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
271 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
273 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
274 def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
276 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
277 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
278 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
280 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
281 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
283 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
284 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
285 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
287 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
288 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
290 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
291 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
292 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
294 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
295 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
297 def X86vpmaddubsw : SDNode<"X86ISD::VPMADDUBSW" , SDTPack>;
298 def X86vpmaddwd : SDNode<"X86ISD::VPMADDWD" , SDTPack>;
300 def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
301 def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
302 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
303 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
304 def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
305 def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
307 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
309 def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
310 def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImmRound>;
311 def X86VReduce : SDNode<"X86ISD::VREDUCE", SDTFPUnaryOpImmRound>;
312 def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;
313 def X86VGetMant : SDNode<"X86ISD::VGETMANT", SDTFPUnaryOpImmRound>;
315 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
316 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
317 SDTCisSubVecOfVec<1, 0>]>, []>;
318 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
319 def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
320 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
321 def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
322 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
324 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
326 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
328 def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
329 def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
330 def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
331 def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
332 def X86fmaxRnd : SDNode<"X86ISD::FMAX_RND", SDTFPBinOpRound>;
333 def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOpRound>;
334 def X86fminRnd : SDNode<"X86ISD::FMIN_RND", SDTFPBinOpRound>;
335 def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>;
336 def X86fgetexpRnd : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
337 def X86fgetexpRnds : SDNode<"X86ISD::FGETEXP_RND", STDFp2SrcRm>;
339 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
340 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
341 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
342 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
343 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
344 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
346 def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
347 def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
348 def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
349 def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
350 def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
351 def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
353 def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
354 def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
355 def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
357 def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
358 def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
359 def X86RndScales : SDNode<"X86ISD::VRNDSCALE", STDFp3SrcRm>;
360 def X86Reduces : SDNode<"X86ISD::VREDUCE", STDFp3SrcRm>;
361 def X86GetMants : SDNode<"X86ISD::VGETMANT", STDFp3SrcRm>;
363 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
364 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
366 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
367 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
368 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
371 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
372 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
374 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
375 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
376 def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
377 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
379 def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
380 SDTCisSameAs<0,1>, SDTCisInt<2>, SDTCisInt<3>]>;
382 def SDTDoubleToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
383 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
384 def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
385 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
387 def SDTDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
388 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
389 def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
390 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
392 def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
393 SDTCisFP<0>, SDTCVecEltisVT<1, i32>,
395 def SDTVlongToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
396 SDTCisFP<0>, SDTCVecEltisVT<1, i64>,
399 def SDTVFPToIntRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
400 SDTCisFP<1>, SDTCVecEltisVT<0, i32>,
402 def SDTVFPToLongRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
403 SDTCisFP<1>, SDTCVecEltisVT<0, i64>,
407 def X86SintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTintToFPRound>;
408 def X86UintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTintToFPRound>;
410 // Vector with rounding mode
412 // cvtt fp-to-int staff
413 def X86VFpToSintRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToIntRound>;
414 def X86VFpToUintRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToIntRound>;
415 def X86VFpToSlongRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToLongRound>;
416 def X86VFpToUlongRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToLongRound>;
418 def X86VSintToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVintToFPRound>;
419 def X86VUintToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVintToFPRound>;
420 def X86VSlongToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVlongToFPRound>;
421 def X86VUlongToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVlongToFPRound>;
423 // cvt fp-to-int staff
424 def X86cvtps2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToIntRnd>;
425 def X86cvtps2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToIntRnd>;
426 def X86cvtpd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToIntRnd>;
427 def X86cvtpd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToIntRnd>;
429 // Vector without rounding mode
430 def X86cvtps2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToInt>;
431 def X86cvtps2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToInt>;
432 def X86cvtpd2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToInt>;
433 def X86cvtpd2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToInt>;
435 def X86vfpextRnd : SDNode<"X86ISD::VFPEXT",
436 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
437 SDTCisFP<0>, SDTCisFP<1>,
438 SDTCisOpSmallerThanOp<1, 0>,
440 def X86vfproundRnd: SDNode<"X86ISD::VFPROUND",
441 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
442 SDTCisFP<0>, SDTCisFP<1>,
443 SDTCVecEltisVT<0, f32>,
444 SDTCVecEltisVT<1, f64>,
447 //===----------------------------------------------------------------------===//
448 // SSE Complex Patterns
449 //===----------------------------------------------------------------------===//
451 // These are 'extloads' from a scalar to the low element of a vector, zeroing
452 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
454 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
455 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
457 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
458 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
461 def ssmem : Operand<v4f32> {
462 let PrintMethod = "printf32mem";
463 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
464 let ParserMatchClass = X86Mem32AsmOperand;
465 let OperandType = "OPERAND_MEMORY";
467 def sdmem : Operand<v2f64> {
468 let PrintMethod = "printf64mem";
469 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
470 let ParserMatchClass = X86Mem64AsmOperand;
471 let OperandType = "OPERAND_MEMORY";
474 //===----------------------------------------------------------------------===//
475 // SSE pattern fragments
476 //===----------------------------------------------------------------------===//
478 // 128-bit load pattern fragments
479 // NOTE: all 128-bit integer vector loads are promoted to v2i64
480 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
481 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
482 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
484 // 256-bit load pattern fragments
485 // NOTE: all 256-bit integer vector loads are promoted to v4i64
486 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
487 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
488 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
490 // 512-bit load pattern fragments
491 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
492 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
493 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
494 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
495 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
496 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
498 // 128-/256-/512-bit extload pattern fragments
499 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
500 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
501 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
503 // These are needed to match a scalar load that is used in a vector-only
504 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
505 // The memory operand is required to be a 128-bit load, so it must be converted
506 // from a vector to a scalar.
507 def loadf32_128 : PatFrag<(ops node:$ptr),
508 (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
509 def loadf64_128 : PatFrag<(ops node:$ptr),
510 (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
512 // Like 'store', but always requires 128-bit vector alignment.
513 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
514 (store node:$val, node:$ptr), [{
515 return cast<StoreSDNode>(N)->getAlignment() >= 16;
518 // Like 'store', but always requires 256-bit vector alignment.
519 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
520 (store node:$val, node:$ptr), [{
521 return cast<StoreSDNode>(N)->getAlignment() >= 32;
524 // Like 'store', but always requires 512-bit vector alignment.
525 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
526 (store node:$val, node:$ptr), [{
527 return cast<StoreSDNode>(N)->getAlignment() >= 64;
530 // Like 'load', but always requires 128-bit vector alignment.
531 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
532 return cast<LoadSDNode>(N)->getAlignment() >= 16;
535 // Like 'X86vzload', but always requires 128-bit vector alignment.
536 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
537 return cast<MemSDNode>(N)->getAlignment() >= 16;
540 // Like 'load', but always requires 256-bit vector alignment.
541 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
542 return cast<LoadSDNode>(N)->getAlignment() >= 32;
545 // Like 'load', but always requires 512-bit vector alignment.
546 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
547 return cast<LoadSDNode>(N)->getAlignment() >= 64;
550 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
551 (f32 (alignedload node:$ptr))>;
552 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
553 (f64 (alignedload node:$ptr))>;
555 // 128-bit aligned load pattern fragments
556 // NOTE: all 128-bit integer vector loads are promoted to v2i64
557 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
558 (v4f32 (alignedload node:$ptr))>;
559 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
560 (v2f64 (alignedload node:$ptr))>;
561 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
562 (v2i64 (alignedload node:$ptr))>;
564 // 256-bit aligned load pattern fragments
565 // NOTE: all 256-bit integer vector loads are promoted to v4i64
566 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
567 (v8f32 (alignedload256 node:$ptr))>;
568 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
569 (v4f64 (alignedload256 node:$ptr))>;
570 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
571 (v4i64 (alignedload256 node:$ptr))>;
573 // 512-bit aligned load pattern fragments
574 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
575 (v16f32 (alignedload512 node:$ptr))>;
576 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
577 (v16i32 (alignedload512 node:$ptr))>;
578 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
579 (v8f64 (alignedload512 node:$ptr))>;
580 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
581 (v8i64 (alignedload512 node:$ptr))>;
583 // Like 'load', but uses special alignment checks suitable for use in
584 // memory operands in most SSE instructions, which are required to
585 // be naturally aligned on some targets but not on others. If the subtarget
586 // allows unaligned accesses, match any load, though this may require
587 // setting a feature bit in the processor (on startup, for example).
588 // Opteron 10h and later implement such a feature.
589 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
590 return Subtarget->hasSSEUnalignedMem()
591 || cast<LoadSDNode>(N)->getAlignment() >= 16;
594 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
595 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
597 // 128-bit memop pattern fragments
598 // NOTE: all 128-bit integer vector loads are promoted to v2i64
599 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
600 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
601 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
603 // These are needed to match a scalar memop that is used in a vector-only
604 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
605 // The memory operand is required to be a 128-bit load, so it must be converted
606 // from a vector to a scalar.
607 def memopfsf32_128 : PatFrag<(ops node:$ptr),
608 (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
609 def memopfsf64_128 : PatFrag<(ops node:$ptr),
610 (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
613 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
615 // FIXME: 8 byte alignment for mmx reads is not required
616 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
617 return cast<LoadSDNode>(N)->getAlignment() >= 8;
620 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
622 def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
623 (masked_gather node:$src1, node:$src2, node:$src3) , [{
624 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
625 return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
626 Mgt->getBasePtr().getValueType() == MVT::v4i32);
630 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
631 (masked_gather node:$src1, node:$src2, node:$src3) , [{
632 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
633 return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
634 Mgt->getBasePtr().getValueType() == MVT::v8i32);
638 def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
639 (masked_gather node:$src1, node:$src2, node:$src3) , [{
640 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
641 return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
642 Mgt->getBasePtr().getValueType() == MVT::v2i64);
645 def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
646 (masked_gather node:$src1, node:$src2, node:$src3) , [{
647 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
648 return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
649 Mgt->getBasePtr().getValueType() == MVT::v4i64);
652 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
653 (masked_gather node:$src1, node:$src2, node:$src3) , [{
654 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
655 return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
656 Mgt->getBasePtr().getValueType() == MVT::v8i64);
659 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
660 (masked_gather node:$src1, node:$src2, node:$src3) , [{
661 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
662 return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
663 Mgt->getBasePtr().getValueType() == MVT::v16i32);
667 def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
668 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
669 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
670 return (Sc->getIndex().getValueType() == MVT::v2i64 ||
671 Sc->getBasePtr().getValueType() == MVT::v2i64);
675 def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
676 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
677 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
678 return (Sc->getIndex().getValueType() == MVT::v4i32 ||
679 Sc->getBasePtr().getValueType() == MVT::v4i32);
683 def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
684 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
685 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
686 return (Sc->getIndex().getValueType() == MVT::v4i64 ||
687 Sc->getBasePtr().getValueType() == MVT::v4i64);
691 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
692 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
693 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
694 return (Sc->getIndex().getValueType() == MVT::v8i32 ||
695 Sc->getBasePtr().getValueType() == MVT::v8i32);
699 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
700 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
701 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
702 return (Sc->getIndex().getValueType() == MVT::v8i64 ||
703 Sc->getBasePtr().getValueType() == MVT::v8i64);
706 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
707 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
708 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
709 return (Sc->getIndex().getValueType() == MVT::v16i32 ||
710 Sc->getBasePtr().getValueType() == MVT::v16i32);
714 // 128-bit bitconvert pattern fragments
715 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
716 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
717 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
718 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
719 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
720 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
722 // 256-bit bitconvert pattern fragments
723 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
724 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
725 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
726 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
727 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
729 // 512-bit bitconvert pattern fragments
730 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
731 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
732 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
733 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
735 def vzmovl_v2i64 : PatFrag<(ops node:$src),
736 (bitconvert (v2i64 (X86vzmovl
737 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
738 def vzmovl_v4i32 : PatFrag<(ops node:$src),
739 (bitconvert (v4i32 (X86vzmovl
740 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
742 def vzload_v2i64 : PatFrag<(ops node:$src),
743 (bitconvert (v2i64 (X86vzload node:$src)))>;
746 def fp32imm0 : PatLeaf<(f32 fpimm), [{
747 return N->isExactlyValue(+0.0);
750 def I8Imm : SDNodeXForm<imm, [{
751 // Transformation function: get the low 8 bits.
752 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
755 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
756 def FROUND_CURRENT : ImmLeaf<i32, [{
757 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
760 // BYTE_imm - Transform bit immediates into byte immediates.
761 def BYTE_imm : SDNodeXForm<imm, [{
762 // Transformation function: imm >> 3
763 return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
766 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
767 // to VEXTRACTF128/VEXTRACTI128 imm.
768 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
769 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
772 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
773 // VINSERTF128/VINSERTI128 imm.
774 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
775 return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
778 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
779 // to VEXTRACTF64x4 imm.
780 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
781 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
784 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
786 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
787 return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
790 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
791 (extract_subvector node:$bigvec,
793 return X86::isVEXTRACT128Index(N);
794 }], EXTRACT_get_vextract128_imm>;
796 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
798 (insert_subvector node:$bigvec, node:$smallvec,
800 return X86::isVINSERT128Index(N);
801 }], INSERT_get_vinsert128_imm>;
804 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
805 (extract_subvector node:$bigvec,
807 return X86::isVEXTRACT256Index(N);
808 }], EXTRACT_get_vextract256_imm>;
810 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
812 (insert_subvector node:$bigvec, node:$smallvec,
814 return X86::isVINSERT256Index(N);
815 }], INSERT_get_vinsert256_imm>;
817 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
818 (masked_load node:$src1, node:$src2, node:$src3), [{
819 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
820 return Load->getAlignment() >= 16;
824 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
825 (masked_load node:$src1, node:$src2, node:$src3), [{
826 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
827 return Load->getAlignment() >= 32;
831 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
832 (masked_load node:$src1, node:$src2, node:$src3), [{
833 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
834 return Load->getAlignment() >= 64;
838 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
839 (masked_load node:$src1, node:$src2, node:$src3), [{
840 return isa<MaskedLoadSDNode>(N);
843 // masked store fragments.
844 // X86mstore can't be implemented in core DAG files because some targets
845 // doesn't support vector type ( llvm-tblgen will fail)
846 def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
847 (masked_store node:$src1, node:$src2, node:$src3), [{
848 return !cast<MaskedStoreSDNode>(N)->isTruncatingStore();
851 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
852 (X86mstore node:$src1, node:$src2, node:$src3), [{
853 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
854 return Store->getAlignment() >= 16;
858 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
859 (X86mstore node:$src1, node:$src2, node:$src3), [{
860 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
861 return Store->getAlignment() >= 32;
865 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
866 (X86mstore node:$src1, node:$src2, node:$src3), [{
867 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
868 return Store->getAlignment() >= 64;
872 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
873 (X86mstore node:$src1, node:$src2, node:$src3), [{
874 return isa<MaskedStoreSDNode>(N);
877 // masked truncstore fragments
878 // X86mtruncstore can't be implemented in core DAG files because some targets
879 // doesn't support vector type ( llvm-tblgen will fail)
880 def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
881 (masked_store node:$src1, node:$src2, node:$src3), [{
882 return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
884 def masked_truncstorevi8 :
885 PatFrag<(ops node:$src1, node:$src2, node:$src3),
886 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
887 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
889 def masked_truncstorevi16 :
890 PatFrag<(ops node:$src1, node:$src2, node:$src3),
891 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
892 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
894 def masked_truncstorevi32 :
895 PatFrag<(ops node:$src1, node:$src2, node:$src3),
896 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
897 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;