1 //===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides pattern fragments useful for SIMD instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // MMX specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // Low word of MMX to GPR.
19 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
21 // GPR to low word of MMX.
22 def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
25 //===----------------------------------------------------------------------===//
26 // MMX Pattern Fragments
27 //===----------------------------------------------------------------------===//
29 def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
30 def load_mvmmx : PatFrag<(ops node:$ptr),
31 (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
32 def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
34 //===----------------------------------------------------------------------===//
35 // SSE specific DAG Nodes.
36 //===----------------------------------------------------------------------===//
38 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
39 SDTCisFP<0>, SDTCisInt<2> ]>;
40 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
41 SDTCisFP<1>, SDTCisVT<3, i8>,
44 def X86umin : SDNode<"X86ISD::UMIN", SDTIntBinOp>;
45 def X86umax : SDNode<"X86ISD::UMAX", SDTIntBinOp>;
46 def X86smin : SDNode<"X86ISD::SMIN", SDTIntBinOp>;
47 def X86smax : SDNode<"X86ISD::SMAX", SDTIntBinOp>;
49 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
50 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
52 // Commutative and Associative FMIN and FMAX.
53 def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
54 [SDNPCommutative, SDNPAssociative]>;
55 def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
56 [SDNPCommutative, SDNPAssociative]>;
58 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
59 [SDNPCommutative, SDNPAssociative]>;
60 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
61 [SDNPCommutative, SDNPAssociative]>;
62 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
63 [SDNPCommutative, SDNPAssociative]>;
64 def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
65 [SDNPCommutative, SDNPAssociative]>;
66 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
67 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
68 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
69 def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
70 def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
71 def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
72 def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
73 def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
74 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
75 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
76 def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
77 //def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
78 def X86pshufb : SDNode<"X86ISD::PSHUFB",
79 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
81 def X86psadbw : SDNode<"X86ISD::PSADBW",
82 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
84 def X86andnp : SDNode<"X86ISD::ANDNP",
85 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
87 def X86psign : SDNode<"X86ISD::PSIGN",
88 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
90 def X86pextrb : SDNode<"X86ISD::PEXTRB",
91 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
92 def X86pextrw : SDNode<"X86ISD::PEXTRW",
93 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
94 def X86pinsrb : SDNode<"X86ISD::PINSRB",
95 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
96 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
97 def X86pinsrw : SDNode<"X86ISD::PINSRW",
98 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
99 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
100 def X86insertps : SDNode<"X86ISD::INSERTPS",
101 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
102 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
103 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
104 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
106 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
107 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
109 def X86vzext : SDNode<"X86ISD::VZEXT",
110 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
111 SDTCisInt<0>, SDTCisInt<1>,
112 SDTCisOpSmallerThanOp<1, 0>]>>;
114 def X86vsext : SDNode<"X86ISD::VSEXT",
115 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
116 SDTCisInt<0>, SDTCisInt<1>,
117 SDTCisOpSmallerThanOp<1, 0>]>>;
119 def X86vtrunc : SDNode<"X86ISD::VTRUNC",
120 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
121 SDTCisInt<0>, SDTCisInt<1>,
122 SDTCisOpSmallerThanOp<0, 1>]>>;
123 def X86trunc : SDNode<"X86ISD::TRUNC",
124 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
125 SDTCisOpSmallerThanOp<0, 1>]>>;
127 def X86vtruncm : SDNode<"X86ISD::VTRUNCM",
128 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
129 SDTCisInt<0>, SDTCisInt<1>,
130 SDTCisVec<2>, SDTCisInt<2>,
131 SDTCisOpSmallerThanOp<0, 2>]>>;
132 def X86vfpext : SDNode<"X86ISD::VFPEXT",
133 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
134 SDTCisFP<0>, SDTCisFP<1>,
135 SDTCisOpSmallerThanOp<1, 0>]>>;
136 def X86vfpround: SDNode<"X86ISD::VFPROUND",
137 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
138 SDTCisFP<0>, SDTCisFP<1>,
139 SDTCisOpSmallerThanOp<0, 1>]>>;
141 def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
142 def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
143 def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
144 def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
145 def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
147 def X86IntCmpMask : SDTypeProfile<1, 2,
148 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
149 def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
150 def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
153 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
154 SDTCisVec<1>, SDTCisSameAs<2, 1>,
155 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
156 def X86CmpMaskCCRound :
157 SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
158 SDTCisVec<1>, SDTCisSameAs<2, 1>,
159 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
161 def X86CmpMaskCCScalar :
162 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
164 def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
165 def X86cmpmRnd : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
166 def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
167 def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
169 def X86vshl : SDNode<"X86ISD::VSHL",
170 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
172 def X86vsrl : SDNode<"X86ISD::VSRL",
173 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
175 def X86vsra : SDNode<"X86ISD::VSRA",
176 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
179 def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
180 def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
181 def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
183 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
185 SDTCisSameAs<2, 1>]>;
186 def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
187 def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
188 def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
189 def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
190 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
191 def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
192 def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
193 def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
194 SDTCisVec<1>, SDTCisSameAs<2, 1>,
195 SDTCVecEltisVT<0, i1>,
196 SDTCisSameNumEltsAs<0, 1>]>>;
197 def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
198 SDTCisVec<1>, SDTCisSameAs<2, 1>,
199 SDTCVecEltisVT<0, i1>,
200 SDTCisSameNumEltsAs<0, 1>]>>;
201 def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
203 def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
204 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
205 SDTCisSameAs<1,2>]>>;
206 def X86pmuldq : SDNode<"X86ISD::PMULDQ",
207 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
208 SDTCisSameAs<1,2>]>>;
210 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
211 // translated into one of the target nodes below during lowering.
212 // Note: this is a work in progress...
213 def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
214 def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
216 def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
217 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
219 def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
221 def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
222 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
223 def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
224 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
225 def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
226 SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
228 def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
229 def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
231 def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
232 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
234 def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
235 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
237 def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
238 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
239 def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
240 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
241 def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
242 SDTCisVec<0>, SDTCisInt<2>]>;
243 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
244 SDTCisVec<0>, SDTCisInt<3>]>;
245 def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
246 SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
248 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
249 def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
251 def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
252 def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
253 def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
255 def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
257 def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
258 def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
259 def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
261 def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
262 def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
264 def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
265 def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
266 def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
268 def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
269 def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
271 def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
272 def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
273 def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
275 def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
276 def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
278 def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
279 def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
280 def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
281 def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
282 def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
283 def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
285 def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
287 def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
289 def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
290 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
291 SDTCisSubVecOfVec<1, 0>]>, []>;
292 def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
293 def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
294 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
295 def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
296 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
298 def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
300 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
302 def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
303 def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
304 def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
305 def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
306 def X86fmaxRnd : SDNode<"X86ISD::FMAX_RND", SDTFPBinOpRound>;
307 def X86fminRnd : SDNode<"X86ISD::FMIN_RND", SDTFPBinOpRound>;
309 def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
310 def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
311 def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
312 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
313 def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
314 def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
316 def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
317 def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
318 def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
319 def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
320 def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
321 def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
323 def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
324 def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
325 def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
327 def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
328 def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
329 def X86RndScale : SDNode<"X86ISD::RNDSCALE", STDFp3SrcRm>;
331 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
332 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
334 def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
335 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
336 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
339 def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
340 def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
342 def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 3,
343 [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
344 SDTCisVec<3>, SDTCisVec<1>, SDTCisInt<1>]>, []>;
345 def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 3,
347 SDTCisVec<3>, SDTCisVec<1>, SDTCisInt<1>]>, []>;
349 //===----------------------------------------------------------------------===//
350 // SSE Complex Patterns
351 //===----------------------------------------------------------------------===//
353 // These are 'extloads' from a scalar to the low element of a vector, zeroing
354 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
356 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
357 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
359 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
360 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
363 def ssmem : Operand<v4f32> {
364 let PrintMethod = "printf32mem";
365 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
366 let ParserMatchClass = X86Mem32AsmOperand;
367 let OperandType = "OPERAND_MEMORY";
369 def sdmem : Operand<v2f64> {
370 let PrintMethod = "printf64mem";
371 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
372 let ParserMatchClass = X86Mem64AsmOperand;
373 let OperandType = "OPERAND_MEMORY";
376 //===----------------------------------------------------------------------===//
377 // SSE pattern fragments
378 //===----------------------------------------------------------------------===//
380 // 128-bit load pattern fragments
381 // NOTE: all 128-bit integer vector loads are promoted to v2i64
382 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
383 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
384 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
386 // 256-bit load pattern fragments
387 // NOTE: all 256-bit integer vector loads are promoted to v4i64
388 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
389 def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
390 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
392 // 512-bit load pattern fragments
393 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
394 def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
395 def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
396 def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
397 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
398 def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
400 // 128-/256-/512-bit extload pattern fragments
401 def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
402 def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
403 def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
405 // These are needed to match a scalar load that is used in a vector-only
406 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
407 // The memory operand is required to be a 128-bit load, so it must be converted
408 // from a vector to a scalar.
409 def loadf32_128 : PatFrag<(ops node:$ptr),
410 (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
411 def loadf64_128 : PatFrag<(ops node:$ptr),
412 (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
414 // Like 'store', but always requires 128-bit vector alignment.
415 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
416 (store node:$val, node:$ptr), [{
417 return cast<StoreSDNode>(N)->getAlignment() >= 16;
420 // Like 'store', but always requires 256-bit vector alignment.
421 def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
422 (store node:$val, node:$ptr), [{
423 return cast<StoreSDNode>(N)->getAlignment() >= 32;
426 // Like 'store', but always requires 512-bit vector alignment.
427 def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
428 (store node:$val, node:$ptr), [{
429 return cast<StoreSDNode>(N)->getAlignment() >= 64;
432 // Like 'load', but always requires 128-bit vector alignment.
433 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
434 return cast<LoadSDNode>(N)->getAlignment() >= 16;
437 // Like 'X86vzload', but always requires 128-bit vector alignment.
438 def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
439 return cast<MemSDNode>(N)->getAlignment() >= 16;
442 // Like 'load', but always requires 256-bit vector alignment.
443 def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
444 return cast<LoadSDNode>(N)->getAlignment() >= 32;
447 // Like 'load', but always requires 512-bit vector alignment.
448 def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
449 return cast<LoadSDNode>(N)->getAlignment() >= 64;
452 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
453 (f32 (alignedload node:$ptr))>;
454 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
455 (f64 (alignedload node:$ptr))>;
457 // 128-bit aligned load pattern fragments
458 // NOTE: all 128-bit integer vector loads are promoted to v2i64
459 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
460 (v4f32 (alignedload node:$ptr))>;
461 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
462 (v2f64 (alignedload node:$ptr))>;
463 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
464 (v2i64 (alignedload node:$ptr))>;
466 // 256-bit aligned load pattern fragments
467 // NOTE: all 256-bit integer vector loads are promoted to v4i64
468 def alignedloadv8f32 : PatFrag<(ops node:$ptr),
469 (v8f32 (alignedload256 node:$ptr))>;
470 def alignedloadv4f64 : PatFrag<(ops node:$ptr),
471 (v4f64 (alignedload256 node:$ptr))>;
472 def alignedloadv4i64 : PatFrag<(ops node:$ptr),
473 (v4i64 (alignedload256 node:$ptr))>;
475 // 512-bit aligned load pattern fragments
476 def alignedloadv16f32 : PatFrag<(ops node:$ptr),
477 (v16f32 (alignedload512 node:$ptr))>;
478 def alignedloadv16i32 : PatFrag<(ops node:$ptr),
479 (v16i32 (alignedload512 node:$ptr))>;
480 def alignedloadv8f64 : PatFrag<(ops node:$ptr),
481 (v8f64 (alignedload512 node:$ptr))>;
482 def alignedloadv8i64 : PatFrag<(ops node:$ptr),
483 (v8i64 (alignedload512 node:$ptr))>;
485 // Like 'load', but uses special alignment checks suitable for use in
486 // memory operands in most SSE instructions, which are required to
487 // be naturally aligned on some targets but not on others. If the subtarget
488 // allows unaligned accesses, match any load, though this may require
489 // setting a feature bit in the processor (on startup, for example).
490 // Opteron 10h and later implement such a feature.
491 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
492 return Subtarget->hasSSEUnalignedMem()
493 || cast<LoadSDNode>(N)->getAlignment() >= 16;
496 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
497 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
499 // 128-bit memop pattern fragments
500 // NOTE: all 128-bit integer vector loads are promoted to v2i64
501 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
502 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
503 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
505 // These are needed to match a scalar memop that is used in a vector-only
506 // math instruction such as the FP logical ops: andps, andnps, orps, xorps.
507 // The memory operand is required to be a 128-bit load, so it must be converted
508 // from a vector to a scalar.
509 def memopfsf32_128 : PatFrag<(ops node:$ptr),
510 (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
511 def memopfsf64_128 : PatFrag<(ops node:$ptr),
512 (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
515 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
517 // FIXME: 8 byte alignment for mmx reads is not required
518 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
519 return cast<LoadSDNode>(N)->getAlignment() >= 8;
522 def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
525 // Like 'store', but requires the non-temporal bit to be set
526 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
527 (st node:$val, node:$ptr), [{
528 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
529 return ST->isNonTemporal();
533 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
534 (st node:$val, node:$ptr), [{
535 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
536 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
537 ST->getAddressingMode() == ISD::UNINDEXED &&
538 ST->getAlignment() >= 16;
542 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
543 (st node:$val, node:$ptr), [{
544 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
545 return ST->isNonTemporal() &&
546 ST->getAlignment() < 16;
550 def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
551 (masked_gather node:$src1, node:$src2, node:$src3) , [{
552 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
553 return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
554 Mgt->getBasePtr().getValueType() == MVT::v8i32);
558 def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
559 (masked_gather node:$src1, node:$src2, node:$src3) , [{
560 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
561 return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
562 Mgt->getBasePtr().getValueType() == MVT::v8i64);
565 def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
566 (masked_gather node:$src1, node:$src2, node:$src3) , [{
567 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
568 return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
569 Mgt->getBasePtr().getValueType() == MVT::v16i32);
573 def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
574 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
575 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
576 return (Sc->getIndex().getValueType() == MVT::v8i32 ||
577 Sc->getBasePtr().getValueType() == MVT::v8i32);
581 def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
582 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
583 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
584 return (Sc->getIndex().getValueType() == MVT::v8i64 ||
585 Sc->getBasePtr().getValueType() == MVT::v8i64);
588 def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
589 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
590 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
591 return (Sc->getIndex().getValueType() == MVT::v16i32 ||
592 Sc->getBasePtr().getValueType() == MVT::v16i32);
596 // 128-bit bitconvert pattern fragments
597 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
598 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
599 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
600 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
601 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
602 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
604 // 256-bit bitconvert pattern fragments
605 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
606 def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
607 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
608 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
609 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
611 // 512-bit bitconvert pattern fragments
612 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
613 def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
614 def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
615 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
617 def vzmovl_v2i64 : PatFrag<(ops node:$src),
618 (bitconvert (v2i64 (X86vzmovl
619 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
620 def vzmovl_v4i32 : PatFrag<(ops node:$src),
621 (bitconvert (v4i32 (X86vzmovl
622 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
624 def vzload_v2i64 : PatFrag<(ops node:$src),
625 (bitconvert (v2i64 (X86vzload node:$src)))>;
628 def fp32imm0 : PatLeaf<(f32 fpimm), [{
629 return N->isExactlyValue(+0.0);
632 def I8Imm : SDNodeXForm<imm, [{
633 // Transformation function: get the low 8 bits.
634 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
637 def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
638 def FROUND_CURRENT : ImmLeaf<i32, [{
639 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
642 // BYTE_imm - Transform bit immediates into byte immediates.
643 def BYTE_imm : SDNodeXForm<imm, [{
644 // Transformation function: imm >> 3
645 return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
648 // EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
649 // to VEXTRACTF128/VEXTRACTI128 imm.
650 def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
651 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
654 // INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
655 // VINSERTF128/VINSERTI128 imm.
656 def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
657 return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
660 // EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
661 // to VEXTRACTF64x4 imm.
662 def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
663 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
666 // INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
668 def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
669 return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
672 def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
673 (extract_subvector node:$bigvec,
675 return X86::isVEXTRACT128Index(N);
676 }], EXTRACT_get_vextract128_imm>;
678 def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
680 (insert_subvector node:$bigvec, node:$smallvec,
682 return X86::isVINSERT128Index(N);
683 }], INSERT_get_vinsert128_imm>;
686 def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
687 (extract_subvector node:$bigvec,
689 return X86::isVEXTRACT256Index(N);
690 }], EXTRACT_get_vextract256_imm>;
692 def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
694 (insert_subvector node:$bigvec, node:$smallvec,
696 return X86::isVINSERT256Index(N);
697 }], INSERT_get_vinsert256_imm>;
699 def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
700 (masked_load node:$src1, node:$src2, node:$src3), [{
701 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
702 return Load->getAlignment() >= 16;
706 def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
707 (masked_load node:$src1, node:$src2, node:$src3), [{
708 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
709 return Load->getAlignment() >= 32;
713 def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
714 (masked_load node:$src1, node:$src2, node:$src3), [{
715 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
716 return Load->getAlignment() >= 64;
720 def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
721 (masked_load node:$src1, node:$src2, node:$src3), [{
722 return isa<MaskedLoadSDNode>(N);
725 def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
726 (masked_store node:$src1, node:$src2, node:$src3), [{
727 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
728 return Store->getAlignment() >= 16;
732 def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
733 (masked_store node:$src1, node:$src2, node:$src3), [{
734 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
735 return Store->getAlignment() >= 32;
739 def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
740 (masked_store node:$src1, node:$src2, node:$src3), [{
741 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
742 return Store->getAlignment() >= 64;
746 def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
747 (masked_store node:$src1, node:$src2, node:$src3), [{
748 return isa<MaskedStoreSDNode>(N);