1 //===- X86InstrFormats.td - X86 Instruction Formats --------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>;
25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
27 def MRM6r : Format<22>; def MRM7r : Format<23>;
28 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
30 def MRM6m : Format<30>; def MRM7m : Format<31>;
31 def MRMInitReg : Format<32>;
32 def MRM_C1 : Format<33>;
33 def MRM_C8 : Format<34>;
34 def MRM_C9 : Format<35>;
35 def MRM_E8 : Format<36>;
36 def MRM_F0 : Format<37>;
39 // ImmType - This specifies the immediate type used by an instruction. This is
40 // part of the ad-hoc solution used to emit machine instruction encodings by our
41 // machine code emitter.
42 class ImmType<bits<3> val> {
45 def NoImm : ImmType<0>;
46 def Imm8 : ImmType<1>;
47 def Imm16 : ImmType<2>;
48 def Imm32 : ImmType<3>;
49 def Imm64 : ImmType<4>;
51 // FPFormat - This specifies what form this FP instruction has. This is used by
52 // the Floating-Point stackifier pass.
53 class FPFormat<bits<3> val> {
56 def NotFP : FPFormat<0>;
57 def ZeroArgFP : FPFormat<1>;
58 def OneArgFP : FPFormat<2>;
59 def OneArgFPRW : FPFormat<3>;
60 def TwoArgFP : FPFormat<4>;
61 def CompareFP : FPFormat<5>;
62 def CondMovFP : FPFormat<6>;
63 def SpecialFP : FPFormat<7>;
65 // Prefix byte classes which are used to indicate to the ad-hoc machine code
66 // emitter that various prefix bytes are required.
67 class OpSize { bit hasOpSizePrefix = 1; }
68 class AdSize { bit hasAdSizePrefix = 1; }
69 class REX_W { bit hasREX_WPrefix = 1; }
70 class LOCK { bit hasLockPrefix = 1; }
71 class SegFS { bits<2> SegOvrBits = 1; }
72 class SegGS { bits<2> SegOvrBits = 2; }
73 class TB { bits<4> Prefix = 1; }
74 class REP { bits<4> Prefix = 2; }
75 class D8 { bits<4> Prefix = 3; }
76 class D9 { bits<4> Prefix = 4; }
77 class DA { bits<4> Prefix = 5; }
78 class DB { bits<4> Prefix = 6; }
79 class DC { bits<4> Prefix = 7; }
80 class DD { bits<4> Prefix = 8; }
81 class DE { bits<4> Prefix = 9; }
82 class DF { bits<4> Prefix = 10; }
83 class XD { bits<4> Prefix = 11; }
84 class XS { bits<4> Prefix = 12; }
85 class T8 { bits<4> Prefix = 13; }
86 class TA { bits<4> Prefix = 14; }
87 class TF { bits<4> Prefix = 15; }
89 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
92 let Namespace = "X86";
94 bits<8> Opcode = opcod;
96 bits<6> FormBits = Form.Value;
98 bits<3> ImmTypeBits = ImmT.Value;
100 dag OutOperandList = outs;
101 dag InOperandList = ins;
102 string AsmString = AsmStr;
105 // Attributes specific to X86 instructions...
107 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
108 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
110 bits<4> Prefix = 0; // Which prefix byte does this inst have?
111 bit hasREX_WPrefix = 0; // Does this inst requires the REX.W prefix?
112 FPFormat FPForm; // What flavor of FP instruction is this?
113 bits<3> FPFormBits = 0;
114 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
115 bits<2> SegOvrBits = 0; // Segment override prefix.
118 class I<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern>
119 : X86Inst<o, f, NoImm, outs, ins, asm> {
120 let Pattern = pattern;
123 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
125 : X86Inst<o, f, Imm8 , outs, ins, asm> {
126 let Pattern = pattern;
129 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
131 : X86Inst<o, f, Imm16, outs, ins, asm> {
132 let Pattern = pattern;
135 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
137 : X86Inst<o, f, Imm32, outs, ins, asm> {
138 let Pattern = pattern;
142 // FPStack Instruction Templates:
143 // FPI - Floating Point Instruction template.
144 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
145 : I<o, F, outs, ins, asm, []> {}
147 // FpI_ - Floating Point Psuedo Instruction template. Not Predicated.
148 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>
149 : X86Inst<0, Pseudo, NoImm, outs, ins, ""> {
150 let FPForm = fp; let FPFormBits = FPForm.Value;
151 let Pattern = pattern;
154 // Templates for instructions that use a 16- or 32-bit segmented address as
155 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
157 // Iseg16 - 16-bit segment selector, 16-bit offset
158 // Iseg32 - 16-bit segment selector, 32-bit offset
160 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
161 list<dag> pattern> : X86Inst<o, f, NoImm, outs, ins, asm> {
162 let Pattern = pattern;
166 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
167 list<dag> pattern> : X86Inst<o, f, NoImm, outs, ins, asm> {
168 let Pattern = pattern;
172 // SSE1 Instruction Templates:
174 // SSI - SSE1 instructions with XS prefix.
175 // PSI - SSE1 instructions with TB prefix.
176 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
178 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
179 : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
180 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
182 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
183 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
184 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasSSE1]>;
185 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
187 : Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasSSE1]>;
189 // SSE2 Instruction Templates:
191 // SDI - SSE2 instructions with XD prefix.
192 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
193 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
194 // PDI - SSE2 instructions with TB and OpSize prefixes.
195 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
197 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
198 : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
199 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
201 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
202 class SSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
204 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
205 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
206 : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
207 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
209 : Ii8<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
211 // SSE3 Instruction Templates:
213 // S3I - SSE3 instructions with TB and OpSize prefixes.
214 // S3SI - SSE3 instructions with XS prefix.
215 // S3DI - SSE3 instructions with XD prefix.
217 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
219 : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE3]>;
220 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
222 : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE3]>;
223 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
224 : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
227 // SSSE3 Instruction Templates:
229 // SS38I - SSSE3 instructions with T8 prefix.
230 // SS3AI - SSSE3 instructions with TA prefix.
232 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
233 // uses the MMX registers. We put those instructions here because they better
234 // fit into the SSSE3 instruction category rather than the MMX category.
236 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
238 : Ii8<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSSE3]>;
239 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
241 : Ii8<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSSE3]>;
243 // SSE4.1 Instruction Templates:
245 // SS48I - SSE 4.1 instructions with T8 prefix.
246 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
248 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
250 : I<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSE41]>;
251 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
253 : Ii8<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSE41]>;
255 // SSE4.2 Instruction Templates:
257 // SS428I - SSE 4.2 instructions with T8 prefix.
258 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
260 : I<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSE42]>;
262 // SS42FI - SSE 4.2 instructions with TF prefix.
263 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
265 : I<o, F, outs, ins, asm, pattern>, TF, Requires<[HasSSE42]>;
267 // SS42AI = SSE 4.2 instructions with TA prefix
268 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
270 : I<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSE42]>;
272 // X86-64 Instruction templates...
275 class RI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
276 : I<o, F, outs, ins, asm, pattern>, REX_W;
277 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
279 : Ii8<o, F, outs, ins, asm, pattern>, REX_W;
280 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
282 : Ii32<o, F, outs, ins, asm, pattern>, REX_W;
284 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
286 : X86Inst<o, f, Imm64, outs, ins, asm>, REX_W {
287 let Pattern = pattern;
291 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
293 : SSI<o, F, outs, ins, asm, pattern>, REX_W;
294 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
296 : SDI<o, F, outs, ins, asm, pattern>, REX_W;
297 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
299 : PDI<o, F, outs, ins, asm, pattern>, REX_W;
301 // MMX Instruction templates
304 // MMXI - MMX instructions with TB prefix.
305 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
306 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
307 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
308 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
309 // MMXID - MMX instructions with XD prefix.
310 // MMXIS - MMX instructions with XS prefix.
311 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
313 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
314 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
316 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX,In64BitMode]>;
317 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
319 : I<o, F, outs, ins, asm, pattern>, TB, REX_W, Requires<[HasMMX]>;
320 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
322 : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasMMX]>;
323 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
325 : Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
326 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
328 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX]>;
329 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
331 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>;