1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>; def RawFrmMemOffs : Format<7>;
25 def RawFrmSrc : Format<8>; def RawFrmDst : Format<9>;
26 def RawFrmDstSrc: Format<10>;
27 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
28 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
29 def MRM6r : Format<22>; def MRM7r : Format<23>;
30 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
31 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
32 def MRM6m : Format<30>; def MRM7m : Format<31>;
33 def MRM_C1 : Format<33>;
34 def MRM_C2 : Format<34>;
35 def MRM_C3 : Format<35>;
36 def MRM_C4 : Format<36>;
37 def MRM_C8 : Format<37>;
38 def MRM_C9 : Format<38>;
39 def MRM_CA : Format<39>;
40 def MRM_CB : Format<40>;
41 def MRM_E8 : Format<41>;
42 def MRM_F0 : Format<42>;
43 def RawFrmImm8 : Format<43>;
44 def RawFrmImm16 : Format<44>;
45 def MRM_F8 : Format<45>;
46 def MRM_F9 : Format<46>;
47 def MRM_D0 : Format<47>;
48 def MRM_D1 : Format<48>;
49 def MRM_D4 : Format<49>;
50 def MRM_D5 : Format<50>;
51 def MRM_D6 : Format<51>;
52 def MRM_D8 : Format<52>;
53 def MRM_D9 : Format<53>;
54 def MRM_DA : Format<54>;
55 def MRM_DB : Format<55>;
56 def MRM_DC : Format<56>;
57 def MRM_DD : Format<57>;
58 def MRM_DE : Format<58>;
59 def MRM_DF : Format<59>;
61 // ImmType - This specifies the immediate type used by an instruction. This is
62 // part of the ad-hoc solution used to emit machine instruction encodings by our
63 // machine code emitter.
64 class ImmType<bits<3> val> {
67 def NoImm : ImmType<0>;
68 def Imm8 : ImmType<1>;
69 def Imm8PCRel : ImmType<2>;
70 def Imm16 : ImmType<3>;
71 def Imm16PCRel : ImmType<4>;
72 def Imm32 : ImmType<5>;
73 def Imm32PCRel : ImmType<6>;
74 def Imm64 : ImmType<7>;
76 // FPFormat - This specifies what form this FP instruction has. This is used by
77 // the Floating-Point stackifier pass.
78 class FPFormat<bits<3> val> {
81 def NotFP : FPFormat<0>;
82 def ZeroArgFP : FPFormat<1>;
83 def OneArgFP : FPFormat<2>;
84 def OneArgFPRW : FPFormat<3>;
85 def TwoArgFP : FPFormat<4>;
86 def CompareFP : FPFormat<5>;
87 def CondMovFP : FPFormat<6>;
88 def SpecialFP : FPFormat<7>;
90 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
91 // Keep in sync with tables in X86InstrInfo.cpp.
92 class Domain<bits<2> val> {
95 def GenericDomain : Domain<0>;
96 def SSEPackedSingle : Domain<1>;
97 def SSEPackedDouble : Domain<2>;
98 def SSEPackedInt : Domain<3>;
100 // Class specifying the vector form of the decompressed
101 // displacement of 8-bit.
102 class CD8VForm<bits<3> val> {
105 def CD8VF : CD8VForm<0>; // v := VL
106 def CD8VH : CD8VForm<1>; // v := VL/2
107 def CD8VQ : CD8VForm<2>; // v := VL/4
108 def CD8VO : CD8VForm<3>; // v := VL/8
109 def CD8VT1 : CD8VForm<4>; // v := 1
110 def CD8VT2 : CD8VForm<5>; // v := 2
111 def CD8VT4 : CD8VForm<6>; // v := 4
112 def CD8VT8 : CD8VForm<7>; // v := 8
114 // Prefix byte classes which are used to indicate to the ad-hoc machine code
115 // emitter that various prefix bytes are required.
116 class OpSize { bit hasOpSizePrefix = 1; }
117 class OpSize16 { bit hasOpSize16Prefix = 1; }
118 class AdSize { bit hasAdSizePrefix = 1; }
119 class REX_W { bit hasREX_WPrefix = 1; }
120 class LOCK { bit hasLockPrefix = 1; }
121 class TB { bits<5> Prefix = 1; }
122 class REP { bits<5> Prefix = 2; }
123 class D8 { bits<5> Prefix = 3; }
124 class D9 { bits<5> Prefix = 4; }
125 class DA { bits<5> Prefix = 5; }
126 class DB { bits<5> Prefix = 6; }
127 class DC { bits<5> Prefix = 7; }
128 class DD { bits<5> Prefix = 8; }
129 class DE { bits<5> Prefix = 9; }
130 class DF { bits<5> Prefix = 10; }
131 class XD { bits<5> Prefix = 11; }
132 class XS { bits<5> Prefix = 12; }
133 class T8 { bits<5> Prefix = 13; }
134 class TA { bits<5> Prefix = 14; }
135 class A6 { bits<5> Prefix = 15; }
136 class A7 { bits<5> Prefix = 16; }
137 class T8XD { bits<5> Prefix = 17; }
138 class T8XS { bits<5> Prefix = 18; }
139 class TAXD { bits<5> Prefix = 19; }
140 class XOP8 { bits<5> Prefix = 20; }
141 class XOP9 { bits<5> Prefix = 21; }
142 class XOPA { bits<5> Prefix = 22; }
143 class PD { bits<5> Prefix = 23; }
144 class T8PD { bits<5> Prefix = 24; }
145 class TAPD { bits<5> Prefix = 25; }
146 class VEX { bit hasVEXPrefix = 1; }
147 class VEX_W { bit hasVEX_WPrefix = 1; }
148 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
149 class VEX_4VOp3 : VEX { bit hasVEX_4VOp3Prefix = 1; }
150 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
151 class VEX_L { bit hasVEX_L = 1; }
152 class VEX_LIG { bit ignoresVEX_L = 1; }
153 class EVEX : VEX { bit hasEVEXPrefix = 1; }
154 class EVEX_4V : VEX_4V { bit hasEVEXPrefix = 1; }
155 class EVEX_K { bit hasEVEX_K = 1; }
156 class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; }
157 class EVEX_B { bit hasEVEX_B = 1; }
158 class EVEX_RC { bit hasEVEX_RC = 1; }
159 class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; }
160 class EVEX_CD8<int esize, CD8VForm form> {
161 bits<2> EVEX_CD8E = !if(!eq(esize, 8), 0b00,
162 !if(!eq(esize, 16), 0b01,
163 !if(!eq(esize, 32), 0b10,
164 !if(!eq(esize, 64), 0b11, ?))));
165 bits<3> EVEX_CD8V = form.Value;
167 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
168 class MemOp4 { bit hasMemOp4Prefix = 1; }
169 class XOP { bit hasXOP_Prefix = 1; }
170 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
173 Domain d = GenericDomain>
175 let Namespace = "X86";
177 bits<8> Opcode = opcod;
179 bits<6> FormBits = Form.Value;
182 dag OutOperandList = outs;
183 dag InOperandList = ins;
184 string AsmString = AsmStr;
186 // If this is a pseudo instruction, mark it isCodeGenOnly.
187 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
189 let Itinerary = itin;
192 // Attributes specific to X86 instructions...
194 bit ForceDisassemble = 0; // Force instruction to disassemble even though it's
195 // isCodeGenonly. Needed to hide an ambiguous
196 // AsmString from the parser, but still disassemble.
198 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
199 bit hasOpSize16Prefix = 0;// Does this inst have a 0x66 prefix in 16-bit mode?
200 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
202 bits<5> Prefix = 0; // Which prefix byte does this inst have?
203 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
204 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
205 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
206 Domain ExeDomain = d;
207 bit hasVEXPrefix = 0; // Does this inst require a VEX prefix?
208 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
209 bit hasVEX_4VPrefix = 0; // Does this inst require the VEX.VVVV field?
210 bit hasVEX_4VOp3Prefix = 0; // Does this inst require the VEX.VVVV field to
211 // encode the third operand?
212 bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register
213 // to be encoded in a immediate field?
214 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
215 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
216 bit hasEVEXPrefix = 0; // Does this inst require EVEX form?
217 bit hasEVEX_K = 0; // Does this inst require masking?
218 bit hasEVEX_Z = 0; // Does this inst set the EVEX_Z field?
219 bit hasEVEX_L2 = 0; // Does this inst set the EVEX_L2 field?
220 bit hasEVEX_B = 0; // Does this inst set the EVEX_B field?
221 bits<2> EVEX_CD8E = 0; // Compressed disp8 form - element-size.
222 bits<3> EVEX_CD8V = 0; // Compressed disp8 form - vector-width.
223 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
224 bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands
225 bit hasXOP_Prefix = 0; // Does this inst require an XOP prefix?
226 bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction.
228 // TSFlags layout should be kept in sync with X86InstrInfo.h.
229 let TSFlags{5-0} = FormBits;
230 let TSFlags{6} = hasOpSizePrefix;
231 let TSFlags{7} = hasOpSize16Prefix;
232 let TSFlags{8} = hasAdSizePrefix;
233 let TSFlags{13-9} = Prefix;
234 let TSFlags{14} = hasREX_WPrefix;
235 let TSFlags{17-15} = ImmT.Value;
236 let TSFlags{20-18} = FPForm.Value;
237 let TSFlags{21} = hasLockPrefix;
238 let TSFlags{23-22} = ExeDomain.Value;
239 let TSFlags{31-24} = Opcode;
240 let TSFlags{32} = hasVEXPrefix;
241 let TSFlags{33} = hasVEX_WPrefix;
242 let TSFlags{34} = hasVEX_4VPrefix;
243 let TSFlags{35} = hasVEX_4VOp3Prefix;
244 let TSFlags{36} = hasVEX_i8ImmReg;
245 let TSFlags{37} = hasVEX_L;
246 let TSFlags{38} = ignoresVEX_L;
247 let TSFlags{39} = hasEVEXPrefix;
248 let TSFlags{40} = hasEVEX_K;
249 let TSFlags{41} = hasEVEX_Z;
250 let TSFlags{42} = hasEVEX_L2;
251 let TSFlags{43} = hasEVEX_B;
252 let TSFlags{45-44} = EVEX_CD8E;
253 let TSFlags{48-46} = EVEX_CD8V;
254 let TSFlags{49} = has3DNow0F0FOpcode;
255 let TSFlags{50} = hasMemOp4Prefix;
256 let TSFlags{51} = hasXOP_Prefix;
257 let TSFlags{52} = hasEVEX_RC;
260 class PseudoI<dag oops, dag iops, list<dag> pattern>
261 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> {
262 let Pattern = pattern;
265 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
266 list<dag> pattern, InstrItinClass itin = NoItinerary,
267 Domain d = GenericDomain>
268 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
269 let Pattern = pattern;
272 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
273 list<dag> pattern, InstrItinClass itin = NoItinerary,
274 Domain d = GenericDomain>
275 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
276 let Pattern = pattern;
279 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
280 list<dag> pattern, InstrItinClass itin = NoItinerary>
281 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
282 let Pattern = pattern;
285 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
286 list<dag> pattern, InstrItinClass itin = NoItinerary>
287 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
288 let Pattern = pattern;
291 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
292 list<dag> pattern, InstrItinClass itin = NoItinerary>
293 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
294 let Pattern = pattern;
298 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
299 list<dag> pattern, InstrItinClass itin = NoItinerary>
300 : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> {
301 let Pattern = pattern;
305 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
306 list<dag> pattern, InstrItinClass itin = NoItinerary>
307 : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> {
308 let Pattern = pattern;
312 // FPStack Instruction Templates:
313 // FPI - Floating Point Instruction template.
314 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm,
315 InstrItinClass itin = NoItinerary>
316 : I<o, F, outs, ins, asm, [], itin> {}
318 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
319 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
320 InstrItinClass itin = NoItinerary>
321 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
323 let Pattern = pattern;
326 // Templates for instructions that use a 16- or 32-bit segmented address as
327 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
329 // Iseg16 - 16-bit segment selector, 16-bit offset
330 // Iseg32 - 16-bit segment selector, 32-bit offset
332 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
333 list<dag> pattern, InstrItinClass itin = NoItinerary>
334 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
335 let Pattern = pattern;
339 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
340 list<dag> pattern, InstrItinClass itin = NoItinerary>
341 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
342 let Pattern = pattern;
350 // SI - SSE 1 & 2 scalar instructions
351 class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
352 list<dag> pattern, InstrItinClass itin = NoItinerary>
353 : I<o, F, outs, ins, asm, pattern, itin> {
354 let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
355 !if(hasVEXPrefix /* VEX */, [UseAVX],
356 !if(!eq(Prefix, __xs.Prefix), [UseSSE1],
357 !if(!eq(Prefix, __xd.Prefix), [UseSSE2],
358 !if(!eq(Prefix, __pd.Prefix), [UseSSE2], [UseSSE1])))));
360 // AVX instructions have a 'v' prefix in the mnemonic
361 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
364 // SIi8 - SSE 1 & 2 scalar instructions
365 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
366 list<dag> pattern, InstrItinClass itin = NoItinerary>
367 : Ii8<o, F, outs, ins, asm, pattern, itin> {
368 let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
369 !if(hasVEXPrefix /* VEX */, [UseAVX],
370 !if(!eq(Prefix, __xs.Prefix), [UseSSE1], [UseSSE2])));
372 // AVX instructions have a 'v' prefix in the mnemonic
373 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
376 // PI - SSE 1 & 2 packed instructions
377 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
378 InstrItinClass itin, Domain d>
379 : I<o, F, outs, ins, asm, pattern, itin, d> {
380 let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
381 !if(hasVEXPrefix /* VEX */, [HasAVX],
382 !if(!eq(Prefix, __pd.Prefix), [UseSSE2], [UseSSE1])));
384 // AVX instructions have a 'v' prefix in the mnemonic
385 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
388 // MMXPI - SSE 1 & 2 packed instructions with MMX operands
389 class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
390 InstrItinClass itin, Domain d>
391 : I<o, F, outs, ins, asm, pattern, itin, d> {
392 let Predicates = !if(!eq(Prefix, __pd.Prefix), [HasSSE2], [HasSSE1]);
395 // PIi8 - SSE 1 & 2 packed instructions with immediate
396 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
397 list<dag> pattern, InstrItinClass itin, Domain d>
398 : Ii8<o, F, outs, ins, asm, pattern, itin, d> {
399 let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
400 !if(hasVEXPrefix /* VEX */, [HasAVX],
401 !if(!eq(Prefix, __pd.Prefix), [UseSSE2], [UseSSE1])));
403 // AVX instructions have a 'v' prefix in the mnemonic
404 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
407 // SSE1 Instruction Templates:
409 // SSI - SSE1 instructions with XS prefix.
410 // PSI - SSE1 instructions with TB prefix.
411 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
412 // VSSI - SSE1 instructions with XS prefix in AVX form.
413 // VPSI - SSE1 instructions with TB prefix in AVX form, packed single.
415 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm,
416 list<dag> pattern, InstrItinClass itin = NoItinerary>
417 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
418 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
419 list<dag> pattern, InstrItinClass itin = NoItinerary>
420 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
421 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
422 list<dag> pattern, InstrItinClass itin = NoItinerary>
423 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
425 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
426 list<dag> pattern, InstrItinClass itin = NoItinerary>
427 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
429 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
430 list<dag> pattern, InstrItinClass itin = NoItinerary>
431 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
433 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
434 list<dag> pattern, InstrItinClass itin = NoItinerary>
435 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, TB,
438 // SSE2 Instruction Templates:
440 // SDI - SSE2 instructions with XD prefix.
441 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
442 // S2SI - SSE2 instructions with XS prefix.
443 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
444 // PDI - SSE2 instructions with PD prefix, packed double domain.
445 // PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix.
446 // VSDI - SSE2 scalar instructions with XD prefix in AVX form.
447 // VPDI - SSE2 vector instructions with PD prefix in AVX form,
448 // packed double domain.
449 // VS2I - SSE2 scalar instructions with PD prefix in AVX form.
450 // S2I - SSE2 scalar instructions with PD prefix.
451 // MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as
453 // MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as
456 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
457 list<dag> pattern, InstrItinClass itin = NoItinerary>
458 : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
459 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
460 list<dag> pattern, InstrItinClass itin = NoItinerary>
461 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
462 class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
463 list<dag> pattern, InstrItinClass itin = NoItinerary>
464 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE2]>;
465 class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
466 list<dag> pattern, InstrItinClass itin = NoItinerary>
467 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>;
468 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
469 list<dag> pattern, InstrItinClass itin = NoItinerary>
470 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
472 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
473 list<dag> pattern, InstrItinClass itin = NoItinerary>
474 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
476 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
477 list<dag> pattern, InstrItinClass itin = NoItinerary>
478 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
480 class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
481 list<dag> pattern, InstrItinClass itin = NoItinerary>
482 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
484 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
485 list<dag> pattern, InstrItinClass itin = NoItinerary>
486 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>,
487 PD, Requires<[HasAVX]>;
488 class VS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
489 list<dag> pattern, InstrItinClass itin = NoItinerary>
490 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, PD,
492 class S2I<bits<8> o, Format F, dag outs, dag ins, string asm,
493 list<dag> pattern, InstrItinClass itin = NoItinerary>
494 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[UseSSE2]>;
495 class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
496 list<dag> pattern, InstrItinClass itin = NoItinerary>
497 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
498 class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
499 list<dag> pattern, InstrItinClass itin = NoItinerary>
500 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
502 // SSE3 Instruction Templates:
504 // S3I - SSE3 instructions with PD prefixes.
505 // S3SI - SSE3 instructions with XS prefix.
506 // S3DI - SSE3 instructions with XD prefix.
508 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
509 list<dag> pattern, InstrItinClass itin = NoItinerary>
510 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS,
512 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
513 list<dag> pattern, InstrItinClass itin = NoItinerary>
514 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD,
516 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
517 list<dag> pattern, InstrItinClass itin = NoItinerary>
518 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
522 // SSSE3 Instruction Templates:
524 // SS38I - SSSE3 instructions with T8 prefix.
525 // SS3AI - SSSE3 instructions with TA prefix.
526 // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands.
527 // MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands.
529 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
530 // uses the MMX registers. The 64-bit versions are grouped with the MMX
531 // classes. They need to be enabled even if AVX is enabled.
533 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
534 list<dag> pattern, InstrItinClass itin = NoItinerary>
535 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
536 Requires<[UseSSSE3]>;
537 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
538 list<dag> pattern, InstrItinClass itin = NoItinerary>
539 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
540 Requires<[UseSSSE3]>;
541 class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
542 list<dag> pattern, InstrItinClass itin = NoItinerary>
543 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
544 Requires<[HasSSSE3]>;
545 class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
546 list<dag> pattern, InstrItinClass itin = NoItinerary>
547 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
548 Requires<[HasSSSE3]>;
550 // SSE4.1 Instruction Templates:
552 // SS48I - SSE 4.1 instructions with T8 prefix.
553 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
555 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
556 list<dag> pattern, InstrItinClass itin = NoItinerary>
557 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
558 Requires<[UseSSE41]>;
559 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
560 list<dag> pattern, InstrItinClass itin = NoItinerary>
561 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
562 Requires<[UseSSE41]>;
564 // SSE4.2 Instruction Templates:
566 // SS428I - SSE 4.2 instructions with T8 prefix.
567 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
568 list<dag> pattern, InstrItinClass itin = NoItinerary>
569 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
570 Requires<[UseSSE42]>;
572 // SS42FI - SSE 4.2 instructions with T8XD prefix.
573 // NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns.
574 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
575 list<dag> pattern, InstrItinClass itin = NoItinerary>
576 : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>;
578 // SS42AI = SSE 4.2 instructions with TA prefix
579 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
580 list<dag> pattern, InstrItinClass itin = NoItinerary>
581 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
582 Requires<[UseSSE42]>;
584 // AVX Instruction Templates:
585 // Instructions introduced in AVX (no SSE equivalent forms)
587 // AVX8I - AVX instructions with T8PD prefix.
588 // AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8.
589 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
590 list<dag> pattern, InstrItinClass itin = NoItinerary>
591 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
593 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
594 list<dag> pattern, InstrItinClass itin = NoItinerary>
595 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
598 // AVX2 Instruction Templates:
599 // Instructions introduced in AVX2 (no SSE equivalent forms)
601 // AVX28I - AVX2 instructions with T8PD prefix.
602 // AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8.
603 class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
604 list<dag> pattern, InstrItinClass itin = NoItinerary>
605 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
607 class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
608 list<dag> pattern, InstrItinClass itin = NoItinerary>
609 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
613 // AVX-512 Instruction Templates:
614 // Instructions introduced in AVX-512 (no SSE equivalent forms)
616 // AVX5128I - AVX-512 instructions with T8PD prefix.
617 // AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8.
618 // AVX512PDI - AVX-512 instructions with PD, double packed.
619 // AVX512PSI - AVX-512 instructions with TB, single packed.
620 // AVX512XS8I - AVX-512 instructions with T8 and XS prefixes.
621 // AVX512XSI - AVX-512 instructions with XS prefix, generic domain.
622 // AVX512BI - AVX-512 instructions with PD, int packed domain.
623 // AVX512SI - AVX-512 scalar instructions with PD prefix.
625 class AVX5128I<bits<8> o, Format F, dag outs, dag ins, string asm,
626 list<dag> pattern, InstrItinClass itin = NoItinerary>
627 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
628 Requires<[HasAVX512]>;
629 class AVX512XS8I<bits<8> o, Format F, dag outs, dag ins, string asm,
630 list<dag> pattern, InstrItinClass itin = NoItinerary>
631 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8XS,
632 Requires<[HasAVX512]>;
633 class AVX512XSI<bits<8> o, Format F, dag outs, dag ins, string asm,
634 list<dag> pattern, InstrItinClass itin = NoItinerary>
635 : I<o, F, outs, ins, asm, pattern, itin>, XS,
636 Requires<[HasAVX512]>;
637 class AVX512XDI<bits<8> o, Format F, dag outs, dag ins, string asm,
638 list<dag> pattern, InstrItinClass itin = NoItinerary>
639 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, XD,
640 Requires<[HasAVX512]>;
641 class AVX512BI<bits<8> o, Format F, dag outs, dag ins, string asm,
642 list<dag> pattern, InstrItinClass itin = NoItinerary>
643 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
644 Requires<[HasAVX512]>;
645 class AVX512BIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
646 list<dag> pattern, InstrItinClass itin = NoItinerary>
647 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
648 Requires<[HasAVX512]>;
649 class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
650 list<dag> pattern, InstrItinClass itin = NoItinerary>
651 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
652 Requires<[HasAVX512]>;
653 class AVX512Ii8<bits<8> o, Format F, dag outs, dag ins, string asm,
654 list<dag> pattern, InstrItinClass itin = NoItinerary>
655 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB,
656 Requires<[HasAVX512]>;
657 class AVX512PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
658 list<dag> pattern, InstrItinClass itin = NoItinerary>
659 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
660 Requires<[HasAVX512]>;
661 class AVX512PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
662 list<dag> pattern, InstrItinClass itin = NoItinerary>
663 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
664 Requires<[HasAVX512]>;
665 class AVX512PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
666 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
667 : Ii8<o, F, outs, ins, asm, pattern, itin, d>, TB, Requires<[HasAVX512]>;
668 class AVX512PI<bits<8> o, Format F, dag outs, dag ins, string asm,
669 list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
670 : I<o, F, outs, ins, asm, pattern, itin, d>, TB, Requires<[HasAVX512]>;
671 class AVX512FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
672 list<dag>pattern, InstrItinClass itin = NoItinerary>
673 : I<o, F, outs, ins, asm, pattern, itin>, T8PD,
674 EVEX_4V, Requires<[HasAVX512]>;
676 // AES Instruction Templates:
679 // These use the same encoding as the SSE4.2 T8 and TA encodings.
680 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
681 list<dag>pattern, InstrItinClass itin = IIC_AES>
682 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
685 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
686 list<dag> pattern, InstrItinClass itin = NoItinerary>
687 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
690 // PCLMUL Instruction Templates
691 class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
692 list<dag>pattern, InstrItinClass itin = NoItinerary>
693 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
694 Requires<[HasPCLMUL]>;
696 class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
697 list<dag>pattern, InstrItinClass itin = NoItinerary>
698 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
699 VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
701 // FMA3 Instruction Templates
702 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
703 list<dag>pattern, InstrItinClass itin = NoItinerary>
704 : I<o, F, outs, ins, asm, pattern, itin>, T8PD,
705 VEX_4V, FMASC, Requires<[HasFMA]>;
707 // FMA4 Instruction Templates
708 class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
709 list<dag>pattern, InstrItinClass itin = NoItinerary>
710 : Ii8<o, F, outs, ins, asm, pattern, itin>, TAPD,
711 VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>;
713 // XOP 2, 3 and 4 Operand Instruction Template
714 class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
715 list<dag> pattern, InstrItinClass itin = NoItinerary>
716 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
717 XOP, XOP9, Requires<[HasXOP]>;
719 // XOP 2, 3 and 4 Operand Instruction Templates with imm byte
720 class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
721 list<dag> pattern, InstrItinClass itin = NoItinerary>
722 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
723 XOP, XOP8, Requires<[HasXOP]>;
725 // XOP 5 operand instruction (VEX encoding!)
726 class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
727 list<dag>pattern, InstrItinClass itin = NoItinerary>
728 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
729 VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
731 // X86-64 Instruction templates...
734 class RI<bits<8> o, Format F, dag outs, dag ins, string asm,
735 list<dag> pattern, InstrItinClass itin = NoItinerary>
736 : I<o, F, outs, ins, asm, pattern, itin>, REX_W;
737 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
738 list<dag> pattern, InstrItinClass itin = NoItinerary>
739 : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W;
740 class RIi16 <bits<8> o, Format F, dag outs, dag ins, string asm,
741 list<dag> pattern, InstrItinClass itin = NoItinerary>
742 : Ii16<o, F, outs, ins, asm, pattern, itin>, REX_W;
743 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
744 list<dag> pattern, InstrItinClass itin = NoItinerary>
745 : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W;
747 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
748 list<dag> pattern, InstrItinClass itin = NoItinerary>
749 : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W {
750 let Pattern = pattern;
754 class RIi64_NOREX<bits<8> o, Format f, dag outs, dag ins, string asm,
755 list<dag> pattern, InstrItinClass itin = NoItinerary>
756 : X86Inst<o, f, Imm64, outs, ins, asm, itin> {
757 let Pattern = pattern;
761 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
762 list<dag> pattern, InstrItinClass itin = NoItinerary>
763 : SSI<o, F, outs, ins, asm, pattern, itin>, REX_W;
764 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
765 list<dag> pattern, InstrItinClass itin = NoItinerary>
766 : SDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
767 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
768 list<dag> pattern, InstrItinClass itin = NoItinerary>
769 : PDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
770 class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
771 list<dag> pattern, InstrItinClass itin = NoItinerary>
772 : VPDI<o, F, outs, ins, asm, pattern, itin>, VEX_W;
773 class RS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
774 list<dag> pattern, InstrItinClass itin = NoItinerary>
775 : S2I<o, F, outs, ins, asm, pattern, itin>, REX_W;
776 class VRS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
777 list<dag> pattern, InstrItinClass itin = NoItinerary>
778 : VS2I<o, F, outs, ins, asm, pattern, itin>, VEX_W;
780 // MMX Instruction templates
783 // MMXI - MMX instructions with TB prefix.
784 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
785 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
786 // MMX2I - MMX / SSE2 instructions with PD prefix.
787 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
788 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
789 // MMXID - MMX instructions with XD prefix.
790 // MMXIS - MMX instructions with XS prefix.
791 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
792 list<dag> pattern, InstrItinClass itin = NoItinerary>
793 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
794 class MMXI32<bits<8> o, Format F, dag outs, dag ins, string asm,
795 list<dag> pattern, InstrItinClass itin = NoItinerary>
796 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,Not64BitMode]>;
797 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
798 list<dag> pattern, InstrItinClass itin = NoItinerary>
799 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,In64BitMode]>;
800 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
801 list<dag> pattern, InstrItinClass itin = NoItinerary>
802 : I<o, F, outs, ins, asm, pattern, itin>, TB, REX_W, Requires<[HasMMX]>;
803 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
804 list<dag> pattern, InstrItinClass itin = NoItinerary>
805 : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[HasMMX]>;
806 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
807 list<dag> pattern, InstrItinClass itin = NoItinerary>
808 : Ii8<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
809 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
810 list<dag> pattern, InstrItinClass itin = NoItinerary>
811 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>;
812 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
813 list<dag> pattern, InstrItinClass itin = NoItinerary>
814 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>;