1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>;
25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
27 def MRM6r : Format<22>; def MRM7r : Format<23>;
28 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
30 def MRM6m : Format<30>; def MRM7m : Format<31>;
31 def MRMInitReg : Format<32>;
32 def MRM_C1 : Format<33>;
33 def MRM_C2 : Format<34>;
34 def MRM_C3 : Format<35>;
35 def MRM_C4 : Format<36>;
36 def MRM_C8 : Format<37>;
37 def MRM_C9 : Format<38>;
38 def MRM_E8 : Format<39>;
39 def MRM_F0 : Format<40>;
40 def MRM_F8 : Format<41>;
41 def MRM_F9 : Format<42>;
42 def RawFrmImm8 : Format<43>;
43 def RawFrmImm16 : Format<44>;
44 def MRM_D0 : Format<45>;
45 def MRM_D1 : Format<46>;
46 def MRM_D8 : Format<47>;
47 def MRM_D9 : Format<48>;
48 def MRM_DA : Format<49>;
49 def MRM_DB : Format<50>;
50 def MRM_DC : Format<51>;
51 def MRM_DD : Format<52>;
52 def MRM_DE : Format<53>;
53 def MRM_DF : Format<54>;
55 // ImmType - This specifies the immediate type used by an instruction. This is
56 // part of the ad-hoc solution used to emit machine instruction encodings by our
57 // machine code emitter.
58 class ImmType<bits<3> val> {
61 def NoImm : ImmType<0>;
62 def Imm8 : ImmType<1>;
63 def Imm8PCRel : ImmType<2>;
64 def Imm16 : ImmType<3>;
65 def Imm16PCRel : ImmType<4>;
66 def Imm32 : ImmType<5>;
67 def Imm32PCRel : ImmType<6>;
68 def Imm64 : ImmType<7>;
70 // FPFormat - This specifies what form this FP instruction has. This is used by
71 // the Floating-Point stackifier pass.
72 class FPFormat<bits<3> val> {
75 def NotFP : FPFormat<0>;
76 def ZeroArgFP : FPFormat<1>;
77 def OneArgFP : FPFormat<2>;
78 def OneArgFPRW : FPFormat<3>;
79 def TwoArgFP : FPFormat<4>;
80 def CompareFP : FPFormat<5>;
81 def CondMovFP : FPFormat<6>;
82 def SpecialFP : FPFormat<7>;
84 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
85 // Keep in sync with tables in X86InstrInfo.cpp.
86 class Domain<bits<2> val> {
89 def GenericDomain : Domain<0>;
90 def SSEPackedSingle : Domain<1>;
91 def SSEPackedDouble : Domain<2>;
92 def SSEPackedInt : Domain<3>;
94 // Prefix byte classes which are used to indicate to the ad-hoc machine code
95 // emitter that various prefix bytes are required.
96 class OpSize { bit hasOpSizePrefix = 1; }
97 class AdSize { bit hasAdSizePrefix = 1; }
98 class REX_W { bit hasREX_WPrefix = 1; }
99 class LOCK { bit hasLockPrefix = 1; }
100 class SegFS { bits<2> SegOvrBits = 1; }
101 class SegGS { bits<2> SegOvrBits = 2; }
102 class TB { bits<5> Prefix = 1; }
103 class REP { bits<5> Prefix = 2; }
104 class D8 { bits<5> Prefix = 3; }
105 class D9 { bits<5> Prefix = 4; }
106 class DA { bits<5> Prefix = 5; }
107 class DB { bits<5> Prefix = 6; }
108 class DC { bits<5> Prefix = 7; }
109 class DD { bits<5> Prefix = 8; }
110 class DE { bits<5> Prefix = 9; }
111 class DF { bits<5> Prefix = 10; }
112 class XD { bits<5> Prefix = 11; }
113 class XS { bits<5> Prefix = 12; }
114 class T8 { bits<5> Prefix = 13; }
115 class TA { bits<5> Prefix = 14; }
116 class A6 { bits<5> Prefix = 15; }
117 class A7 { bits<5> Prefix = 16; }
118 class T8XD { bits<5> Prefix = 17; }
119 class T8XS { bits<5> Prefix = 18; }
120 class TAXD { bits<5> Prefix = 19; }
121 class XOP8 { bits<5> Prefix = 20; }
122 class XOP9 { bits<5> Prefix = 21; }
123 class VEX { bit hasVEXPrefix = 1; }
124 class VEX_W { bit hasVEX_WPrefix = 1; }
125 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
126 class VEX_4VOp3 : VEX { bit hasVEX_4VOp3Prefix = 1; }
127 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
128 class VEX_L { bit hasVEX_L = 1; }
129 class VEX_LIG { bit ignoresVEX_L = 1; }
130 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
131 class MemOp4 { bit hasMemOp4Prefix = 1; }
132 class XOP { bit hasXOP_Prefix = 1; }
133 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
136 Domain d = GenericDomain>
138 let Namespace = "X86";
140 bits<8> Opcode = opcod;
142 bits<6> FormBits = Form.Value;
145 dag OutOperandList = outs;
146 dag InOperandList = ins;
147 string AsmString = AsmStr;
149 // If this is a pseudo instruction, mark it isCodeGenOnly.
150 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
152 let Itinerary = itin;
155 // Attributes specific to X86 instructions...
157 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
158 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
160 bits<5> Prefix = 0; // Which prefix byte does this inst have?
161 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
162 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
163 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
164 bits<2> SegOvrBits = 0; // Segment override prefix.
165 Domain ExeDomain = d;
166 bit hasVEXPrefix = 0; // Does this inst require a VEX prefix?
167 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
168 bit hasVEX_4VPrefix = 0; // Does this inst require the VEX.VVVV field?
169 bit hasVEX_4VOp3Prefix = 0; // Does this inst require the VEX.VVVV field to
170 // encode the third operand?
171 bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register
172 // to be encoded in a immediate field?
173 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
174 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
175 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
176 bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands
177 bit hasXOP_Prefix = 0; // Does this inst require an XOP prefix?
179 // TSFlags layout should be kept in sync with X86InstrInfo.h.
180 let TSFlags{5-0} = FormBits;
181 let TSFlags{6} = hasOpSizePrefix;
182 let TSFlags{7} = hasAdSizePrefix;
183 let TSFlags{12-8} = Prefix;
184 let TSFlags{13} = hasREX_WPrefix;
185 let TSFlags{16-14} = ImmT.Value;
186 let TSFlags{19-17} = FPForm.Value;
187 let TSFlags{20} = hasLockPrefix;
188 let TSFlags{22-21} = SegOvrBits;
189 let TSFlags{24-23} = ExeDomain.Value;
190 let TSFlags{32-25} = Opcode;
191 let TSFlags{33} = hasVEXPrefix;
192 let TSFlags{34} = hasVEX_WPrefix;
193 let TSFlags{35} = hasVEX_4VPrefix;
194 let TSFlags{36} = hasVEX_4VOp3Prefix;
195 let TSFlags{37} = hasVEX_i8ImmReg;
196 let TSFlags{38} = hasVEX_L;
197 let TSFlags{39} = ignoresVEX_L;
198 let TSFlags{40} = has3DNow0F0FOpcode;
199 let TSFlags{41} = hasMemOp4Prefix;
200 let TSFlags{42} = hasXOP_Prefix;
203 class PseudoI<dag oops, dag iops, list<dag> pattern>
204 : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> {
205 let Pattern = pattern;
208 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
209 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT,
210 Domain d = GenericDomain>
211 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
212 let Pattern = pattern;
215 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
216 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT,
217 Domain d = GenericDomain>
218 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
219 let Pattern = pattern;
222 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
223 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
224 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
225 let Pattern = pattern;
228 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
229 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
230 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
231 let Pattern = pattern;
234 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
235 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
236 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
237 let Pattern = pattern;
241 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
242 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
243 : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> {
244 let Pattern = pattern;
248 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
249 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
250 : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> {
251 let Pattern = pattern;
255 // FPStack Instruction Templates:
256 // FPI - Floating Point Instruction template.
257 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
258 : I<o, F, outs, ins, asm, []> {}
260 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
261 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
262 InstrItinClass itin = IIC_DEFAULT>
263 : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
265 let Pattern = pattern;
268 // Templates for instructions that use a 16- or 32-bit segmented address as
269 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
271 // Iseg16 - 16-bit segment selector, 16-bit offset
272 // Iseg32 - 16-bit segment selector, 32-bit offset
274 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
275 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
276 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
277 let Pattern = pattern;
281 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
282 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
283 : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
284 let Pattern = pattern;
288 // SI - SSE 1 & 2 scalar instructions
289 class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
290 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
291 : I<o, F, outs, ins, asm, pattern, itin> {
292 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
293 !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
295 // AVX instructions have a 'v' prefix in the mnemonic
296 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
299 // SIi8 - SSE 1 & 2 scalar instructions
300 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
301 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
302 : Ii8<o, F, outs, ins, asm, pattern, itin> {
303 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
304 !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
306 // AVX instructions have a 'v' prefix in the mnemonic
307 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
310 // PI - SSE 1 & 2 packed instructions
311 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
312 InstrItinClass itin, Domain d>
313 : I<o, F, outs, ins, asm, pattern, itin, d> {
314 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
315 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
317 // AVX instructions have a 'v' prefix in the mnemonic
318 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
321 // PIi8 - SSE 1 & 2 packed instructions with immediate
322 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
323 list<dag> pattern, InstrItinClass itin, Domain d>
324 : Ii8<o, F, outs, ins, asm, pattern, itin, d> {
325 let Predicates = !if(hasVEX_4VPrefix /* VEX */, [HasAVX],
326 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
328 // AVX instructions have a 'v' prefix in the mnemonic
329 let AsmString = !if(hasVEX_4VPrefix, !strconcat("v", asm), asm);
332 // SSE1 Instruction Templates:
334 // SSI - SSE1 instructions with XS prefix.
335 // PSI - SSE1 instructions with TB prefix.
336 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
337 // VSSI - SSE1 instructions with XS prefix in AVX form.
338 // VPSI - SSE1 instructions with TB prefix in AVX form.
340 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm,
341 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
342 : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasSSE1]>;
343 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
344 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
345 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasSSE1]>;
346 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
347 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
348 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
350 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
351 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
352 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
354 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
355 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
356 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
358 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
359 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
360 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, TB,
363 // SSE2 Instruction Templates:
365 // SDI - SSE2 instructions with XD prefix.
366 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
367 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
368 // PDI - SSE2 instructions with TB and OpSize prefixes.
369 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
370 // VSDI - SSE2 instructions with XD prefix in AVX form.
371 // VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.
373 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
374 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
375 : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
376 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
377 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
378 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
379 class SSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
381 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
382 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
383 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
384 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
386 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
387 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
388 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
390 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
391 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
392 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
394 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
395 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
396 : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>, TB,
397 OpSize, Requires<[HasAVX]>;
399 // SSE3 Instruction Templates:
401 // S3I - SSE3 instructions with TB and OpSize prefixes.
402 // S3SI - SSE3 instructions with XS prefix.
403 // S3DI - SSE3 instructions with XD prefix.
405 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
406 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
407 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS,
409 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
410 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
411 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD,
413 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
414 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
415 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
419 // SSSE3 Instruction Templates:
421 // SS38I - SSSE3 instructions with T8 prefix.
422 // SS3AI - SSSE3 instructions with TA prefix.
424 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
425 // uses the MMX registers. The 64-bit versions are grouped with the MMX
426 // classes. They need to be enabled even if AVX is enabled.
428 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
429 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
430 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
431 Requires<[HasSSSE3]>;
432 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
433 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
434 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
435 Requires<[HasSSSE3]>;
437 // SSE4.1 Instruction Templates:
439 // SS48I - SSE 4.1 instructions with T8 prefix.
440 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
442 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
443 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
444 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
445 Requires<[HasSSE41]>;
446 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
447 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
448 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
449 Requires<[HasSSE41]>;
451 // SSE4.2 Instruction Templates:
453 // SS428I - SSE 4.2 instructions with T8 prefix.
454 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
455 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
456 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
457 Requires<[HasSSE42]>;
459 // SS42FI - SSE 4.2 instructions with T8XD prefix.
460 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
461 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
462 : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>;
464 // SS42AI = SSE 4.2 instructions with TA prefix
465 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
466 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
467 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
468 Requires<[HasSSE42]>;
470 // AVX Instruction Templates:
471 // Instructions introduced in AVX (no SSE equivalent forms)
473 // AVX8I - AVX instructions with T8 and OpSize prefix.
474 // AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8.
475 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
476 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
477 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
479 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
480 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
481 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
484 // AVX2 Instruction Templates:
485 // Instructions introduced in AVX2 (no SSE equivalent forms)
487 // AVX28I - AVX2 instructions with T8 and OpSize prefix.
488 // AVX2AIi8 - AVX2 instructions with TA, OpSize prefix and ImmT = Imm8.
489 class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
490 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
491 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
493 class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
494 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
495 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
498 // AES Instruction Templates:
501 // These use the same encoding as the SSE4.2 T8 and TA encodings.
502 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
503 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
504 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
505 Requires<[HasSSE2, HasAES]>;
507 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
508 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
509 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
510 Requires<[HasSSE2, HasAES]>;
512 // CLMUL Instruction Templates
513 class CLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
514 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
515 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
516 OpSize, Requires<[HasSSE2, HasCLMUL]>;
518 class AVXCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
519 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
520 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
521 OpSize, VEX_4V, Requires<[HasAVX, HasCLMUL]>;
523 // FMA3 Instruction Templates
524 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
525 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
526 : I<o, F, outs, ins, asm, pattern, itin>, T8,
527 OpSize, VEX_4V, Requires<[HasFMA3]>;
529 // FMA4 Instruction Templates
530 class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
531 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
532 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
533 OpSize, VEX_4V, VEX_I8IMM, Requires<[HasFMA4]>;
535 // XOP 2, 3 and 4 Operand Instruction Template
536 class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
537 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
538 : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
539 XOP, XOP9, Requires<[HasXOP]>;
541 // XOP 2, 3 and 4 Operand Instruction Templates with imm byte
542 class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
543 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
544 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
545 XOP, XOP8, Requires<[HasXOP]>;
547 // XOP 5 operand instruction (VEX encoding!)
548 class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
549 list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
550 : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
551 OpSize, VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
553 // X86-64 Instruction templates...
556 class RI<bits<8> o, Format F, dag outs, dag ins, string asm,
557 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
558 : I<o, F, outs, ins, asm, pattern, itin>, REX_W;
559 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
560 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
561 : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W;
562 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
563 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
564 : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W;
566 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
567 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
568 : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W {
569 let Pattern = pattern;
573 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
574 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
575 : SSI<o, F, outs, ins, asm, pattern, itin>, REX_W;
576 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
577 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
578 : SDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
579 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
580 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
581 : PDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
582 class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
583 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
584 : VPDI<o, F, outs, ins, asm, pattern, itin>, VEX_W;
586 // MMX Instruction templates
589 // MMXI - MMX instructions with TB prefix.
590 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
591 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
592 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
593 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
594 // MMXID - MMX instructions with XD prefix.
595 // MMXIS - MMX instructions with XS prefix.
596 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
597 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
598 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
599 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
600 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
601 : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,In64BitMode]>;
602 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
603 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
604 : I<o, F, outs, ins, asm, pattern, itin>, TB, REX_W, Requires<[HasMMX]>;
605 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
606 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
607 : I<o, F, outs, ins, asm, pattern, itin>, TB, OpSize, Requires<[HasMMX]>;
608 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
609 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
610 : Ii8<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
611 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
612 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
613 : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>;
614 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
615 list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
616 : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>;