1 //===- X86InstrFormats.td - X86 Instruction Formats --------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
21 def Pseudo : Format<0>; def RawFrm : Format<1>;
22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
23 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
24 def MRMSrcMem : Format<6>;
25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
27 def MRM6r : Format<22>; def MRM7r : Format<23>;
28 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
30 def MRM6m : Format<30>; def MRM7m : Format<31>;
31 def MRMInitReg : Format<32>;
32 def MRM_C1 : Format<33>;
33 def MRM_C2 : Format<34>;
34 def MRM_C3 : Format<35>;
35 def MRM_C4 : Format<36>;
36 def MRM_C8 : Format<37>;
37 def MRM_C9 : Format<38>;
38 def MRM_E8 : Format<39>;
39 def MRM_F0 : Format<40>;
40 def MRM_F8 : Format<41>;
41 def MRM_F9 : Format<42>;
42 def RawFrmImm8 : Format<43>;
43 def RawFrmImm16 : Format<44>;
44 def MRM_D0 : Format<45>;
45 def MRM_D1 : Format<46>;
47 // ImmType - This specifies the immediate type used by an instruction. This is
48 // part of the ad-hoc solution used to emit machine instruction encodings by our
49 // machine code emitter.
50 class ImmType<bits<3> val> {
53 def NoImm : ImmType<0>;
54 def Imm8 : ImmType<1>;
55 def Imm8PCRel : ImmType<2>;
56 def Imm16 : ImmType<3>;
57 def Imm16PCRel : ImmType<4>;
58 def Imm32 : ImmType<5>;
59 def Imm32PCRel : ImmType<6>;
60 def Imm64 : ImmType<7>;
62 // FPFormat - This specifies what form this FP instruction has. This is used by
63 // the Floating-Point stackifier pass.
64 class FPFormat<bits<3> val> {
67 def NotFP : FPFormat<0>;
68 def ZeroArgFP : FPFormat<1>;
69 def OneArgFP : FPFormat<2>;
70 def OneArgFPRW : FPFormat<3>;
71 def TwoArgFP : FPFormat<4>;
72 def CompareFP : FPFormat<5>;
73 def CondMovFP : FPFormat<6>;
74 def SpecialFP : FPFormat<7>;
76 // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
77 // Keep in sync with tables in X86InstrInfo.cpp.
78 class Domain<bits<2> val> {
81 def GenericDomain : Domain<0>;
82 def SSEPackedSingle : Domain<1>;
83 def SSEPackedDouble : Domain<2>;
84 def SSEPackedInt : Domain<3>;
86 // Prefix byte classes which are used to indicate to the ad-hoc machine code
87 // emitter that various prefix bytes are required.
88 class OpSize { bit hasOpSizePrefix = 1; }
89 class AdSize { bit hasAdSizePrefix = 1; }
90 class REX_W { bit hasREX_WPrefix = 1; }
91 class LOCK { bit hasLockPrefix = 1; }
92 class SegFS { bits<2> SegOvrBits = 1; }
93 class SegGS { bits<2> SegOvrBits = 2; }
94 class TB { bits<5> Prefix = 1; }
95 class REP { bits<5> Prefix = 2; }
96 class D8 { bits<5> Prefix = 3; }
97 class D9 { bits<5> Prefix = 4; }
98 class DA { bits<5> Prefix = 5; }
99 class DB { bits<5> Prefix = 6; }
100 class DC { bits<5> Prefix = 7; }
101 class DD { bits<5> Prefix = 8; }
102 class DE { bits<5> Prefix = 9; }
103 class DF { bits<5> Prefix = 10; }
104 class XD { bits<5> Prefix = 11; }
105 class XS { bits<5> Prefix = 12; }
106 class T8 { bits<5> Prefix = 13; }
107 class TA { bits<5> Prefix = 14; }
108 class A6 { bits<5> Prefix = 15; }
109 class A7 { bits<5> Prefix = 16; }
110 class T8XD { bits<5> Prefix = 17; }
111 class T8XS { bits<5> Prefix = 18; }
112 class VEX { bit hasVEXPrefix = 1; }
113 class VEX_W { bit hasVEX_WPrefix = 1; }
114 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
115 class VEX_4VOp3 : VEX { bit hasVEX_4VOp3Prefix = 1; }
116 class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
117 class VEX_L { bit hasVEX_L = 1; }
118 class VEX_LIG { bit ignoresVEX_L = 1; }
119 class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
121 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
122 string AsmStr, Domain d = GenericDomain>
124 let Namespace = "X86";
126 bits<8> Opcode = opcod;
128 bits<6> FormBits = Form.Value;
131 dag OutOperandList = outs;
132 dag InOperandList = ins;
133 string AsmString = AsmStr;
135 // If this is a pseudo instruction, mark it isCodeGenOnly.
136 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
139 // Attributes specific to X86 instructions...
141 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
142 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
144 bits<5> Prefix = 0; // Which prefix byte does this inst have?
145 bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
146 FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
147 bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
148 bits<2> SegOvrBits = 0; // Segment override prefix.
149 Domain ExeDomain = d;
150 bit hasVEXPrefix = 0; // Does this inst require a VEX prefix?
151 bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
152 bit hasVEX_4VPrefix = 0; // Does this inst require the VEX.VVVV field?
153 bit hasVEX_4VOp3Prefix = 0; // Does this inst require the VEX.VVVV field to
154 // encode the third operand?
155 bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register
156 // to be encoded in a immediate field?
157 bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
158 bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
159 bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
161 // TSFlags layout should be kept in sync with X86InstrInfo.h.
162 let TSFlags{5-0} = FormBits;
163 let TSFlags{6} = hasOpSizePrefix;
164 let TSFlags{7} = hasAdSizePrefix;
165 let TSFlags{12-8} = Prefix;
166 let TSFlags{13} = hasREX_WPrefix;
167 let TSFlags{16-14} = ImmT.Value;
168 let TSFlags{19-17} = FPForm.Value;
169 let TSFlags{20} = hasLockPrefix;
170 let TSFlags{22-21} = SegOvrBits;
171 let TSFlags{24-23} = ExeDomain.Value;
172 let TSFlags{32-25} = Opcode;
173 let TSFlags{33} = hasVEXPrefix;
174 let TSFlags{34} = hasVEX_WPrefix;
175 let TSFlags{35} = hasVEX_4VPrefix;
176 let TSFlags{36} = hasVEX_4VOp3Prefix;
177 let TSFlags{37} = hasVEX_i8ImmReg;
178 let TSFlags{38} = hasVEX_L;
179 let TSFlags{39} = ignoresVEX_L;
180 let TSFlags{40} = has3DNow0F0FOpcode;
183 class PseudoI<dag oops, dag iops, list<dag> pattern>
184 : X86Inst<0, Pseudo, NoImm, oops, iops, ""> {
185 let Pattern = pattern;
188 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
189 list<dag> pattern, Domain d = GenericDomain>
190 : X86Inst<o, f, NoImm, outs, ins, asm, d> {
191 let Pattern = pattern;
194 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
195 list<dag> pattern, Domain d = GenericDomain>
196 : X86Inst<o, f, Imm8, outs, ins, asm, d> {
197 let Pattern = pattern;
200 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
202 : X86Inst<o, f, Imm8PCRel, outs, ins, asm> {
203 let Pattern = pattern;
206 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
208 : X86Inst<o, f, Imm16, outs, ins, asm> {
209 let Pattern = pattern;
212 class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
214 : X86Inst<o, f, Imm32, outs, ins, asm> {
215 let Pattern = pattern;
219 class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
221 : X86Inst<o, f, Imm16PCRel, outs, ins, asm> {
222 let Pattern = pattern;
226 class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
228 : X86Inst<o, f, Imm32PCRel, outs, ins, asm> {
229 let Pattern = pattern;
233 // FPStack Instruction Templates:
234 // FPI - Floating Point Instruction template.
235 class FPI<bits<8> o, Format F, dag outs, dag ins, string asm>
236 : I<o, F, outs, ins, asm, []> {}
238 // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
239 class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern>
240 : X86Inst<0, Pseudo, NoImm, outs, ins, ""> {
242 let Pattern = pattern;
245 // Templates for instructions that use a 16- or 32-bit segmented address as
246 // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
248 // Iseg16 - 16-bit segment selector, 16-bit offset
249 // Iseg32 - 16-bit segment selector, 32-bit offset
251 class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
252 list<dag> pattern> : X86Inst<o, f, Imm16, outs, ins, asm> {
253 let Pattern = pattern;
257 class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
258 list<dag> pattern> : X86Inst<o, f, Imm32, outs, ins, asm> {
259 let Pattern = pattern;
263 // SI - SSE 1 & 2 scalar instructions
264 class SI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
265 : I<o, F, outs, ins, asm, pattern> {
266 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
267 !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
269 // AVX instructions have a 'v' prefix in the mnemonic
270 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
273 // SIi8 - SSE 1 & 2 scalar instructions
274 class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
276 : Ii8<o, F, outs, ins, asm, pattern> {
277 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
278 !if(!eq(Prefix, 12 /* XS */), [HasSSE1], [HasSSE2]));
280 // AVX instructions have a 'v' prefix in the mnemonic
281 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
284 // PI - SSE 1 & 2 packed instructions
285 class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
287 : I<o, F, outs, ins, asm, pattern, d> {
288 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
289 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
291 // AVX instructions have a 'v' prefix in the mnemonic
292 let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
295 // PIi8 - SSE 1 & 2 packed instructions with immediate
296 class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
297 list<dag> pattern, Domain d>
298 : Ii8<o, F, outs, ins, asm, pattern, d> {
299 let Predicates = !if(hasVEX_4VPrefix /* VEX */, [HasAVX],
300 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
302 // AVX instructions have a 'v' prefix in the mnemonic
303 let AsmString = !if(hasVEX_4VPrefix, !strconcat("v", asm), asm);
306 // SSE1 Instruction Templates:
308 // SSI - SSE1 instructions with XS prefix.
309 // PSI - SSE1 instructions with TB prefix.
310 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
311 // VSSI - SSE1 instructions with XS prefix in AVX form.
312 // VPSI - SSE1 instructions with TB prefix in AVX form.
314 class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
315 : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
316 class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
318 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>;
319 class PSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
320 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
322 class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
324 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedSingle>, TB,
326 class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
328 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, XS,
330 class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
332 : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedSingle>, TB,
335 // SSE2 Instruction Templates:
337 // SDI - SSE2 instructions with XD prefix.
338 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
339 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
340 // PDI - SSE2 instructions with TB and OpSize prefixes.
341 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
342 // VSDI - SSE2 instructions with XD prefix in AVX form.
343 // VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.
345 class SDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
346 : I<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
347 class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
349 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
350 class SSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
352 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
353 class PDI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
354 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
356 class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
358 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
360 class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
362 : I<o, F, outs, ins, !strconcat("v", asm), pattern>, XD,
364 class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
366 : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedDouble>, TB,
367 OpSize, Requires<[HasAVX]>;
369 // SSE3 Instruction Templates:
371 // S3I - SSE3 instructions with TB and OpSize prefixes.
372 // S3SI - SSE3 instructions with XS prefix.
373 // S3DI - SSE3 instructions with XD prefix.
375 class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
377 : I<o, F, outs, ins, asm, pattern, SSEPackedSingle>, XS,
379 class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
381 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, XD,
383 class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
384 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
388 // SSSE3 Instruction Templates:
390 // SS38I - SSSE3 instructions with T8 prefix.
391 // SS3AI - SSSE3 instructions with TA prefix.
393 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
394 // uses the MMX registers. We put those instructions here because they better
395 // fit into the SSSE3 instruction category rather than the MMX category.
397 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
399 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
400 Requires<[HasSSSE3]>;
401 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
403 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
404 Requires<[HasSSSE3]>;
406 // SSE4.1 Instruction Templates:
408 // SS48I - SSE 4.1 instructions with T8 prefix.
409 // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
411 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
413 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
414 Requires<[HasSSE41]>;
415 class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
417 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
418 Requires<[HasSSE41]>;
420 // SSE4.2 Instruction Templates:
422 // SS428I - SSE 4.2 instructions with T8 prefix.
423 class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
425 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
426 Requires<[HasSSE42]>;
428 // SS42FI - SSE 4.2 instructions with T8XD prefix.
429 class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
431 : I<o, F, outs, ins, asm, pattern>, T8XD, Requires<[HasSSE42]>;
433 // SS42AI = SSE 4.2 instructions with TA prefix
434 class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
436 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
437 Requires<[HasSSE42]>;
439 // AVX Instruction Templates:
440 // Instructions introduced in AVX (no SSE equivalent forms)
442 // AVX8I - AVX instructions with T8 and OpSize prefix.
443 // AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8.
444 class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
446 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, OpSize,
448 class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
450 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, OpSize,
453 // AES Instruction Templates:
456 // These use the same encoding as the SSE4.2 T8 and TA encodings.
457 class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
459 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
462 class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
464 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
467 // CLMUL Instruction Templates
468 class CLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
470 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
471 OpSize, Requires<[HasCLMUL]>;
473 class AVXCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
475 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA,
476 OpSize, VEX_4V, Requires<[HasAVX, HasCLMUL]>;
478 // FMA3 Instruction Templates
479 class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
481 : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8,
482 OpSize, VEX_4V, Requires<[HasFMA3]>;
484 // X86-64 Instruction templates...
487 class RI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
488 : I<o, F, outs, ins, asm, pattern>, REX_W;
489 class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
491 : Ii8<o, F, outs, ins, asm, pattern>, REX_W;
492 class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
494 : Ii32<o, F, outs, ins, asm, pattern>, REX_W;
496 class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
498 : X86Inst<o, f, Imm64, outs, ins, asm>, REX_W {
499 let Pattern = pattern;
503 class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
505 : SSI<o, F, outs, ins, asm, pattern>, REX_W;
506 class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
508 : SDI<o, F, outs, ins, asm, pattern>, REX_W;
509 class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
511 : PDI<o, F, outs, ins, asm, pattern>, REX_W;
512 class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
514 : VPDI<o, F, outs, ins, asm, pattern>, VEX_W;
516 // MMX Instruction templates
519 // MMXI - MMX instructions with TB prefix.
520 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
521 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
522 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
523 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
524 // MMXID - MMX instructions with XD prefix.
525 // MMXIS - MMX instructions with XS prefix.
526 class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
528 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
529 class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
531 : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX,In64BitMode]>;
532 class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
534 : I<o, F, outs, ins, asm, pattern>, TB, REX_W, Requires<[HasMMX]>;
535 class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
537 : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasMMX]>;
538 class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
540 : Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
541 class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
543 : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX]>;
544 class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
546 : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>;