1 //==- X86InstrFPStack.td - Describe the X86 Instruction Set -------*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 x87 FPU instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // FPStack specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def SDTX86FpGet : SDTypeProfile<1, 0, [SDTCisFP<0>]>;
21 def SDTX86FpSet : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
22 def SDTX86Fld : SDTypeProfile<1, 2, [SDTCisFP<0>,
24 SDTCisVT<2, OtherVT>]>;
25 def SDTX86Fst : SDTypeProfile<0, 3, [SDTCisFP<0>,
27 SDTCisVT<2, OtherVT>]>;
28 def SDTX86Fild : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisPtrTy<1>,
29 SDTCisVT<2, OtherVT>]>;
30 def SDTX86FpToIMem : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
32 def X86fpget : SDNode<"X86ISD::FP_GET_RESULT", SDTX86FpGet,
33 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
34 def X86fpset : SDNode<"X86ISD::FP_SET_RESULT", SDTX86FpSet,
35 [SDNPHasChain, SDNPOutFlag]>;
36 def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
38 def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
39 [SDNPHasChain, SDNPInFlag]>;
40 def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
42 def X86fildflag : SDNode<"X86ISD::FILD_FLAG",SDTX86Fild,
43 [SDNPHasChain, SDNPOutFlag]>;
44 def X86fp_to_i16mem : SDNode<"X86ISD::FP_TO_INT16_IN_MEM", SDTX86FpToIMem,
46 def X86fp_to_i32mem : SDNode<"X86ISD::FP_TO_INT32_IN_MEM", SDTX86FpToIMem,
48 def X86fp_to_i64mem : SDNode<"X86ISD::FP_TO_INT64_IN_MEM", SDTX86FpToIMem,
51 def extloadf80f32 : PatFrag<(ops node:$ptr), (f80 (extloadf32 node:$ptr))>;
52 def extloadf80f64 : PatFrag<(ops node:$ptr), (f80 (extloadf64 node:$ptr))>;
53 def extloadf64f32 : PatFrag<(ops node:$ptr), (f64 (extloadf32 node:$ptr))>;
55 //===----------------------------------------------------------------------===//
56 // FPStack pattern fragments
57 //===----------------------------------------------------------------------===//
59 def fpimm0 : PatLeaf<(fpimm), [{
60 return N->isExactlyValue(+0.0);
63 def fpimmneg0 : PatLeaf<(fpimm), [{
64 return N->isExactlyValue(-0.0);
67 def fpimm1 : PatLeaf<(fpimm), [{
68 return N->isExactlyValue(+1.0);
71 def fpimmneg1 : PatLeaf<(fpimm), [{
72 return N->isExactlyValue(-1.0);
75 // Some 'special' instructions
76 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
77 def FP32_TO_INT16_IN_MEM : I<0, Pseudo,
78 (outs), (ins i16mem:$dst, RFP32:$src),
79 "#FP32_TO_INT16_IN_MEM PSEUDO!",
80 [(X86fp_to_i16mem RFP32:$src, addr:$dst)]>;
81 def FP32_TO_INT32_IN_MEM : I<0, Pseudo,
82 (outs), (ins i32mem:$dst, RFP32:$src),
83 "#FP32_TO_INT32_IN_MEM PSEUDO!",
84 [(X86fp_to_i32mem RFP32:$src, addr:$dst)]>;
85 def FP32_TO_INT64_IN_MEM : I<0, Pseudo,
86 (outs), (ins i64mem:$dst, RFP32:$src),
87 "#FP32_TO_INT64_IN_MEM PSEUDO!",
88 [(X86fp_to_i64mem RFP32:$src, addr:$dst)]>;
89 def FP64_TO_INT16_IN_MEM : I<0, Pseudo,
90 (outs), (ins i16mem:$dst, RFP64:$src),
91 "#FP64_TO_INT16_IN_MEM PSEUDO!",
92 [(X86fp_to_i16mem RFP64:$src, addr:$dst)]>;
93 def FP64_TO_INT32_IN_MEM : I<0, Pseudo,
94 (outs), (ins i32mem:$dst, RFP64:$src),
95 "#FP64_TO_INT32_IN_MEM PSEUDO!",
96 [(X86fp_to_i32mem RFP64:$src, addr:$dst)]>;
97 def FP64_TO_INT64_IN_MEM : I<0, Pseudo,
98 (outs), (ins i64mem:$dst, RFP64:$src),
99 "#FP64_TO_INT64_IN_MEM PSEUDO!",
100 [(X86fp_to_i64mem RFP64:$src, addr:$dst)]>;
101 def FP80_TO_INT16_IN_MEM : I<0, Pseudo,
102 (outs), (ins i16mem:$dst, RFP80:$src),
103 "#FP80_TO_INT16_IN_MEM PSEUDO!",
104 [(X86fp_to_i16mem RFP80:$src, addr:$dst)]>;
105 def FP80_TO_INT32_IN_MEM : I<0, Pseudo,
106 (outs), (ins i32mem:$dst, RFP80:$src),
107 "#FP80_TO_INT32_IN_MEM PSEUDO!",
108 [(X86fp_to_i32mem RFP80:$src, addr:$dst)]>;
109 def FP80_TO_INT64_IN_MEM : I<0, Pseudo,
110 (outs), (ins i64mem:$dst, RFP80:$src),
111 "#FP80_TO_INT64_IN_MEM PSEUDO!",
112 [(X86fp_to_i64mem RFP80:$src, addr:$dst)]>;
115 let isTerminator = 1 in
116 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
117 def FP_REG_KILL : I<0, Pseudo, (outs), (ins), "#FP_REG_KILL", []>;
119 // All FP Stack operations are represented with three instructions here. The
120 // first two instructions, generated by the instruction selector, uses "RFP32"
121 // or "RFP64" registers: traditional register files to reference 32-bit or
122 // 64-bit floating point values. These sizes apply to the values, not the
123 // registers, which are always 64 bits; RFP32 and RFP64 can be copied to
124 // each other without losing information. These instructions are all psuedo
125 // instructions and use the "_Fp" suffix.
126 // In some cases there are additional variants with a mixture of 32-bit and
128 // The second instruction is defined with FPI, which is the actual instruction
129 // emitted by the assembler. These use "RST" registers, although frequently
130 // the actual register(s) used are implicit. These are always 64-bits.
131 // The FP stackifier pass converts one to the other after register allocation
134 // Note that the FpI instruction should have instruction selection info (e.g.
135 // a pattern) and the FPI instruction should have emission info (e.g. opcode
136 // encoding and asm printing info).
138 // Random Pseudo Instructions.
139 def FpGETRESULT32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP,
140 [(set RFP32:$dst, X86fpget)]>; // FPR = ST(0)
142 def FpGETRESULT64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP,
143 [(set RFP64:$dst, X86fpget)]>; // FPR = ST(0)
145 def FpGETRESULT80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP,
146 [(set RFP80:$dst, X86fpget)]>; // FPR = ST(0)
148 def FpSETRESULT32 : FpI_<(outs), (ins RFP32:$src), SpecialFP,
149 [(X86fpset RFP32:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
151 def FpSETRESULT64 : FpI_<(outs), (ins RFP64:$src), SpecialFP,
152 [(X86fpset RFP64:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
154 def FpSETRESULT80 : FpI_<(outs), (ins RFP80:$src), SpecialFP,
155 [(X86fpset RFP80:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
157 // FpI - Floating Point Psuedo Instruction template. Predicated on FPStack.
158 class FpI<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
159 FpI_<outs, ins, fp, pattern>, Requires<[FPStack]>;
161 // Register copies. Just copies, the shortening ones do not truncate.
162 def MOV_Fp3232 : FpI<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>;
163 def MOV_Fp3264 : FpI<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>;
164 def MOV_Fp6432 : FpI<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>;
165 def MOV_Fp6464 : FpI<(outs RFP64:$dst), (ins RFP64:$src), SpecialFP, []>;
166 def MOV_Fp8032 : FpI<(outs RFP32:$dst), (ins RFP80:$src), SpecialFP, []>;
167 def MOV_Fp3280 : FpI<(outs RFP80:$dst), (ins RFP32:$src), SpecialFP, []>;
168 def MOV_Fp8064 : FpI<(outs RFP64:$dst), (ins RFP80:$src), SpecialFP, []>;
169 def MOV_Fp6480 : FpI<(outs RFP80:$dst), (ins RFP64:$src), SpecialFP, []>;
170 def MOV_Fp8080 : FpI<(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>;
172 // Factoring for arithmetic.
173 multiclass FPBinary_rr<SDNode OpNode> {
174 // Register op register -> register
175 // These are separated out because they have no reversed form.
176 def _Fp32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP,
177 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
178 def _Fp64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP,
179 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
180 def _Fp80 : FpI<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP,
181 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
183 // The FopST0 series are not included here because of the irregularities
184 // in where the 'r' goes in assembly output.
185 // These instructions cannot address 80-bit memory.
186 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring> {
187 // ST(0) = ST(0) + [mem]
188 def _Fp32m : FpI<(outs RFP32:$dst), (ins RFP32:$src1, f32mem:$src2), OneArgFPRW,
190 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>;
191 def _Fp64m : FpI<(outs RFP64:$dst), (ins RFP64:$src1, f64mem:$src2), OneArgFPRW,
193 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
194 def _Fp64m32: FpI<(outs RFP64:$dst), (ins RFP64:$src1, f32mem:$src2), OneArgFPRW,
196 (OpNode RFP64:$src1, (extloadf64f32 addr:$src2)))]>;
197 def _Fp80m32: FpI<(outs RFP80:$dst), (ins RFP80:$src1, f32mem:$src2), OneArgFPRW,
199 (OpNode RFP80:$src1, (extloadf80f32 addr:$src2)))]>;
200 def _Fp80m64: FpI<(outs RFP80:$dst), (ins RFP80:$src1, f64mem:$src2), OneArgFPRW,
202 (OpNode RFP80:$src1, (extloadf80f64 addr:$src2)))]>;
203 def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src),
204 !strconcat("f", !strconcat(asmstring, "{s}\t$src"))>;
205 def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src),
206 !strconcat("f", !strconcat(asmstring, "{l}\t$src"))>;
207 // ST(0) = ST(0) + [memint]
208 def _FpI16m32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2), OneArgFPRW,
209 [(set RFP32:$dst, (OpNode RFP32:$src1,
210 (X86fild addr:$src2, i16)))]>;
211 def _FpI32m32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2), OneArgFPRW,
212 [(set RFP32:$dst, (OpNode RFP32:$src1,
213 (X86fild addr:$src2, i32)))]>;
214 def _FpI16m64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2), OneArgFPRW,
215 [(set RFP64:$dst, (OpNode RFP64:$src1,
216 (X86fild addr:$src2, i16)))]>;
217 def _FpI32m64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2), OneArgFPRW,
218 [(set RFP64:$dst, (OpNode RFP64:$src1,
219 (X86fild addr:$src2, i32)))]>;
220 def _FpI16m80 : FpI<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2), OneArgFPRW,
221 [(set RFP80:$dst, (OpNode RFP80:$src1,
222 (X86fild addr:$src2, i16)))]>;
223 def _FpI32m80 : FpI<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2), OneArgFPRW,
224 [(set RFP80:$dst, (OpNode RFP80:$src1,
225 (X86fild addr:$src2, i32)))]>;
226 def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src),
227 !strconcat("fi", !strconcat(asmstring, "{s}\t$src"))>;
228 def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src),
229 !strconcat("fi", !strconcat(asmstring, "{l}\t$src"))>;
232 defm ADD : FPBinary_rr<fadd>;
233 defm SUB : FPBinary_rr<fsub>;
234 defm MUL : FPBinary_rr<fmul>;
235 defm DIV : FPBinary_rr<fdiv>;
236 defm ADD : FPBinary<fadd, MRM0m, "add">;
237 defm SUB : FPBinary<fsub, MRM4m, "sub">;
238 defm SUBR: FPBinary<fsub ,MRM5m, "subr">;
239 defm MUL : FPBinary<fmul, MRM1m, "mul">;
240 defm DIV : FPBinary<fdiv, MRM6m, "div">;
241 defm DIVR: FPBinary<fdiv, MRM7m, "divr">;
243 class FPST0rInst<bits<8> o, string asm>
244 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, D8;
245 class FPrST0Inst<bits<8> o, string asm>
246 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DC;
247 class FPrST0PInst<bits<8> o, string asm>
248 : FPI<o, AddRegFrm, (outs), (ins RST:$op), asm>, DE;
250 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
251 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
252 // we have to put some 'r's in and take them out of weird places.
253 def ADD_FST0r : FPST0rInst <0xC0, "fadd\t$op">;
254 def ADD_FrST0 : FPrST0Inst <0xC0, "fadd\t{%st(0), $op|$op, %ST(0)}">;
255 def ADD_FPrST0 : FPrST0PInst<0xC0, "faddp\t$op">;
256 def SUBR_FST0r : FPST0rInst <0xE8, "fsubr\t$op">;
257 def SUB_FrST0 : FPrST0Inst <0xE8, "fsub{r}\t{%st(0), $op|$op, %ST(0)}">;
258 def SUB_FPrST0 : FPrST0PInst<0xE8, "fsub{r}p\t$op">;
259 def SUB_FST0r : FPST0rInst <0xE0, "fsub\t$op">;
260 def SUBR_FrST0 : FPrST0Inst <0xE0, "fsub{|r}\t{%st(0), $op|$op, %ST(0)}">;
261 def SUBR_FPrST0 : FPrST0PInst<0xE0, "fsub{|r}p\t$op">;
262 def MUL_FST0r : FPST0rInst <0xC8, "fmul\t$op">;
263 def MUL_FrST0 : FPrST0Inst <0xC8, "fmul\t{%st(0), $op|$op, %ST(0)}">;
264 def MUL_FPrST0 : FPrST0PInst<0xC8, "fmulp\t$op">;
265 def DIVR_FST0r : FPST0rInst <0xF8, "fdivr\t$op">;
266 def DIV_FrST0 : FPrST0Inst <0xF8, "fdiv{r}\t{%st(0), $op|$op, %ST(0)}">;
267 def DIV_FPrST0 : FPrST0PInst<0xF8, "fdiv{r}p\t$op">;
268 def DIV_FST0r : FPST0rInst <0xF0, "fdiv\t$op">;
269 def DIVR_FrST0 : FPrST0Inst <0xF0, "fdiv{|r}\t{%st(0), $op|$op, %ST(0)}">;
270 def DIVR_FPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p\t$op">;
273 multiclass FPUnary<SDNode OpNode, bits<8> opcode, string asmstring> {
274 def _Fp32 : FpI<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW,
275 [(set RFP32:$dst, (OpNode RFP32:$src))]>;
276 def _Fp64 : FpI<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW,
277 [(set RFP64:$dst, (OpNode RFP64:$src))]>;
278 def _Fp80 : FpI<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,
279 [(set RFP80:$dst, (OpNode RFP80:$src))]>;
280 def _F : FPI<opcode, RawFrm, (outs), (ins), asmstring>, D9;
283 defm CHS : FPUnary<fneg, 0xE0, "fchs">;
284 defm ABS : FPUnary<fabs, 0xE1, "fabs">;
285 defm SQRT: FPUnary<fsqrt,0xFA, "fsqrt">;
286 defm SIN : FPUnary<fsin, 0xFE, "fsin">;
287 defm COS : FPUnary<fcos, 0xFF, "fcos">;
289 def TST_Fp32 : FpI<(outs), (ins RFP32:$src), OneArgFP,
291 def TST_Fp64 : FpI<(outs), (ins RFP64:$src), OneArgFP,
293 def TST_Fp80 : FpI<(outs), (ins RFP80:$src), OneArgFP,
295 def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9;
297 // Floating point cmovs.
298 multiclass FPCMov<PatLeaf cc> {
299 def _Fp32 : FpI<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), CondMovFP,
300 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2,
302 def _Fp64 : FpI<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), CondMovFP,
303 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,
305 def _Fp80 : FpI<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), CondMovFP,
306 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
309 let isTwoAddress = 1 in {
310 defm CMOVB : FPCMov<X86_COND_B>;
311 defm CMOVBE : FPCMov<X86_COND_BE>;
312 defm CMOVE : FPCMov<X86_COND_E>;
313 defm CMOVP : FPCMov<X86_COND_P>;
314 defm CMOVNB : FPCMov<X86_COND_AE>;
315 defm CMOVNBE: FPCMov<X86_COND_A>;
316 defm CMOVNE : FPCMov<X86_COND_NE>;
317 defm CMOVNP : FPCMov<X86_COND_NP>;
320 // These are not factored because there's no clean way to pass DA/DB.
321 def CMOVB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
322 "fcmovb\t{$op, %st(0)|%ST(0), $op}">, DA;
323 def CMOVBE_F : FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
324 "fcmovbe\t{$op, %st(0)|%ST(0), $op}">, DA;
325 def CMOVE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
326 "fcmove\t{$op, %st(0)|%ST(0), $op}">, DA;
327 def CMOVP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
328 "fcmovu\t {$op, %st(0)|%ST(0), $op}">, DA;
329 def CMOVNB_F : FPI<0xC0, AddRegFrm, (outs RST:$op), (ins),
330 "fcmovnb\t{$op, %st(0)|%ST(0), $op}">, DB;
331 def CMOVNBE_F: FPI<0xD0, AddRegFrm, (outs RST:$op), (ins),
332 "fcmovnbe\t{$op, %st(0)|%ST(0), $op}">, DB;
333 def CMOVNE_F : FPI<0xC8, AddRegFrm, (outs RST:$op), (ins),
334 "fcmovne\t{$op, %st(0)|%ST(0), $op}">, DB;
335 def CMOVNP_F : FPI<0xD8, AddRegFrm, (outs RST:$op), (ins),
336 "fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB;
338 // Floating point loads & stores.
339 def LD_Fp32m : FpI<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
340 [(set RFP32:$dst, (loadf32 addr:$src))]>;
341 def LD_Fp64m : FpI<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP,
342 [(set RFP64:$dst, (loadf64 addr:$src))]>;
343 def LD_Fp80m : FpI<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP,
344 [(set RFP80:$dst, (loadf80 addr:$src))]>;
345 def ILD_Fp16m32: FpI<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP,
346 [(set RFP32:$dst, (X86fild addr:$src, i16))]>;
347 def ILD_Fp32m32: FpI<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP,
348 [(set RFP32:$dst, (X86fild addr:$src, i32))]>;
349 def ILD_Fp64m32: FpI<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP,
350 [(set RFP32:$dst, (X86fild addr:$src, i64))]>;
351 def ILD_Fp16m64: FpI<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP,
352 [(set RFP64:$dst, (X86fild addr:$src, i16))]>;
353 def ILD_Fp32m64: FpI<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP,
354 [(set RFP64:$dst, (X86fild addr:$src, i32))]>;
355 def ILD_Fp64m64: FpI<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP,
356 [(set RFP64:$dst, (X86fild addr:$src, i64))]>;
357 def ILD_Fp16m80: FpI<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP,
358 [(set RFP80:$dst, (X86fild addr:$src, i16))]>;
359 def ILD_Fp32m80: FpI<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP,
360 [(set RFP80:$dst, (X86fild addr:$src, i32))]>;
361 def ILD_Fp64m80: FpI<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP,
362 [(set RFP80:$dst, (X86fild addr:$src, i64))]>;
364 def ST_Fp32m : FpI<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP,
365 [(store RFP32:$src, addr:$op)]>;
366 def ST_Fp64m32 : FpI<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP,
367 [(truncstoref32 RFP64:$src, addr:$op)]>;
368 def ST_Fp64m : FpI<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP,
369 [(store RFP64:$src, addr:$op)]>;
370 def ST_Fp80m32 : FpI<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP,
371 [(truncstoref32 RFP80:$src, addr:$op)]>;
372 def ST_Fp80m64 : FpI<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP,
373 [(truncstoref64 RFP80:$src, addr:$op)]>;
374 // FST does not support 80-bit memory target; FSTP must be used.
376 def ST_FpP32m : FpI<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>;
377 def ST_FpP64m32 : FpI<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>;
378 def ST_FpP64m : FpI<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>;
379 def ST_FpP80m32 : FpI<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>;
380 def ST_FpP80m64 : FpI<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>;
381 def ST_FpP80m : FpI<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP,
382 [(store RFP80:$src, addr:$op)]>;
383 def IST_Fp16m32 : FpI<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>;
384 def IST_Fp32m32 : FpI<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>;
385 def IST_Fp64m32 : FpI<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>;
386 def IST_Fp16m64 : FpI<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>;
387 def IST_Fp32m64 : FpI<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>;
388 def IST_Fp64m64 : FpI<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>;
389 def IST_Fp16m80 : FpI<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>;
390 def IST_Fp32m80 : FpI<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>;
391 def IST_Fp64m80 : FpI<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>;
393 def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
394 def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
395 def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;
396 def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
397 def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
398 def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
399 def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
400 def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
401 def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;
402 def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">;
403 def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">;
404 def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">;
405 def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">;
406 def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">;
407 def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">;
408 def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;
410 // FISTTP requires SSE3 even though it's a FPStack op.
411 def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP,
412 [(X86fp_to_i16mem RFP32:$src, addr:$op)]>,
414 def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP,
415 [(X86fp_to_i32mem RFP32:$src, addr:$op)]>,
417 def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP,
418 [(X86fp_to_i64mem RFP32:$src, addr:$op)]>,
420 def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP,
421 [(X86fp_to_i16mem RFP64:$src, addr:$op)]>,
423 def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP,
424 [(X86fp_to_i32mem RFP64:$src, addr:$op)]>,
426 def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP,
427 [(X86fp_to_i64mem RFP64:$src, addr:$op)]>,
429 def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP,
430 [(X86fp_to_i16mem RFP80:$src, addr:$op)]>,
432 def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP,
433 [(X86fp_to_i32mem RFP80:$src, addr:$op)]>,
435 def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP,
436 [(X86fp_to_i64mem RFP80:$src, addr:$op)]>,
439 def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;
440 def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;
441 def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">;
443 // FP Stack manipulation instructions.
444 def LD_Frr : FPI<0xC0, AddRegFrm, (outs), (ins RST:$op), "fld\t$op">, D9;
445 def ST_Frr : FPI<0xD0, AddRegFrm, (outs), (ins RST:$op), "fst\t$op">, DD;
446 def ST_FPrr : FPI<0xD8, AddRegFrm, (outs), (ins RST:$op), "fstp\t$op">, DD;
447 def XCH_F : FPI<0xC8, AddRegFrm, (outs), (ins RST:$op), "fxch\t$op">, D9;
449 // Floating point constant loads.
450 let isReMaterializable = 1 in {
451 def LD_Fp032 : FpI<(outs RFP32:$dst), (ins), ZeroArgFP,
452 [(set RFP32:$dst, fpimm0)]>;
453 def LD_Fp132 : FpI<(outs RFP32:$dst), (ins), ZeroArgFP,
454 [(set RFP32:$dst, fpimm1)]>;
455 def LD_Fp064 : FpI<(outs RFP64:$dst), (ins), ZeroArgFP,
456 [(set RFP64:$dst, fpimm0)]>;
457 def LD_Fp164 : FpI<(outs RFP64:$dst), (ins), ZeroArgFP,
458 [(set RFP64:$dst, fpimm1)]>;
459 def LD_Fp080 : FpI<(outs RFP80:$dst), (ins), ZeroArgFP,
460 [(set RFP80:$dst, fpimm0)]>;
461 def LD_Fp180 : FpI<(outs RFP80:$dst), (ins), ZeroArgFP,
462 [(set RFP80:$dst, fpimm1)]>;
465 def LD_F0 : FPI<0xEE, RawFrm, (outs), (ins), "fldz">, D9;
466 def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1">, D9;
469 // Floating point compares.
470 def UCOM_Fpr32 : FpI<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
471 []>; // FPSW = cmp ST(0) with ST(i)
472 def UCOM_FpIr32: FpI<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
473 [(X86cmp RFP32:$lhs, RFP32:$rhs)]>; // CC = ST(0) cmp ST(i)
474 def UCOM_Fpr64 : FpI<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
475 []>; // FPSW = cmp ST(0) with ST(i)
476 def UCOM_FpIr64: FpI<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
477 [(X86cmp RFP64:$lhs, RFP64:$rhs)]>; // CC = ST(0) cmp ST(i)
478 def UCOM_Fpr80 : FpI<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
479 []>; // FPSW = cmp ST(0) with ST(i)
480 def UCOM_FpIr80: FpI<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
481 [(X86cmp RFP80:$lhs, RFP80:$rhs)]>; // CC = ST(0) cmp ST(i)
483 def UCOM_Fr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
484 (outs), (ins RST:$reg),
485 "fucom\t$reg">, DD, Imp<[ST0],[]>;
486 def UCOM_FPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
487 (outs), (ins RST:$reg),
488 "fucomp\t$reg">, DD, Imp<[ST0],[]>;
489 def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
491 "fucompp">, DA, Imp<[ST0],[]>;
493 def UCOM_FIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
494 (outs), (ins RST:$reg),
495 "fucomi\t{$reg, %st(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
496 def UCOM_FIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
497 (outs), (ins RST:$reg),
498 "fucomip\t{$reg, %st(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>;
500 // Floating point flag ops.
501 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
502 (outs), (ins), "fnstsw", []>, DF, Imp<[],[AX]>;
504 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
505 (outs), (ins i16mem:$dst), "fnstcw\t$dst", []>;
506 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
507 (outs), (ins i16mem:$dst), "fldcw\t$dst", []>;
509 //===----------------------------------------------------------------------===//
510 // Non-Instruction Patterns
511 //===----------------------------------------------------------------------===//
513 // Required for RET of f32 / f64 values.
514 def : Pat<(X86fld addr:$src, f32), (LD_Fp32m addr:$src)>;
515 def : Pat<(X86fld addr:$src, f64), (LD_Fp64m addr:$src)>;
516 def : Pat<(X86fld addr:$src, f80), (LD_Fp80m addr:$src)>;
518 // Required for CALL which return f32 / f64 values.
519 def : Pat<(X86fst RFP32:$src, addr:$op, f32), (ST_Fp32m addr:$op, RFP32:$src)>;
520 def : Pat<(X86fst RFP64:$src, addr:$op, f32), (ST_Fp64m32 addr:$op, RFP64:$src)>;
521 def : Pat<(X86fst RFP64:$src, addr:$op, f64), (ST_Fp64m addr:$op, RFP64:$src)>;
522 def : Pat<(X86fst RFP80:$src, addr:$op, f32), (ST_Fp80m32 addr:$op, RFP80:$src)>;
523 def : Pat<(X86fst RFP80:$src, addr:$op, f64), (ST_Fp80m64 addr:$op, RFP80:$src)>;
524 def : Pat<(X86fst RFP80:$src, addr:$op, f80), (ST_FpP80m addr:$op, RFP80:$src)>;
526 // Floating point constant -0.0 and -1.0
527 def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStack]>;
528 def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStack]>;
529 def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStack]>;
530 def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStack]>;
531 def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>, Requires<[FPStack]>;
532 def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>, Requires<[FPStack]>;
534 // Used to conv. i64 to f64 since there isn't a SSE version.
535 def : Pat<(X86fildflag addr:$src, i64), (ILD_Fp64m64 addr:$src)>;
537 def : Pat<(extloadf80f32 addr:$src),
538 (MOV_Fp3280 (LD_Fp32m addr:$src))>, Requires<[FPStack]>;
539 def : Pat<(extloadf80f64 addr:$src),
540 (MOV_Fp6480 (LD_Fp64m addr:$src))>, Requires<[FPStack]>;
541 def : Pat<(extloadf64f32 addr:$src),
542 (MOV_Fp3264 (LD_Fp32m addr:$src))>, Requires<[FPStack]>;
544 def : Pat<(f64 (fextend RFP32:$src)), (MOV_Fp3264 RFP32:$src)>, Requires<[FPStack]>;
545 def : Pat<(f80 (fextend RFP32:$src)), (MOV_Fp3280 RFP32:$src)>, Requires<[FPStack]>;
546 def : Pat<(f80 (fextend RFP64:$src)), (MOV_Fp6480 RFP64:$src)>, Requires<[FPStack]>;