1 //==- X86InstrFPStack.td - Describe the X86 Instruction Set -------*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 x87 FPU instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // FPStack pattern fragments
18 //===----------------------------------------------------------------------===//
20 def fp32imm0 : PatLeaf<(f32 fpimm), [{
21 return N->isExactlyValue(+0.0);
24 def fp64imm0 : PatLeaf<(f64 fpimm), [{
25 return N->isExactlyValue(+0.0);
28 def fp64immneg0 : PatLeaf<(f64 fpimm), [{
29 return N->isExactlyValue(-0.0);
32 def fp64imm1 : PatLeaf<(f64 fpimm), [{
33 return N->isExactlyValue(+1.0);
36 def fp64immneg1 : PatLeaf<(f64 fpimm), [{
37 return N->isExactlyValue(-1.0);
40 def extloadf64f32 : PatFrag<(ops node:$ptr), (f64 (extload node:$ptr, f32))>;
42 // Some 'special' instructions
43 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
44 def FP_TO_INT16_IN_MEM : I<0, Pseudo,
45 (ops i16mem:$dst, RFP:$src),
46 "#FP_TO_INT16_IN_MEM PSEUDO!",
47 [(X86fp_to_i16mem RFP:$src, addr:$dst)]>;
48 def FP_TO_INT32_IN_MEM : I<0, Pseudo,
49 (ops i32mem:$dst, RFP:$src),
50 "#FP_TO_INT32_IN_MEM PSEUDO!",
51 [(X86fp_to_i32mem RFP:$src, addr:$dst)]>;
52 def FP_TO_INT64_IN_MEM : I<0, Pseudo,
53 (ops i64mem:$dst, RFP:$src),
54 "#FP_TO_INT64_IN_MEM PSEUDO!",
55 [(X86fp_to_i64mem RFP:$src, addr:$dst)]>;
58 let isTerminator = 1 in
59 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
60 def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL", []>;
62 // All FP Stack operations are represented with two instructions here. The
63 // first instruction, generated by the instruction selector, uses "RFP"
64 // registers: a traditional register file to reference floating point values.
65 // These instructions are all psuedo instructions and use the "Fp" prefix.
66 // The second instruction is defined with FPI, which is the actual instruction
67 // emitted by the assembler. The FP stackifier pass converts one to the other
68 // after register allocation occurs.
70 // Note that the FpI instruction should have instruction selection info (e.g.
71 // a pattern) and the FPI instruction should have emission info (e.g. opcode
72 // encoding and asm printing info).
74 // FPI - Floating Point Instruction template.
75 class FPI<bits<8> o, Format F, dag ops, string asm> : I<o, F, ops, asm, []> {}
77 // FpI_ - Floating Point Psuedo Instruction template. Not Predicated.
78 class FpI_<dag ops, FPFormat fp, list<dag> pattern>
79 : X86Inst<0, Pseudo, NoImm, ops, ""> {
80 let FPForm = fp; let FPFormBits = FPForm.Value;
81 let Pattern = pattern;
84 // Random Pseudo Instructions.
85 def FpGETRESULT : FpI_<(ops RFP:$dst), SpecialFP,
86 [(set RFP:$dst, X86fpget)]>; // FPR = ST(0)
89 def FpSETRESULT : FpI_<(ops RFP:$src), SpecialFP,
90 [(X86fpset RFP:$src)]>, Imp<[], [ST0]>; // ST(0) = FPR
92 // FpI - Floating Point Psuedo Instruction template. Predicated on FPStack.
93 class FpI<dag ops, FPFormat fp, list<dag> pattern> :
94 FpI_<ops, fp, pattern>, Requires<[FPStack]>;
97 def FpMOV : FpI<(ops RFP:$dst, RFP:$src), SpecialFP, []>; // f1 = fmov f2
100 // Add, Sub, Mul, Div.
101 def FpADD : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP,
102 [(set RFP:$dst, (fadd RFP:$src1, RFP:$src2))]>;
103 def FpSUB : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP,
104 [(set RFP:$dst, (fsub RFP:$src1, RFP:$src2))]>;
105 def FpMUL : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP,
106 [(set RFP:$dst, (fmul RFP:$src1, RFP:$src2))]>;
107 def FpDIV : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), TwoArgFP,
108 [(set RFP:$dst, (fdiv RFP:$src1, RFP:$src2))]>;
110 class FPST0rInst<bits<8> o, string asm>
111 : FPI<o, AddRegFrm, (ops RST:$op), asm>, D8;
112 class FPrST0Inst<bits<8> o, string asm>
113 : FPI<o, AddRegFrm, (ops RST:$op), asm>, DC;
114 class FPrST0PInst<bits<8> o, string asm>
115 : FPI<o, AddRegFrm, (ops RST:$op), asm>, DE;
117 // Binary Ops with a memory source.
118 def FpADD32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
119 [(set RFP:$dst, (fadd RFP:$src1,
120 (extloadf64f32 addr:$src2)))]>;
121 // ST(0) = ST(0) + [mem32]
122 def FpADD64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW,
123 [(set RFP:$dst, (fadd RFP:$src1, (loadf64 addr:$src2)))]>;
124 // ST(0) = ST(0) + [mem64]
125 def FpMUL32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
126 [(set RFP:$dst, (fmul RFP:$src1,
127 (extloadf64f32 addr:$src2)))]>;
128 // ST(0) = ST(0) * [mem32]
129 def FpMUL64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW,
130 [(set RFP:$dst, (fmul RFP:$src1, (loadf64 addr:$src2)))]>;
131 // ST(0) = ST(0) * [mem64]
132 def FpSUB32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
133 [(set RFP:$dst, (fsub RFP:$src1,
134 (extloadf64f32 addr:$src2)))]>;
135 // ST(0) = ST(0) - [mem32]
136 def FpSUB64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW,
137 [(set RFP:$dst, (fsub RFP:$src1, (loadf64 addr:$src2)))]>;
138 // ST(0) = ST(0) - [mem64]
139 def FpSUBR32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
140 [(set RFP:$dst, (fsub (extloadf64f32 addr:$src2),
142 // ST(0) = [mem32] - ST(0)
143 def FpSUBR64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW,
144 [(set RFP:$dst, (fsub (loadf64 addr:$src2), RFP:$src1))]>;
145 // ST(0) = [mem64] - ST(0)
146 def FpDIV32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
147 [(set RFP:$dst, (fdiv RFP:$src1,
148 (extloadf64f32 addr:$src2)))]>;
149 // ST(0) = ST(0) / [mem32]
150 def FpDIV64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW,
151 [(set RFP:$dst, (fdiv RFP:$src1, (loadf64 addr:$src2)))]>;
152 // ST(0) = ST(0) / [mem64]
153 def FpDIVR32m : FpI<(ops RFP:$dst, RFP:$src1, f32mem:$src2), OneArgFPRW,
154 [(set RFP:$dst, (fdiv (extloadf64f32 addr:$src2),
156 // ST(0) = [mem32] / ST(0)
157 def FpDIVR64m : FpI<(ops RFP:$dst, RFP:$src1, f64mem:$src2), OneArgFPRW,
158 [(set RFP:$dst, (fdiv (loadf64 addr:$src2), RFP:$src1))]>;
159 // ST(0) = [mem64] / ST(0)
162 def FADD32m : FPI<0xD8, MRM0m, (ops f32mem:$src), "fadd{s} $src">;
163 def FADD64m : FPI<0xDC, MRM0m, (ops f64mem:$src), "fadd{l} $src">;
164 def FMUL32m : FPI<0xD8, MRM1m, (ops f32mem:$src), "fmul{s} $src">;
165 def FMUL64m : FPI<0xDC, MRM1m, (ops f64mem:$src), "fmul{l} $src">;
166 def FSUB32m : FPI<0xD8, MRM4m, (ops f32mem:$src), "fsub{s} $src">;
167 def FSUB64m : FPI<0xDC, MRM4m, (ops f64mem:$src), "fsub{l} $src">;
168 def FSUBR32m : FPI<0xD8, MRM5m, (ops f32mem:$src), "fsubr{s} $src">;
169 def FSUBR64m : FPI<0xDC, MRM5m, (ops f64mem:$src), "fsubr{l} $src">;
170 def FDIV32m : FPI<0xD8, MRM6m, (ops f32mem:$src), "fdiv{s} $src">;
171 def FDIV64m : FPI<0xDC, MRM6m, (ops f64mem:$src), "fdiv{l} $src">;
172 def FDIVR32m : FPI<0xD8, MRM7m, (ops f32mem:$src), "fdivr{s} $src">;
173 def FDIVR64m : FPI<0xDC, MRM7m, (ops f64mem:$src), "fdivr{l} $src">;
175 def FpIADD16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
176 [(set RFP:$dst, (fadd RFP:$src1,
177 (X86fild addr:$src2, i16)))]>;
178 // ST(0) = ST(0) + [mem16int]
179 def FpIADD32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW,
180 [(set RFP:$dst, (fadd RFP:$src1,
181 (X86fild addr:$src2, i32)))]>;
182 // ST(0) = ST(0) + [mem32int]
183 def FpIMUL16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
184 [(set RFP:$dst, (fmul RFP:$src1,
185 (X86fild addr:$src2, i16)))]>;
186 // ST(0) = ST(0) * [mem16int]
187 def FpIMUL32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW,
188 [(set RFP:$dst, (fmul RFP:$src1,
189 (X86fild addr:$src2, i32)))]>;
190 // ST(0) = ST(0) * [mem32int]
191 def FpISUB16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
192 [(set RFP:$dst, (fsub RFP:$src1,
193 (X86fild addr:$src2, i16)))]>;
194 // ST(0) = ST(0) - [mem16int]
195 def FpISUB32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW,
196 [(set RFP:$dst, (fsub RFP:$src1,
197 (X86fild addr:$src2, i32)))]>;
198 // ST(0) = ST(0) - [mem32int]
199 def FpISUBR16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
200 [(set RFP:$dst, (fsub (X86fild addr:$src2, i16),
202 // ST(0) = [mem16int] - ST(0)
203 def FpISUBR32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW,
204 [(set RFP:$dst, (fsub (X86fild addr:$src2, i32),
206 // ST(0) = [mem32int] - ST(0)
207 def FpIDIV16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
208 [(set RFP:$dst, (fdiv RFP:$src1,
209 (X86fild addr:$src2, i16)))]>;
210 // ST(0) = ST(0) / [mem16int]
211 def FpIDIV32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW,
212 [(set RFP:$dst, (fdiv RFP:$src1,
213 (X86fild addr:$src2, i32)))]>;
214 // ST(0) = ST(0) / [mem32int]
215 def FpIDIVR16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
216 [(set RFP:$dst, (fdiv (X86fild addr:$src2, i16),
218 // ST(0) = [mem16int] / ST(0)
219 def FpIDIVR32m : FpI<(ops RFP:$dst, RFP:$src1, i32mem:$src2), OneArgFPRW,
220 [(set RFP:$dst, (fdiv (X86fild addr:$src2, i32),
222 // ST(0) = [mem32int] / ST(0)
224 def FIADD16m : FPI<0xDE, MRM0m, (ops i16mem:$src), "fiadd{s} $src">;
225 def FIADD32m : FPI<0xDA, MRM0m, (ops i32mem:$src), "fiadd{l} $src">;
226 def FIMUL16m : FPI<0xDE, MRM1m, (ops i16mem:$src), "fimul{s} $src">;
227 def FIMUL32m : FPI<0xDA, MRM1m, (ops i32mem:$src), "fimul{l} $src">;
228 def FISUB16m : FPI<0xDE, MRM4m, (ops i16mem:$src), "fisub{s} $src">;
229 def FISUB32m : FPI<0xDA, MRM4m, (ops i32mem:$src), "fisub{l} $src">;
230 def FISUBR16m : FPI<0xDE, MRM5m, (ops i16mem:$src), "fisubr{s} $src">;
231 def FISUBR32m : FPI<0xDA, MRM5m, (ops i32mem:$src), "fisubr{l} $src">;
232 def FIDIV16m : FPI<0xDE, MRM6m, (ops i16mem:$src), "fidiv{s} $src">;
233 def FIDIV32m : FPI<0xDA, MRM6m, (ops i32mem:$src), "fidiv{l} $src">;
234 def FIDIVR16m : FPI<0xDE, MRM7m, (ops i16mem:$src), "fidivr{s} $src">;
235 def FIDIVR32m : FPI<0xDA, MRM7m, (ops i32mem:$src), "fidivr{l} $src">;
237 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
238 // of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
239 // we have to put some 'r's in and take them out of weird places.
240 def FADDST0r : FPST0rInst <0xC0, "fadd $op">;
241 def FADDrST0 : FPrST0Inst <0xC0, "fadd {%st(0), $op|$op, %ST(0)}">;
242 def FADDPrST0 : FPrST0PInst<0xC0, "faddp $op">;
243 def FSUBRST0r : FPST0rInst <0xE8, "fsubr $op">;
244 def FSUBrST0 : FPrST0Inst <0xE8, "fsub{r} {%st(0), $op|$op, %ST(0)}">;
245 def FSUBPrST0 : FPrST0PInst<0xE8, "fsub{r}p $op">;
246 def FSUBST0r : FPST0rInst <0xE0, "fsub $op">;
247 def FSUBRrST0 : FPrST0Inst <0xE0, "fsub{|r} {%st(0), $op|$op, %ST(0)}">;
248 def FSUBRPrST0 : FPrST0PInst<0xE0, "fsub{|r}p $op">;
249 def FMULST0r : FPST0rInst <0xC8, "fmul $op">;
250 def FMULrST0 : FPrST0Inst <0xC8, "fmul {%st(0), $op|$op, %ST(0)}">;
251 def FMULPrST0 : FPrST0PInst<0xC8, "fmulp $op">;
252 def FDIVRST0r : FPST0rInst <0xF8, "fdivr $op">;
253 def FDIVrST0 : FPrST0Inst <0xF8, "fdiv{r} {%st(0), $op|$op, %ST(0)}">;
254 def FDIVPrST0 : FPrST0PInst<0xF8, "fdiv{r}p $op">;
255 def FDIVST0r : FPST0rInst <0xF0, "fdiv $op">;
256 def FDIVRrST0 : FPrST0Inst <0xF0, "fdiv{|r} {%st(0), $op|$op, %ST(0)}">;
257 def FDIVRPrST0 : FPrST0PInst<0xF0, "fdiv{|r}p $op">;
261 def FpCHS : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW,
262 [(set RFP:$dst, (fneg RFP:$src))]>;
263 def FpABS : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW,
264 [(set RFP:$dst, (fabs RFP:$src))]>;
265 def FpSQRT : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW,
266 [(set RFP:$dst, (fsqrt RFP:$src))]>;
267 def FpSIN : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW,
268 [(set RFP:$dst, (fsin RFP:$src))]>;
269 def FpCOS : FpI<(ops RFP:$dst, RFP:$src), OneArgFPRW,
270 [(set RFP:$dst, (fcos RFP:$src))]>;
271 def FpTST : FpI<(ops RFP:$src), OneArgFP,
274 def FCHS : FPI<0xE0, RawFrm, (ops), "fchs">, D9;
275 def FABS : FPI<0xE1, RawFrm, (ops), "fabs">, D9;
276 def FSQRT : FPI<0xFA, RawFrm, (ops), "fsqrt">, D9;
277 def FSIN : FPI<0xFE, RawFrm, (ops), "fsin">, D9;
278 def FCOS : FPI<0xFF, RawFrm, (ops), "fcos">, D9;
279 def FTST : FPI<0xE4, RawFrm, (ops), "ftst">, D9;
282 // Floating point cmovs.
283 let isTwoAddress = 1 in {
284 def FpCMOVB : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
285 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
287 def FpCMOVBE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
288 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
290 def FpCMOVE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
291 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
293 def FpCMOVP : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
294 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
296 def FpCMOVNB : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
297 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
299 def FpCMOVNBE: FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
300 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
302 def FpCMOVNE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
303 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
305 def FpCMOVNP : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
306 [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
310 def FCMOVB : FPI<0xC0, AddRegFrm, (ops RST:$op),
311 "fcmovb {$op, %st(0)|%ST(0), $op}">, DA;
312 def FCMOVBE : FPI<0xD0, AddRegFrm, (ops RST:$op),
313 "fcmovbe {$op, %st(0)|%ST(0), $op}">, DA;
314 def FCMOVE : FPI<0xC8, AddRegFrm, (ops RST:$op),
315 "fcmove {$op, %st(0)|%ST(0), $op}">, DA;
316 def FCMOVP : FPI<0xD8, AddRegFrm, (ops RST:$op),
317 "fcmovu {$op, %st(0)|%ST(0), $op}">, DA;
318 def FCMOVNB : FPI<0xC0, AddRegFrm, (ops RST:$op),
319 "fcmovnb {$op, %st(0)|%ST(0), $op}">, DB;
320 def FCMOVNBE : FPI<0xD0, AddRegFrm, (ops RST:$op),
321 "fcmovnbe {$op, %st(0)|%ST(0), $op}">, DB;
322 def FCMOVNE : FPI<0xC8, AddRegFrm, (ops RST:$op),
323 "fcmovne {$op, %st(0)|%ST(0), $op}">, DB;
324 def FCMOVNP : FPI<0xD8, AddRegFrm, (ops RST:$op),
325 "fcmovnu {$op, %st(0)|%ST(0), $op}">, DB;
327 // Floating point loads & stores.
328 def FpLD32m : FpI<(ops RFP:$dst, f32mem:$src), ZeroArgFP,
329 [(set RFP:$dst, (extloadf64f32 addr:$src))]>;
330 def FpLD64m : FpI<(ops RFP:$dst, f64mem:$src), ZeroArgFP,
331 [(set RFP:$dst, (loadf64 addr:$src))]>;
332 def FpILD16m : FpI<(ops RFP:$dst, i16mem:$src), ZeroArgFP,
333 [(set RFP:$dst, (X86fild addr:$src, i16))]>;
334 def FpILD32m : FpI<(ops RFP:$dst, i32mem:$src), ZeroArgFP,
335 [(set RFP:$dst, (X86fild addr:$src, i32))]>;
336 def FpILD64m : FpI<(ops RFP:$dst, i64mem:$src), ZeroArgFP,
337 [(set RFP:$dst, (X86fild addr:$src, i64))]>;
339 def FpST32m : FpI<(ops f32mem:$op, RFP:$src), OneArgFP,
340 [(truncstore RFP:$src, addr:$op, f32)]>;
341 def FpST64m : FpI<(ops f64mem:$op, RFP:$src), OneArgFP,
342 [(store RFP:$src, addr:$op)]>;
344 def FpSTP32m : FpI<(ops f32mem:$op, RFP:$src), OneArgFP, []>;
345 def FpSTP64m : FpI<(ops f64mem:$op, RFP:$src), OneArgFP, []>;
346 def FpIST16m : FpI<(ops i16mem:$op, RFP:$src), OneArgFP, []>;
347 def FpIST32m : FpI<(ops i32mem:$op, RFP:$src), OneArgFP, []>;
348 def FpIST64m : FpI<(ops i64mem:$op, RFP:$src), OneArgFP, []>;
350 def FLD32m : FPI<0xD9, MRM0m, (ops f32mem:$src), "fld{s} $src">;
351 def FLD64m : FPI<0xDD, MRM0m, (ops f64mem:$src), "fld{l} $src">;
352 def FILD16m : FPI<0xDF, MRM0m, (ops i16mem:$src), "fild{s} $src">;
353 def FILD32m : FPI<0xDB, MRM0m, (ops i32mem:$src), "fild{l} $src">;
354 def FILD64m : FPI<0xDF, MRM5m, (ops i64mem:$src), "fild{ll} $src">;
355 def FST32m : FPI<0xD9, MRM2m, (ops f32mem:$dst), "fst{s} $dst">;
356 def FST64m : FPI<0xDD, MRM2m, (ops f64mem:$dst), "fst{l} $dst">;
357 def FSTP32m : FPI<0xD9, MRM3m, (ops f32mem:$dst), "fstp{s} $dst">;
358 def FSTP64m : FPI<0xDD, MRM3m, (ops f64mem:$dst), "fstp{l} $dst">;
359 def FIST16m : FPI<0xDF, MRM2m, (ops i16mem:$dst), "fist{s} $dst">;
360 def FIST32m : FPI<0xDB, MRM2m, (ops i32mem:$dst), "fist{l} $dst">;
361 def FISTP16m : FPI<0xDF, MRM3m, (ops i16mem:$dst), "fistp{s} $dst">;
362 def FISTP32m : FPI<0xDB, MRM3m, (ops i32mem:$dst), "fistp{l} $dst">;
363 def FISTP64m : FPI<0xDF, MRM7m, (ops i64mem:$dst), "fistp{ll} $dst">;
365 // FISTTP requires SSE3 even though it's a FPStack op.
366 def FpISTT16m : FpI_<(ops i16mem:$op, RFP:$src), OneArgFP,
367 [(X86fp_to_i16mem RFP:$src, addr:$op)]>,
369 def FpISTT32m : FpI_<(ops i32mem:$op, RFP:$src), OneArgFP,
370 [(X86fp_to_i32mem RFP:$src, addr:$op)]>,
372 def FpISTT64m : FpI_<(ops i64mem:$op, RFP:$src), OneArgFP,
373 [(X86fp_to_i64mem RFP:$src, addr:$op)]>,
376 def FISTTP16m : FPI<0xDF, MRM1m, (ops i16mem:$dst), "fisttp{s} $dst">;
377 def FISTTP32m : FPI<0xDB, MRM1m, (ops i32mem:$dst), "fisttp{l} $dst">;
378 def FISTTP64m : FPI<0xDD, MRM1m, (ops i64mem:$dst), "fisttp{ll} $dst">;
380 // FP Stack manipulation instructions.
381 def FLDrr : FPI<0xC0, AddRegFrm, (ops RST:$op), "fld $op">, D9;
382 def FSTrr : FPI<0xD0, AddRegFrm, (ops RST:$op), "fst $op">, DD;
383 def FSTPrr : FPI<0xD8, AddRegFrm, (ops RST:$op), "fstp $op">, DD;
384 def FXCH : FPI<0xC8, AddRegFrm, (ops RST:$op), "fxch $op">, D9;
386 // Floating point constant loads.
387 def FpLD0 : FpI<(ops RFP:$dst), ZeroArgFP,
388 [(set RFP:$dst, fp64imm0)]>;
389 def FpLD1 : FpI<(ops RFP:$dst), ZeroArgFP,
390 [(set RFP:$dst, fp64imm1)]>;
392 def FLD0 : FPI<0xEE, RawFrm, (ops), "fldz">, D9;
393 def FLD1 : FPI<0xE8, RawFrm, (ops), "fld1">, D9;
396 // Floating point compares.
397 def FpUCOMr : FpI<(ops RFP:$lhs, RFP:$rhs), CompareFP,
398 []>; // FPSW = cmp ST(0) with ST(i)
399 def FpUCOMIr : FpI<(ops RFP:$lhs, RFP:$rhs), CompareFP,
400 [(X86cmp RFP:$lhs, RFP:$rhs)]>; // CC = cmp ST(0) with ST(i)
402 def FUCOMr : FPI<0xE0, AddRegFrm, // FPSW = cmp ST(0) with ST(i)
404 "fucom $reg">, DD, Imp<[ST0],[]>;
405 def FUCOMPr : FPI<0xE8, AddRegFrm, // FPSW = cmp ST(0) with ST(i), pop
407 "fucomp $reg">, DD, Imp<[ST0],[]>;
408 def FUCOMPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
410 "fucompp">, DA, Imp<[ST0],[]>;
412 def FUCOMIr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i)
414 "fucomi {$reg, %st(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>;
415 def FUCOMIPr : FPI<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop
417 "fucomip {$reg, %st(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>;
420 // Floating point flag ops.
421 def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags
422 (ops), "fnstsw", []>, DF, Imp<[],[AX]>;
424 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
425 (ops i16mem:$dst), "fnstcw $dst", []>;
426 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
427 (ops i16mem:$dst), "fldcw $dst", []>;
429 //===----------------------------------------------------------------------===//
430 // Non-Instruction Patterns
431 //===----------------------------------------------------------------------===//
433 // Required for RET of f32 / f64 values.
434 def : Pat<(X86fld addr:$src, f32), (FpLD32m addr:$src)>;
435 def : Pat<(X86fld addr:$src, f64), (FpLD64m addr:$src)>;
437 // Required for CALL which return f32 / f64 values.
438 def : Pat<(X86fst RFP:$src, addr:$op, f32), (FpST32m addr:$op, RFP:$src)>;
439 def : Pat<(X86fst RFP:$src, addr:$op, f64), (FpST64m addr:$op, RFP:$src)>;
441 // Floating point constant -0.0 and -1.0
442 def : Pat<(f64 fp64immneg0), (FpCHS (FpLD0))>, Requires<[FPStack]>;
443 def : Pat<(f64 fp64immneg1), (FpCHS (FpLD1))>, Requires<[FPStack]>;
445 // Used to conv. i64 to f64 since there isn't a SSE version.
446 def : Pat<(X86fildflag addr:$src, i64), (FpILD64m addr:$src)>;