lib/Target/X86/X86InstrFMA.td

   1 //====- X86InstrFMA.td - Describe the X86 Instruction Set --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes FMA (Fused Multiply-Add) instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // FMA3 - Intel 3 operand Fused Multiply-Add instructions
  16 //===----------------------------------------------------------------------===//
  17
  18 multiclass fma3p_rm<bits<8> opc, string OpcodeStr> {
  19   def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
  20            (ins VR128:$src1, VR128:$src2),
  21            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
  22            []>;
  23   def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
  24            (ins VR128:$src1, f128mem:$src2),
  25            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
  26            []>;
  27   def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
  28            (ins VR256:$src1, VR256:$src2),
  29            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
  30            []>;
  31   def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
  32            (ins VR256:$src1, f256mem:$src2),
  33            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
  34            []>;
  35 }
  36
  37 multiclass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
  38                        string OpcodeStr, string PackTy> {
  39   defm r132 : fma3p_rm<opc132, !strconcat(OpcodeStr, !strconcat("132", PackTy))>;
  40   defm r213 : fma3p_rm<opc213, !strconcat(OpcodeStr, !strconcat("213", PackTy))>;
  41   defm r231 : fma3p_rm<opc231, !strconcat(OpcodeStr, !strconcat("231", PackTy))>;
  42 }
  43
  44 // Fused Multiply-Add
  45 let ExeDomain = SSEPackedSingle in {
  46   defm VFMADDPS    : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps">;
  47   defm VFMSUBPS    : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps">;
  48   defm VFMADDSUBPS : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps">;
  49   defm VFMSUBADDPS : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps">;
  50 }
  51
  52 let ExeDomain = SSEPackedDouble in {
  53   defm VFMADDPD    : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd">, VEX_W;
  54   defm VFMSUBPD    : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd">, VEX_W;
  55   defm VFMADDSUBPD : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd">, VEX_W;
  56   defm VFMSUBADDPD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd">, VEX_W;
  57 }
  58
  59 // Fused Negative Multiply-Add
  60 let ExeDomain = SSEPackedSingle in {
  61   defm VFNMADDPS : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps">;
  62   defm VFNMSUBPS : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps">;
  63 }
  64 let ExeDomain = SSEPackedDouble in {
  65   defm VFNMADDPD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd">, VEX_W;
  66   defm VFNMSUBPD : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd">, VEX_W;
  67 }
  68
  69 multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop> {
  70   def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
  71            (ins VR128:$src1, VR128:$src2),
  72            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
  73            []>;
  74   def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
  75            (ins VR128:$src1, x86memop:$src2),
  76            !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
  77            []>;
  78 }
  79
  80 multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
  81                        string OpcodeStr> {
  82   defm SSr132 : fma3s_rm<opc132, !strconcat(OpcodeStr, "132ss"), f32mem>;
  83   defm SSr213 : fma3s_rm<opc213, !strconcat(OpcodeStr, "213ss"), f32mem>;
  84   defm SSr231 : fma3s_rm<opc231, !strconcat(OpcodeStr, "231ss"), f32mem>;
  85   defm SDr132 : fma3s_rm<opc132, !strconcat(OpcodeStr, "132sd"), f64mem>, VEX_W;
  86   defm SDr213 : fma3s_rm<opc213, !strconcat(OpcodeStr, "213sd"), f64mem>, VEX_W;
  87   defm SDr231 : fma3s_rm<opc231, !strconcat(OpcodeStr, "231sd"), f64mem>, VEX_W;
  88 }
  89
  90 defm VFMADD : fma3s_forms<0x99, 0xA9, 0xB9, "vfmadd">;
  91 defm VFMSUB : fma3s_forms<0x9B, 0xAB, 0xBB, "vfmsub">;
  92
  93 defm VFNMADD : fma3s_forms<0x9D, 0xAD, 0xBD, "vfnmadd">;
  94 defm VFNMSUB : fma3s_forms<0x9F, 0xAF, 0xBF, "vfnmsub">;
  95
  96 //===----------------------------------------------------------------------===//
  97 // FMA4 - AMD 4 operand Fused Multiply-Add instructions
  98 //===----------------------------------------------------------------------===//
  99
 100
 101 multiclass fma4s<bits<8> opc, string OpcodeStr> {
 102   def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
 103            (ins VR128:$src1, VR128:$src2, VR128:$src3),
 104            !strconcat(OpcodeStr,
 105            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
 106            []>, XOP_W;
 107   def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
 108            (ins VR128:$src1, VR128:$src2, f128mem:$src3),
 109            !strconcat(OpcodeStr,
 110            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
 111            []>, XOP_W;
 112   def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
 113            (ins VR128:$src1, f128mem:$src2, VR128:$src3),
 114            !strconcat(OpcodeStr,
 115            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
 116            []>;
 117
 118 }
 119
 120 multiclass fma4p<bits<8> opc, string OpcodeStr> {
 121   def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
 122            (ins VR128:$src1, VR128:$src2, VR128:$src3),
 123            !strconcat(OpcodeStr,
 124            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
 125            []>, XOP_W;
 126   def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
 127            (ins VR128:$src1, VR128:$src2, f128mem:$src3),
 128            !strconcat(OpcodeStr,
 129            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
 130            []>, XOP_W;
 131   def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
 132            (ins VR128:$src1, f128mem:$src2, VR128:$src3),
 133            !strconcat(OpcodeStr,
 134            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
 135            []>;
 136   def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
 137            (ins VR256:$src1, VR256:$src2, VR256:$src3),
 138            !strconcat(OpcodeStr,
 139            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
 140            []>, XOP_W;
 141   def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
 142            (ins VR256:$src1, VR256:$src2, f256mem:$src3),
 143            !strconcat(OpcodeStr,
 144            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
 145            []>, XOP_W;
 146   def mrY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
 147            (ins VR256:$src1, f256mem:$src2, VR256:$src3),
 148            !strconcat(OpcodeStr,
 149            "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
 150            []>;
 151 }
 152
 153 let isAsmParserOnly = 1 in {
 154   defm VFMADDSS4    : fma4s<0x6A, "vfmaddss">;
 155   defm VFMADDSD4    : fma4s<0x6B, "vfmaddsd">;
 156   defm VFMADDPS4    : fma4p<0x68, "vfmaddps">;
 157   defm VFMADDPD4    : fma4p<0x69, "vfmaddpd">;
 158   defm VFMSUBSS4    : fma4s<0x6E, "vfmsubss">;
 159   defm VFMSUBSD4    : fma4s<0x6F, "vfmsubsd">;
 160   defm VFMSUBPS4    : fma4p<0x6C, "vfmsubps">;
 161   defm VFMSUBPD4    : fma4p<0x6D, "vfmsubpd">;
 162   defm VFNMADDSS4   : fma4s<0x7A, "vfnmaddss">;
 163   defm VFNMADDSD4   : fma4s<0x7B, "vfnmaddsd">;
 164   defm VFNMADDPS4   : fma4p<0x78, "vfnmaddps">;
 165   defm VFNMADDPD4   : fma4p<0x79, "vfnmaddpd">;
 166   defm VFNMSUBSS4   : fma4s<0x7E, "vfnmsubss">;
 167   defm VFNMSUBSD4   : fma4s<0x7F, "vfnmsubsd">;
 168   defm VFNMSUBPS4   : fma4p<0x7C, "vfnmsubps">;
 169   defm VFNMSUBPD4   : fma4p<0x7D, "vfnmsubpd">;
 170   defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps">;
 171   defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd">;
 172   defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps">;
 173   defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd">;
 174 }
 175
 176 // FMA4 Intrinsics patterns
 177
 178 // VFMADD
 179 def : Pat<(int_x86_fma4_vfmadd_ss VR128:$src1, VR128:$src2, VR128:$src3),
 180           (VFMADDSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 181 def : Pat<(int_x86_fma4_vfmadd_ss VR128:$src1, VR128:$src2,
 182                                   (alignedloadv4f32 addr:$src3)),
 183           (VFMADDSS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 184 def : Pat<(int_x86_fma4_vfmadd_ss VR128:$src1, (alignedloadv4f32 addr:$src2),
 185                                   VR128:$src3),
 186           (VFMADDSS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 187
 188 def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, VR128:$src2, VR128:$src3),
 189           (VFMADDSD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 190 def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, VR128:$src2,
 191                                   (alignedloadv2f64 addr:$src3)),
 192           (VFMADDSD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 193 def : Pat<(int_x86_fma4_vfmadd_sd VR128:$src1, (alignedloadv2f64 addr:$src2),
 194                                   VR128:$src3),
 195           (VFMADDSD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 196
 197 def : Pat<(int_x86_fma4_vfmadd_ps VR128:$src1, VR128:$src2, VR128:$src3),
 198           (VFMADDPS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 199 def : Pat<(int_x86_fma4_vfmadd_ps VR128:$src1, VR128:$src2,
 200                                   (alignedloadv4f32 addr:$src3)),
 201           (VFMADDPS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 202 def : Pat<(int_x86_fma4_vfmadd_ps VR128:$src1, (alignedloadv4f32 addr:$src2),
 203                                   VR128:$src3),
 204           (VFMADDPS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 205
 206 def : Pat<(int_x86_fma4_vfmadd_pd VR128:$src1, VR128:$src2, VR128:$src3),
 207           (VFMADDPD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 208 def : Pat<(int_x86_fma4_vfmadd_pd VR128:$src1, VR128:$src2,
 209                                   (alignedloadv2f64 addr:$src3)),
 210           (VFMADDPD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 211 def : Pat<(int_x86_fma4_vfmadd_pd VR128:$src1, (alignedloadv2f64 addr:$src2),
 212                                   VR128:$src3),
 213           (VFMADDPD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 214
 215 def : Pat<(int_x86_fma4_vfmadd_ps_256 VR256:$src1, VR256:$src2, VR256:$src3),
 216           (VFMADDPS4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 217 def : Pat<(int_x86_fma4_vfmadd_ps_256 VR256:$src1, VR256:$src2,
 218                                   (alignedloadv8f32 addr:$src3)),
 219           (VFMADDPS4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 220 def : Pat<(int_x86_fma4_vfmadd_ps_256 VR256:$src1,
 221                                       (alignedloadv8f32 addr:$src2),
 222                                       VR256:$src3),
 223           (VFMADDPS4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
 224
 225 def : Pat<(int_x86_fma4_vfmadd_pd_256 VR256:$src1, VR256:$src2, VR256:$src3),
 226           (VFMADDPD4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 227 def : Pat<(int_x86_fma4_vfmadd_pd_256 VR256:$src1, VR256:$src2,
 228                                   (alignedloadv4f64 addr:$src3)),
 229           (VFMADDPD4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 230 def : Pat<(int_x86_fma4_vfmadd_pd_256 VR256:$src1,
 231                                       (alignedloadv4f64 addr:$src2),
 232                                       VR256:$src3),
 233           (VFMADDPD4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
 234
 235 // VFMSUB
 236 def : Pat<(int_x86_fma4_vfmsub_ss VR128:$src1, VR128:$src2, VR128:$src3),
 237           (VFMSUBSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 238 def : Pat<(int_x86_fma4_vfmsub_ss VR128:$src1, VR128:$src2,
 239                                   (alignedloadv4f32 addr:$src3)),
 240           (VFMSUBSS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 241 def : Pat<(int_x86_fma4_vfmsub_ss VR128:$src1, (alignedloadv4f32 addr:$src2),
 242                                   VR128:$src3),
 243           (VFMSUBSS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 244
 245 def : Pat<(int_x86_fma4_vfmsub_sd VR128:$src1, VR128:$src2, VR128:$src3),
 246           (VFMSUBSD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 247 def : Pat<(int_x86_fma4_vfmsub_sd VR128:$src1, VR128:$src2,
 248                                   (alignedloadv2f64 addr:$src3)),
 249           (VFMSUBSD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 250 def : Pat<(int_x86_fma4_vfmsub_sd VR128:$src1, (alignedloadv2f64 addr:$src2),
 251                                   VR128:$src3),
 252           (VFMSUBSD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 253
 254 def : Pat<(int_x86_fma4_vfmsub_ps VR128:$src1, VR128:$src2, VR128:$src3),
 255           (VFMSUBPS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 256 def : Pat<(int_x86_fma4_vfmsub_ps VR128:$src1, VR128:$src2,
 257                                   (alignedloadv4f32 addr:$src3)),
 258           (VFMSUBPS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 259 def : Pat<(int_x86_fma4_vfmsub_ps VR128:$src1, (alignedloadv4f32 addr:$src2),
 260                                   VR128:$src3),
 261           (VFMSUBPS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 262
 263 def : Pat<(int_x86_fma4_vfmsub_pd VR128:$src1, VR128:$src2, VR128:$src3),
 264           (VFMSUBPD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 265 def : Pat<(int_x86_fma4_vfmsub_pd VR128:$src1, VR128:$src2,
 266                                   (alignedloadv2f64 addr:$src3)),
 267           (VFMSUBPD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 268 def : Pat<(int_x86_fma4_vfmsub_pd VR128:$src1, (alignedloadv2f64 addr:$src2),
 269                                   VR128:$src3),
 270           (VFMSUBPD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 271
 272 def : Pat<(int_x86_fma4_vfmsub_ps_256 VR256:$src1, VR256:$src2, VR256:$src3),
 273           (VFMSUBPS4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 274 def : Pat<(int_x86_fma4_vfmsub_ps_256 VR256:$src1, VR256:$src2,
 275                                   (alignedloadv8f32 addr:$src3)),
 276           (VFMSUBPS4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 277 def : Pat<(int_x86_fma4_vfmsub_ps_256 VR256:$src1,
 278                                       (alignedloadv8f32 addr:$src2),
 279                                       VR256:$src3),
 280           (VFMSUBPS4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
 281
 282 def : Pat<(int_x86_fma4_vfmsub_pd_256 VR256:$src1, VR256:$src2, VR256:$src3),
 283           (VFMSUBPD4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 284 def : Pat<(int_x86_fma4_vfmsub_pd_256 VR256:$src1, VR256:$src2,
 285                                   (alignedloadv4f64 addr:$src3)),
 286           (VFMSUBPD4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 287 def : Pat<(int_x86_fma4_vfmsub_pd_256 VR256:$src1,
 288                                       (alignedloadv4f64 addr:$src2),
 289                                       VR256:$src3),
 290           (VFMSUBPD4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
 291
 292 // VFNMADD
 293 def : Pat<(int_x86_fma4_vfnmadd_ss VR128:$src1, VR128:$src2, VR128:$src3),
 294           (VFNMADDSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 295 def : Pat<(int_x86_fma4_vfnmadd_ss VR128:$src1, VR128:$src2,
 296                                   (alignedloadv4f32 addr:$src3)),
 297           (VFNMADDSS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 298 def : Pat<(int_x86_fma4_vfnmadd_ss VR128:$src1, (alignedloadv4f32 addr:$src2),
 299                                   VR128:$src3),
 300           (VFNMADDSS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 301
 302 def : Pat<(int_x86_fma4_vfnmadd_sd VR128:$src1, VR128:$src2, VR128:$src3),
 303           (VFNMADDSD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 304 def : Pat<(int_x86_fma4_vfnmadd_sd VR128:$src1, VR128:$src2,
 305                                   (alignedloadv2f64 addr:$src3)),
 306           (VFNMADDSD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 307 def : Pat<(int_x86_fma4_vfnmadd_sd VR128:$src1, (alignedloadv2f64 addr:$src2),
 308                                   VR128:$src3),
 309           (VFNMADDSD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 310
 311 def : Pat<(int_x86_fma4_vfnmadd_ps VR128:$src1, VR128:$src2, VR128:$src3),
 312           (VFNMADDPS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 313 def : Pat<(int_x86_fma4_vfnmadd_ps VR128:$src1, VR128:$src2,
 314                                   (alignedloadv4f32 addr:$src3)),
 315           (VFNMADDPS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 316 def : Pat<(int_x86_fma4_vfnmadd_ps VR128:$src1, (alignedloadv4f32 addr:$src2),
 317                                   VR128:$src3),
 318           (VFNMADDPS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 319
 320 def : Pat<(int_x86_fma4_vfnmadd_pd VR128:$src1, VR128:$src2, VR128:$src3),
 321           (VFNMADDPD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 322 def : Pat<(int_x86_fma4_vfnmadd_pd VR128:$src1, VR128:$src2,
 323                                   (alignedloadv2f64 addr:$src3)),
 324           (VFNMADDPD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 325 def : Pat<(int_x86_fma4_vfnmadd_pd VR128:$src1, (alignedloadv2f64 addr:$src2),
 326                                   VR128:$src3),
 327           (VFNMADDPD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 328
 329 def : Pat<(int_x86_fma4_vfnmadd_ps_256 VR256:$src1, VR256:$src2, VR256:$src3),
 330           (VFNMADDPS4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 331 def : Pat<(int_x86_fma4_vfnmadd_ps_256 VR256:$src1, VR256:$src2,
 332                                   (alignedloadv8f32 addr:$src3)),
 333           (VFNMADDPS4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 334 def : Pat<(int_x86_fma4_vfnmadd_ps_256 VR256:$src1,
 335                                       (alignedloadv8f32 addr:$src2),
 336                                       VR256:$src3),
 337           (VFNMADDPS4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
 338
 339 def : Pat<(int_x86_fma4_vfnmadd_pd_256 VR256:$src1, VR256:$src2, VR256:$src3),
 340           (VFNMADDPD4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 341 def : Pat<(int_x86_fma4_vfnmadd_pd_256 VR256:$src1, VR256:$src2,
 342                                   (alignedloadv4f64 addr:$src3)),
 343           (VFNMADDPD4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 344 def : Pat<(int_x86_fma4_vfnmadd_pd_256 VR256:$src1,
 345                                       (alignedloadv4f64 addr:$src2),
 346                                       VR256:$src3),
 347           (VFNMADDPD4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
 348
 349 // VFNMSUB
 350 def : Pat<(int_x86_fma4_vfnmsub_ss VR128:$src1, VR128:$src2, VR128:$src3),
 351           (VFNMSUBSS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 352 def : Pat<(int_x86_fma4_vfnmsub_ss VR128:$src1, VR128:$src2,
 353                                   (alignedloadv4f32 addr:$src3)),
 354           (VFNMSUBSS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 355 def : Pat<(int_x86_fma4_vfnmsub_ss VR128:$src1, (alignedloadv4f32 addr:$src2),
 356                                   VR128:$src3),
 357           (VFNMSUBSS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 358
 359 def : Pat<(int_x86_fma4_vfnmsub_sd VR128:$src1, VR128:$src2, VR128:$src3),
 360           (VFNMSUBSD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 361 def : Pat<(int_x86_fma4_vfnmsub_sd VR128:$src1, VR128:$src2,
 362                                   (alignedloadv2f64 addr:$src3)),
 363           (VFNMSUBSD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 364 def : Pat<(int_x86_fma4_vfnmsub_sd VR128:$src1, (alignedloadv2f64 addr:$src2),
 365                                   VR128:$src3),
 366           (VFNMSUBSD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 367
 368 def : Pat<(int_x86_fma4_vfnmsub_ps VR128:$src1, VR128:$src2, VR128:$src3),
 369           (VFNMSUBPS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 370 def : Pat<(int_x86_fma4_vfnmsub_ps VR128:$src1, VR128:$src2,
 371                                   (alignedloadv4f32 addr:$src3)),
 372           (VFNMSUBPS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 373 def : Pat<(int_x86_fma4_vfnmsub_ps VR128:$src1, (alignedloadv4f32 addr:$src2),
 374                                   VR128:$src3),
 375           (VFNMSUBPS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 376
 377 def : Pat<(int_x86_fma4_vfnmsub_pd VR128:$src1, VR128:$src2, VR128:$src3),
 378           (VFNMSUBPD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 379 def : Pat<(int_x86_fma4_vfnmsub_pd VR128:$src1, VR128:$src2,
 380                                   (alignedloadv2f64 addr:$src3)),
 381           (VFNMSUBPD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 382 def : Pat<(int_x86_fma4_vfnmsub_pd VR128:$src1, (alignedloadv2f64 addr:$src2),
 383                                   VR128:$src3),
 384           (VFNMSUBPD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 385
 386 def : Pat<(int_x86_fma4_vfnmsub_ps_256 VR256:$src1, VR256:$src2, VR256:$src3),
 387           (VFNMSUBPS4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 388 def : Pat<(int_x86_fma4_vfnmsub_ps_256 VR256:$src1, VR256:$src2,
 389                                   (alignedloadv8f32 addr:$src3)),
 390           (VFNMSUBPS4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 391 def : Pat<(int_x86_fma4_vfnmsub_ps_256 VR256:$src1,
 392                                       (alignedloadv8f32 addr:$src2),
 393                                       VR256:$src3),
 394           (VFNMSUBPS4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
 395
 396 def : Pat<(int_x86_fma4_vfnmsub_pd_256 VR256:$src1, VR256:$src2, VR256:$src3),
 397           (VFNMSUBPD4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 398 def : Pat<(int_x86_fma4_vfnmsub_pd_256 VR256:$src1, VR256:$src2,
 399                                   (alignedloadv4f64 addr:$src3)),
 400           (VFNMSUBPD4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 401 def : Pat<(int_x86_fma4_vfnmsub_pd_256 VR256:$src1,
 402                                       (alignedloadv4f64 addr:$src2),
 403                                       VR256:$src3),
 404           (VFNMSUBPD4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
 405
 406 // VFMADDSUB
 407 def : Pat<(int_x86_fma4_vfmaddsub_ps VR128:$src1, VR128:$src2, VR128:$src3),
 408           (VFMADDSUBPS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 409 def : Pat<(int_x86_fma4_vfmaddsub_ps VR128:$src1, VR128:$src2,
 410                                   (alignedloadv4f32 addr:$src3)),
 411           (VFMADDSUBPS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 412 def : Pat<(int_x86_fma4_vfmaddsub_ps VR128:$src1, (alignedloadv4f32 addr:$src2),
 413                                   VR128:$src3),
 414           (VFMADDSUBPS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 415
 416 def : Pat<(int_x86_fma4_vfmaddsub_pd VR128:$src1, VR128:$src2, VR128:$src3),
 417           (VFMADDSUBPD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 418 def : Pat<(int_x86_fma4_vfmaddsub_pd VR128:$src1, VR128:$src2,
 419                                   (alignedloadv2f64 addr:$src3)),
 420           (VFMADDSUBPD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 421 def : Pat<(int_x86_fma4_vfmaddsub_pd VR128:$src1, (alignedloadv2f64 addr:$src2),
 422                                   VR128:$src3),
 423           (VFMADDSUBPD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 424
 425 def : Pat<(int_x86_fma4_vfmaddsub_ps_256 VR256:$src1, VR256:$src2, VR256:$src3),
 426           (VFMADDSUBPS4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 427 def : Pat<(int_x86_fma4_vfmaddsub_ps_256 VR256:$src1, VR256:$src2,
 428                                   (alignedloadv8f32 addr:$src3)),
 429           (VFMADDSUBPS4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 430 def : Pat<(int_x86_fma4_vfmaddsub_ps_256 VR256:$src1,
 431                                       (alignedloadv8f32 addr:$src2),
 432                                       VR256:$src3),
 433           (VFMADDSUBPS4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
 434
 435 def : Pat<(int_x86_fma4_vfmaddsub_pd_256 VR256:$src1, VR256:$src2, VR256:$src3),
 436           (VFMADDSUBPD4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 437 def : Pat<(int_x86_fma4_vfmaddsub_pd_256 VR256:$src1, VR256:$src2,
 438                                   (alignedloadv4f64 addr:$src3)),
 439           (VFMADDSUBPD4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 440 def : Pat<(int_x86_fma4_vfmaddsub_pd_256 VR256:$src1,
 441                                       (alignedloadv4f64 addr:$src2),
 442                                       VR256:$src3),
 443           (VFMADDSUBPD4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
 444
 445 // VFMSUBADD
 446 def : Pat<(int_x86_fma4_vfmsubadd_ps VR128:$src1, VR128:$src2, VR128:$src3),
 447           (VFMSUBADDPS4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 448 def : Pat<(int_x86_fma4_vfmsubadd_ps VR128:$src1, VR128:$src2,
 449                                   (alignedloadv4f32 addr:$src3)),
 450           (VFMSUBADDPS4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 451 def : Pat<(int_x86_fma4_vfmsubadd_ps VR128:$src1, (alignedloadv4f32 addr:$src2),
 452                                   VR128:$src3),
 453           (VFMSUBADDPS4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 454
 455 def : Pat<(int_x86_fma4_vfmsubadd_pd VR128:$src1, VR128:$src2, VR128:$src3),
 456           (VFMSUBADDPD4rr VR128:$src1, VR128:$src2, VR128:$src3)>;
 457 def : Pat<(int_x86_fma4_vfmsubadd_pd VR128:$src1, VR128:$src2,
 458                                   (alignedloadv2f64 addr:$src3)),
 459           (VFMSUBADDPD4rm VR128:$src1, VR128:$src2, addr:$src3)>;
 460 def : Pat<(int_x86_fma4_vfmsubadd_pd VR128:$src1, (alignedloadv2f64 addr:$src2),
 461                                   VR128:$src3),
 462           (VFMSUBADDPD4mr VR128:$src1, addr:$src2, VR128:$src3)>;
 463
 464 def : Pat<(int_x86_fma4_vfmsubadd_ps_256 VR256:$src1, VR256:$src2, VR256:$src3),
 465           (VFMSUBADDPS4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 466 def : Pat<(int_x86_fma4_vfmsubadd_ps_256 VR256:$src1, VR256:$src2,
 467                                   (alignedloadv8f32 addr:$src3)),
 468           (VFMSUBADDPS4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 469 def : Pat<(int_x86_fma4_vfmsubadd_ps_256 VR256:$src1,
 470                                       (alignedloadv8f32 addr:$src2),
 471                                       VR256:$src3),
 472           (VFMSUBADDPS4mrY VR256:$src1, addr:$src2, VR256:$src3)>;
 473
 474 def : Pat<(int_x86_fma4_vfmsubadd_pd_256 VR256:$src1, VR256:$src2, VR256:$src3),
 475           (VFMSUBADDPD4rrY VR256:$src1, VR256:$src2, VR256:$src3)>;
 476 def : Pat<(int_x86_fma4_vfmsubadd_pd_256 VR256:$src1, VR256:$src2,
 477                                   (alignedloadv4f64 addr:$src3)),
 478           (VFMSUBADDPD4rmY VR256:$src1, VR256:$src2, addr:$src3)>;
 479 def : Pat<(int_x86_fma4_vfmsubadd_pd_256 VR256:$src1,
 480                                       (alignedloadv4f64 addr:$src2),
 481                                       VR256:$src3),
 482           (VFMSUBADDPD4mrY VR256:$src1, addr:$src2, VR256:$src3)>;