1 //===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes FMA (Fused Multiply-Add) instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // FMA3 - Intel 3 operand Fused Multiply-Add instructions
16 //===----------------------------------------------------------------------===//
18 let Constraints = "$src1 = $dst" in {
19 multiclass fma3p_rm<bits<8> opc, string OpcodeStr> {
20 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
21 (ins VR128:$src1, VR128:$src2, VR128:$src3),
22 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
25 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
26 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
27 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
29 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
30 (ins VR256:$src1, VR256:$src2, VR256:$src3),
31 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
34 def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
35 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
36 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
40 // Intrinsic for 132 pattern
41 multiclass fma3p_rm_int<bits<8> opc, string OpcodeStr,
42 PatFrag MemFrag128, PatFrag MemFrag256,
43 Intrinsic Int128, Intrinsic Int256> {
44 def r_Int : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
45 (ins VR128:$src1, VR128:$src2, VR128:$src3),
46 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
47 [(set VR128:$dst, (Int128 VR128:$src1, VR128:$src3, VR128:$src2))]>;
48 def m_Int : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
49 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
50 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
52 (Int128 VR128:$src1, (MemFrag128 addr:$src3), VR128:$src2))]>;
53 def rY_Int : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
54 (ins VR256:$src1, VR256:$src2, VR256:$src3),
55 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
56 [(set VR256:$dst, (Int256 VR256:$src1, VR256:$src3, VR256:$src2))]>;
57 def mY_Int : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
58 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
59 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
61 (Int256 VR256:$src1, (MemFrag256 addr:$src3), VR256:$src2))]>;
65 multiclass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
66 string OpcodeStr, string PackTy,
67 PatFrag MemFrag128, PatFrag MemFrag256,
68 Intrinsic Int128, Intrinsic Int256> {
69 defm r132 : fma3p_rm_int <opc132, !strconcat(OpcodeStr,
70 !strconcat("132", PackTy)), MemFrag128, MemFrag256,
72 defm r132 : fma3p_rm <opc132, !strconcat(OpcodeStr, !strconcat("132", PackTy))>;
73 defm r213 : fma3p_rm <opc213, !strconcat(OpcodeStr, !strconcat("213", PackTy))>;
74 defm r231 : fma3p_rm <opc231, !strconcat(OpcodeStr, !strconcat("231", PackTy))>;
78 let ExeDomain = SSEPackedSingle in {
79 defm VFMADDPS : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", memopv4f32,
80 memopv8f32, int_x86_fma4_vfmadd_ps, int_x86_fma4_vfmadd_ps_256>;
81 defm VFMSUBPS : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", memopv4f32,
82 memopv8f32, int_x86_fma4_vfmsub_ps, int_x86_fma4_vfmsub_ps_256>;
83 defm VFMADDSUBPS : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps",
84 memopv4f32, memopv8f32, int_x86_fma4_vfmaddsub_ps,
85 int_x86_fma4_vfmaddsub_ps_256>;
86 defm VFMSUBADDPS : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps",
87 memopv4f32, memopv8f32, int_x86_fma4_vfmsubadd_ps,
88 int_x86_fma4_vfmaddsub_ps_256>;
91 let ExeDomain = SSEPackedDouble in {
92 defm VFMADDPD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", memopv2f64,
93 memopv4f64, int_x86_fma4_vfmadd_pd, int_x86_fma4_vfmadd_pd_256>, VEX_W;
94 defm VFMSUBPD : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", memopv2f64,
95 memopv4f64, int_x86_fma4_vfmsub_pd, int_x86_fma4_vfmsub_pd_256>, VEX_W;
96 defm VFMADDSUBPD : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd", memopv2f64,
97 memopv4f64, int_x86_fma4_vfmaddsub_pd, int_x86_fma4_vfmaddsub_pd_256>, VEX_W;
98 defm VFMSUBADDPD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd", memopv2f64,
99 memopv4f64, int_x86_fma4_vfmsubadd_pd, int_x86_fma4_vfmsubadd_pd_256>, VEX_W;
102 // Fused Negative Multiply-Add
103 let ExeDomain = SSEPackedSingle in {
104 defm VFNMADDPS : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps", memopv4f32,
105 memopv8f32, int_x86_fma4_vfnmadd_ps, int_x86_fma4_vfnmadd_ps_256>;
106 defm VFNMSUBPS : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps", memopv4f32,
107 memopv8f32, int_x86_fma4_vfnmsub_ps, int_x86_fma4_vfnmsub_ps_256>;
109 let ExeDomain = SSEPackedDouble in {
110 defm VFNMADDPD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd", memopv2f64,
111 memopv4f64, int_x86_fma4_vfnmadd_pd, int_x86_fma4_vfnmadd_pd_256>, VEX_W;
112 defm VFNMSUBPD : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd", memopv2f64,
113 memopv4f64, int_x86_fma4_vfnmsub_pd, int_x86_fma4_vfnmsub_pd_256>, VEX_W;
117 let Constraints = "$src1 = $dst" in {
118 multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,
120 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
121 (ins RC:$src1, RC:$src2, RC:$src3),
122 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
124 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
125 (ins RC:$src1, RC:$src2, x86memop:$src3),
126 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
130 multiclass fma3s_rm_int<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,
131 RegisterClass RC, Intrinsic IntId> {
132 def r_Int : FMA3<opc, MRMSrcReg, (outs RC:$dst),
133 (ins RC:$src1, RC:$src2, RC:$src3),
134 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
135 [(set RC:$dst, (IntId RC:$src1, RC:$src3, RC:$src2))]>;
136 def m_Int : FMA3<opc, MRMSrcMem, (outs RC:$dst),
137 (ins RC:$src1, VR128:$src2, x86memop:$src3),
138 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
139 [(set RC:$dst, (IntId RC:$src1, (load addr:$src3), RC:$src2))]>;
143 multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
144 string OpcodeStr, string PackTy, X86MemOperand MemOp,
145 RegisterClass RC, Intrinsic IntId> {
146 defm r132 : fma3s_rm <opc132, !strconcat(OpcodeStr,
147 !strconcat("132", PackTy)), MemOp, RC>;
148 defm r213 : fma3s_rm <opc213, !strconcat(OpcodeStr,
149 !strconcat("213", PackTy)), MemOp, RC>;
150 defm r231 : fma3s_rm <opc231, !strconcat(OpcodeStr,
151 !strconcat("231", PackTy)), MemOp, RC>;
152 defm r132_Int : fma3s_rm_int <opc132, !strconcat(OpcodeStr,
153 !strconcat("132", PackTy)), MemOp, VR128, IntId>;
156 defm VFMADDSS : fma3s_forms<0x99, 0xA9, 0xB9, "vfmadd", "ss", f32mem, FR32,
157 int_x86_fma4_vfmadd_ss>, VEX_LIG;
158 defm VFMADDSD : fma3s_forms<0x99, 0xA9, 0xB9, "vfmadd", "sd", f64mem, FR64,
159 int_x86_fma4_vfmadd_sd>, VEX_W, VEX_LIG;
160 defm VFMSUBSS : fma3s_forms<0x9B, 0xAB, 0xBB, "vfmsub", "ss", f32mem, FR32,
161 int_x86_fma4_vfmsub_ss>, VEX_LIG;
162 defm VFMSUBSD : fma3s_forms<0x9B, 0xAB, 0xBB, "vfmsub", "sd", f64mem, FR64,
163 int_x86_fma4_vfmsub_sd>, VEX_W, VEX_LIG;
165 defm VFNMADDSS : fma3s_forms<0x9D, 0xAD, 0xBD, "vfnmadd", "ss", f32mem, FR32,
166 int_x86_fma4_vfnmadd_ss>, VEX_LIG;
167 defm VFNMADDSD : fma3s_forms<0x9D, 0xAD, 0xBD, "vfnmadd", "sd", f64mem, FR64,
168 int_x86_fma4_vfnmadd_sd>, VEX_W, VEX_LIG;
169 defm VFNMSUBSS : fma3s_forms<0x9F, 0xAF, 0xBF, "vfnmsub", "ss", f32mem, FR32,
170 int_x86_fma4_vfnmsub_ss>, VEX_LIG;
171 defm VFNMSUBSD : fma3s_forms<0x9F, 0xAF, 0xBF, "vfnmsub", "sd", f64mem, FR64,
172 int_x86_fma4_vfnmsub_sd>, VEX_W, VEX_LIG;
175 //===----------------------------------------------------------------------===//
176 // FMA4 - AMD 4 operand Fused Multiply-Add instructions
177 //===----------------------------------------------------------------------===//
180 multiclass fma4s<bits<8> opc, string OpcodeStr, Operand memop,
181 ComplexPattern mem_cpat, Intrinsic Int> {
182 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
183 (ins VR128:$src1, VR128:$src2, VR128:$src3),
184 !strconcat(OpcodeStr,
185 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
187 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, MemOp4;
188 def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
189 (ins VR128:$src1, VR128:$src2, memop:$src3),
190 !strconcat(OpcodeStr,
191 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
193 (Int VR128:$src1, VR128:$src2, mem_cpat:$src3))]>, VEX_W, MemOp4;
194 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
195 (ins VR128:$src1, memop:$src2, VR128:$src3),
196 !strconcat(OpcodeStr,
197 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
199 (Int VR128:$src1, mem_cpat:$src2, VR128:$src3))]>;
201 let isCodeGenOnly = 1 in
202 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
203 (ins VR128:$src1, VR128:$src2, VR128:$src3),
204 !strconcat(OpcodeStr,
205 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
208 multiclass fma4p<bits<8> opc, string OpcodeStr,
209 Intrinsic Int128, Intrinsic Int256,
210 PatFrag ld_frag128, PatFrag ld_frag256> {
211 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
212 (ins VR128:$src1, VR128:$src2, VR128:$src3),
213 !strconcat(OpcodeStr,
214 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
216 (Int128 VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, MemOp4;
217 def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
218 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
219 !strconcat(OpcodeStr,
220 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
221 [(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2,
222 (ld_frag128 addr:$src3)))]>, VEX_W, MemOp4;
223 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
224 (ins VR128:$src1, f128mem:$src2, VR128:$src3),
225 !strconcat(OpcodeStr,
226 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
228 (Int128 VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>;
229 def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
230 (ins VR256:$src1, VR256:$src2, VR256:$src3),
231 !strconcat(OpcodeStr,
232 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
234 (Int256 VR256:$src1, VR256:$src2, VR256:$src3))]>, VEX_W, MemOp4;
235 def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
236 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
237 !strconcat(OpcodeStr,
238 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
239 [(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2,
240 (ld_frag256 addr:$src3)))]>, VEX_W, MemOp4;
241 def mrY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
242 (ins VR256:$src1, f256mem:$src2, VR256:$src3),
243 !strconcat(OpcodeStr,
244 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
246 (Int256 VR256:$src1, (ld_frag256 addr:$src2), VR256:$src3))]>;
248 let isCodeGenOnly = 1 in {
249 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
250 (ins VR128:$src1, VR128:$src2, VR128:$src3),
251 !strconcat(OpcodeStr,
252 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
253 def rrY_REV : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
254 (ins VR256:$src1, VR256:$src2, VR256:$src3),
255 !strconcat(OpcodeStr,
256 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
257 } // isCodeGenOnly = 1
260 let Predicates = [HasFMA4] in {
262 defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", ssmem, sse_load_f32,
263 int_x86_fma4_vfmadd_ss>;
264 defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", sdmem, sse_load_f64,
265 int_x86_fma4_vfmadd_sd>;
266 defm VFMADDPS4 : fma4p<0x68, "vfmaddps", int_x86_fma4_vfmadd_ps,
267 int_x86_fma4_vfmadd_ps_256, memopv4f32, memopv8f32>;
268 defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", int_x86_fma4_vfmadd_pd,
269 int_x86_fma4_vfmadd_pd_256, memopv2f64, memopv4f64>;
270 defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", ssmem, sse_load_f32,
271 int_x86_fma4_vfmsub_ss>;
272 defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", sdmem, sse_load_f64,
273 int_x86_fma4_vfmsub_sd>;
274 defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", int_x86_fma4_vfmsub_ps,
275 int_x86_fma4_vfmsub_ps_256, memopv4f32, memopv8f32>;
276 defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", int_x86_fma4_vfmsub_pd,
277 int_x86_fma4_vfmsub_pd_256, memopv2f64, memopv4f64>;
278 defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", ssmem, sse_load_f32,
279 int_x86_fma4_vfnmadd_ss>;
280 defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", sdmem, sse_load_f64,
281 int_x86_fma4_vfnmadd_sd>;
282 defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", int_x86_fma4_vfnmadd_ps,
283 int_x86_fma4_vfnmadd_ps_256, memopv4f32, memopv8f32>;
284 defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", int_x86_fma4_vfnmadd_pd,
285 int_x86_fma4_vfnmadd_pd_256, memopv2f64, memopv4f64>;
286 defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", ssmem, sse_load_f32,
287 int_x86_fma4_vfnmsub_ss>;
288 defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", sdmem, sse_load_f64,
289 int_x86_fma4_vfnmsub_sd>;
290 defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", int_x86_fma4_vfnmsub_ps,
291 int_x86_fma4_vfnmsub_ps_256, memopv4f32, memopv8f32>;
292 defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", int_x86_fma4_vfnmsub_pd,
293 int_x86_fma4_vfnmsub_pd_256, memopv2f64, memopv4f64>;
294 defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", int_x86_fma4_vfmaddsub_ps,
295 int_x86_fma4_vfmaddsub_ps_256, memopv4f32, memopv8f32>;
296 defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", int_x86_fma4_vfmaddsub_pd,
297 int_x86_fma4_vfmaddsub_pd_256, memopv2f64, memopv4f64>;
298 defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", int_x86_fma4_vfmsubadd_ps,
299 int_x86_fma4_vfmsubadd_ps_256, memopv4f32, memopv8f32>;
300 defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", int_x86_fma4_vfmsubadd_pd,
301 int_x86_fma4_vfmsubadd_pd_256, memopv2f64, memopv4f64>;