1 //===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes FMA (Fused Multiply-Add) instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // FMA3 - Intel 3 operand Fused Multiply-Add instructions
16 //===----------------------------------------------------------------------===//
18 // For all FMA opcodes declared in fma3p_rm and fma3s_rm milticlasses defined
19 // below, both the register and memory variants are commutable.
20 // For the register form the commutable operands are 1, 2 and 3.
21 // For the memory variant the folded operand must be in 3. Thus,
22 // in that case, only the operands 1 and 2 can be swapped.
23 // Commuting some of operands may require the opcode change.
25 // operands 1 and 2 (memory & register forms): *213* --> *213*(no changes);
26 // operands 1 and 3 (register forms only): *213* --> *231*;
27 // operands 2 and 3 (register forms only): *213* --> *132*.
29 // operands 1 and 2 (memory & register forms): *132* --> *231*;
30 // operands 1 and 3 (register forms only): *132* --> *132*(no changes);
31 // operands 2 and 3 (register forms only): *132* --> *213*.
33 // operands 1 and 2 (memory & register forms): *231* --> *132*;
34 // operands 1 and 3 (register forms only): *231* --> *213*;
35 // operands 2 and 3 (register forms only): *231* --> *231*(no changes).
37 let Constraints = "$src1 = $dst", hasSideEffects = 0, isCommutable = 1 in
38 multiclass fma3p_rm<bits<8> opc, string OpcodeStr,
39 PatFrag MemFrag128, PatFrag MemFrag256,
40 ValueType OpVT128, ValueType OpVT256,
41 SDPatternOperator Op = null_frag> {
42 let usesCustomInserter = 1 in
43 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
44 (ins VR128:$src1, VR128:$src2, VR128:$src3),
46 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
47 [(set VR128:$dst, (OpVT128 (Op VR128:$src2,
48 VR128:$src1, VR128:$src3)))]>;
51 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
52 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
54 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
55 [(set VR128:$dst, (OpVT128 (Op VR128:$src2, VR128:$src1,
56 (MemFrag128 addr:$src3))))]>;
58 let usesCustomInserter = 1 in
59 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
60 (ins VR256:$src1, VR256:$src2, VR256:$src3),
62 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
63 [(set VR256:$dst, (OpVT256 (Op VR256:$src2, VR256:$src1,
64 VR256:$src3)))]>, VEX_L;
67 def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
68 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
70 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
72 (OpVT256 (Op VR256:$src2, VR256:$src1,
73 (MemFrag256 addr:$src3))))]>, VEX_L;
76 multiclass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
77 string OpcodeStr, string PackTy,
78 PatFrag MemFrag128, PatFrag MemFrag256,
79 SDNode Op, ValueType OpTy128, ValueType OpTy256> {
80 defm r213 : fma3p_rm<opc213,
81 !strconcat(OpcodeStr, "213", PackTy),
82 MemFrag128, MemFrag256, OpTy128, OpTy256, Op>;
83 defm r132 : fma3p_rm<opc132,
84 !strconcat(OpcodeStr, "132", PackTy),
85 MemFrag128, MemFrag256, OpTy128, OpTy256>;
86 defm r231 : fma3p_rm<opc231,
87 !strconcat(OpcodeStr, "231", PackTy),
88 MemFrag128, MemFrag256, OpTy128, OpTy256>;
92 let ExeDomain = SSEPackedSingle in {
93 defm VFMADDPS : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", loadv4f32,
94 loadv8f32, X86Fmadd, v4f32, v8f32>;
95 defm VFMSUBPS : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", loadv4f32,
96 loadv8f32, X86Fmsub, v4f32, v8f32>;
97 defm VFMADDSUBPS : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps",
98 loadv4f32, loadv8f32, X86Fmaddsub,
100 defm VFMSUBADDPS : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps",
101 loadv4f32, loadv8f32, X86Fmsubadd,
105 let ExeDomain = SSEPackedDouble in {
106 defm VFMADDPD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", loadv2f64,
107 loadv4f64, X86Fmadd, v2f64, v4f64>, VEX_W;
108 defm VFMSUBPD : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", loadv2f64,
109 loadv4f64, X86Fmsub, v2f64, v4f64>, VEX_W;
110 defm VFMADDSUBPD : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd",
111 loadv2f64, loadv4f64, X86Fmaddsub,
112 v2f64, v4f64>, VEX_W;
113 defm VFMSUBADDPD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd",
114 loadv2f64, loadv4f64, X86Fmsubadd,
115 v2f64, v4f64>, VEX_W;
118 // Fused Negative Multiply-Add
119 let ExeDomain = SSEPackedSingle in {
120 defm VFNMADDPS : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps", loadv4f32,
121 loadv8f32, X86Fnmadd, v4f32, v8f32>;
122 defm VFNMSUBPS : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps", loadv4f32,
123 loadv8f32, X86Fnmsub, v4f32, v8f32>;
125 let ExeDomain = SSEPackedDouble in {
126 defm VFNMADDPD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd", loadv2f64,
127 loadv4f64, X86Fnmadd, v2f64, v4f64>, VEX_W;
128 defm VFNMSUBPD : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd",
129 loadv2f64, loadv4f64, X86Fnmsub, v2f64,
133 // All source register operands of FMA opcodes defined in fma3s_rm multiclass
134 // can be commuted. In many cases such commute transformation requres an opcode
135 // adjustment, for example, commuting the operands 1 and 2 in FMA*132 form
136 // would require an opcode change to FMA*231:
137 // FMA*132* reg1, reg2, reg3; // reg1 * reg3 + reg2;
139 // FMA*231* reg2, reg1, reg3; // reg1 * reg3 + reg2;
140 // Please see more detailed comment at the very beginning of the section
141 // defining FMA3 opcodes above.
142 let Constraints = "$src1 = $dst", isCommutable = 1, hasSideEffects = 0 in
143 multiclass fma3s_rm<bits<8> opc, string OpcodeStr,
144 X86MemOperand x86memop, RegisterClass RC,
145 SDPatternOperator OpNode = null_frag> {
146 let usesCustomInserter = 1 in
147 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
148 (ins RC:$src1, RC:$src2, RC:$src3),
149 !strconcat(OpcodeStr,
150 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
151 [(set RC:$dst, (OpNode RC:$src2, RC:$src1, RC:$src3))]>;
154 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
155 (ins RC:$src1, RC:$src2, x86memop:$src3),
156 !strconcat(OpcodeStr,
157 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
159 (OpNode RC:$src2, RC:$src1, (load addr:$src3)))]>;
162 // These FMA*_Int instructions are defined specially for being used when
163 // the scalar FMA intrinsics are lowered to machine instructions, and in that
164 // sense, they are similar to existing ADD*_Int, SUB*_Int, MUL*_Int, etc.
167 // All of the FMA*_Int opcodes are defined as commutable here.
168 // Commuting the 2nd and 3rd source register operands of FMAs is quite trivial
169 // and the corresponding optimizations have been developed.
170 // Commuting the 1st operand of FMA*_Int requires some additional analysis,
171 // the commute optimization is legal only if all users of FMA*_Int use only
172 // the lowest element of the FMA*_Int instruction. Even though such analysis
173 // may be not implemented yet we allow the routines doing the actual commute
174 // transformation to decide if one or another instruction is commutable or not.
175 let Constraints = "$src1 = $dst", isCommutable = 1, isCodeGenOnly = 1,
176 hasSideEffects = 0 in
177 multiclass fma3s_rm_int<bits<8> opc, string OpcodeStr,
178 Operand memopr, RegisterClass RC> {
179 def r_Int : FMA3<opc, MRMSrcReg, (outs RC:$dst),
180 (ins RC:$src1, RC:$src2, RC:$src3),
181 !strconcat(OpcodeStr,
182 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
186 def m_Int : FMA3<opc, MRMSrcMem, (outs RC:$dst),
187 (ins RC:$src1, RC:$src2, memopr:$src3),
188 !strconcat(OpcodeStr,
189 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
193 multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
194 string OpStr, string PackTy,
195 SDNode OpNode, RegisterClass RC,
196 X86MemOperand x86memop> {
197 defm r132 : fma3s_rm<opc132, !strconcat(OpStr, "132", PackTy), x86memop, RC>;
198 defm r213 : fma3s_rm<opc213, !strconcat(OpStr, "213", PackTy), x86memop, RC,
200 defm r231 : fma3s_rm<opc231, !strconcat(OpStr, "231", PackTy), x86memop, RC>;
203 // The FMA 213 form is created for lowering of scalar FMA intrinscis
204 // to machine instructions.
205 // The FMA 132 form can trivially be get by commuting the 2nd and 3rd operands
207 // The FMA 231 form can be get only by commuting the 1st operand of 213 or 132
208 // forms and is possible only after special analysis of all uses of the initial
209 // instruction. Such analysis do not exist yet and thus introducing the 231
210 // form of FMA*_Int instructions is done using an optimistic assumption that
211 // such analysis will be implemented eventually.
212 multiclass fma3s_int_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
213 string OpStr, string PackTy,
214 RegisterClass RC, Operand memop> {
215 defm r132 : fma3s_rm_int<opc132, !strconcat(OpStr, "132", PackTy),
217 defm r213 : fma3s_rm_int<opc213, !strconcat(OpStr, "213", PackTy),
219 defm r231 : fma3s_rm_int<opc231, !strconcat(OpStr, "231", PackTy),
223 multiclass fma3s<bits<8> opc132, bits<8> opc213, bits<8> opc231,
224 string OpStr, Intrinsic IntF32, Intrinsic IntF64,
226 defm SS : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", OpNode,
228 fma3s_int_forms<opc132, opc213, opc231, OpStr, "ss", VR128, ssmem>;
229 defm SD : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", OpNode,
231 fma3s_int_forms<opc132, opc213, opc231, OpStr, "sd", VR128, sdmem>,
234 // These patterns use the 123 ordering, instead of 213, even though
235 // they match the intrinsic to the 213 version of the instruction.
236 // This is because src1 is tied to dest, and the scalar intrinsics
237 // require the pass-through values to come from the first source
238 // operand, not the second.
239 def : Pat<(IntF32 VR128:$src1, VR128:$src2, VR128:$src3),
240 (COPY_TO_REGCLASS(!cast<Instruction>(NAME#"SSr213r_Int")
241 $src1, $src2, $src3), VR128)>;
243 def : Pat<(IntF64 VR128:$src1, VR128:$src2, VR128:$src3),
244 (COPY_TO_REGCLASS(!cast<Instruction>(NAME#"SDr213r_Int")
245 $src1, $src2, $src3), VR128)>;
248 defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", int_x86_fma_vfmadd_ss,
249 int_x86_fma_vfmadd_sd, X86Fmadd>, VEX_LIG;
250 defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", int_x86_fma_vfmsub_ss,
251 int_x86_fma_vfmsub_sd, X86Fmsub>, VEX_LIG;
253 defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", int_x86_fma_vfnmadd_ss,
254 int_x86_fma_vfnmadd_sd, X86Fnmadd>, VEX_LIG;
255 defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", int_x86_fma_vfnmsub_ss,
256 int_x86_fma_vfnmsub_sd, X86Fnmsub>, VEX_LIG;
259 //===----------------------------------------------------------------------===//
260 // FMA4 - AMD 4 operand Fused Multiply-Add instructions
261 //===----------------------------------------------------------------------===//
264 multiclass fma4s<bits<8> opc, string OpcodeStr, RegisterClass RC,
265 X86MemOperand x86memop, ValueType OpVT, SDNode OpNode,
267 let isCommutable = 1 in
268 def rr : FMA4<opc, MRMSrcReg, (outs RC:$dst),
269 (ins RC:$src1, RC:$src2, RC:$src3),
270 !strconcat(OpcodeStr,
271 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
273 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, VEX_LIG, MemOp4;
274 def rm : FMA4<opc, MRMSrcMem, (outs RC:$dst),
275 (ins RC:$src1, RC:$src2, x86memop:$src3),
276 !strconcat(OpcodeStr,
277 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
278 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
279 (mem_frag addr:$src3)))]>, VEX_W, VEX_LIG, MemOp4;
280 def mr : FMA4<opc, MRMSrcMem, (outs RC:$dst),
281 (ins RC:$src1, x86memop:$src2, RC:$src3),
282 !strconcat(OpcodeStr,
283 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
285 (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3))]>, VEX_LIG;
287 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
288 def rr_REV : FMA4<opc, MRMSrcReg, (outs RC:$dst),
289 (ins RC:$src1, RC:$src2, RC:$src3),
290 !strconcat(OpcodeStr,
291 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
295 multiclass fma4s_int<bits<8> opc, string OpcodeStr, Operand memop,
296 ComplexPattern mem_cpat, Intrinsic Int> {
297 let isCodeGenOnly = 1 in {
298 let isCommutable = 1 in
299 def rr_Int : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
300 (ins VR128:$src1, VR128:$src2, VR128:$src3),
301 !strconcat(OpcodeStr,
302 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
304 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, VEX_LIG, MemOp4;
305 def rm_Int : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
306 (ins VR128:$src1, VR128:$src2, memop:$src3),
307 !strconcat(OpcodeStr,
308 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
309 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2,
310 mem_cpat:$src3))]>, VEX_W, VEX_LIG, MemOp4;
311 def mr_Int : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
312 (ins VR128:$src1, memop:$src2, VR128:$src3),
313 !strconcat(OpcodeStr,
314 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
316 (Int VR128:$src1, mem_cpat:$src2, VR128:$src3))]>, VEX_LIG;
317 } // isCodeGenOnly = 1
320 multiclass fma4p<bits<8> opc, string OpcodeStr, SDNode OpNode,
321 ValueType OpVT128, ValueType OpVT256,
322 PatFrag ld_frag128, PatFrag ld_frag256> {
323 let isCommutable = 1 in
324 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
325 (ins VR128:$src1, VR128:$src2, VR128:$src3),
326 !strconcat(OpcodeStr,
327 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
329 (OpVT128 (OpNode VR128:$src1, VR128:$src2, VR128:$src3)))]>,
331 def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
332 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
333 !strconcat(OpcodeStr,
334 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
335 [(set VR128:$dst, (OpNode VR128:$src1, VR128:$src2,
336 (ld_frag128 addr:$src3)))]>, VEX_W, MemOp4;
337 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
338 (ins VR128:$src1, f128mem:$src2, VR128:$src3),
339 !strconcat(OpcodeStr,
340 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
342 (OpNode VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>;
343 let isCommutable = 1 in
344 def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
345 (ins VR256:$src1, VR256:$src2, VR256:$src3),
346 !strconcat(OpcodeStr,
347 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
349 (OpVT256 (OpNode VR256:$src1, VR256:$src2, VR256:$src3)))]>,
350 VEX_W, MemOp4, VEX_L;
351 def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
352 (ins VR256:$src1, VR256:$src2, f256mem:$src3),
353 !strconcat(OpcodeStr,
354 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
355 [(set VR256:$dst, (OpNode VR256:$src1, VR256:$src2,
356 (ld_frag256 addr:$src3)))]>, VEX_W, MemOp4, VEX_L;
357 def mrY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
358 (ins VR256:$src1, f256mem:$src2, VR256:$src3),
359 !strconcat(OpcodeStr,
360 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
361 [(set VR256:$dst, (OpNode VR256:$src1,
362 (ld_frag256 addr:$src2), VR256:$src3))]>, VEX_L;
364 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
365 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
366 (ins VR128:$src1, VR128:$src2, VR128:$src3),
367 !strconcat(OpcodeStr,
368 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>;
369 def rrY_REV : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
370 (ins VR256:$src1, VR256:$src2, VR256:$src3),
371 !strconcat(OpcodeStr,
372 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>,
374 } // isCodeGenOnly = 1
377 defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", FR32, f32mem, f32, X86Fmadd, loadf32>,
378 fma4s_int<0x6A, "vfmaddss", ssmem, sse_load_f32,
379 int_x86_fma_vfmadd_ss>;
380 defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", FR64, f64mem, f64, X86Fmadd, loadf64>,
381 fma4s_int<0x6B, "vfmaddsd", sdmem, sse_load_f64,
382 int_x86_fma_vfmadd_sd>;
383 defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", FR32, f32mem, f32, X86Fmsub, loadf32>,
384 fma4s_int<0x6E, "vfmsubss", ssmem, sse_load_f32,
385 int_x86_fma_vfmsub_ss>;
386 defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", FR64, f64mem, f64, X86Fmsub, loadf64>,
387 fma4s_int<0x6F, "vfmsubsd", sdmem, sse_load_f64,
388 int_x86_fma_vfmsub_sd>;
389 defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", FR32, f32mem, f32,
391 fma4s_int<0x7A, "vfnmaddss", ssmem, sse_load_f32,
392 int_x86_fma_vfnmadd_ss>;
393 defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", FR64, f64mem, f64,
395 fma4s_int<0x7B, "vfnmaddsd", sdmem, sse_load_f64,
396 int_x86_fma_vfnmadd_sd>;
397 defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", FR32, f32mem, f32,
399 fma4s_int<0x7E, "vfnmsubss", ssmem, sse_load_f32,
400 int_x86_fma_vfnmsub_ss>;
401 defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", FR64, f64mem, f64,
403 fma4s_int<0x7F, "vfnmsubsd", sdmem, sse_load_f64,
404 int_x86_fma_vfnmsub_sd>;
406 let ExeDomain = SSEPackedSingle in {
407 defm VFMADDPS4 : fma4p<0x68, "vfmaddps", X86Fmadd, v4f32, v8f32,
408 loadv4f32, loadv8f32>;
409 defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", X86Fmsub, v4f32, v8f32,
410 loadv4f32, loadv8f32>;
411 defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", X86Fnmadd, v4f32, v8f32,
412 loadv4f32, loadv8f32>;
413 defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", X86Fnmsub, v4f32, v8f32,
414 loadv4f32, loadv8f32>;
415 defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", X86Fmaddsub, v4f32, v8f32,
416 loadv4f32, loadv8f32>;
417 defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", X86Fmsubadd, v4f32, v8f32,
418 loadv4f32, loadv8f32>;
421 let ExeDomain = SSEPackedDouble in {
422 defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", X86Fmadd, v2f64, v4f64,
423 loadv2f64, loadv4f64>;
424 defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", X86Fmsub, v2f64, v4f64,
425 loadv2f64, loadv4f64>;
426 defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", X86Fnmadd, v2f64, v4f64,
427 loadv2f64, loadv4f64>;
428 defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", X86Fnmsub, v2f64, v4f64,
429 loadv2f64, loadv4f64>;
430 defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", X86Fmaddsub, v2f64, v4f64,
431 loadv2f64, loadv4f64>;
432 defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", X86Fmsubadd, v2f64, v4f64,
433 loadv2f64, loadv4f64>;