1 //===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 jump, return, call, and related instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Control Flow Instructions.
18 // Return instructions.
20 // The X86retflag return instructions are variadic because we may add ST0 and
21 // ST1 arguments when returning values on the x87 stack.
22 let isTerminator = 1, isReturn = 1, isBarrier = 1,
23 hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
24 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
26 [(X86retflag 0)], IIC_RET>;
27 def RETW : I <0xC3, RawFrm, (outs), (ins),
30 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
32 [(X86retflag timm:$amt)], IIC_RET_IMM>;
33 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
35 [], IIC_RET_IMM>, OpSize;
36 def LRETL : I <0xCB, RawFrm, (outs), (ins),
37 "{l}ret{l|f}", [], IIC_RET>;
38 def LRETW : I <0xCB, RawFrm, (outs), (ins),
39 "{l}ret{w|f}", [], IIC_RET>, OpSize;
40 def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
41 "{l}ret{q|f}", [], IIC_RET>;
42 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
43 "{l}ret{l|f}\t$amt", [], IIC_RET>;
44 def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
45 "{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize;
48 // Unconditional branches.
49 let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
50 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
51 "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>;
52 let hasSideEffects = 0 in
53 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
54 "jmp\t$dst", [], IIC_JMP_REL>;
57 // Conditional Branches.
58 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
59 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
60 let hasSideEffects = 0 in
61 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, [],
63 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
64 [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, TB;
68 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
69 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
70 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
71 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
72 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
73 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
74 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
75 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
76 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
77 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
78 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
79 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
80 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
81 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
82 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
83 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
85 // jcx/jecx/jrcx instructions.
86 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
87 // These are the 32-bit versions of this instruction for the asmparser. In
88 // 32-bit mode, the address size prefix is jcxz and the unprefixed version is
91 def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
92 "jcxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[Not64BitMode]>;
94 def JECXZ_32 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
95 "jecxz\t$dst", [], IIC_JCXZ>, Requires<[Not64BitMode]>;
97 // J*CXZ instruction: 64-bit versions of this instruction for the asmparser.
98 // In 64-bit mode, the address size prefix is jecxz and the unprefixed version
101 def JECXZ_64 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
102 "jecxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[In64BitMode]>;
104 def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
105 "jrcxz\t$dst", [], IIC_JCXZ>, Requires<[In64BitMode]>;
109 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
110 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
111 [(brind GR32:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>,
113 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
114 [(brind (loadi32 addr:$dst))], IIC_JMP_MEM>,
115 Requires<[Not64BitMode]>, Sched<[WriteJumpLd]>;
117 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
118 [(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>,
120 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
121 [(brind (loadi64 addr:$dst))], IIC_JMP_MEM>,
122 Requires<[In64BitMode]>, Sched<[WriteJumpLd]>;
124 def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
125 (ins i16imm:$off, i16imm:$seg),
126 "ljmp{w}\t{$seg, $off|$off, $seg}", [],
127 IIC_JMP_FAR_PTR>, OpSize, Sched<[WriteJump]>;
128 def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
129 (ins i32imm:$off, i16imm:$seg),
130 "ljmp{l}\t{$seg, $off|$off, $seg}", [],
131 IIC_JMP_FAR_PTR>, Sched<[WriteJump]>;
132 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
133 "ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>,
136 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
137 "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize,
138 Sched<[WriteJumpLd]>;
139 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
140 "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>,
141 Sched<[WriteJumpLd]>;
146 let SchedRW = [WriteJump] in {
147 def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", [], IIC_LOOP>;
148 def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", [], IIC_LOOPE>;
149 def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", [], IIC_LOOPNE>;
152 //===----------------------------------------------------------------------===//
153 // Call Instructions...
156 // All calls clobber the non-callee saved registers. ESP is marked as
157 // a use to prevent stack-pointer assignments that appear immediately
158 // before calls from potentially appearing dead. Uses for argument
159 // registers are added manually.
160 let Uses = [ESP] in {
161 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
162 (outs), (ins i32imm_pcrel:$dst),
163 "call{l}\t$dst", [], IIC_CALL_RI>,
164 Requires<[Not64BitMode]>, Sched<[WriteJump]>;
165 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
166 "call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>,
167 Requires<[Not64BitMode]>, Sched<[WriteJump]>;
168 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
169 "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))],
171 Requires<[Not64BitMode,FavorMemIndirectCall]>,
172 Sched<[WriteJumpLd]>;
174 def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
175 (ins i16imm:$off, i16imm:$seg),
176 "lcall{w}\t{$seg, $off|$off, $seg}", [],
177 IIC_CALL_FAR_PTR>, OpSize, Sched<[WriteJump]>;
178 def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
179 (ins i32imm:$off, i16imm:$seg),
180 "lcall{l}\t{$seg, $off|$off, $seg}", [],
181 IIC_CALL_FAR_PTR>, Sched<[WriteJump]>;
183 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
184 "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize,
185 Sched<[WriteJumpLd]>;
186 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
187 "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>,
188 Sched<[WriteJumpLd]>;
190 // callw for 16 bit code for the assembler.
191 let isAsmParserOnly = 1 in
192 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
193 (outs), (ins i16imm_pcrel:$dst),
194 "callw\t$dst", []>, OpSize;
200 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
201 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
202 let Uses = [ESP] in {
203 def TCRETURNdi : PseudoI<(outs),
204 (ins i32imm_pcrel:$dst, i32imm:$offset), []>;
205 def TCRETURNri : PseudoI<(outs),
206 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>;
208 def TCRETURNmi : PseudoI<(outs),
209 (ins i32mem_TC:$dst, i32imm:$offset), []>;
211 // FIXME: The should be pseudo instructions that are lowered when going to
213 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
214 (ins i32imm_pcrel:$dst),
215 "jmp\t$dst # TAILCALL",
217 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
218 "", [], IIC_JMP_REG>; // FIXME: Remove encoding when JIT is dead.
220 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst),
221 "jmp{l}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;
225 //===----------------------------------------------------------------------===//
226 // Call Instructions...
229 // RSP is marked as a use to prevent stack-pointer assignments that appear
230 // immediately before calls from potentially appearing dead. Uses for argument
231 // registers are added manually.
232 let isCall = 1, Uses = [RSP], SchedRW = [WriteJump] in {
233 // NOTE: this pattern doesn't match "X86call imm", because we do not know
234 // that the offset between an arbitrary immediate and the call will fit in
235 // the 32-bit pcrel field that we have.
236 def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
237 (outs), (ins i64i32imm_pcrel:$dst),
238 "call{q}\t$dst", [], IIC_CALL_RI>,
239 Requires<[In64BitMode]>;
240 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst),
241 "call{q}\t{*}$dst", [(X86call GR64:$dst)],
243 Requires<[In64BitMode]>;
244 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst),
245 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))],
247 Requires<[In64BitMode,FavorMemIndirectCall]>;
249 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
250 "lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>;
253 let isCall = 1, isCodeGenOnly = 1 in
254 // __chkstk(MSVC): clobber R10, R11 and EFLAGS.
255 // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP.
256 let Defs = [RAX, R10, R11, RSP, EFLAGS],
258 def W64ALLOCA : Ii32PCRel<0xE8, RawFrm,
259 (outs), (ins i64i32imm_pcrel:$dst),
260 "call{q}\t$dst", [], IIC_CALL_RI>,
261 Requires<[IsWin64]>, Sched<[WriteJump]>;
264 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
265 isCodeGenOnly = 1, Uses = [RSP], usesCustomInserter = 1,
266 SchedRW = [WriteJump] in {
267 def TCRETURNdi64 : PseudoI<(outs),
268 (ins i64i32imm_pcrel:$dst, i32imm:$offset),
270 def TCRETURNri64 : PseudoI<(outs),
271 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>;
273 def TCRETURNmi64 : PseudoI<(outs),
274 (ins i64mem_TC:$dst, i32imm:$offset), []>;
276 def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs),
277 (ins i64i32imm_pcrel:$dst),
278 "jmp\t$dst # TAILCALL", [], IIC_JMP_REL>;
279 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
280 "jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;
283 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst),
284 "jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;