1 //===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 jump, return, call, and related instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Control Flow Instructions.
18 // Return instructions.
20 // The X86retflag return instructions are variadic because we may add ST0 and
21 // ST1 arguments when returning values on the x87 stack.
22 let isTerminator = 1, isReturn = 1, isBarrier = 1,
23 hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
24 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
26 [(X86retflag 0)], IIC_RET>, OpSize16;
27 def RETW : I <0xC3, RawFrm, (outs), (ins),
30 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
32 [(X86retflag timm:$amt)], IIC_RET_IMM>, OpSize16;
33 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
35 [], IIC_RET_IMM>, OpSize;
36 def LRETL : I <0xCB, RawFrm, (outs), (ins),
37 "{l}ret{l|f}", [], IIC_RET>, OpSize16;
38 def LRETW : I <0xCB, RawFrm, (outs), (ins),
39 "{l}ret{w|f}", [], IIC_RET>, OpSize;
40 def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
41 "{l}ret{q|f}", [], IIC_RET>;
42 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
43 "{l}ret{l|f}\t$amt", [], IIC_RET>, OpSize16;
44 def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
45 "{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize;
48 // Unconditional branches.
49 let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
50 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
51 "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>, OpSize16;
52 let hasSideEffects = 0 in
53 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
54 "jmp\t$dst", [], IIC_JMP_REL>;
57 // Conditional Branches.
58 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
59 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
60 let hasSideEffects = 0 in
61 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, [],
63 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
64 [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, TB,
69 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
70 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
71 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
72 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
73 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
74 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
75 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
76 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
77 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
78 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
79 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
80 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
81 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
82 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
83 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
84 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
86 // jcx/jecx/jrcx instructions.
87 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
88 // These are the 32-bit versions of this instruction for the asmparser. In
89 // 32-bit mode, the address size prefix is jcxz and the unprefixed version is
92 def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
93 "jcxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[Not64BitMode]>;
95 def JECXZ_32 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
96 "jecxz\t$dst", [], IIC_JCXZ>, Requires<[Not64BitMode]>;
98 // J*CXZ instruction: 64-bit versions of this instruction for the asmparser.
99 // In 64-bit mode, the address size prefix is jecxz and the unprefixed version
102 def JECXZ_64 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
103 "jecxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[In64BitMode]>;
105 def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
106 "jrcxz\t$dst", [], IIC_JCXZ>, Requires<[In64BitMode]>;
110 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
111 def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst",
112 [(brind GR16:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>,
113 OpSize, Sched<[WriteJump]>;
114 def JMP16m : I<0xFF, MRM4m, (outs), (ins i16mem:$dst), "jmp{w}\t{*}$dst",
115 [(brind (loadi16 addr:$dst))], IIC_JMP_MEM>,
116 Requires<[Not64BitMode]>, OpSize, Sched<[WriteJumpLd]>;
118 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
119 [(brind GR32:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>,
120 OpSize16, Sched<[WriteJump]>;
121 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
122 [(brind (loadi32 addr:$dst))], IIC_JMP_MEM>,
123 Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>;
125 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
126 [(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>,
128 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
129 [(brind (loadi64 addr:$dst))], IIC_JMP_MEM>,
130 Requires<[In64BitMode]>, Sched<[WriteJumpLd]>;
132 def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
133 (ins i16imm:$off, i16imm:$seg),
134 "ljmp{w}\t{$seg, $off|$off, $seg}", [],
135 IIC_JMP_FAR_PTR>, OpSize, Sched<[WriteJump]>;
136 def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
137 (ins i32imm:$off, i16imm:$seg),
138 "ljmp{l}\t{$seg, $off|$off, $seg}", [],
139 IIC_JMP_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
140 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
141 "ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>,
144 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
145 "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize,
146 Sched<[WriteJumpLd]>;
147 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
148 "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize16,
149 Sched<[WriteJumpLd]>;
154 let SchedRW = [WriteJump] in {
155 def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", [], IIC_LOOP>;
156 def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", [], IIC_LOOPE>;
157 def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", [], IIC_LOOPNE>;
160 //===----------------------------------------------------------------------===//
161 // Call Instructions...
164 // All calls clobber the non-callee saved registers. ESP is marked as
165 // a use to prevent stack-pointer assignments that appear immediately
166 // before calls from potentially appearing dead. Uses for argument
167 // registers are added manually.
168 let Uses = [ESP] in {
169 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
170 (outs), (ins i32imm_pcrel:$dst),
171 "call{l}\t$dst", [], IIC_CALL_RI>, OpSize16,
172 Requires<[Not64BitMode]>, Sched<[WriteJump]>;
173 def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst),
174 "call{w}\t{*}$dst", [(X86call GR16:$dst)], IIC_CALL_RI>,
175 OpSize, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
176 def CALL16m : I<0xFF, MRM2m, (outs), (ins i16mem:$dst),
177 "call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))],
178 IIC_CALL_MEM>, OpSize,
179 Requires<[Not64BitMode,FavorMemIndirectCall]>,
180 Sched<[WriteJumpLd]>;
181 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
182 "call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>,
183 OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
184 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
185 "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))],
186 IIC_CALL_MEM>, OpSize16,
187 Requires<[Not64BitMode,FavorMemIndirectCall]>,
188 Sched<[WriteJumpLd]>;
190 def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
191 (ins i16imm:$off, i16imm:$seg),
192 "lcall{w}\t{$seg, $off|$off, $seg}", [],
193 IIC_CALL_FAR_PTR>, OpSize, Sched<[WriteJump]>;
194 def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
195 (ins i32imm:$off, i16imm:$seg),
196 "lcall{l}\t{$seg, $off|$off, $seg}", [],
197 IIC_CALL_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
199 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
200 "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize,
201 Sched<[WriteJumpLd]>;
202 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
203 "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize16,
204 Sched<[WriteJumpLd]>;
206 // callw for 16 bit code for the assembler.
207 let isAsmParserOnly = 1 in
208 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
209 (outs), (ins i16imm_pcrel:$dst),
210 "callw\t$dst", []>, OpSize;
216 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
217 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
218 let Uses = [ESP] in {
219 def TCRETURNdi : PseudoI<(outs),
220 (ins i32imm_pcrel:$dst, i32imm:$offset), []>;
221 def TCRETURNri : PseudoI<(outs),
222 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>;
224 def TCRETURNmi : PseudoI<(outs),
225 (ins i32mem_TC:$dst, i32imm:$offset), []>;
227 // FIXME: The should be pseudo instructions that are lowered when going to
229 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
230 (ins i32imm_pcrel:$dst),
231 "jmp\t$dst # TAILCALL",
233 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
234 "", [], IIC_JMP_REG>; // FIXME: Remove encoding when JIT is dead.
236 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst),
237 "jmp{l}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;
241 //===----------------------------------------------------------------------===//
242 // Call Instructions...
245 // RSP is marked as a use to prevent stack-pointer assignments that appear
246 // immediately before calls from potentially appearing dead. Uses for argument
247 // registers are added manually.
248 let isCall = 1, Uses = [RSP], SchedRW = [WriteJump] in {
249 // NOTE: this pattern doesn't match "X86call imm", because we do not know
250 // that the offset between an arbitrary immediate and the call will fit in
251 // the 32-bit pcrel field that we have.
252 def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
253 (outs), (ins i64i32imm_pcrel:$dst),
254 "call{q}\t$dst", [], IIC_CALL_RI>,
255 Requires<[In64BitMode]>;
256 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst),
257 "call{q}\t{*}$dst", [(X86call GR64:$dst)],
259 Requires<[In64BitMode]>;
260 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst),
261 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))],
263 Requires<[In64BitMode,FavorMemIndirectCall]>;
265 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
266 "lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>;
269 let isCall = 1, isCodeGenOnly = 1 in
270 // __chkstk(MSVC): clobber R10, R11 and EFLAGS.
271 // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP.
272 let Defs = [RAX, R10, R11, RSP, EFLAGS],
274 def W64ALLOCA : Ii32PCRel<0xE8, RawFrm,
275 (outs), (ins i64i32imm_pcrel:$dst),
276 "call{q}\t$dst", [], IIC_CALL_RI>,
277 Requires<[IsWin64]>, Sched<[WriteJump]>;
280 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
281 isCodeGenOnly = 1, Uses = [RSP], usesCustomInserter = 1,
282 SchedRW = [WriteJump] in {
283 def TCRETURNdi64 : PseudoI<(outs),
284 (ins i64i32imm_pcrel:$dst, i32imm:$offset),
286 def TCRETURNri64 : PseudoI<(outs),
287 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>;
289 def TCRETURNmi64 : PseudoI<(outs),
290 (ins i64mem_TC:$dst, i32imm:$offset), []>;
292 def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs),
293 (ins i64i32imm_pcrel:$dst),
294 "jmp\t$dst # TAILCALL", [], IIC_JMP_REL>;
295 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
296 "jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;
299 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst),
300 "jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;