1 //===- X86InstrControl.td - Control Flow Instructions ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 jump, return, call, and related instructions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Control Flow Instructions.
18 // Return instructions.
19 let isTerminator = 1, isReturn = 1, isBarrier = 1,
20 hasCtrlDep = 1, FPForm = SpecialFP in {
21 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
23 [(X86retflag 0)], IIC_RET>;
24 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
26 [(X86retflag timm:$amt)], IIC_RET_IMM>;
27 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
29 [], IIC_RET_IMM>, OpSize;
30 def LRETL : I <0xCB, RawFrm, (outs), (ins),
31 "lretl", [], IIC_RET>;
32 def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
33 "lretq", [], IIC_RET>;
34 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
35 "lret\t$amt", [], IIC_RET>;
36 def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
37 "lretw\t$amt", [], IIC_RET>, OpSize;
40 // Unconditional branches.
41 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
42 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
43 "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>;
44 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
45 "jmp\t$dst", [], IIC_JMP_REL>;
46 // FIXME : Intel syntax for JMP64pcrel32 such that it is not ambiguious
48 def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst),
49 "jmpq\t$dst", [], IIC_JMP_REL>;
52 // Conditional Branches.
53 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
54 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
55 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, [],
57 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
58 [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, TB;
62 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
63 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
64 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
65 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
66 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
67 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
68 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
69 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
70 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
71 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
72 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
73 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
74 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
75 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
76 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
77 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
79 // jcx/jecx/jrcx instructions.
80 let isAsmParserOnly = 1, isBranch = 1, isTerminator = 1 in {
81 // These are the 32-bit versions of this instruction for the asmparser. In
82 // 32-bit mode, the address size prefix is jcxz and the unprefixed version is
85 def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
86 "jcxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[In32BitMode]>;
88 def JECXZ_32 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
89 "jecxz\t$dst", [], IIC_JCXZ>, Requires<[In32BitMode]>;
91 // J*CXZ instruction: 64-bit versions of this instruction for the asmparser.
92 // In 64-bit mode, the address size prefix is jecxz and the unprefixed version
95 def JECXZ_64 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
96 "jecxz\t$dst", [], IIC_JCXZ>, AdSize, Requires<[In64BitMode]>;
98 def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
99 "jrcxz\t$dst", [], IIC_JCXZ>, Requires<[In64BitMode]>;
103 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
104 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
105 [(brind GR32:$dst)], IIC_JMP_REG>, Requires<[In32BitMode]>;
106 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
107 [(brind (loadi32 addr:$dst))], IIC_JMP_MEM>, Requires<[In32BitMode]>;
109 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
110 [(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>;
111 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
112 [(brind (loadi64 addr:$dst))], IIC_JMP_MEM>, Requires<[In64BitMode]>;
114 def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
115 (ins i16imm:$off, i16imm:$seg),
116 "ljmp{w}\t{$seg, $off|$off, $seg}", [], IIC_JMP_FAR_PTR>, OpSize;
117 def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
118 (ins i32imm:$off, i16imm:$seg),
119 "ljmp{l}\t{$seg, $off|$off, $seg}", [], IIC_JMP_FAR_PTR>;
120 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
121 "ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>;
123 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
124 "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize;
125 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
126 "ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>;
132 def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", [], IIC_LOOP>;
133 def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", [], IIC_LOOPE>;
134 def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", [], IIC_LOOPNE>;
136 //===----------------------------------------------------------------------===//
137 // Call Instructions...
140 // All calls clobber the non-callee saved registers. ESP is marked as
141 // a use to prevent stack-pointer assignments that appear immediately
142 // before calls from potentially appearing dead. Uses for argument
143 // registers are added manually.
144 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
145 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
146 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
147 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
149 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
150 (outs), (ins i32imm_pcrel:$dst,variable_ops),
151 "call{l}\t$dst", [], IIC_CALL_RI>, Requires<[In32BitMode]>;
152 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
153 "call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>,
154 Requires<[In32BitMode]>;
155 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
156 "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))], IIC_CALL_MEM>,
157 Requires<[In32BitMode]>;
159 def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
160 (ins i16imm:$off, i16imm:$seg),
161 "lcall{w}\t{$seg, $off|$off, $seg}", [],
162 IIC_CALL_FAR_PTR>, OpSize;
163 def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
164 (ins i32imm:$off, i16imm:$seg),
165 "lcall{l}\t{$seg, $off|$off, $seg}", [],
168 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
169 "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize;
170 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
171 "lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>;
173 // callw for 16 bit code for the assembler.
174 let isAsmParserOnly = 1 in
175 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
176 (outs), (ins i16imm_pcrel:$dst, variable_ops),
177 "callw\t$dst", []>, OpSize;
183 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
185 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
186 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
187 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
188 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
190 def TCRETURNdi : PseudoI<(outs),
191 (ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops), []>;
192 def TCRETURNri : PseudoI<(outs),
193 (ins GR32_TC:$dst, i32imm:$offset, variable_ops), []>;
195 def TCRETURNmi : PseudoI<(outs),
196 (ins i32mem_TC:$dst, i32imm:$offset, variable_ops), []>;
198 // FIXME: The should be pseudo instructions that are lowered when going to
200 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
201 (ins i32imm_pcrel:$dst, variable_ops),
202 "jmp\t$dst # TAILCALL",
204 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
205 "", [], IIC_JMP_REG>; // FIXME: Remove encoding when JIT is dead.
207 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
208 "jmp{l}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;
212 //===----------------------------------------------------------------------===//
213 // Call Instructions...
216 // All calls clobber the non-callee saved registers. RSP is marked as
217 // a use to prevent stack-pointer assignments that appear immediately
218 // before calls from potentially appearing dead. Uses for argument
219 // registers are added manually.
220 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
221 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
222 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
223 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
224 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
227 // NOTE: this pattern doesn't match "X86call imm", because we do not know
228 // that the offset between an arbitrary immediate and the call will fit in
229 // the 32-bit pcrel field that we have.
230 def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
231 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
232 "call{q}\t$dst", [], IIC_CALL_RI>,
233 Requires<[In64BitMode, NotWin64]>;
234 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
235 "call{q}\t{*}$dst", [(X86call GR64:$dst)],
237 Requires<[In64BitMode, NotWin64]>;
238 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
239 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))],
241 Requires<[In64BitMode, NotWin64]>;
243 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
244 "lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>;
247 // FIXME: We need to teach codegen about single list of call-clobbered
249 let isCall = 1, isCodeGenOnly = 1 in
250 // All calls clobber the non-callee saved registers. RSP is marked as
251 // a use to prevent stack-pointer assignments that appear immediately
252 // before calls from potentially appearing dead. Uses for argument
253 // registers are added manually.
254 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
255 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
256 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
257 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, YMM_HI_6_15, EFLAGS],
259 def WINCALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
260 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
261 "call{q}\t$dst", [], IIC_CALL_RI>,
263 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
265 [(X86call GR64:$dst)], IIC_CALL_RI>,
267 def WINCALL64m : I<0xFF, MRM2m, (outs),
268 (ins i64mem:$dst,variable_ops),
270 [(X86call (loadi64 addr:$dst))], IIC_CALL_MEM>,
274 let isCall = 1, isCodeGenOnly = 1 in
275 // __chkstk(MSVC): clobber R10, R11 and EFLAGS.
276 // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP.
277 let Defs = [RAX, R10, R11, RSP, EFLAGS],
279 def W64ALLOCA : Ii32PCRel<0xE8, RawFrm,
280 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
281 "call{q}\t$dst", [], IIC_CALL_RI>,
285 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
287 // AMD64 cc clobbers RSI, RDI, XMM6-XMM15.
288 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
289 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
290 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
291 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
293 usesCustomInserter = 1 in {
294 def TCRETURNdi64 : PseudoI<(outs),
295 (ins i64i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
297 def TCRETURNri64 : PseudoI<(outs),
298 (ins ptr_rc_tailcall:$dst, i32imm:$offset, variable_ops), []>;
300 def TCRETURNmi64 : PseudoI<(outs),
301 (ins i64mem_TC:$dst, i32imm:$offset, variable_ops), []>;
303 def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs),
304 (ins i64i32imm_pcrel:$dst, variable_ops),
305 "jmp\t$dst # TAILCALL", [], IIC_JMP_REL>;
306 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst, variable_ops),
307 "jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;
310 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst, variable_ops),
311 "jmp{q}\t{*}$dst # TAILCALL", [], IIC_JMP_MEM>;