1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue());
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue());
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
48 [(X86callseq_start timm:$amt)]>,
49 Requires<[In32BitMode]>;
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
53 Requires<[In32BitMode]>;
56 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
57 // a stack adjustment and the codegen must know that they may modify the stack
58 // pointer before prolog-epilog rewriting occurs.
59 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
60 // sub / add which can clobber EFLAGS.
61 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
62 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
64 [(X86callseq_start timm:$amt)]>,
65 Requires<[In64BitMode]>;
66 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
68 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
69 Requires<[In64BitMode]>;
74 // x86-64 va_start lowering magic.
75 let usesCustomInserter = 1 in {
76 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
79 i64imm:$regsavefi, i64imm:$offset,
81 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
82 [(X86vastart_save_xmm_regs GR8:$al,
86 // The VAARG_64 pseudo-instruction takes the address of the va_list,
87 // and places the address of the next argument into a register.
88 let Defs = [EFLAGS] in
89 def VAARG_64 : I<0, Pseudo,
91 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
92 "#VAARG_64 $dst, $ap, $size, $mode, $align",
94 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
97 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
98 // targets. These calls are needed to probe the stack when allocating more than
99 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
100 // ensure that the guard pages used by the OS virtual memory manager are
101 // allocated in correct sequence.
102 // The main point of having separate instruction are extra unmodelled effects
103 // (compared to ordinary calls) like stack pointer change.
105 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
106 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
107 "# dynamic stack allocation",
113 //===----------------------------------------------------------------------===//
114 // EH Pseudo Instructions
116 let isTerminator = 1, isReturn = 1, isBarrier = 1,
117 hasCtrlDep = 1, isCodeGenOnly = 1 in {
118 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
119 "ret\t#eh_return, addr: $addr",
120 [(X86ehret GR32:$addr)]>;
124 let isTerminator = 1, isReturn = 1, isBarrier = 1,
125 hasCtrlDep = 1, isCodeGenOnly = 1 in {
126 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
127 "ret\t#eh_return, addr: $addr",
128 [(X86ehret GR64:$addr)]>;
132 //===----------------------------------------------------------------------===//
133 // Alias Instructions
134 //===----------------------------------------------------------------------===//
136 // Alias instructions that map movr0 to xor.
137 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
138 // FIXME: Set encoding to pseudo.
139 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
140 isCodeGenOnly = 1 in {
141 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
142 [(set GR8:$dst, 0)]>;
144 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
145 // encoding and avoids a partial-register update sometimes, but doing so
146 // at isel time interferes with rematerialization in the current register
147 // allocator. For now, this is rewritten when the instruction is lowered
149 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
151 [(set GR16:$dst, 0)]>, OpSize;
153 // FIXME: Set encoding to pseudo.
154 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
155 [(set GR32:$dst, 0)]>;
158 // We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
159 // smaller encoding, but doing so at isel time interferes with rematerialization
160 // in the current register allocator. For now, this is rewritten when the
161 // instruction is lowered to an MCInst.
162 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
163 // when we have a better way to specify isel priority.
164 let Defs = [EFLAGS], isCodeGenOnly=1,
165 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
166 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
167 [(set GR64:$dst, 0)]>;
169 // Materialize i64 constant where top 32-bits are zero. This could theoretically
170 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
171 // that would make it more difficult to rematerialize.
172 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
174 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
175 "", [(set GR64:$dst, i64immZExt32:$src)]>;
177 // Use sbb to materialize carry bit.
178 let Uses = [EFLAGS], Defs = [EFLAGS], isCodeGenOnly = 1 in {
179 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
180 // However, Pat<> can't replicate the destination reg into the inputs of the
182 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
184 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
185 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
186 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
187 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
189 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
190 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
191 def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
192 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
196 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
200 //===----------------------------------------------------------------------===//
201 // String Pseudo Instructions
203 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
204 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
205 [(X86rep_movs i8)]>, REP;
206 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
207 [(X86rep_movs i16)]>, REP, OpSize;
208 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
209 [(X86rep_movs i32)]>, REP;
212 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in
213 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
214 [(X86rep_movs i64)]>, REP;
217 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
218 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
219 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
220 [(X86rep_stos i8)]>, REP;
221 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
222 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
223 [(X86rep_stos i16)]>, REP, OpSize;
224 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
225 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
226 [(X86rep_stos i32)]>, REP;
228 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI], isCodeGenOnly = 1 in
229 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
230 [(X86rep_stos i64)]>, REP;
233 //===----------------------------------------------------------------------===//
234 // Thread Local Storage Instructions
238 // All calls clobber the non-callee saved registers. ESP is marked as
239 // a use to prevent stack-pointer assignments that appear immediately
240 // before calls from potentially appearing dead.
241 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
242 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
243 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
244 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
246 usesCustomInserter = 1 in
247 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
249 [(X86tlsaddr tls32addr:$sym)]>,
250 Requires<[In32BitMode]>;
252 // All calls clobber the non-callee saved registers. RSP is marked as
253 // a use to prevent stack-pointer assignments that appear immediately
254 // before calls from potentially appearing dead.
255 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
256 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
257 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
258 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
259 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
261 usesCustomInserter = 1 in
262 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
264 [(X86tlsaddr tls64addr:$sym)]>,
265 Requires<[In64BitMode]>;
267 // Darwin TLS Support
268 // For i386, the address of the thunk is passed on the stack, on return the
269 // address of the variable is in %eax. %ecx is trashed during the function
270 // call. All other registers are preserved.
271 let Defs = [EAX, ECX],
273 usesCustomInserter = 1 in
274 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
276 [(X86TLSCall addr:$sym)]>,
277 Requires<[In32BitMode]>;
279 // For x86_64, the address of the thunk is passed in %rdi, on return
280 // the address of the variable is in %rax. All other registers are preserved.
283 usesCustomInserter = 1 in
284 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
286 [(X86TLSCall addr:$sym)]>,
287 Requires<[In64BitMode]>;
290 //===----------------------------------------------------------------------===//
291 // Conditional Move Pseudo Instructions
293 let Constraints = "$src1 = $dst" in {
296 let Uses = [EFLAGS] in {
298 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
299 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
300 // however that requires promoting the operands, and can induce additional
301 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
302 // clobber EFLAGS, because if one of the operands is zero, the expansion
303 // could involve an xor.
304 let usesCustomInserter = 1, Constraints = "", Defs = [EFLAGS] in {
305 def CMOV_GR8 : I<0, Pseudo,
306 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
308 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
309 imm:$cond, EFLAGS))]>;
311 let Predicates = [NoCMov] in {
312 def CMOV_GR32 : I<0, Pseudo,
313 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
314 "#CMOV_GR32* PSEUDO!",
316 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
317 def CMOV_GR16 : I<0, Pseudo,
318 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
319 "#CMOV_GR16* PSEUDO!",
321 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
322 def CMOV_RFP32 : I<0, Pseudo,
324 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
325 "#CMOV_RFP32 PSEUDO!",
327 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
329 def CMOV_RFP64 : I<0, Pseudo,
331 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
332 "#CMOV_RFP64 PSEUDO!",
334 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
336 def CMOV_RFP80 : I<0, Pseudo,
338 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
339 "#CMOV_RFP80 PSEUDO!",
341 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
343 } // Predicates = [NoCMov]
344 } // UsesCustomInserter = 1, Constraints = "", Defs = [EFLAGS]
347 } // Constraints = "$src1 = $dst" in
350 //===----------------------------------------------------------------------===//
351 // Atomic Instruction Pseudo Instructions
352 //===----------------------------------------------------------------------===//
354 // Atomic exchange, and, or, xor
355 let Constraints = "$val = $dst", Defs = [EFLAGS],
356 usesCustomInserter = 1 in {
358 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
360 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
361 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
363 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
364 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
366 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
367 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
368 "#ATOMNAND8 PSEUDO!",
369 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
371 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
372 "#ATOMAND16 PSEUDO!",
373 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
374 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
376 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
377 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
378 "#ATOMXOR16 PSEUDO!",
379 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
380 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
381 "#ATOMNAND16 PSEUDO!",
382 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
383 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
384 "#ATOMMIN16 PSEUDO!",
385 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
386 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
387 "#ATOMMAX16 PSEUDO!",
388 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
389 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
390 "#ATOMUMIN16 PSEUDO!",
391 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
392 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
393 "#ATOMUMAX16 PSEUDO!",
394 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
397 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
398 "#ATOMAND32 PSEUDO!",
399 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
400 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
402 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
403 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
404 "#ATOMXOR32 PSEUDO!",
405 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
406 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
407 "#ATOMNAND32 PSEUDO!",
408 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
409 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
410 "#ATOMMIN32 PSEUDO!",
411 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
412 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
413 "#ATOMMAX32 PSEUDO!",
414 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
415 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
416 "#ATOMUMIN32 PSEUDO!",
417 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
418 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
419 "#ATOMUMAX32 PSEUDO!",
420 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
424 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
425 "#ATOMAND64 PSEUDO!",
426 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
427 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
429 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
430 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
431 "#ATOMXOR64 PSEUDO!",
432 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
433 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
434 "#ATOMNAND64 PSEUDO!",
435 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
436 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
437 "#ATOMMIN64 PSEUDO!",
438 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
439 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
440 "#ATOMMAX64 PSEUDO!",
441 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
442 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
443 "#ATOMUMIN64 PSEUDO!",
444 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
445 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
446 "#ATOMUMAX64 PSEUDO!",
447 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
450 let Constraints = "$val1 = $dst1, $val2 = $dst2",
451 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
452 Uses = [EAX, EBX, ECX, EDX],
453 mayLoad = 1, mayStore = 1,
454 usesCustomInserter = 1 in {
455 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
456 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
457 "#ATOMAND6432 PSEUDO!", []>;
458 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
459 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
460 "#ATOMOR6432 PSEUDO!", []>;
461 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
462 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
463 "#ATOMXOR6432 PSEUDO!", []>;
464 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
465 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
466 "#ATOMNAND6432 PSEUDO!", []>;
467 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
468 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
469 "#ATOMADD6432 PSEUDO!", []>;
470 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
471 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
472 "#ATOMSUB6432 PSEUDO!", []>;
473 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
474 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
475 "#ATOMSWAP6432 PSEUDO!", []>;
478 //===----------------------------------------------------------------------===//
479 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
480 //===----------------------------------------------------------------------===//
482 // FIXME: Use normal instructions and add lock prefix dynamically.
486 // TODO: Get this to fold the constant into the instruction.
487 let isCodeGenOnly = 1 in
488 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
490 "or{l}\t{$zero, $dst|$dst, $zero}",
491 []>, Requires<[In32BitMode]>, LOCK;
493 let hasSideEffects = 1 in
494 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
496 [(X86MemBarrier)]>, Requires<[HasSSE2]>;
498 // TODO: Get this to fold the constant into the instruction.
499 let hasSideEffects = 1, Defs = [ESP], isCodeGenOnly = 1 in
500 def Int_MemBarrierNoSSE64 : RI<0x09, MRM1r, (outs), (ins GR64:$zero),
502 "or{q}\t{$zero, (%rsp)|(%rsp), $zero}",
503 [(X86MemBarrierNoSSE GR64:$zero)]>,
504 Requires<[In64BitMode]>, LOCK;
507 // Optimized codegen when the non-memory output is not used.
508 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {
509 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
511 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
512 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
514 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
515 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
517 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
518 def LOCK_ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
520 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
522 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
524 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
525 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
527 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
528 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
530 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
531 def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
532 (ins i64mem:$dst, i64i32imm :$src2),
534 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
536 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
538 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
539 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
541 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
542 def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
543 (ins i64mem:$dst, i64i8imm :$src2),
545 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
547 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
549 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
550 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
552 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
553 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
555 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
556 def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
558 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
561 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
563 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
564 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
566 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
567 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
569 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
570 def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
571 (ins i64mem:$dst, i64i32imm:$src2),
573 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
576 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
578 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
579 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
581 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
582 def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
583 (ins i64mem:$dst, i64i8imm :$src2),
585 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
587 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
589 "inc{b}\t$dst", []>, LOCK;
590 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
592 "inc{w}\t$dst", []>, OpSize, LOCK;
593 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
595 "inc{l}\t$dst", []>, LOCK;
596 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
598 "inc{q}\t$dst", []>, LOCK;
600 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
602 "dec{b}\t$dst", []>, LOCK;
603 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
605 "dec{w}\t$dst", []>, OpSize, LOCK;
606 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
608 "dec{l}\t$dst", []>, LOCK;
609 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
611 "dec{q}\t$dst", []>, LOCK;
614 // Atomic compare and swap.
615 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
616 isCodeGenOnly = 1 in {
617 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
620 [(X86cas8 addr:$ptr)]>, TB, LOCK;
622 let Defs = [AL, EFLAGS], Uses = [AL], isCodeGenOnly = 1 in {
623 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
625 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
626 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
629 let Defs = [AX, EFLAGS], Uses = [AX], isCodeGenOnly = 1 in {
630 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
632 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
633 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
636 let Defs = [EAX, EFLAGS], Uses = [EAX], isCodeGenOnly = 1 in {
637 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
639 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
640 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
643 let Defs = [RAX, EFLAGS], Uses = [RAX], isCodeGenOnly = 1 in {
644 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
646 "cmpxchgq\t$swap,$ptr",
647 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
650 // Atomic exchange and add
651 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1 in {
652 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
654 "xadd{b}\t{$val, $ptr|$ptr, $val}",
655 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
657 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
659 "xadd{w}\t{$val, $ptr|$ptr, $val}",
660 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
662 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
664 "xadd{l}\t{$val, $ptr|$ptr, $val}",
665 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
667 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr),
670 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
674 //===----------------------------------------------------------------------===//
675 // Conditional Move Pseudo Instructions.
676 //===----------------------------------------------------------------------===//
679 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
680 // instruction selection into a branch sequence.
681 let Uses = [EFLAGS], usesCustomInserter = 1 in {
682 def CMOV_FR32 : I<0, Pseudo,
683 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
684 "#CMOV_FR32 PSEUDO!",
685 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
687 def CMOV_FR64 : I<0, Pseudo,
688 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
689 "#CMOV_FR64 PSEUDO!",
690 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
692 def CMOV_V4F32 : I<0, Pseudo,
693 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
694 "#CMOV_V4F32 PSEUDO!",
696 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
698 def CMOV_V2F64 : I<0, Pseudo,
699 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
700 "#CMOV_V2F64 PSEUDO!",
702 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
704 def CMOV_V2I64 : I<0, Pseudo,
705 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
706 "#CMOV_V2I64 PSEUDO!",
708 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
713 //===----------------------------------------------------------------------===//
714 // DAG Pattern Matching Rules
715 //===----------------------------------------------------------------------===//
717 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
718 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
719 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
720 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
721 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
722 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
723 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
725 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
726 (ADD32ri GR32:$src1, tconstpool:$src2)>;
727 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
728 (ADD32ri GR32:$src1, tjumptable:$src2)>;
729 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
730 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
731 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
732 (ADD32ri GR32:$src1, texternalsym:$src2)>;
733 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
734 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
736 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
737 (MOV32mi addr:$dst, tglobaladdr:$src)>;
738 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
739 (MOV32mi addr:$dst, texternalsym:$src)>;
740 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
741 (MOV32mi addr:$dst, tblockaddress:$src)>;
745 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
746 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
747 // 'movabs' predicate should handle this sort of thing.
748 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
749 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
750 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
751 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
752 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
753 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
754 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
755 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
756 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
757 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
759 // In static codegen with small code model, we can get the address of a label
760 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
761 // the MOV64ri64i32 should accept these.
762 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
763 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
764 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
765 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
766 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
767 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
768 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
769 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
770 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
771 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
773 // In kernel code model, we can get the address of a label
774 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
775 // the MOV64ri32 should accept these.
776 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
777 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
778 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
779 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
780 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
781 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
782 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
783 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
784 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
785 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
787 // If we have small model and -static mode, it is safe to store global addresses
788 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
789 // for MOV64mi32 should handle this sort of thing.
790 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
791 (MOV64mi32 addr:$dst, tconstpool:$src)>,
792 Requires<[NearData, IsStatic]>;
793 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
794 (MOV64mi32 addr:$dst, tjumptable:$src)>,
795 Requires<[NearData, IsStatic]>;
796 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
797 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
798 Requires<[NearData, IsStatic]>;
799 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
800 (MOV64mi32 addr:$dst, texternalsym:$src)>,
801 Requires<[NearData, IsStatic]>;
802 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
803 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
804 Requires<[NearData, IsStatic]>;
810 // tls has some funny stuff here...
811 // This corresponds to movabs $foo@tpoff, %rax
812 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
813 (MOV64ri tglobaltlsaddr :$dst)>;
814 // This corresponds to add $foo@tpoff, %rax
815 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
816 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
817 // This corresponds to mov foo@tpoff(%rbx), %eax
818 def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))),
819 (MOV64rm tglobaltlsaddr :$dst)>;
822 // Direct PC relative function call for small code model. 32-bit displacement
823 // sign extended to 64-bit.
824 def : Pat<(X86call (i64 tglobaladdr:$dst)),
825 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
826 def : Pat<(X86call (i64 texternalsym:$dst)),
827 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
829 def : Pat<(X86call (i64 tglobaladdr:$dst)),
830 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
831 def : Pat<(X86call (i64 texternalsym:$dst)),
832 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
835 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
836 (TCRETURNri GR32_TC:$dst, imm:$off)>,
837 Requires<[In32BitMode]>;
839 // FIXME: This is disabled for 32-bit PIC mode because the global base
840 // register which is part of the address mode may be assigned a
841 // callee-saved register.
842 def : Pat<(X86tcret (load addr:$dst), imm:$off),
843 (TCRETURNmi addr:$dst, imm:$off)>,
844 Requires<[In32BitMode, IsNotPIC]>;
846 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
847 (TCRETURNdi texternalsym:$dst, imm:$off)>,
848 Requires<[In32BitMode]>;
850 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
851 (TCRETURNdi texternalsym:$dst, imm:$off)>,
852 Requires<[In32BitMode]>;
854 def : Pat<(X86tcret GR64_TC:$dst, imm:$off),
855 (TCRETURNri64 GR64_TC:$dst, imm:$off)>,
856 Requires<[In64BitMode]>;
858 def : Pat<(X86tcret (load addr:$dst), imm:$off),
859 (TCRETURNmi64 addr:$dst, imm:$off)>,
860 Requires<[In64BitMode]>;
862 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
863 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
864 Requires<[In64BitMode]>;
866 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
867 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
868 Requires<[In64BitMode]>;
870 // Normal calls, with various flavors of addresses.
871 def : Pat<(X86call (i32 tglobaladdr:$dst)),
872 (CALLpcrel32 tglobaladdr:$dst)>;
873 def : Pat<(X86call (i32 texternalsym:$dst)),
874 (CALLpcrel32 texternalsym:$dst)>;
875 def : Pat<(X86call (i32 imm:$dst)),
876 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
878 // X86 specific add which produces a flag.
879 def : Pat<(addc GR32:$src1, GR32:$src2),
880 (ADD32rr GR32:$src1, GR32:$src2)>;
881 def : Pat<(addc GR32:$src1, (load addr:$src2)),
882 (ADD32rm GR32:$src1, addr:$src2)>;
883 def : Pat<(addc GR32:$src1, imm:$src2),
884 (ADD32ri GR32:$src1, imm:$src2)>;
885 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
886 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
888 def : Pat<(addc GR64:$src1, GR64:$src2),
889 (ADD64rr GR64:$src1, GR64:$src2)>;
890 def : Pat<(addc GR64:$src1, (load addr:$src2)),
891 (ADD64rm GR64:$src1, addr:$src2)>;
892 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
893 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
894 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
895 (ADD64ri32 GR64:$src1, imm:$src2)>;
897 def : Pat<(subc GR32:$src1, GR32:$src2),
898 (SUB32rr GR32:$src1, GR32:$src2)>;
899 def : Pat<(subc GR32:$src1, (load addr:$src2)),
900 (SUB32rm GR32:$src1, addr:$src2)>;
901 def : Pat<(subc GR32:$src1, imm:$src2),
902 (SUB32ri GR32:$src1, imm:$src2)>;
903 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
904 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
906 def : Pat<(subc GR64:$src1, GR64:$src2),
907 (SUB64rr GR64:$src1, GR64:$src2)>;
908 def : Pat<(subc GR64:$src1, (load addr:$src2)),
909 (SUB64rm GR64:$src1, addr:$src2)>;
910 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
911 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
912 def : Pat<(subc GR64:$src1, imm:$src2),
913 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
917 // TEST R,R is smaller than CMP R,0
918 def : Pat<(X86cmp GR8:$src1, 0),
919 (TEST8rr GR8:$src1, GR8:$src1)>;
920 def : Pat<(X86cmp GR16:$src1, 0),
921 (TEST16rr GR16:$src1, GR16:$src1)>;
922 def : Pat<(X86cmp GR32:$src1, 0),
923 (TEST32rr GR32:$src1, GR32:$src1)>;
924 def : Pat<(X86cmp GR64:$src1, 0),
925 (TEST64rr GR64:$src1, GR64:$src1)>;
927 // Conditional moves with folded loads with operands swapped and conditions
929 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
930 Instruction Inst64> {
931 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
932 (Inst16 GR16:$src2, addr:$src1)>;
933 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
934 (Inst32 GR32:$src2, addr:$src1)>;
935 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
936 (Inst64 GR64:$src2, addr:$src1)>;
939 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
940 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
941 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
942 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
943 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
944 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
945 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
946 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
947 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
948 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
949 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
950 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
951 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
952 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
953 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
954 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
956 // zextload bool -> zextload byte
957 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
958 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
959 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
960 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
962 // extload bool -> extload byte
963 // When extloading from 16-bit and smaller memory locations into 64-bit
964 // registers, use zero-extending loads so that the entire 64-bit register is
965 // defined, avoiding partial-register updates.
967 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
968 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
969 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
970 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
971 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
972 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
974 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
975 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
976 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
977 // For other extloads, use subregs, since the high contents of the register are
978 // defined after an extload.
979 def : Pat<(extloadi64i32 addr:$src),
980 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
983 // anyext. Define these to do an explicit zero-extend to
984 // avoid partial-register updates.
985 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
986 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
988 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
989 def : Pat<(i32 (anyext GR16:$src)),
990 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
992 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
993 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
994 def : Pat<(i64 (anyext GR32:$src)),
995 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
998 // Any instruction that defines a 32-bit result leaves the high half of the
999 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1000 // be copying from a truncate. And x86's cmov doesn't do anything if the
1001 // condition is false. But any other 32-bit operation will zero-extend
1003 def def32 : PatLeaf<(i32 GR32:$src), [{
1004 return N->getOpcode() != ISD::TRUNCATE &&
1005 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1006 N->getOpcode() != ISD::CopyFromReg &&
1007 N->getOpcode() != X86ISD::CMOV;
1010 // In the case of a 32-bit def that is known to implicitly zero-extend,
1011 // we can use a SUBREG_TO_REG.
1012 def : Pat<(i64 (zext def32:$src)),
1013 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1015 //===----------------------------------------------------------------------===//
1016 // Pattern match OR as ADD
1017 //===----------------------------------------------------------------------===//
1019 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1020 // 3-addressified into an LEA instruction to avoid copies. However, we also
1021 // want to finally emit these instructions as an or at the end of the code
1022 // generator to make the generated code easier to read. To do this, we select
1023 // into "disjoint bits" pseudo ops.
1025 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1026 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1027 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1028 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1030 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
1031 APInt Mask = APInt::getAllOnesValue(BitWidth);
1032 APInt KnownZero0, KnownOne0;
1033 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
1034 APInt KnownZero1, KnownOne1;
1035 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
1036 return (~KnownZero0 & ~KnownZero1) == 0;
1040 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1041 let AddedComplexity = 5 in { // Try this before the selecting to OR
1043 let isCommutable = 1, isConvertibleToThreeAddress = 1,
1044 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1045 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1046 "", // orw/addw REG, REG
1047 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1048 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1049 "", // orl/addl REG, REG
1050 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1051 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1052 "", // orq/addq REG, REG
1053 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1055 // NOTE: These are order specific, we want the ri8 forms to be listed
1056 // first so that they are slightly preferred to the ri forms.
1058 def ADD16ri8_DB : I<0, Pseudo,
1059 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1060 "", // orw/addw REG, imm8
1061 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1062 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1063 "", // orw/addw REG, imm
1064 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1066 def ADD32ri8_DB : I<0, Pseudo,
1067 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1068 "", // orl/addl REG, imm8
1069 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1070 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1071 "", // orl/addl REG, imm
1072 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1075 def ADD64ri8_DB : I<0, Pseudo,
1076 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1077 "", // orq/addq REG, imm8
1078 [(set GR64:$dst, (or_is_add GR64:$src1,
1079 i64immSExt8:$src2))]>;
1080 def ADD64ri32_DB : I<0, Pseudo,
1081 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1082 "", // orq/addq REG, imm
1083 [(set GR64:$dst, (or_is_add GR64:$src1,
1084 i64immSExt32:$src2))]>;
1086 } // AddedComplexity
1089 //===----------------------------------------------------------------------===//
1091 //===----------------------------------------------------------------------===//
1093 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1094 // +128 doesn't, so in this special case use a sub instead of an add.
1095 def : Pat<(add GR16:$src1, 128),
1096 (SUB16ri8 GR16:$src1, -128)>;
1097 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1098 (SUB16mi8 addr:$dst, -128)>;
1100 def : Pat<(add GR32:$src1, 128),
1101 (SUB32ri8 GR32:$src1, -128)>;
1102 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1103 (SUB32mi8 addr:$dst, -128)>;
1105 def : Pat<(add GR64:$src1, 128),
1106 (SUB64ri8 GR64:$src1, -128)>;
1107 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1108 (SUB64mi8 addr:$dst, -128)>;
1110 // The same trick applies for 32-bit immediate fields in 64-bit
1112 def : Pat<(add GR64:$src1, 0x0000000080000000),
1113 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1114 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1115 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1117 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1118 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1119 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1120 // represented with a sign extension of a 8 bit constant, use that.
1122 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1126 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1127 (i32 (GetLo8XForm imm:$imm))),
1130 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1134 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1135 (i32 (GetLo32XForm imm:$imm))),
1139 // r & (2^16-1) ==> movz
1140 def : Pat<(and GR32:$src1, 0xffff),
1141 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1142 // r & (2^8-1) ==> movz
1143 def : Pat<(and GR32:$src1, 0xff),
1144 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1147 Requires<[In32BitMode]>;
1148 // r & (2^8-1) ==> movz
1149 def : Pat<(and GR16:$src1, 0xff),
1150 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
1153 Requires<[In32BitMode]>;
1155 // r & (2^32-1) ==> movz
1156 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1157 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1158 // r & (2^16-1) ==> movz
1159 def : Pat<(and GR64:$src, 0xffff),
1160 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit)))>;
1161 // r & (2^8-1) ==> movz
1162 def : Pat<(and GR64:$src, 0xff),
1163 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit)))>;
1164 // r & (2^8-1) ==> movz
1165 def : Pat<(and GR32:$src1, 0xff),
1166 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1167 Requires<[In64BitMode]>;
1168 // r & (2^8-1) ==> movz
1169 def : Pat<(and GR16:$src1, 0xff),
1170 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)))>,
1171 Requires<[In64BitMode]>;
1174 // sext_inreg patterns
1175 def : Pat<(sext_inreg GR32:$src, i16),
1176 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1177 def : Pat<(sext_inreg GR32:$src, i8),
1178 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1181 Requires<[In32BitMode]>;
1182 def : Pat<(sext_inreg GR16:$src, i8),
1183 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1186 Requires<[In32BitMode]>;
1188 def : Pat<(sext_inreg GR64:$src, i32),
1189 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1190 def : Pat<(sext_inreg GR64:$src, i16),
1191 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1192 def : Pat<(sext_inreg GR64:$src, i8),
1193 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1194 def : Pat<(sext_inreg GR32:$src, i8),
1195 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1196 Requires<[In64BitMode]>;
1197 def : Pat<(sext_inreg GR16:$src, i8),
1198 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, sub_8bit)))>,
1199 Requires<[In64BitMode]>;
1203 def : Pat<(i16 (trunc GR32:$src)),
1204 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1205 def : Pat<(i8 (trunc GR32:$src)),
1206 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1208 Requires<[In32BitMode]>;
1209 def : Pat<(i8 (trunc GR16:$src)),
1210 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1212 Requires<[In32BitMode]>;
1213 def : Pat<(i32 (trunc GR64:$src)),
1214 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1215 def : Pat<(i16 (trunc GR64:$src)),
1216 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1217 def : Pat<(i8 (trunc GR64:$src)),
1218 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1219 def : Pat<(i8 (trunc GR32:$src)),
1220 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1221 Requires<[In64BitMode]>;
1222 def : Pat<(i8 (trunc GR16:$src)),
1223 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1224 Requires<[In64BitMode]>;
1226 // h-register tricks
1227 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1228 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1230 Requires<[In32BitMode]>;
1231 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1232 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1234 Requires<[In32BitMode]>;
1235 def : Pat<(srl GR16:$src, (i8 8)),
1238 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1241 Requires<[In32BitMode]>;
1242 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1243 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1246 Requires<[In32BitMode]>;
1247 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1248 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1251 Requires<[In32BitMode]>;
1252 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1253 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1256 Requires<[In32BitMode]>;
1257 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1258 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1261 Requires<[In32BitMode]>;
1263 // h-register tricks.
1264 // For now, be conservative on x86-64 and use an h-register extract only if the
1265 // value is immediately zero-extended or stored, which are somewhat common
1266 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1267 // from being allocated in the same instruction as the h register, as there's
1268 // currently no way to describe this requirement to the register allocator.
1270 // h-register extract and zero-extend.
1271 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1275 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1278 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1280 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1282 Requires<[In64BitMode]>;
1283 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1284 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1287 Requires<[In64BitMode]>;
1288 def : Pat<(srl GR16:$src, (i8 8)),
1291 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1294 Requires<[In64BitMode]>;
1295 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1297 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1299 Requires<[In64BitMode]>;
1300 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1302 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1304 Requires<[In64BitMode]>;
1305 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1309 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1312 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1316 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1320 // h-register extract and store.
1321 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1324 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1326 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1329 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1331 Requires<[In64BitMode]>;
1332 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1335 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1337 Requires<[In64BitMode]>;
1340 // (shl x, 1) ==> (add x, x)
1341 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1342 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1343 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1344 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1346 // (shl x (and y, 31)) ==> (shl x, y)
1347 def : Pat<(shl GR8:$src1, (and CL, 31)),
1348 (SHL8rCL GR8:$src1)>;
1349 def : Pat<(shl GR16:$src1, (and CL, 31)),
1350 (SHL16rCL GR16:$src1)>;
1351 def : Pat<(shl GR32:$src1, (and CL, 31)),
1352 (SHL32rCL GR32:$src1)>;
1353 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
1354 (SHL8mCL addr:$dst)>;
1355 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
1356 (SHL16mCL addr:$dst)>;
1357 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
1358 (SHL32mCL addr:$dst)>;
1360 def : Pat<(srl GR8:$src1, (and CL, 31)),
1361 (SHR8rCL GR8:$src1)>;
1362 def : Pat<(srl GR16:$src1, (and CL, 31)),
1363 (SHR16rCL GR16:$src1)>;
1364 def : Pat<(srl GR32:$src1, (and CL, 31)),
1365 (SHR32rCL GR32:$src1)>;
1366 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
1367 (SHR8mCL addr:$dst)>;
1368 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
1369 (SHR16mCL addr:$dst)>;
1370 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
1371 (SHR32mCL addr:$dst)>;
1373 def : Pat<(sra GR8:$src1, (and CL, 31)),
1374 (SAR8rCL GR8:$src1)>;
1375 def : Pat<(sra GR16:$src1, (and CL, 31)),
1376 (SAR16rCL GR16:$src1)>;
1377 def : Pat<(sra GR32:$src1, (and CL, 31)),
1378 (SAR32rCL GR32:$src1)>;
1379 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
1380 (SAR8mCL addr:$dst)>;
1381 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
1382 (SAR16mCL addr:$dst)>;
1383 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
1384 (SAR32mCL addr:$dst)>;
1386 // (shl x (and y, 63)) ==> (shl x, y)
1387 def : Pat<(shl GR64:$src1, (and CL, 63)),
1388 (SHL64rCL GR64:$src1)>;
1389 def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1390 (SHL64mCL addr:$dst)>;
1392 def : Pat<(srl GR64:$src1, (and CL, 63)),
1393 (SHR64rCL GR64:$src1)>;
1394 def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1395 (SHR64mCL addr:$dst)>;
1397 def : Pat<(sra GR64:$src1, (and CL, 63)),
1398 (SAR64rCL GR64:$src1)>;
1399 def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1400 (SAR64mCL addr:$dst)>;
1403 // (anyext (setcc_carry)) -> (setcc_carry)
1404 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1406 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1408 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1414 //===----------------------------------------------------------------------===//
1415 // EFLAGS-defining Patterns
1416 //===----------------------------------------------------------------------===//
1419 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1420 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1421 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1424 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1425 (ADD8rm GR8:$src1, addr:$src2)>;
1426 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1427 (ADD16rm GR16:$src1, addr:$src2)>;
1428 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1429 (ADD32rm GR32:$src1, addr:$src2)>;
1432 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1433 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1434 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1435 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1436 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1437 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1438 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1441 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1442 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1443 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1446 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1447 (SUB8rm GR8:$src1, addr:$src2)>;
1448 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1449 (SUB16rm GR16:$src1, addr:$src2)>;
1450 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1451 (SUB32rm GR32:$src1, addr:$src2)>;
1454 def : Pat<(sub GR8:$src1, imm:$src2),
1455 (SUB8ri GR8:$src1, imm:$src2)>;
1456 def : Pat<(sub GR16:$src1, imm:$src2),
1457 (SUB16ri GR16:$src1, imm:$src2)>;
1458 def : Pat<(sub GR32:$src1, imm:$src2),
1459 (SUB32ri GR32:$src1, imm:$src2)>;
1460 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1461 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1462 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1463 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1466 def : Pat<(mul GR16:$src1, GR16:$src2),
1467 (IMUL16rr GR16:$src1, GR16:$src2)>;
1468 def : Pat<(mul GR32:$src1, GR32:$src2),
1469 (IMUL32rr GR32:$src1, GR32:$src2)>;
1472 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1473 (IMUL16rm GR16:$src1, addr:$src2)>;
1474 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1475 (IMUL32rm GR32:$src1, addr:$src2)>;
1478 def : Pat<(mul GR16:$src1, imm:$src2),
1479 (IMUL16rri GR16:$src1, imm:$src2)>;
1480 def : Pat<(mul GR32:$src1, imm:$src2),
1481 (IMUL32rri GR32:$src1, imm:$src2)>;
1482 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1483 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1484 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1485 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1487 // reg = mul mem, imm
1488 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1489 (IMUL16rmi addr:$src1, imm:$src2)>;
1490 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1491 (IMUL32rmi addr:$src1, imm:$src2)>;
1492 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1493 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1494 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1495 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1497 // Optimize multiply by 2 with EFLAGS result.
1498 let AddedComplexity = 2 in {
1499 def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>;
1500 def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>;
1503 // Patterns for nodes that do not produce flags, for instructions that do.
1506 def : Pat<(add GR64:$src1, GR64:$src2),
1507 (ADD64rr GR64:$src1, GR64:$src2)>;
1508 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1509 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1510 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1511 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1512 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1513 (ADD64rm GR64:$src1, addr:$src2)>;
1516 def : Pat<(sub GR64:$src1, GR64:$src2),
1517 (SUB64rr GR64:$src1, GR64:$src2)>;
1518 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1519 (SUB64rm GR64:$src1, addr:$src2)>;
1520 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1521 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1522 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1523 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1526 def : Pat<(mul GR64:$src1, GR64:$src2),
1527 (IMUL64rr GR64:$src1, GR64:$src2)>;
1528 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1529 (IMUL64rm GR64:$src1, addr:$src2)>;
1530 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1531 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1532 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1533 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1534 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1535 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1536 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1537 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1540 def : Pat<(add GR8 :$src, 1), (INC8r GR8 :$src)>;
1541 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
1542 def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1543 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
1544 def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1545 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1548 def : Pat<(add GR8 :$src, -1), (DEC8r GR8 :$src)>;
1549 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
1550 def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1551 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
1552 def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1553 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1556 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1557 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1558 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1559 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1562 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1563 (OR8rm GR8:$src1, addr:$src2)>;
1564 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1565 (OR16rm GR16:$src1, addr:$src2)>;
1566 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1567 (OR32rm GR32:$src1, addr:$src2)>;
1568 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1569 (OR64rm GR64:$src1, addr:$src2)>;
1572 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1573 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1574 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1575 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1576 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1577 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1578 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1579 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1580 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1581 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1582 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1585 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1586 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1587 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1588 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1591 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1592 (XOR8rm GR8:$src1, addr:$src2)>;
1593 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1594 (XOR16rm GR16:$src1, addr:$src2)>;
1595 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1596 (XOR32rm GR32:$src1, addr:$src2)>;
1597 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1598 (XOR64rm GR64:$src1, addr:$src2)>;
1601 def : Pat<(xor GR8:$src1, imm:$src2),
1602 (XOR8ri GR8:$src1, imm:$src2)>;
1603 def : Pat<(xor GR16:$src1, imm:$src2),
1604 (XOR16ri GR16:$src1, imm:$src2)>;
1605 def : Pat<(xor GR32:$src1, imm:$src2),
1606 (XOR32ri GR32:$src1, imm:$src2)>;
1607 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1608 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1609 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1610 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1611 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1612 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1613 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1614 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1617 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1618 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1619 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1620 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1623 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1624 (AND8rm GR8:$src1, addr:$src2)>;
1625 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1626 (AND16rm GR16:$src1, addr:$src2)>;
1627 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1628 (AND32rm GR32:$src1, addr:$src2)>;
1629 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1630 (AND64rm GR64:$src1, addr:$src2)>;
1633 def : Pat<(and GR8:$src1, imm:$src2),
1634 (AND8ri GR8:$src1, imm:$src2)>;
1635 def : Pat<(and GR16:$src1, imm:$src2),
1636 (AND16ri GR16:$src1, imm:$src2)>;
1637 def : Pat<(and GR32:$src1, imm:$src2),
1638 (AND32ri GR32:$src1, imm:$src2)>;
1639 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1640 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1641 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1642 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1643 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1644 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1645 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1646 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;