1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
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3 // The LLVM Compiler Infrastructure
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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8 //===----------------------------------------------------------------------===//
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10 // This file describes the various pseudo instructions used by the compiler,
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11 // as well as Pat patterns used during instruction selection.
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13 //===----------------------------------------------------------------------===//
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15 //===----------------------------------------------------------------------===//
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16 // Pattern Matching Support
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18 def GetLo32XForm : SDNodeXForm<imm, [{
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19 // Transformation function: get the low 32 bits.
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20 return getI32Imm((unsigned)N->getZExtValue());
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23 def GetLo8XForm : SDNodeXForm<imm, [{
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24 // Transformation function: get the low 8 bits.
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25 return getI8Imm((uint8_t)N->getZExtValue());
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29 //===----------------------------------------------------------------------===//
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30 // Random Pseudo Instructions.
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32 // PIC base construction. This expands to code that looks like this:
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35 let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP] in
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36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
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40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
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41 // a stack adjustment and the codegen must know that they may modify the stack
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42 // pointer before prolog-epilog rewriting occurs.
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43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
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44 // sub / add which can clobber EFLAGS.
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45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
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46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
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47 "#ADJCALLSTACKDOWN",
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49 Requires<[NotLP64]>;
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50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
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52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
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53 Requires<[NotLP64]>;
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55 def : Pat<(X86callseq_start timm:$amt1),
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56 (ADJCALLSTACKDOWN32 i32imm:$amt1, 0)>, Requires<[NotLP64]>;
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59 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
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60 // a stack adjustment and the codegen must know that they may modify the stack
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61 // pointer before prolog-epilog rewriting occurs.
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62 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
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63 // sub / add which can clobber EFLAGS.
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64 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
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65 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
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66 "#ADJCALLSTACKDOWN",
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69 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
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71 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
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74 def : Pat<(X86callseq_start timm:$amt1),
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75 (ADJCALLSTACKDOWN64 i32imm:$amt1, 0)>, Requires<[IsLP64]>;
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78 // x86-64 va_start lowering magic.
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79 let usesCustomInserter = 1, Defs = [EFLAGS] in {
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80 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
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83 i64imm:$regsavefi, i64imm:$offset,
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85 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
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86 [(X86vastart_save_xmm_regs GR8:$al,
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89 (implicit EFLAGS)]>;
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91 // The VAARG_64 pseudo-instruction takes the address of the va_list,
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92 // and places the address of the next argument into a register.
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93 let Defs = [EFLAGS] in
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94 def VAARG_64 : I<0, Pseudo,
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96 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
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97 "#VAARG_64 $dst, $ap, $size, $mode, $align",
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99 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
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100 (implicit EFLAGS)]>;
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102 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
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103 // targets. These calls are needed to probe the stack when allocating more than
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104 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
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105 // ensure that the guard pages used by the OS virtual memory manager are
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106 // allocated in correct sequence.
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107 // The main point of having separate instruction are extra unmodelled effects
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108 // (compared to ordinary calls) like stack pointer change.
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110 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
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111 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
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112 "# dynamic stack allocation",
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115 // When using segmented stacks these are lowered into instructions which first
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116 // check if the current stacklet has enough free memory. If it does, memory is
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117 // allocated by bumping the stack pointer. Otherwise memory is allocated from
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120 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
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121 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
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122 "# variable sized alloca for segmented stacks",
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124 (X86SegAlloca GR32:$size))]>,
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125 Requires<[NotLP64]>;
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127 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
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128 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
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129 "# variable sized alloca for segmented stacks",
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131 (X86SegAlloca GR64:$size))]>,
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132 Requires<[In64BitMode]>;
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135 // The MSVC runtime contains an _ftol2 routine for converting floating-point
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136 // to integer values. It has a strange calling convention: the input is
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137 // popped from the x87 stack, and the return value is given in EDX:EAX. ECX is
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138 // used as a temporary register. No other registers (aside from flags) are
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140 // Microsoft toolchains do not support 80-bit precision, so a WIN_FTOL_80
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141 // variant is unnecessary.
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143 let Defs = [EAX, EDX, ECX, EFLAGS], FPForm = SpecialFP in {
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144 def WIN_FTOL_32 : I<0, Pseudo, (outs), (ins RFP32:$src),
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146 [(X86WinFTOL RFP32:$src)]>,
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147 Requires<[Not64BitMode]>;
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149 def WIN_FTOL_64 : I<0, Pseudo, (outs), (ins RFP64:$src),
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151 [(X86WinFTOL RFP64:$src)]>,
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152 Requires<[Not64BitMode]>;
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155 //===----------------------------------------------------------------------===//
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156 // EH Pseudo Instructions
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158 let SchedRW = [WriteSystem] in {
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159 let isTerminator = 1, isReturn = 1, isBarrier = 1,
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160 hasCtrlDep = 1, isCodeGenOnly = 1 in {
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161 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
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162 "ret\t#eh_return, addr: $addr",
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163 [(X86ehret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
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167 let isTerminator = 1, isReturn = 1, isBarrier = 1,
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168 hasCtrlDep = 1, isCodeGenOnly = 1 in {
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169 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
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170 "ret\t#eh_return, addr: $addr",
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171 [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
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175 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
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176 usesCustomInserter = 1 in {
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177 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
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178 "#EH_SJLJ_SETJMP32",
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179 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
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180 Requires<[Not64BitMode]>;
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181 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
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182 "#EH_SJLJ_SETJMP64",
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183 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
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184 Requires<[In64BitMode]>;
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185 let isTerminator = 1 in {
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186 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
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187 "#EH_SJLJ_LONGJMP32",
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188 [(X86eh_sjlj_longjmp addr:$buf)]>,
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189 Requires<[Not64BitMode]>;
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190 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
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191 "#EH_SJLJ_LONGJMP64",
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192 [(X86eh_sjlj_longjmp addr:$buf)]>,
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193 Requires<[In64BitMode]>;
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198 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
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199 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
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200 "#EH_SjLj_Setup\t$dst", []>;
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203 //===----------------------------------------------------------------------===//
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204 // Pseudo instructions used by unwind info.
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206 let isPseudo = 1 in {
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207 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg),
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208 "#SEH_PushReg $reg", []>;
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209 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
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210 "#SEH_SaveReg $reg, $dst", []>;
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211 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
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212 "#SEH_SaveXMM $reg, $dst", []>;
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213 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size),
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214 "#SEH_StackAlloc $size", []>;
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215 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset),
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216 "#SEH_SetFrame $reg, $offset", []>;
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217 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode),
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218 "#SEH_PushFrame $mode", []>;
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219 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins),
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220 "#SEH_EndPrologue", []>;
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221 def SEH_Epilogue : I<0, Pseudo, (outs), (ins),
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222 "#SEH_Epilogue", []>;
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225 //===----------------------------------------------------------------------===//
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226 // Pseudo instructions used by segmented stacks.
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229 // This is lowered into a RET instruction by MCInstLower. We need
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230 // this so that we don't have to have a MachineBasicBlock which ends
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231 // with a RET and also has successors.
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232 let isPseudo = 1 in {
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233 def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
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236 // This instruction is lowered to a RET followed by a MOV. The two
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237 // instructions are not generated on a higher level since then the
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238 // verifier sees a MachineBasicBlock ending with a non-terminator.
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239 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
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243 //===----------------------------------------------------------------------===//
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244 // Alias Instructions
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245 //===----------------------------------------------------------------------===//
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247 // Alias instruction mapping movr0 to xor.
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248 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
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249 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
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251 def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
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252 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
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254 // Other widths can also make use of the 32-bit xor, which may have a smaller
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255 // encoding and avoid partial register updates.
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256 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
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257 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
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258 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> {
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259 let AddedComplexity = 20;
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262 // Materialize i64 constant where top 32-bits are zero. This could theoretically
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263 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
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264 // that would make it more difficult to rematerialize.
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265 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
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266 isCodeGenOnly = 1, hasSideEffects = 0 in
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267 def MOV32ri64 : Ii32<0xb8, AddRegFrm, (outs GR32:$dst), (ins i64i32imm:$src),
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268 "", [], IIC_ALU_NONMEM>, Sched<[WriteALU]>;
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270 // This 64-bit pseudo-move can be used for both a 64-bit constant that is
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271 // actually the zero-extension of a 32-bit constant, and for labels in the
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272 // x86-64 small code model.
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273 def mov64imm32 : ComplexPattern<i64, 1, "SelectMOV64Imm32", [imm, X86Wrapper]>;
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275 let AddedComplexity = 1 in
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276 def : Pat<(i64 mov64imm32:$src),
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277 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>;
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279 // Use sbb to materialize carry bit.
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280 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in {
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281 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
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282 // However, Pat<> can't replicate the destination reg into the inputs of the
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284 def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "",
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285 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
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286 def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "",
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287 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
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288 def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "",
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289 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
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290 def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "",
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291 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
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295 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
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297 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
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299 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
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302 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
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304 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
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306 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
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309 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
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310 // will be eliminated and that the sbb can be extended up to a wider type. When
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311 // this happens, it is great. However, if we are left with an 8-bit sbb and an
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312 // and, we might as well just match it as a setb.
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313 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
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316 // (add OP, SETB) -> (adc OP, 0)
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317 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
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318 (ADC8ri GR8:$op, 0)>;
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319 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
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320 (ADC32ri8 GR32:$op, 0)>;
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321 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
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322 (ADC64ri8 GR64:$op, 0)>;
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324 // (sub OP, SETB) -> (sbb OP, 0)
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325 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
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326 (SBB8ri GR8:$op, 0)>;
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327 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
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328 (SBB32ri8 GR32:$op, 0)>;
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329 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
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330 (SBB64ri8 GR64:$op, 0)>;
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332 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
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333 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
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334 (ADC8ri GR8:$op, 0)>;
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335 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
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336 (ADC32ri8 GR32:$op, 0)>;
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337 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
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338 (ADC64ri8 GR64:$op, 0)>;
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340 //===----------------------------------------------------------------------===//
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341 // String Pseudo Instructions
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343 let SchedRW = [WriteMicrocoded] in {
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344 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
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345 def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
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346 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
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347 Requires<[Not64BitMode]>;
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348 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
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349 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
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350 Requires<[Not64BitMode]>;
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351 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
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352 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
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353 Requires<[Not64BitMode]>;
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356 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
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357 def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
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358 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
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359 Requires<[In64BitMode]>;
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360 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
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361 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
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362 Requires<[In64BitMode]>;
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363 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
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364 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
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365 Requires<[In64BitMode]>;
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366 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
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367 [(X86rep_movs i64)], IIC_REP_MOVS>, REP,
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368 Requires<[In64BitMode]>;
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371 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
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372 let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
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373 let Uses = [AL,ECX,EDI] in
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374 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
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375 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
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376 Requires<[Not64BitMode]>;
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377 let Uses = [AX,ECX,EDI] in
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378 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
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379 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
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380 Requires<[Not64BitMode]>;
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381 let Uses = [EAX,ECX,EDI] in
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382 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
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383 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
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384 Requires<[Not64BitMode]>;
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387 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
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388 let Uses = [AL,RCX,RDI] in
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389 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
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390 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
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391 Requires<[In64BitMode]>;
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392 let Uses = [AX,RCX,RDI] in
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393 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
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394 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
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395 Requires<[In64BitMode]>;
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396 let Uses = [RAX,RCX,RDI] in
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397 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
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398 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
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399 Requires<[In64BitMode]>;
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401 let Uses = [RAX,RCX,RDI] in
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402 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
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403 [(X86rep_stos i64)], IIC_REP_STOS>, REP,
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404 Requires<[In64BitMode]>;
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408 //===----------------------------------------------------------------------===//
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409 // Thread Local Storage Instructions
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413 // All calls clobber the non-callee saved registers. ESP is marked as
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414 // a use to prevent stack-pointer assignments that appear immediately
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415 // before calls from potentially appearing dead.
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416 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
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417 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
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418 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
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419 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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420 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
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422 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
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424 [(X86tlsaddr tls32addr:$sym)]>,
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425 Requires<[Not64BitMode]>;
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426 def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
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427 "# TLS_base_addr32",
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428 [(X86tlsbaseaddr tls32baseaddr:$sym)]>,
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429 Requires<[Not64BitMode]>;
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432 // All calls clobber the non-callee saved registers. RSP is marked as
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433 // a use to prevent stack-pointer assignments that appear immediately
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434 // before calls from potentially appearing dead.
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435 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
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436 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
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437 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
\r
438 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
\r
439 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
\r
440 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
\r
442 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
\r
444 [(X86tlsaddr tls64addr:$sym)]>,
\r
445 Requires<[In64BitMode]>;
\r
446 def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
\r
447 "# TLS_base_addr64",
\r
448 [(X86tlsbaseaddr tls64baseaddr:$sym)]>,
\r
449 Requires<[In64BitMode]>;
\r
452 // Darwin TLS Support
\r
453 // For i386, the address of the thunk is passed on the stack, on return the
\r
454 // address of the variable is in %eax. %ecx is trashed during the function
\r
455 // call. All other registers are preserved.
\r
456 let Defs = [EAX, ECX, EFLAGS],
\r
458 usesCustomInserter = 1 in
\r
459 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
\r
461 [(X86TLSCall addr:$sym)]>,
\r
462 Requires<[Not64BitMode]>;
\r
464 // For x86_64, the address of the thunk is passed in %rdi, on return
\r
465 // the address of the variable is in %rax. All other registers are preserved.
\r
466 let Defs = [RAX, EFLAGS],
\r
468 usesCustomInserter = 1 in
\r
469 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
\r
471 [(X86TLSCall addr:$sym)]>,
\r
472 Requires<[In64BitMode]>;
\r
475 //===----------------------------------------------------------------------===//
\r
476 // Conditional Move Pseudo Instructions
\r
478 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
\r
479 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
\r
480 // however that requires promoting the operands, and can induce additional
\r
481 // i8 register pressure.
\r
482 let usesCustomInserter = 1, Uses = [EFLAGS] in {
\r
483 def CMOV_GR8 : I<0, Pseudo,
\r
484 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
\r
485 "#CMOV_GR8 PSEUDO!",
\r
486 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
\r
487 imm:$cond, EFLAGS))]>;
\r
489 let Predicates = [NoCMov] in {
\r
490 def CMOV_GR32 : I<0, Pseudo,
\r
491 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
\r
492 "#CMOV_GR32* PSEUDO!",
\r
494 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
\r
495 def CMOV_GR16 : I<0, Pseudo,
\r
496 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
\r
497 "#CMOV_GR16* PSEUDO!",
\r
499 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
\r
500 } // Predicates = [NoCMov]
\r
502 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
\r
504 let Predicates = [FPStackf32] in
\r
505 def CMOV_RFP32 : I<0, Pseudo,
\r
507 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
\r
508 "#CMOV_RFP32 PSEUDO!",
\r
510 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
\r
512 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
\r
514 let Predicates = [FPStackf64] in
\r
515 def CMOV_RFP64 : I<0, Pseudo,
\r
517 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
\r
518 "#CMOV_RFP64 PSEUDO!",
\r
520 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
\r
522 def CMOV_RFP80 : I<0, Pseudo,
\r
524 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
\r
525 "#CMOV_RFP80 PSEUDO!",
\r
527 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
\r
529 } // UsesCustomInserter = 1, Uses = [EFLAGS]
\r
532 //===----------------------------------------------------------------------===//
\r
533 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
\r
534 //===----------------------------------------------------------------------===//
\r
536 // FIXME: Use normal instructions and add lock prefix dynamically.
\r
540 // TODO: Get this to fold the constant into the instruction.
\r
541 let isCodeGenOnly = 1, Defs = [EFLAGS] in
\r
542 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
\r
543 "or{l}\t{$zero, $dst|$dst, $zero}",
\r
544 [], IIC_ALU_MEM>, Requires<[Not64BitMode]>, LOCK,
\r
545 Sched<[WriteALULd, WriteRMW]>;
\r
547 let hasSideEffects = 1 in
\r
548 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
\r
550 [(X86MemBarrier)]>, Sched<[WriteLoad]>;
\r
552 // RegOpc corresponds to the mr version of the instruction
\r
553 // ImmOpc corresponds to the mi version of the instruction
\r
554 // ImmOpc8 corresponds to the mi8 version of the instruction
\r
555 // ImmMod corresponds to the instruction format of the mi and mi8 versions
\r
556 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
\r
557 Format ImmMod, string mnemonic> {
\r
558 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
\r
559 SchedRW = [WriteALULd, WriteRMW] in {
\r
561 def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
\r
562 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
\r
563 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
\r
564 !strconcat(mnemonic, "{b}\t",
\r
565 "{$src2, $dst|$dst, $src2}"),
\r
566 [], IIC_ALU_NONMEM>, LOCK;
\r
567 def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
\r
568 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
\r
569 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
\r
570 !strconcat(mnemonic, "{w}\t",
\r
571 "{$src2, $dst|$dst, $src2}"),
\r
572 [], IIC_ALU_NONMEM>, OpSize16, LOCK;
\r
573 def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
\r
574 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
\r
575 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
\r
576 !strconcat(mnemonic, "{l}\t",
\r
577 "{$src2, $dst|$dst, $src2}"),
\r
578 [], IIC_ALU_NONMEM>, OpSize32, LOCK;
\r
579 def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
\r
580 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
\r
581 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
\r
582 !strconcat(mnemonic, "{q}\t",
\r
583 "{$src2, $dst|$dst, $src2}"),
\r
584 [], IIC_ALU_NONMEM>, LOCK;
\r
586 def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
\r
587 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
\r
588 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
\r
589 !strconcat(mnemonic, "{b}\t",
\r
590 "{$src2, $dst|$dst, $src2}"),
\r
591 [], IIC_ALU_MEM>, LOCK;
\r
593 def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
\r
594 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
\r
595 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
\r
596 !strconcat(mnemonic, "{w}\t",
\r
597 "{$src2, $dst|$dst, $src2}"),
\r
598 [], IIC_ALU_MEM>, OpSize16, LOCK;
\r
600 def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
\r
601 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
\r
602 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
\r
603 !strconcat(mnemonic, "{l}\t",
\r
604 "{$src2, $dst|$dst, $src2}"),
\r
605 [], IIC_ALU_MEM>, OpSize32, LOCK;
\r
607 def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
\r
608 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
\r
609 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
\r
610 !strconcat(mnemonic, "{q}\t",
\r
611 "{$src2, $dst|$dst, $src2}"),
\r
612 [], IIC_ALU_MEM>, LOCK;
\r
614 def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
\r
615 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
\r
616 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
\r
617 !strconcat(mnemonic, "{w}\t",
\r
618 "{$src2, $dst|$dst, $src2}"),
\r
619 [], IIC_ALU_MEM>, OpSize16, LOCK;
\r
620 def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
\r
621 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
\r
622 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
\r
623 !strconcat(mnemonic, "{l}\t",
\r
624 "{$src2, $dst|$dst, $src2}"),
\r
625 [], IIC_ALU_MEM>, OpSize32, LOCK;
\r
626 def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
\r
627 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
\r
628 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
\r
629 !strconcat(mnemonic, "{q}\t",
\r
630 "{$src2, $dst|$dst, $src2}"),
\r
631 [], IIC_ALU_MEM>, LOCK;
\r
637 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
\r
638 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
\r
639 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
\r
640 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
\r
641 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
\r
643 // Optimized codegen when the non-memory output is not used.
\r
644 multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,
\r
646 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
\r
647 SchedRW = [WriteALULd, WriteRMW] in {
\r
649 def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
\r
650 !strconcat(mnemonic, "{b}\t$dst"),
\r
651 [], IIC_UNARY_MEM>, LOCK;
\r
652 def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
\r
653 !strconcat(mnemonic, "{w}\t$dst"),
\r
654 [], IIC_UNARY_MEM>, OpSize16, LOCK;
\r
655 def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
\r
656 !strconcat(mnemonic, "{l}\t$dst"),
\r
657 [], IIC_UNARY_MEM>, OpSize32, LOCK;
\r
658 def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
\r
659 !strconcat(mnemonic, "{q}\t$dst"),
\r
660 [], IIC_UNARY_MEM>, LOCK;
\r
664 defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">;
\r
665 defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">;
\r
667 // Atomic compare and swap.
\r
668 multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,
\r
669 SDPatternOperator frag, X86MemOperand x86memop,
\r
670 InstrItinClass itin> {
\r
671 let isCodeGenOnly = 1 in {
\r
672 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr),
\r
673 !strconcat(mnemonic, "\t$ptr"),
\r
674 [(frag addr:$ptr)], itin>, TB, LOCK;
\r
678 multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
\r
679 string mnemonic, SDPatternOperator frag,
\r
680 InstrItinClass itin8, InstrItinClass itin> {
\r
681 let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
\r
682 let Defs = [AL, EFLAGS], Uses = [AL] in
\r
683 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
\r
684 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"),
\r
685 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK;
\r
686 let Defs = [AX, EFLAGS], Uses = [AX] in
\r
687 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
\r
688 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
\r
689 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK;
\r
690 let Defs = [EAX, EFLAGS], Uses = [EAX] in
\r
691 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
\r
692 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
\r
693 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK;
\r
694 let Defs = [RAX, EFLAGS], Uses = [RAX] in
\r
695 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
\r
696 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
\r
697 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK;
\r
701 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
\r
702 SchedRW = [WriteALULd, WriteRMW] in {
\r
703 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",
\r
708 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
\r
709 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in {
\r
710 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
\r
712 IIC_CMPX_LOCK_16B>, REX_W;
\r
715 defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg",
\r
716 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>;
\r
718 // Atomic exchange and add
\r
719 multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
\r
721 InstrItinClass itin8, InstrItinClass itin> {
\r
722 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1,
\r
723 SchedRW = [WriteALULd, WriteRMW] in {
\r
724 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),
\r
725 (ins GR8:$val, i8mem:$ptr),
\r
726 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
\r
728 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
\r
730 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
\r
731 (ins GR16:$val, i16mem:$ptr),
\r
732 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
\r
735 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
\r
737 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
\r
738 (ins GR32:$val, i32mem:$ptr),
\r
739 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
\r
742 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
\r
744 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
\r
745 (ins GR64:$val, i64mem:$ptr),
\r
746 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
\r
749 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
\r
754 defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",
\r
755 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>,
\r
758 /* The following multiclass tries to make sure that in code like
\r
759 * x.store (immediate op x.load(acquire), release)
\r
760 * an operation directly on memory is generated instead of wasting a register.
\r
761 * It is not automatic as atomic_store/load are only lowered to MOV instructions
\r
762 * extremely late to prevent them from being accidentally reordered in the backend
\r
763 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions)
\r
765 multiclass RELEASE_BINOP_MI<string op> {
\r
766 def NAME#8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
\r
767 "#RELEASE_BINOP PSEUDO!",
\r
768 [(atomic_store_8 addr:$dst, (!cast<PatFrag>(op)
\r
769 (atomic_load_8 addr:$dst), (i8 imm:$src)))]>;
\r
770 // NAME#16 is not generated as 16-bit arithmetic instructions are considered
\r
771 // costly and avoided as far as possible by this backend anyway
\r
772 def NAME#32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
\r
773 "#RELEASE_BINOP PSEUDO!",
\r
774 [(atomic_store_32 addr:$dst, (!cast<PatFrag>(op)
\r
775 (atomic_load_32 addr:$dst), (i32 imm:$src)))]>;
\r
776 def NAME#64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
\r
777 "#RELEASE_BINOP PSEUDO!",
\r
778 [(atomic_store_64 addr:$dst, (!cast<PatFrag>(op)
\r
779 (atomic_load_64 addr:$dst), (i64immSExt32:$src)))]>;
\r
781 defm RELEASE_ADD : RELEASE_BINOP_MI<"add">;
\r
782 defm RELEASE_AND : RELEASE_BINOP_MI<"and">;
\r
783 defm RELEASE_OR : RELEASE_BINOP_MI<"or">;
\r
784 defm RELEASE_XOR : RELEASE_BINOP_MI<"xor">;
\r
785 // Note: we don't deal with sub, because substractions of constants are
\r
786 // optimized into additions before this code can run
\r
788 multiclass RELEASE_UNOP<dag dag8, dag dag16, dag dag32, dag dag64> {
\r
789 def NAME#8m : I<0, Pseudo, (outs), (ins i8mem:$dst),
\r
790 "#RELEASE_UNOP PSEUDO!",
\r
791 [(atomic_store_8 addr:$dst, dag8)]>;
\r
792 def NAME#16m : I<0, Pseudo, (outs), (ins i16mem:$dst),
\r
793 "#RELEASE_UNOP PSEUDO!",
\r
794 [(atomic_store_16 addr:$dst, dag16)]>;
\r
795 def NAME#32m : I<0, Pseudo, (outs), (ins i32mem:$dst),
\r
796 "#RELEASE_UNOP PSEUDO!",
\r
797 [(atomic_store_32 addr:$dst, dag32)]>;
\r
798 def NAME#64m : I<0, Pseudo, (outs), (ins i64mem:$dst),
\r
799 "#RELEASE_UNOP PSEUDO!",
\r
800 [(atomic_store_64 addr:$dst, dag64)]>;
\r
803 defm RELEASE_INC : RELEASE_UNOP<
\r
804 (add (atomic_load_8 addr:$dst), (i8 1)),
\r
805 (add (atomic_load_16 addr:$dst), (i16 1)),
\r
806 (add (atomic_load_32 addr:$dst), (i32 1)),
\r
807 (add (atomic_load_64 addr:$dst), (i64 1))>, Requires<[NotSlowIncDec]>;
\r
808 defm RELEASE_DEC : RELEASE_UNOP<
\r
809 (add (atomic_load_8 addr:$dst), (i8 -1)),
\r
810 (add (atomic_load_16 addr:$dst), (i16 -1)),
\r
811 (add (atomic_load_32 addr:$dst), (i32 -1)),
\r
812 (add (atomic_load_64 addr:$dst), (i64 -1))>, Requires<[NotSlowIncDec]>;
\r
814 TODO: These don't work because the type inference of TableGen fails.
\r
815 TODO: find a way to fix it.
\r
816 defm RELEASE_NEG : RELEASE_UNOP<
\r
817 (ineg (atomic_load_8 addr:$dst)),
\r
818 (ineg (atomic_load_16 addr:$dst)),
\r
819 (ineg (atomic_load_32 addr:$dst)),
\r
820 (ineg (atomic_load_64 addr:$dst))>;
\r
821 defm RELEASE_NOT : RELEASE_UNOP<
\r
822 (not (atomic_load_8 addr:$dst)),
\r
823 (not (atomic_load_16 addr:$dst)),
\r
824 (not (atomic_load_32 addr:$dst)),
\r
825 (not (atomic_load_64 addr:$dst))>;
\r
828 def RELEASE_MOV8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
\r
829 "#RELEASE_MOV PSEUDO !",
\r
830 [(atomic_store_8 addr:$dst, (i8 imm:$src))]>;
\r
831 def RELEASE_MOV16mi : I<0, Pseudo, (outs), (ins i16mem:$dst, i16imm:$src),
\r
832 "#RELEASE_MOV PSEUDO !",
\r
833 [(atomic_store_16 addr:$dst, (i16 imm:$src))]>;
\r
834 def RELEASE_MOV32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
\r
835 "#RELEASE_MOV PSEUDO !",
\r
836 [(atomic_store_32 addr:$dst, (i32 imm:$src))]>;
\r
837 def RELEASE_MOV64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
\r
838 "#RELEASE_MOV PSEUDO !",
\r
839 [(atomic_store_64 addr:$dst, i64immSExt32:$src)]>;
\r
841 def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
\r
842 "#RELEASE_MOV PSEUDO!",
\r
843 [(atomic_store_8 addr:$dst, GR8 :$src)]>;
\r
844 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
\r
845 "#RELEASE_MOV PSEUDO!",
\r
846 [(atomic_store_16 addr:$dst, GR16:$src)]>;
\r
847 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
\r
848 "#RELEASE_MOV PSEUDO!",
\r
849 [(atomic_store_32 addr:$dst, GR32:$src)]>;
\r
850 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
\r
851 "#RELEASE_MOV PSEUDO!",
\r
852 [(atomic_store_64 addr:$dst, GR64:$src)]>;
\r
854 def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
\r
855 "#ACQUIRE_MOV PSEUDO!",
\r
856 [(set GR8:$dst, (atomic_load_8 addr:$src))]>;
\r
857 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
\r
858 "#ACQUIRE_MOV PSEUDO!",
\r
859 [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
\r
860 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
\r
861 "#ACQUIRE_MOV PSEUDO!",
\r
862 [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
\r
863 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
\r
864 "#ACQUIRE_MOV PSEUDO!",
\r
865 [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
\r
866 //===----------------------------------------------------------------------===//
\r
867 // Conditional Move Pseudo Instructions.
\r
868 //===----------------------------------------------------------------------===//
\r
870 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
\r
871 // instruction selection into a branch sequence.
\r
872 let Uses = [EFLAGS], usesCustomInserter = 1 in {
\r
873 def CMOV_FR32 : I<0, Pseudo,
\r
874 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
\r
875 "#CMOV_FR32 PSEUDO!",
\r
876 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
\r
878 def CMOV_FR64 : I<0, Pseudo,
\r
879 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
\r
880 "#CMOV_FR64 PSEUDO!",
\r
881 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
\r
883 def CMOV_V4F32 : I<0, Pseudo,
\r
884 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
\r
885 "#CMOV_V4F32 PSEUDO!",
\r
887 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
\r
889 def CMOV_V2F64 : I<0, Pseudo,
\r
890 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
\r
891 "#CMOV_V2F64 PSEUDO!",
\r
893 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
\r
895 def CMOV_V2I64 : I<0, Pseudo,
\r
896 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
\r
897 "#CMOV_V2I64 PSEUDO!",
\r
899 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
\r
901 def CMOV_V8F32 : I<0, Pseudo,
\r
902 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
\r
903 "#CMOV_V8F32 PSEUDO!",
\r
905 (v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond,
\r
907 def CMOV_V4F64 : I<0, Pseudo,
\r
908 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
\r
909 "#CMOV_V4F64 PSEUDO!",
\r
911 (v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
\r
913 def CMOV_V4I64 : I<0, Pseudo,
\r
914 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
\r
915 "#CMOV_V4I64 PSEUDO!",
\r
917 (v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
\r
919 def CMOV_V8I64 : I<0, Pseudo,
\r
920 (outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond),
\r
921 "#CMOV_V8I64 PSEUDO!",
\r
923 (v8i64 (X86cmov VR512:$t, VR512:$f, imm:$cond,
\r
925 def CMOV_V8F64 : I<0, Pseudo,
\r
926 (outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond),
\r
927 "#CMOV_V8F64 PSEUDO!",
\r
929 (v8f64 (X86cmov VR512:$t, VR512:$f, imm:$cond,
\r
931 def CMOV_V16F32 : I<0, Pseudo,
\r
932 (outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond),
\r
933 "#CMOV_V16F32 PSEUDO!",
\r
935 (v16f32 (X86cmov VR512:$t, VR512:$f, imm:$cond,
\r
940 //===----------------------------------------------------------------------===//
\r
941 // DAG Pattern Matching Rules
\r
942 //===----------------------------------------------------------------------===//
\r
944 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
\r
945 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
\r
946 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
\r
947 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
\r
948 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
\r
949 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
\r
950 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
\r
952 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
\r
953 (ADD32ri GR32:$src1, tconstpool:$src2)>;
\r
954 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
\r
955 (ADD32ri GR32:$src1, tjumptable:$src2)>;
\r
956 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
\r
957 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
\r
958 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
\r
959 (ADD32ri GR32:$src1, texternalsym:$src2)>;
\r
960 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
\r
961 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
\r
963 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
\r
964 (MOV32mi addr:$dst, tglobaladdr:$src)>;
\r
965 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
\r
966 (MOV32mi addr:$dst, texternalsym:$src)>;
\r
967 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
\r
968 (MOV32mi addr:$dst, tblockaddress:$src)>;
\r
970 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
\r
971 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
\r
972 // 'movabs' predicate should handle this sort of thing.
\r
973 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
\r
974 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
\r
975 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
\r
976 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
\r
977 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
\r
978 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
\r
979 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
\r
980 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
\r
981 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
\r
982 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
\r
984 // In kernel code model, we can get the address of a label
\r
985 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
\r
986 // the MOV64ri32 should accept these.
\r
987 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
\r
988 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
\r
989 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
\r
990 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
\r
991 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
\r
992 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
\r
993 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
\r
994 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
\r
995 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
\r
996 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
\r
998 // If we have small model and -static mode, it is safe to store global addresses
\r
999 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
\r
1000 // for MOV64mi32 should handle this sort of thing.
\r
1001 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
\r
1002 (MOV64mi32 addr:$dst, tconstpool:$src)>,
\r
1003 Requires<[NearData, IsStatic]>;
\r
1004 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
\r
1005 (MOV64mi32 addr:$dst, tjumptable:$src)>,
\r
1006 Requires<[NearData, IsStatic]>;
\r
1007 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
\r
1008 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
\r
1009 Requires<[NearData, IsStatic]>;
\r
1010 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
\r
1011 (MOV64mi32 addr:$dst, texternalsym:$src)>,
\r
1012 Requires<[NearData, IsStatic]>;
\r
1013 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
\r
1014 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
\r
1015 Requires<[NearData, IsStatic]>;
\r
1017 def : Pat<(i32 (X86RecoverFrameAlloc texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
\r
1018 def : Pat<(i64 (X86RecoverFrameAlloc texternalsym:$dst)), (MOV64ri texternalsym:$dst)>;
\r
1022 // tls has some funny stuff here...
\r
1023 // This corresponds to movabs $foo@tpoff, %rax
\r
1024 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
\r
1025 (MOV64ri32 tglobaltlsaddr :$dst)>;
\r
1026 // This corresponds to add $foo@tpoff, %rax
\r
1027 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
\r
1028 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
\r
1031 // Direct PC relative function call for small code model. 32-bit displacement
\r
1032 // sign extended to 64-bit.
\r
1033 def : Pat<(X86call (i64 tglobaladdr:$dst)),
\r
1034 (CALL64pcrel32 tglobaladdr:$dst)>;
\r
1035 def : Pat<(X86call (i64 texternalsym:$dst)),
\r
1036 (CALL64pcrel32 texternalsym:$dst)>;
\r
1038 // Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
\r
1039 // can never use callee-saved registers. That is the purpose of the GR64_TC
\r
1040 // register classes.
\r
1042 // The only volatile register that is never used by the calling convention is
\r
1043 // %r11. This happens when calling a vararg function with 6 arguments.
\r
1045 // Match an X86tcret that uses less than 7 volatile registers.
\r
1046 def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
\r
1047 (X86tcret node:$ptr, node:$off), [{
\r
1048 // X86tcret args: (*chain, ptr, imm, regs..., glue)
\r
1049 unsigned NumRegs = 0;
\r
1050 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
\r
1051 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
\r
1056 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
\r
1057 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>,
\r
1058 Requires<[Not64BitMode]>;
\r
1060 // FIXME: This is disabled for 32-bit PIC mode because the global base
\r
1061 // register which is part of the address mode may be assigned a
\r
1062 // callee-saved register.
\r
1063 def : Pat<(X86tcret (load addr:$dst), imm:$off),
\r
1064 (TCRETURNmi addr:$dst, imm:$off)>,
\r
1065 Requires<[Not64BitMode, IsNotPIC]>;
\r
1067 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
\r
1068 (TCRETURNdi tglobaladdr:$dst, imm:$off)>,
\r
1069 Requires<[NotLP64]>;
\r
1071 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
\r
1072 (TCRETURNdi texternalsym:$dst, imm:$off)>,
\r
1073 Requires<[NotLP64]>;
\r
1075 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
\r
1076 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
\r
1077 Requires<[In64BitMode]>;
\r
1079 // Don't fold loads into X86tcret requiring more than 6 regs.
\r
1080 // There wouldn't be enough scratch registers for base+index.
\r
1081 def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
\r
1082 (TCRETURNmi64 addr:$dst, imm:$off)>,
\r
1083 Requires<[In64BitMode]>;
\r
1085 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
\r
1086 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
\r
1087 Requires<[IsLP64]>;
\r
1089 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
\r
1090 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
\r
1091 Requires<[IsLP64]>;
\r
1093 // Normal calls, with various flavors of addresses.
\r
1094 def : Pat<(X86call (i32 tglobaladdr:$dst)),
\r
1095 (CALLpcrel32 tglobaladdr:$dst)>;
\r
1096 def : Pat<(X86call (i32 texternalsym:$dst)),
\r
1097 (CALLpcrel32 texternalsym:$dst)>;
\r
1098 def : Pat<(X86call (i32 imm:$dst)),
\r
1099 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
\r
1103 // TEST R,R is smaller than CMP R,0
\r
1104 def : Pat<(X86cmp GR8:$src1, 0),
\r
1105 (TEST8rr GR8:$src1, GR8:$src1)>;
\r
1106 def : Pat<(X86cmp GR16:$src1, 0),
\r
1107 (TEST16rr GR16:$src1, GR16:$src1)>;
\r
1108 def : Pat<(X86cmp GR32:$src1, 0),
\r
1109 (TEST32rr GR32:$src1, GR32:$src1)>;
\r
1110 def : Pat<(X86cmp GR64:$src1, 0),
\r
1111 (TEST64rr GR64:$src1, GR64:$src1)>;
\r
1113 // Conditional moves with folded loads with operands swapped and conditions
\r
1115 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
\r
1116 Instruction Inst64> {
\r
1117 let Predicates = [HasCMov] in {
\r
1118 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
\r
1119 (Inst16 GR16:$src2, addr:$src1)>;
\r
1120 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
\r
1121 (Inst32 GR32:$src2, addr:$src1)>;
\r
1122 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
\r
1123 (Inst64 GR64:$src2, addr:$src1)>;
\r
1127 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
\r
1128 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
\r
1129 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
\r
1130 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
\r
1131 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
\r
1132 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
\r
1133 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
\r
1134 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
\r
1135 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
\r
1136 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
\r
1137 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
\r
1138 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
\r
1139 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
\r
1140 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
\r
1141 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
\r
1142 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
\r
1144 // zextload bool -> zextload byte
\r
1145 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
\r
1146 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
\r
1147 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
\r
1148 def : Pat<(zextloadi64i1 addr:$src),
\r
1149 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
\r
1151 // extload bool -> extload byte
\r
1152 // When extloading from 16-bit and smaller memory locations into 64-bit
\r
1153 // registers, use zero-extending loads so that the entire 64-bit register is
\r
1154 // defined, avoiding partial-register updates.
\r
1156 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
\r
1157 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
\r
1158 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
\r
1159 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
\r
1160 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
\r
1161 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
\r
1163 // For other extloads, use subregs, since the high contents of the register are
\r
1164 // defined after an extload.
\r
1165 def : Pat<(extloadi64i1 addr:$src),
\r
1166 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
\r
1167 def : Pat<(extloadi64i8 addr:$src),
\r
1168 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
\r
1169 def : Pat<(extloadi64i16 addr:$src),
\r
1170 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
\r
1171 def : Pat<(extloadi64i32 addr:$src),
\r
1172 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
\r
1174 // anyext. Define these to do an explicit zero-extend to
\r
1175 // avoid partial-register updates.
\r
1176 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
\r
1177 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
\r
1178 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
\r
1180 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
\r
1181 def : Pat<(i32 (anyext GR16:$src)),
\r
1182 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
\r
1184 def : Pat<(i64 (anyext GR8 :$src)),
\r
1185 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
\r
1186 def : Pat<(i64 (anyext GR16:$src)),
\r
1187 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
\r
1188 def : Pat<(i64 (anyext GR32:$src)),
\r
1189 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
\r
1192 // Any instruction that defines a 32-bit result leaves the high half of the
\r
1193 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
\r
1194 // be copying from a truncate. And x86's cmov doesn't do anything if the
\r
1195 // condition is false. But any other 32-bit operation will zero-extend
\r
1197 def def32 : PatLeaf<(i32 GR32:$src), [{
\r
1198 return N->getOpcode() != ISD::TRUNCATE &&
\r
1199 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
\r
1200 N->getOpcode() != ISD::CopyFromReg &&
\r
1201 N->getOpcode() != ISD::AssertSext &&
\r
1202 N->getOpcode() != X86ISD::CMOV;
\r
1205 // In the case of a 32-bit def that is known to implicitly zero-extend,
\r
1206 // we can use a SUBREG_TO_REG.
\r
1207 def : Pat<(i64 (zext def32:$src)),
\r
1208 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
\r
1210 //===----------------------------------------------------------------------===//
\r
1211 // Pattern match OR as ADD
\r
1212 //===----------------------------------------------------------------------===//
\r
1214 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
\r
1215 // 3-addressified into an LEA instruction to avoid copies. However, we also
\r
1216 // want to finally emit these instructions as an or at the end of the code
\r
1217 // generator to make the generated code easier to read. To do this, we select
\r
1218 // into "disjoint bits" pseudo ops.
\r
1220 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
\r
1221 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
\r
1222 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
\r
1223 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
\r
1225 APInt KnownZero0, KnownOne0;
\r
1226 CurDAG->computeKnownBits(N->getOperand(0), KnownZero0, KnownOne0, 0);
\r
1227 APInt KnownZero1, KnownOne1;
\r
1228 CurDAG->computeKnownBits(N->getOperand(1), KnownZero1, KnownOne1, 0);
\r
1229 return (~KnownZero0 & ~KnownZero1) == 0;
\r
1233 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
\r
1234 // Try this before the selecting to OR.
\r
1235 let AddedComplexity = 5, SchedRW = [WriteALU] in {
\r
1237 let isConvertibleToThreeAddress = 1,
\r
1238 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
\r
1239 let isCommutable = 1 in {
\r
1240 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
\r
1241 "", // orw/addw REG, REG
\r
1242 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
\r
1243 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
\r
1244 "", // orl/addl REG, REG
\r
1245 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
\r
1246 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
\r
1247 "", // orq/addq REG, REG
\r
1248 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
\r
1251 // NOTE: These are order specific, we want the ri8 forms to be listed
\r
1252 // first so that they are slightly preferred to the ri forms.
\r
1254 def ADD16ri8_DB : I<0, Pseudo,
\r
1255 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
\r
1256 "", // orw/addw REG, imm8
\r
1257 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
\r
1258 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
\r
1259 "", // orw/addw REG, imm
\r
1260 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
\r
1262 def ADD32ri8_DB : I<0, Pseudo,
\r
1263 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
\r
1264 "", // orl/addl REG, imm8
\r
1265 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
\r
1266 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
\r
1267 "", // orl/addl REG, imm
\r
1268 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
\r
1271 def ADD64ri8_DB : I<0, Pseudo,
\r
1272 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
\r
1273 "", // orq/addq REG, imm8
\r
1274 [(set GR64:$dst, (or_is_add GR64:$src1,
\r
1275 i64immSExt8:$src2))]>;
\r
1276 def ADD64ri32_DB : I<0, Pseudo,
\r
1277 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
\r
1278 "", // orq/addq REG, imm
\r
1279 [(set GR64:$dst, (or_is_add GR64:$src1,
\r
1280 i64immSExt32:$src2))]>;
\r
1282 } // AddedComplexity, SchedRW
\r
1285 //===----------------------------------------------------------------------===//
\r
1287 //===----------------------------------------------------------------------===//
\r
1289 // Odd encoding trick: -128 fits into an 8-bit immediate field while
\r
1290 // +128 doesn't, so in this special case use a sub instead of an add.
\r
1291 def : Pat<(add GR16:$src1, 128),
\r
1292 (SUB16ri8 GR16:$src1, -128)>;
\r
1293 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
\r
1294 (SUB16mi8 addr:$dst, -128)>;
\r
1296 def : Pat<(add GR32:$src1, 128),
\r
1297 (SUB32ri8 GR32:$src1, -128)>;
\r
1298 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
\r
1299 (SUB32mi8 addr:$dst, -128)>;
\r
1301 def : Pat<(add GR64:$src1, 128),
\r
1302 (SUB64ri8 GR64:$src1, -128)>;
\r
1303 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
\r
1304 (SUB64mi8 addr:$dst, -128)>;
\r
1306 // The same trick applies for 32-bit immediate fields in 64-bit
\r
1308 def : Pat<(add GR64:$src1, 0x0000000080000000),
\r
1309 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
\r
1310 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
\r
1311 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
\r
1313 // To avoid needing to materialize an immediate in a register, use a 32-bit and
\r
1314 // with implicit zero-extension instead of a 64-bit and if the immediate has at
\r
1315 // least 32 bits of leading zeros. If in addition the last 32 bits can be
\r
1316 // represented with a sign extension of a 8 bit constant, use that.
\r
1318 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
\r
1322 (EXTRACT_SUBREG GR64:$src, sub_32bit),
\r
1323 (i32 (GetLo8XForm imm:$imm))),
\r
1326 def : Pat<(and GR64:$src, i64immZExt32:$imm),
\r
1330 (EXTRACT_SUBREG GR64:$src, sub_32bit),
\r
1331 (i32 (GetLo32XForm imm:$imm))),
\r
1335 // r & (2^16-1) ==> movz
\r
1336 def : Pat<(and GR32:$src1, 0xffff),
\r
1337 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
\r
1338 // r & (2^8-1) ==> movz
\r
1339 def : Pat<(and GR32:$src1, 0xff),
\r
1340 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
\r
1343 Requires<[Not64BitMode]>;
\r
1344 // r & (2^8-1) ==> movz
\r
1345 def : Pat<(and GR16:$src1, 0xff),
\r
1346 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
\r
1347 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
\r
1349 Requires<[Not64BitMode]>;
\r
1351 // r & (2^32-1) ==> movz
\r
1352 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
\r
1353 (SUBREG_TO_REG (i64 0),
\r
1354 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)),
\r
1356 // r & (2^16-1) ==> movz
\r
1357 def : Pat<(and GR64:$src, 0xffff),
\r
1358 (SUBREG_TO_REG (i64 0),
\r
1359 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))),
\r
1361 // r & (2^8-1) ==> movz
\r
1362 def : Pat<(and GR64:$src, 0xff),
\r
1363 (SUBREG_TO_REG (i64 0),
\r
1364 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))),
\r
1366 // r & (2^8-1) ==> movz
\r
1367 def : Pat<(and GR32:$src1, 0xff),
\r
1368 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
\r
1369 Requires<[In64BitMode]>;
\r
1370 // r & (2^8-1) ==> movz
\r
1371 def : Pat<(and GR16:$src1, 0xff),
\r
1372 (EXTRACT_SUBREG (MOVZX32rr8 (i8
\r
1373 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
\r
1374 Requires<[In64BitMode]>;
\r
1377 // sext_inreg patterns
\r
1378 def : Pat<(sext_inreg GR32:$src, i16),
\r
1379 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
\r
1380 def : Pat<(sext_inreg GR32:$src, i8),
\r
1381 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
\r
1384 Requires<[Not64BitMode]>;
\r
1386 def : Pat<(sext_inreg GR16:$src, i8),
\r
1387 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
\r
1388 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
\r
1390 Requires<[Not64BitMode]>;
\r
1392 def : Pat<(sext_inreg GR64:$src, i32),
\r
1393 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
\r
1394 def : Pat<(sext_inreg GR64:$src, i16),
\r
1395 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
\r
1396 def : Pat<(sext_inreg GR64:$src, i8),
\r
1397 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
\r
1398 def : Pat<(sext_inreg GR32:$src, i8),
\r
1399 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
\r
1400 Requires<[In64BitMode]>;
\r
1401 def : Pat<(sext_inreg GR16:$src, i8),
\r
1402 (EXTRACT_SUBREG (MOVSX32rr8
\r
1403 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
\r
1404 Requires<[In64BitMode]>;
\r
1406 // sext, sext_load, zext, zext_load
\r
1407 def: Pat<(i16 (sext GR8:$src)),
\r
1408 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
\r
1409 def: Pat<(sextloadi16i8 addr:$src),
\r
1410 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
\r
1411 def: Pat<(i16 (zext GR8:$src)),
\r
1412 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
\r
1413 def: Pat<(zextloadi16i8 addr:$src),
\r
1414 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
\r
1417 def : Pat<(i16 (trunc GR32:$src)),
\r
1418 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
\r
1419 def : Pat<(i8 (trunc GR32:$src)),
\r
1420 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
\r
1422 Requires<[Not64BitMode]>;
\r
1423 def : Pat<(i8 (trunc GR16:$src)),
\r
1424 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
\r
1426 Requires<[Not64BitMode]>;
\r
1427 def : Pat<(i32 (trunc GR64:$src)),
\r
1428 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
\r
1429 def : Pat<(i16 (trunc GR64:$src)),
\r
1430 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
\r
1431 def : Pat<(i8 (trunc GR64:$src)),
\r
1432 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
\r
1433 def : Pat<(i8 (trunc GR32:$src)),
\r
1434 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
\r
1435 Requires<[In64BitMode]>;
\r
1436 def : Pat<(i8 (trunc GR16:$src)),
\r
1437 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
\r
1438 Requires<[In64BitMode]>;
\r
1440 // h-register tricks
\r
1441 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
\r
1442 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
\r
1444 Requires<[Not64BitMode]>;
\r
1445 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
\r
1446 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
\r
1448 Requires<[Not64BitMode]>;
\r
1449 def : Pat<(srl GR16:$src, (i8 8)),
\r
1452 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
\r
1455 Requires<[Not64BitMode]>;
\r
1456 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
\r
1457 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
\r
1460 Requires<[Not64BitMode]>;
\r
1461 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
\r
1462 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
\r
1465 Requires<[Not64BitMode]>;
\r
1466 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
\r
1467 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
\r
1470 Requires<[Not64BitMode]>;
\r
1471 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
\r
1472 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
\r
1475 Requires<[Not64BitMode]>;
\r
1477 // h-register tricks.
\r
1478 // For now, be conservative on x86-64 and use an h-register extract only if the
\r
1479 // value is immediately zero-extended or stored, which are somewhat common
\r
1480 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
\r
1481 // from being allocated in the same instruction as the h register, as there's
\r
1482 // currently no way to describe this requirement to the register allocator.
\r
1484 // h-register extract and zero-extend.
\r
1485 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
\r
1489 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
\r
1492 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
\r
1494 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
\r
1496 Requires<[In64BitMode]>;
\r
1497 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
\r
1498 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
\r
1501 Requires<[In64BitMode]>;
\r
1502 def : Pat<(srl GR16:$src, (i8 8)),
\r
1505 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
\r
1508 Requires<[In64BitMode]>;
\r
1509 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
\r
1511 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
\r
1513 Requires<[In64BitMode]>;
\r
1514 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
\r
1516 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
\r
1518 Requires<[In64BitMode]>;
\r
1519 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
\r
1523 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
\r
1526 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
\r
1530 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
\r
1534 // h-register extract and store.
\r
1535 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
\r
1538 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
\r
1540 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
\r
1543 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
\r
1545 Requires<[In64BitMode]>;
\r
1546 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
\r
1549 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
\r
1551 Requires<[In64BitMode]>;
\r
1554 // (shl x, 1) ==> (add x, x)
\r
1555 // Note that if x is undef (immediate or otherwise), we could theoretically
\r
1556 // end up with the two uses of x getting different values, producing a result
\r
1557 // where the least significant bit is not 0. However, the probability of this
\r
1558 // happening is considered low enough that this is officially not a
\r
1559 // "real problem".
\r
1560 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
\r
1561 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
\r
1562 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
\r
1563 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
\r
1565 // Helper imms that check if a mask doesn't change significant shift bits.
\r
1566 def immShift32 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 5; }]>;
\r
1567 def immShift64 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 6; }]>;
\r
1569 // Shift amount is implicitly masked.
\r
1570 multiclass MaskedShiftAmountPats<SDNode frag, string name> {
\r
1571 // (shift x (and y, 31)) ==> (shift x, y)
\r
1572 def : Pat<(frag GR8:$src1, (and CL, immShift32)),
\r
1573 (!cast<Instruction>(name # "8rCL") GR8:$src1)>;
\r
1574 def : Pat<(frag GR16:$src1, (and CL, immShift32)),
\r
1575 (!cast<Instruction>(name # "16rCL") GR16:$src1)>;
\r
1576 def : Pat<(frag GR32:$src1, (and CL, immShift32)),
\r
1577 (!cast<Instruction>(name # "32rCL") GR32:$src1)>;
\r
1578 def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
\r
1579 (!cast<Instruction>(name # "8mCL") addr:$dst)>;
\r
1580 def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
\r
1581 (!cast<Instruction>(name # "16mCL") addr:$dst)>;
\r
1582 def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
\r
1583 (!cast<Instruction>(name # "32mCL") addr:$dst)>;
\r
1585 // (shift x (and y, 63)) ==> (shift x, y)
\r
1586 def : Pat<(frag GR64:$src1, (and CL, immShift64)),
\r
1587 (!cast<Instruction>(name # "64rCL") GR64:$src1)>;
\r
1588 def : Pat<(store (frag (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
\r
1589 (!cast<Instruction>(name # "64mCL") addr:$dst)>;
\r
1592 defm : MaskedShiftAmountPats<shl, "SHL">;
\r
1593 defm : MaskedShiftAmountPats<srl, "SHR">;
\r
1594 defm : MaskedShiftAmountPats<sra, "SAR">;
\r
1595 defm : MaskedShiftAmountPats<rotl, "ROL">;
\r
1596 defm : MaskedShiftAmountPats<rotr, "ROR">;
\r
1598 // (anyext (setcc_carry)) -> (setcc_carry)
\r
1599 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
\r
1601 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
\r
1603 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
\r
1609 //===----------------------------------------------------------------------===//
\r
1610 // EFLAGS-defining Patterns
\r
1611 //===----------------------------------------------------------------------===//
\r
1614 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
\r
1615 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
\r
1616 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
\r
1619 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
\r
1620 (ADD8rm GR8:$src1, addr:$src2)>;
\r
1621 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
\r
1622 (ADD16rm GR16:$src1, addr:$src2)>;
\r
1623 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
\r
1624 (ADD32rm GR32:$src1, addr:$src2)>;
\r
1627 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
\r
1628 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
\r
1629 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
\r
1630 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
\r
1631 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
\r
1632 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
\r
1633 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
\r
1636 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
\r
1637 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
\r
1638 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
\r
1641 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
\r
1642 (SUB8rm GR8:$src1, addr:$src2)>;
\r
1643 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
\r
1644 (SUB16rm GR16:$src1, addr:$src2)>;
\r
1645 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
\r
1646 (SUB32rm GR32:$src1, addr:$src2)>;
\r
1649 def : Pat<(sub GR8:$src1, imm:$src2),
\r
1650 (SUB8ri GR8:$src1, imm:$src2)>;
\r
1651 def : Pat<(sub GR16:$src1, imm:$src2),
\r
1652 (SUB16ri GR16:$src1, imm:$src2)>;
\r
1653 def : Pat<(sub GR32:$src1, imm:$src2),
\r
1654 (SUB32ri GR32:$src1, imm:$src2)>;
\r
1655 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
\r
1656 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
\r
1657 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
\r
1658 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
\r
1661 def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>;
\r
1662 def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>;
\r
1663 def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
\r
1664 def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>;
\r
1667 def : Pat<(mul GR16:$src1, GR16:$src2),
\r
1668 (IMUL16rr GR16:$src1, GR16:$src2)>;
\r
1669 def : Pat<(mul GR32:$src1, GR32:$src2),
\r
1670 (IMUL32rr GR32:$src1, GR32:$src2)>;
\r
1673 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
\r
1674 (IMUL16rm GR16:$src1, addr:$src2)>;
\r
1675 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
\r
1676 (IMUL32rm GR32:$src1, addr:$src2)>;
\r
1679 def : Pat<(mul GR16:$src1, imm:$src2),
\r
1680 (IMUL16rri GR16:$src1, imm:$src2)>;
\r
1681 def : Pat<(mul GR32:$src1, imm:$src2),
\r
1682 (IMUL32rri GR32:$src1, imm:$src2)>;
\r
1683 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
\r
1684 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
\r
1685 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
\r
1686 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
\r
1688 // reg = mul mem, imm
\r
1689 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
\r
1690 (IMUL16rmi addr:$src1, imm:$src2)>;
\r
1691 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
\r
1692 (IMUL32rmi addr:$src1, imm:$src2)>;
\r
1693 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
\r
1694 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
\r
1695 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
\r
1696 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
\r
1698 // Patterns for nodes that do not produce flags, for instructions that do.
\r
1701 def : Pat<(add GR64:$src1, GR64:$src2),
\r
1702 (ADD64rr GR64:$src1, GR64:$src2)>;
\r
1703 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
\r
1704 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
\r
1705 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
\r
1706 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
\r
1707 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
\r
1708 (ADD64rm GR64:$src1, addr:$src2)>;
\r
1711 def : Pat<(sub GR64:$src1, GR64:$src2),
\r
1712 (SUB64rr GR64:$src1, GR64:$src2)>;
\r
1713 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
\r
1714 (SUB64rm GR64:$src1, addr:$src2)>;
\r
1715 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
\r
1716 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
\r
1717 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
\r
1718 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
\r
1721 def : Pat<(mul GR64:$src1, GR64:$src2),
\r
1722 (IMUL64rr GR64:$src1, GR64:$src2)>;
\r
1723 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
\r
1724 (IMUL64rm GR64:$src1, addr:$src2)>;
\r
1725 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
\r
1726 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
\r
1727 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
\r
1728 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
\r
1729 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
\r
1730 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
\r
1731 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
\r
1732 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
\r
1734 // Increment/Decrement reg.
\r
1735 // Do not make INC/DEC if it is slow
\r
1736 let Predicates = [NotSlowIncDec] in {
\r
1737 def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>;
\r
1738 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>;
\r
1739 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>;
\r
1740 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
\r
1741 def : Pat<(add GR8:$src, -1), (DEC8r GR8:$src)>;
\r
1742 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>;
\r
1743 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>;
\r
1744 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
\r
1748 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
\r
1749 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
\r
1750 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
\r
1751 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
\r
1754 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
\r
1755 (OR8rm GR8:$src1, addr:$src2)>;
\r
1756 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
\r
1757 (OR16rm GR16:$src1, addr:$src2)>;
\r
1758 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
\r
1759 (OR32rm GR32:$src1, addr:$src2)>;
\r
1760 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
\r
1761 (OR64rm GR64:$src1, addr:$src2)>;
\r
1764 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
\r
1765 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
\r
1766 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
\r
1767 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
\r
1768 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
\r
1769 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
\r
1770 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
\r
1771 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
\r
1772 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
\r
1773 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
\r
1774 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
\r
1777 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
\r
1778 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
\r
1779 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
\r
1780 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
\r
1783 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
\r
1784 (XOR8rm GR8:$src1, addr:$src2)>;
\r
1785 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
\r
1786 (XOR16rm GR16:$src1, addr:$src2)>;
\r
1787 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
\r
1788 (XOR32rm GR32:$src1, addr:$src2)>;
\r
1789 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
\r
1790 (XOR64rm GR64:$src1, addr:$src2)>;
\r
1793 def : Pat<(xor GR8:$src1, imm:$src2),
\r
1794 (XOR8ri GR8:$src1, imm:$src2)>;
\r
1795 def : Pat<(xor GR16:$src1, imm:$src2),
\r
1796 (XOR16ri GR16:$src1, imm:$src2)>;
\r
1797 def : Pat<(xor GR32:$src1, imm:$src2),
\r
1798 (XOR32ri GR32:$src1, imm:$src2)>;
\r
1799 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
\r
1800 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
\r
1801 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
\r
1802 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
\r
1803 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
\r
1804 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
\r
1805 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
\r
1806 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
\r
1809 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
\r
1810 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
\r
1811 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
\r
1812 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
\r
1815 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
\r
1816 (AND8rm GR8:$src1, addr:$src2)>;
\r
1817 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
\r
1818 (AND16rm GR16:$src1, addr:$src2)>;
\r
1819 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
\r
1820 (AND32rm GR32:$src1, addr:$src2)>;
\r
1821 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
\r
1822 (AND64rm GR64:$src1, addr:$src2)>;
\r
1825 def : Pat<(and GR8:$src1, imm:$src2),
\r
1826 (AND8ri GR8:$src1, imm:$src2)>;
\r
1827 def : Pat<(and GR16:$src1, imm:$src2),
\r
1828 (AND16ri GR16:$src1, imm:$src2)>;
\r
1829 def : Pat<(and GR32:$src1, imm:$src2),
\r
1830 (AND32ri GR32:$src1, imm:$src2)>;
\r
1831 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
\r
1832 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
\r
1833 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
\r
1834 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
\r
1835 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
\r
1836 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
\r
1837 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
\r
1838 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
\r
1840 // Bit scan instruction patterns to match explicit zero-undef behavior.
\r
1841 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
\r
1842 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
\r
1843 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
\r
1844 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
\r
1845 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
\r
1846 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;
\r
1848 // When HasMOVBE is enabled it is possible to get a non-legalized
\r
1849 // register-register 16 bit bswap. This maps it to a ROL instruction.
\r
1850 let Predicates = [HasMOVBE] in {
\r
1851 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>;
\r
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