1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue());
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue());
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
48 [(X86callseq_start timm:$amt)]>,
49 Requires<[Not64BitMode]>;
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
53 Requires<[Not64BitMode]>;
56 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
57 // a stack adjustment and the codegen must know that they may modify the stack
58 // pointer before prolog-epilog rewriting occurs.
59 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
60 // sub / add which can clobber EFLAGS.
61 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
62 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
64 [(X86callseq_start timm:$amt)]>,
65 Requires<[In64BitMode]>;
66 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
68 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
69 Requires<[In64BitMode]>;
74 // x86-64 va_start lowering magic.
75 let usesCustomInserter = 1, Defs = [EFLAGS] in {
76 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
79 i64imm:$regsavefi, i64imm:$offset,
81 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
82 [(X86vastart_save_xmm_regs GR8:$al,
87 // The VAARG_64 pseudo-instruction takes the address of the va_list,
88 // and places the address of the next argument into a register.
89 let Defs = [EFLAGS] in
90 def VAARG_64 : I<0, Pseudo,
92 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
93 "#VAARG_64 $dst, $ap, $size, $mode, $align",
95 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
98 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
99 // targets. These calls are needed to probe the stack when allocating more than
100 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
101 // ensure that the guard pages used by the OS virtual memory manager are
102 // allocated in correct sequence.
103 // The main point of having separate instruction are extra unmodelled effects
104 // (compared to ordinary calls) like stack pointer change.
106 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
107 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
108 "# dynamic stack allocation",
111 // When using segmented stacks these are lowered into instructions which first
112 // check if the current stacklet has enough free memory. If it does, memory is
113 // allocated by bumping the stack pointer. Otherwise memory is allocated from
116 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
117 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
118 "# variable sized alloca for segmented stacks",
120 (X86SegAlloca GR32:$size))]>,
121 Requires<[Not64BitMode]>;
123 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
124 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
125 "# variable sized alloca for segmented stacks",
127 (X86SegAlloca GR64:$size))]>,
128 Requires<[In64BitMode]>;
131 // The MSVC runtime contains an _ftol2 routine for converting floating-point
132 // to integer values. It has a strange calling convention: the input is
133 // popped from the x87 stack, and the return value is given in EDX:EAX. ECX is
134 // used as a temporary register. No other registers (aside from flags) are
136 // Microsoft toolchains do not support 80-bit precision, so a WIN_FTOL_80
137 // variant is unnecessary.
139 let Defs = [EAX, EDX, ECX, EFLAGS], FPForm = SpecialFP in {
140 def WIN_FTOL_32 : I<0, Pseudo, (outs), (ins RFP32:$src),
142 [(X86WinFTOL RFP32:$src)]>,
143 Requires<[Not64BitMode]>;
145 def WIN_FTOL_64 : I<0, Pseudo, (outs), (ins RFP64:$src),
147 [(X86WinFTOL RFP64:$src)]>,
148 Requires<[Not64BitMode]>;
151 //===----------------------------------------------------------------------===//
152 // EH Pseudo Instructions
154 let SchedRW = [WriteSystem] in {
155 let isTerminator = 1, isReturn = 1, isBarrier = 1,
156 hasCtrlDep = 1, isCodeGenOnly = 1 in {
157 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
158 "ret\t#eh_return, addr: $addr",
159 [(X86ehret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
163 let isTerminator = 1, isReturn = 1, isBarrier = 1,
164 hasCtrlDep = 1, isCodeGenOnly = 1 in {
165 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
166 "ret\t#eh_return, addr: $addr",
167 [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
171 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
172 usesCustomInserter = 1 in {
173 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
175 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
176 Requires<[Not64BitMode]>;
177 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
179 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
180 Requires<[In64BitMode]>;
181 let isTerminator = 1 in {
182 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
183 "#EH_SJLJ_LONGJMP32",
184 [(X86eh_sjlj_longjmp addr:$buf)]>,
185 Requires<[Not64BitMode]>;
186 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
187 "#EH_SJLJ_LONGJMP64",
188 [(X86eh_sjlj_longjmp addr:$buf)]>,
189 Requires<[In64BitMode]>;
194 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
195 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
196 "#EH_SjLj_Setup\t$dst", []>;
199 //===----------------------------------------------------------------------===//
200 // Pseudo instructions used by unwind info.
202 let isPseudo = 1 in {
203 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg),
204 "#SEH_PushReg $reg", []>;
205 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
206 "#SEH_SaveReg $reg, $dst", []>;
207 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
208 "#SEH_SaveXMM $reg, $dst", []>;
209 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size),
210 "#SEH_StackAlloc $size", []>;
211 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset),
212 "#SEH_SetFrame $reg, $offset", []>;
213 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode),
214 "#SEH_PushFrame $mode", []>;
215 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins),
216 "#SEH_EndPrologue", []>;
219 //===----------------------------------------------------------------------===//
220 // Pseudo instructions used by segmented stacks.
223 // This is lowered into a RET instruction by MCInstLower. We need
224 // this so that we don't have to have a MachineBasicBlock which ends
225 // with a RET and also has successors.
226 let isPseudo = 1 in {
227 def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
230 // This instruction is lowered to a RET followed by a MOV. The two
231 // instructions are not generated on a higher level since then the
232 // verifier sees a MachineBasicBlock ending with a non-terminator.
233 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
237 //===----------------------------------------------------------------------===//
238 // Alias Instructions
239 //===----------------------------------------------------------------------===//
241 // Alias instruction mapping movr0 to xor.
242 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
243 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
245 def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
246 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
248 // Other widths can also make use of the 32-bit xor, which may have a smaller
249 // encoding and avoid partial register updates.
250 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
251 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
252 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> {
253 let AddedComplexity = 20;
256 // Materialize i64 constant where top 32-bits are zero. This could theoretically
257 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
258 // that would make it more difficult to rematerialize.
259 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
260 isCodeGenOnly = 1, neverHasSideEffects = 1 in
261 def MOV32ri64 : Ii32<0xb8, AddRegFrm, (outs GR32:$dst), (ins i64i32imm:$src),
262 "", [], IIC_ALU_NONMEM>, Sched<[WriteALU]>;
264 // This 64-bit pseudo-move can be used for both a 64-bit constant that is
265 // actually the zero-extension of a 32-bit constant, and for labels in the
266 // x86-64 small code model.
267 def mov64imm32 : ComplexPattern<i64, 1, "SelectMOV64Imm32", [imm, X86Wrapper]>;
269 let AddedComplexity = 1 in
270 def : Pat<(i64 mov64imm32:$src),
271 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>;
273 // Use sbb to materialize carry bit.
274 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in {
275 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
276 // However, Pat<> can't replicate the destination reg into the inputs of the
278 def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "",
279 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
280 def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "",
281 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
282 def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "",
283 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
284 def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "",
285 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
289 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
291 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
293 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
296 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
298 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
300 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
303 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
304 // will be eliminated and that the sbb can be extended up to a wider type. When
305 // this happens, it is great. However, if we are left with an 8-bit sbb and an
306 // and, we might as well just match it as a setb.
307 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
310 // (add OP, SETB) -> (adc OP, 0)
311 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
312 (ADC8ri GR8:$op, 0)>;
313 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
314 (ADC32ri8 GR32:$op, 0)>;
315 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
316 (ADC64ri8 GR64:$op, 0)>;
318 // (sub OP, SETB) -> (sbb OP, 0)
319 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
320 (SBB8ri GR8:$op, 0)>;
321 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
322 (SBB32ri8 GR32:$op, 0)>;
323 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
324 (SBB64ri8 GR64:$op, 0)>;
326 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
327 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
328 (ADC8ri GR8:$op, 0)>;
329 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
330 (ADC32ri8 GR32:$op, 0)>;
331 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
332 (ADC64ri8 GR64:$op, 0)>;
334 //===----------------------------------------------------------------------===//
335 // String Pseudo Instructions
337 let SchedRW = [WriteMicrocoded] in {
338 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
339 def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
340 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
341 Requires<[Not64BitMode]>;
342 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
343 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
344 Requires<[Not64BitMode]>;
345 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
346 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
347 Requires<[Not64BitMode]>;
350 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
351 def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
352 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
353 Requires<[In64BitMode]>;
354 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
355 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
356 Requires<[In64BitMode]>;
357 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
358 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
359 Requires<[In64BitMode]>;
360 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
361 [(X86rep_movs i64)], IIC_REP_MOVS>, REP,
362 Requires<[In64BitMode]>;
365 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
366 let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
367 let Uses = [AL,ECX,EDI] in
368 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
369 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
370 Requires<[Not64BitMode]>;
371 let Uses = [AX,ECX,EDI] in
372 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
373 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
374 Requires<[Not64BitMode]>;
375 let Uses = [EAX,ECX,EDI] in
376 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
377 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
378 Requires<[Not64BitMode]>;
381 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
382 let Uses = [AL,RCX,RDI] in
383 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
384 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
385 Requires<[In64BitMode]>;
386 let Uses = [AX,RCX,RDI] in
387 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
388 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
389 Requires<[In64BitMode]>;
390 let Uses = [RAX,RCX,RDI] in
391 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
392 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
393 Requires<[In64BitMode]>;
395 let Uses = [RAX,RCX,RDI] in
396 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
397 [(X86rep_stos i64)], IIC_REP_STOS>, REP,
398 Requires<[In64BitMode]>;
402 //===----------------------------------------------------------------------===//
403 // Thread Local Storage Instructions
407 // All calls clobber the non-callee saved registers. ESP is marked as
408 // a use to prevent stack-pointer assignments that appear immediately
409 // before calls from potentially appearing dead.
410 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
411 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
412 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
413 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
415 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
417 [(X86tlsaddr tls32addr:$sym)]>,
418 Requires<[Not64BitMode]>;
419 def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
421 [(X86tlsbaseaddr tls32baseaddr:$sym)]>,
422 Requires<[Not64BitMode]>;
425 // All calls clobber the non-callee saved registers. RSP is marked as
426 // a use to prevent stack-pointer assignments that appear immediately
427 // before calls from potentially appearing dead.
428 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
429 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
430 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
431 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
432 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
434 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
436 [(X86tlsaddr tls64addr:$sym)]>,
437 Requires<[In64BitMode]>;
438 def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
440 [(X86tlsbaseaddr tls64baseaddr:$sym)]>,
441 Requires<[In64BitMode]>;
444 // Darwin TLS Support
445 // For i386, the address of the thunk is passed on the stack, on return the
446 // address of the variable is in %eax. %ecx is trashed during the function
447 // call. All other registers are preserved.
448 let Defs = [EAX, ECX, EFLAGS],
450 usesCustomInserter = 1 in
451 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
453 [(X86TLSCall addr:$sym)]>,
454 Requires<[Not64BitMode]>;
456 // For x86_64, the address of the thunk is passed in %rdi, on return
457 // the address of the variable is in %rax. All other registers are preserved.
458 let Defs = [RAX, EFLAGS],
460 usesCustomInserter = 1 in
461 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
463 [(X86TLSCall addr:$sym)]>,
464 Requires<[In64BitMode]>;
467 //===----------------------------------------------------------------------===//
468 // Conditional Move Pseudo Instructions
470 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
471 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
472 // however that requires promoting the operands, and can induce additional
473 // i8 register pressure.
474 let usesCustomInserter = 1, Uses = [EFLAGS] in {
475 def CMOV_GR8 : I<0, Pseudo,
476 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
478 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
479 imm:$cond, EFLAGS))]>;
481 let Predicates = [NoCMov] in {
482 def CMOV_GR32 : I<0, Pseudo,
483 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
484 "#CMOV_GR32* PSEUDO!",
486 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
487 def CMOV_GR16 : I<0, Pseudo,
488 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
489 "#CMOV_GR16* PSEUDO!",
491 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
492 } // Predicates = [NoCMov]
494 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
496 let Predicates = [FPStackf32] in
497 def CMOV_RFP32 : I<0, Pseudo,
499 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
500 "#CMOV_RFP32 PSEUDO!",
502 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
504 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
506 let Predicates = [FPStackf64] in
507 def CMOV_RFP64 : I<0, Pseudo,
509 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
510 "#CMOV_RFP64 PSEUDO!",
512 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
514 def CMOV_RFP80 : I<0, Pseudo,
516 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
517 "#CMOV_RFP80 PSEUDO!",
519 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
521 } // UsesCustomInserter = 1, Uses = [EFLAGS]
524 //===----------------------------------------------------------------------===//
525 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
526 //===----------------------------------------------------------------------===//
528 // FIXME: Use normal instructions and add lock prefix dynamically.
532 // TODO: Get this to fold the constant into the instruction.
533 let isCodeGenOnly = 1, Defs = [EFLAGS] in
534 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
535 "or{l}\t{$zero, $dst|$dst, $zero}",
536 [], IIC_ALU_MEM>, Requires<[Not64BitMode]>, LOCK,
537 Sched<[WriteALULd, WriteRMW]>;
539 let hasSideEffects = 1 in
540 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
542 [(X86MemBarrier)]>, Sched<[WriteLoad]>;
544 // RegOpc corresponds to the mr version of the instruction
545 // ImmOpc corresponds to the mi version of the instruction
546 // ImmOpc8 corresponds to the mi8 version of the instruction
547 // ImmMod corresponds to the instruction format of the mi and mi8 versions
548 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
549 Format ImmMod, string mnemonic> {
550 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
551 SchedRW = [WriteALULd, WriteRMW] in {
553 def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
554 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
555 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
556 !strconcat(mnemonic, "{b}\t",
557 "{$src2, $dst|$dst, $src2}"),
558 [], IIC_ALU_NONMEM>, LOCK;
559 def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
560 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
561 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
562 !strconcat(mnemonic, "{w}\t",
563 "{$src2, $dst|$dst, $src2}"),
564 [], IIC_ALU_NONMEM>, OpSize16, LOCK;
565 def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
566 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
567 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
568 !strconcat(mnemonic, "{l}\t",
569 "{$src2, $dst|$dst, $src2}"),
570 [], IIC_ALU_NONMEM>, OpSize32, LOCK;
571 def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
572 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
573 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
574 !strconcat(mnemonic, "{q}\t",
575 "{$src2, $dst|$dst, $src2}"),
576 [], IIC_ALU_NONMEM>, LOCK;
578 def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
579 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
580 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
581 !strconcat(mnemonic, "{b}\t",
582 "{$src2, $dst|$dst, $src2}"),
583 [], IIC_ALU_MEM>, LOCK;
585 def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
586 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
587 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
588 !strconcat(mnemonic, "{w}\t",
589 "{$src2, $dst|$dst, $src2}"),
590 [], IIC_ALU_MEM>, OpSize16, LOCK;
592 def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
593 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
594 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
595 !strconcat(mnemonic, "{l}\t",
596 "{$src2, $dst|$dst, $src2}"),
597 [], IIC_ALU_MEM>, OpSize32, LOCK;
599 def NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
600 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
601 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
602 !strconcat(mnemonic, "{q}\t",
603 "{$src2, $dst|$dst, $src2}"),
604 [], IIC_ALU_MEM>, LOCK;
606 def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
607 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
608 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
609 !strconcat(mnemonic, "{w}\t",
610 "{$src2, $dst|$dst, $src2}"),
611 [], IIC_ALU_MEM>, OpSize16, LOCK;
612 def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
613 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
614 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
615 !strconcat(mnemonic, "{l}\t",
616 "{$src2, $dst|$dst, $src2}"),
617 [], IIC_ALU_MEM>, OpSize32, LOCK;
618 def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
619 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
620 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
621 !strconcat(mnemonic, "{q}\t",
622 "{$src2, $dst|$dst, $src2}"),
623 [], IIC_ALU_MEM>, LOCK;
629 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
630 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
631 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
632 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
633 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
635 // Optimized codegen when the non-memory output is not used.
636 multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,
638 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
639 SchedRW = [WriteALULd, WriteRMW] in {
641 def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
642 !strconcat(mnemonic, "{b}\t$dst"),
643 [], IIC_UNARY_MEM>, LOCK;
644 def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
645 !strconcat(mnemonic, "{w}\t$dst"),
646 [], IIC_UNARY_MEM>, OpSize16, LOCK;
647 def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
648 !strconcat(mnemonic, "{l}\t$dst"),
649 [], IIC_UNARY_MEM>, OpSize32, LOCK;
650 def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
651 !strconcat(mnemonic, "{q}\t$dst"),
652 [], IIC_UNARY_MEM>, LOCK;
656 defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">;
657 defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">;
659 // Atomic compare and swap.
660 multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,
661 SDPatternOperator frag, X86MemOperand x86memop,
662 InstrItinClass itin> {
663 let isCodeGenOnly = 1 in {
664 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr),
665 !strconcat(mnemonic, "\t$ptr"),
666 [(frag addr:$ptr)], itin>, TB, LOCK;
670 multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
671 string mnemonic, SDPatternOperator frag,
672 InstrItinClass itin8, InstrItinClass itin> {
673 let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
674 let Defs = [AL, EFLAGS], Uses = [AL] in
675 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
676 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"),
677 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK;
678 let Defs = [AX, EFLAGS], Uses = [AX] in
679 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
680 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
681 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK;
682 let Defs = [EAX, EFLAGS], Uses = [EAX] in
683 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
684 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
685 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK;
686 let Defs = [RAX, EFLAGS], Uses = [RAX] in
687 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
688 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
689 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK;
693 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
694 SchedRW = [WriteALULd, WriteRMW] in {
695 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",
700 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
701 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in {
702 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
704 IIC_CMPX_LOCK_16B>, REX_W;
707 defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg",
708 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>;
710 // Atomic exchange and add
711 multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
713 InstrItinClass itin8, InstrItinClass itin> {
714 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1,
715 SchedRW = [WriteALULd, WriteRMW] in {
716 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),
717 (ins GR8:$val, i8mem:$ptr),
718 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
720 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
722 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
723 (ins GR16:$val, i16mem:$ptr),
724 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
727 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
729 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
730 (ins GR32:$val, i32mem:$ptr),
731 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
734 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
736 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
737 (ins GR64:$val, i64mem:$ptr),
738 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
741 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
746 defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",
747 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>,
750 def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
751 "#ACQUIRE_MOV PSEUDO!",
752 [(set GR8:$dst, (atomic_load_8 addr:$src))]>;
753 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
754 "#ACQUIRE_MOV PSEUDO!",
755 [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
756 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
757 "#ACQUIRE_MOV PSEUDO!",
758 [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
759 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
760 "#ACQUIRE_MOV PSEUDO!",
761 [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
763 def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
764 "#RELEASE_MOV PSEUDO!",
765 [(atomic_store_8 addr:$dst, GR8 :$src)]>;
766 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
767 "#RELEASE_MOV PSEUDO!",
768 [(atomic_store_16 addr:$dst, GR16:$src)]>;
769 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
770 "#RELEASE_MOV PSEUDO!",
771 [(atomic_store_32 addr:$dst, GR32:$src)]>;
772 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
773 "#RELEASE_MOV PSEUDO!",
774 [(atomic_store_64 addr:$dst, GR64:$src)]>;
776 //===----------------------------------------------------------------------===//
777 // Conditional Move Pseudo Instructions.
778 //===----------------------------------------------------------------------===//
781 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
782 // instruction selection into a branch sequence.
783 let Uses = [EFLAGS], usesCustomInserter = 1 in {
784 def CMOV_FR32 : I<0, Pseudo,
785 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
786 "#CMOV_FR32 PSEUDO!",
787 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
789 def CMOV_FR64 : I<0, Pseudo,
790 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
791 "#CMOV_FR64 PSEUDO!",
792 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
794 def CMOV_V4F32 : I<0, Pseudo,
795 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
796 "#CMOV_V4F32 PSEUDO!",
798 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
800 def CMOV_V2F64 : I<0, Pseudo,
801 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
802 "#CMOV_V2F64 PSEUDO!",
804 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
806 def CMOV_V2I64 : I<0, Pseudo,
807 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
808 "#CMOV_V2I64 PSEUDO!",
810 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
812 def CMOV_V8F32 : I<0, Pseudo,
813 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
814 "#CMOV_V8F32 PSEUDO!",
816 (v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond,
818 def CMOV_V4F64 : I<0, Pseudo,
819 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
820 "#CMOV_V4F64 PSEUDO!",
822 (v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
824 def CMOV_V4I64 : I<0, Pseudo,
825 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
826 "#CMOV_V4I64 PSEUDO!",
828 (v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
830 def CMOV_V8I64 : I<0, Pseudo,
831 (outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond),
832 "#CMOV_V8I64 PSEUDO!",
834 (v8i64 (X86cmov VR512:$t, VR512:$f, imm:$cond,
836 def CMOV_V8F64 : I<0, Pseudo,
837 (outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond),
838 "#CMOV_V8F64 PSEUDO!",
840 (v8f64 (X86cmov VR512:$t, VR512:$f, imm:$cond,
842 def CMOV_V16F32 : I<0, Pseudo,
843 (outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond),
844 "#CMOV_V16F32 PSEUDO!",
846 (v16f32 (X86cmov VR512:$t, VR512:$f, imm:$cond,
851 //===----------------------------------------------------------------------===//
852 // DAG Pattern Matching Rules
853 //===----------------------------------------------------------------------===//
855 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
856 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
857 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
858 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
859 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
860 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
861 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
863 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
864 (ADD32ri GR32:$src1, tconstpool:$src2)>;
865 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
866 (ADD32ri GR32:$src1, tjumptable:$src2)>;
867 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
868 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
869 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
870 (ADD32ri GR32:$src1, texternalsym:$src2)>;
871 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
872 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
874 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
875 (MOV32mi addr:$dst, tglobaladdr:$src)>;
876 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
877 (MOV32mi addr:$dst, texternalsym:$src)>;
878 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
879 (MOV32mi addr:$dst, tblockaddress:$src)>;
881 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
882 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
883 // 'movabs' predicate should handle this sort of thing.
884 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
885 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
886 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
887 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
888 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
889 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
890 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
891 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
892 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
893 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
895 // In kernel code model, we can get the address of a label
896 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
897 // the MOV64ri32 should accept these.
898 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
899 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
900 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
901 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
902 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
903 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
904 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
905 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
906 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
907 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
909 // If we have small model and -static mode, it is safe to store global addresses
910 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
911 // for MOV64mi32 should handle this sort of thing.
912 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
913 (MOV64mi32 addr:$dst, tconstpool:$src)>,
914 Requires<[NearData, IsStatic]>;
915 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
916 (MOV64mi32 addr:$dst, tjumptable:$src)>,
917 Requires<[NearData, IsStatic]>;
918 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
919 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
920 Requires<[NearData, IsStatic]>;
921 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
922 (MOV64mi32 addr:$dst, texternalsym:$src)>,
923 Requires<[NearData, IsStatic]>;
924 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
925 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
926 Requires<[NearData, IsStatic]>;
930 // tls has some funny stuff here...
931 // This corresponds to movabs $foo@tpoff, %rax
932 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
933 (MOV64ri32 tglobaltlsaddr :$dst)>;
934 // This corresponds to add $foo@tpoff, %rax
935 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
936 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
939 // Direct PC relative function call for small code model. 32-bit displacement
940 // sign extended to 64-bit.
941 def : Pat<(X86call (i64 tglobaladdr:$dst)),
942 (CALL64pcrel32 tglobaladdr:$dst)>;
943 def : Pat<(X86call (i64 texternalsym:$dst)),
944 (CALL64pcrel32 texternalsym:$dst)>;
946 // Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
947 // can never use callee-saved registers. That is the purpose of the GR64_TC
950 // The only volatile register that is never used by the calling convention is
951 // %r11. This happens when calling a vararg function with 6 arguments.
953 // Match an X86tcret that uses less than 7 volatile registers.
954 def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
955 (X86tcret node:$ptr, node:$off), [{
956 // X86tcret args: (*chain, ptr, imm, regs..., glue)
957 unsigned NumRegs = 0;
958 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
959 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
964 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
965 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>,
966 Requires<[Not64BitMode]>;
968 // FIXME: This is disabled for 32-bit PIC mode because the global base
969 // register which is part of the address mode may be assigned a
970 // callee-saved register.
971 def : Pat<(X86tcret (load addr:$dst), imm:$off),
972 (TCRETURNmi addr:$dst, imm:$off)>,
973 Requires<[Not64BitMode, IsNotPIC]>;
975 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
976 (TCRETURNdi texternalsym:$dst, imm:$off)>,
977 Requires<[Not64BitMode]>;
979 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
980 (TCRETURNdi texternalsym:$dst, imm:$off)>,
981 Requires<[Not64BitMode]>;
983 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
984 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
985 Requires<[In64BitMode]>;
987 // Don't fold loads into X86tcret requiring more than 6 regs.
988 // There wouldn't be enough scratch registers for base+index.
989 def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
990 (TCRETURNmi64 addr:$dst, imm:$off)>,
991 Requires<[In64BitMode]>;
993 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
994 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
995 Requires<[In64BitMode]>;
997 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
998 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
999 Requires<[In64BitMode]>;
1001 // Normal calls, with various flavors of addresses.
1002 def : Pat<(X86call (i32 tglobaladdr:$dst)),
1003 (CALLpcrel32 tglobaladdr:$dst)>;
1004 def : Pat<(X86call (i32 texternalsym:$dst)),
1005 (CALLpcrel32 texternalsym:$dst)>;
1006 def : Pat<(X86call (i32 imm:$dst)),
1007 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
1011 // TEST R,R is smaller than CMP R,0
1012 def : Pat<(X86cmp GR8:$src1, 0),
1013 (TEST8rr GR8:$src1, GR8:$src1)>;
1014 def : Pat<(X86cmp GR16:$src1, 0),
1015 (TEST16rr GR16:$src1, GR16:$src1)>;
1016 def : Pat<(X86cmp GR32:$src1, 0),
1017 (TEST32rr GR32:$src1, GR32:$src1)>;
1018 def : Pat<(X86cmp GR64:$src1, 0),
1019 (TEST64rr GR64:$src1, GR64:$src1)>;
1021 // Conditional moves with folded loads with operands swapped and conditions
1023 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
1024 Instruction Inst64> {
1025 let Predicates = [HasCMov] in {
1026 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
1027 (Inst16 GR16:$src2, addr:$src1)>;
1028 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
1029 (Inst32 GR32:$src2, addr:$src1)>;
1030 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
1031 (Inst64 GR64:$src2, addr:$src1)>;
1035 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
1036 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
1037 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
1038 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
1039 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
1040 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
1041 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
1042 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
1043 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
1044 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1045 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1046 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1047 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1048 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1049 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1050 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1052 // zextload bool -> zextload byte
1053 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1054 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1055 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1056 def : Pat<(zextloadi64i1 addr:$src),
1057 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1059 // extload bool -> extload byte
1060 // When extloading from 16-bit and smaller memory locations into 64-bit
1061 // registers, use zero-extending loads so that the entire 64-bit register is
1062 // defined, avoiding partial-register updates.
1064 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1065 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1066 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1067 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1068 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1069 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1071 // For other extloads, use subregs, since the high contents of the register are
1072 // defined after an extload.
1073 def : Pat<(extloadi64i1 addr:$src),
1074 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1075 def : Pat<(extloadi64i8 addr:$src),
1076 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1077 def : Pat<(extloadi64i16 addr:$src),
1078 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1079 def : Pat<(extloadi64i32 addr:$src),
1080 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1082 // anyext. Define these to do an explicit zero-extend to
1083 // avoid partial-register updates.
1084 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1085 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1086 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1088 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1089 def : Pat<(i32 (anyext GR16:$src)),
1090 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1092 def : Pat<(i64 (anyext GR8 :$src)),
1093 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1094 def : Pat<(i64 (anyext GR16:$src)),
1095 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
1096 def : Pat<(i64 (anyext GR32:$src)),
1097 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1100 // Any instruction that defines a 32-bit result leaves the high half of the
1101 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1102 // be copying from a truncate. And x86's cmov doesn't do anything if the
1103 // condition is false. But any other 32-bit operation will zero-extend
1105 def def32 : PatLeaf<(i32 GR32:$src), [{
1106 return N->getOpcode() != ISD::TRUNCATE &&
1107 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1108 N->getOpcode() != ISD::CopyFromReg &&
1109 N->getOpcode() != X86ISD::CMOV;
1112 // In the case of a 32-bit def that is known to implicitly zero-extend,
1113 // we can use a SUBREG_TO_REG.
1114 def : Pat<(i64 (zext def32:$src)),
1115 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1117 //===----------------------------------------------------------------------===//
1118 // Pattern match OR as ADD
1119 //===----------------------------------------------------------------------===//
1121 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1122 // 3-addressified into an LEA instruction to avoid copies. However, we also
1123 // want to finally emit these instructions as an or at the end of the code
1124 // generator to make the generated code easier to read. To do this, we select
1125 // into "disjoint bits" pseudo ops.
1127 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1128 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1129 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1130 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1132 APInt KnownZero0, KnownOne0;
1133 CurDAG->computeKnownBits(N->getOperand(0), KnownZero0, KnownOne0, 0);
1134 APInt KnownZero1, KnownOne1;
1135 CurDAG->computeKnownBits(N->getOperand(1), KnownZero1, KnownOne1, 0);
1136 return (~KnownZero0 & ~KnownZero1) == 0;
1140 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1141 // Try this before the selecting to OR.
1142 let AddedComplexity = 5, SchedRW = [WriteALU] in {
1144 let isConvertibleToThreeAddress = 1,
1145 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1146 let isCommutable = 1 in {
1147 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1148 "", // orw/addw REG, REG
1149 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1150 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1151 "", // orl/addl REG, REG
1152 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1153 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1154 "", // orq/addq REG, REG
1155 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1158 // NOTE: These are order specific, we want the ri8 forms to be listed
1159 // first so that they are slightly preferred to the ri forms.
1161 def ADD16ri8_DB : I<0, Pseudo,
1162 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1163 "", // orw/addw REG, imm8
1164 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1165 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1166 "", // orw/addw REG, imm
1167 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1169 def ADD32ri8_DB : I<0, Pseudo,
1170 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1171 "", // orl/addl REG, imm8
1172 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1173 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1174 "", // orl/addl REG, imm
1175 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1178 def ADD64ri8_DB : I<0, Pseudo,
1179 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1180 "", // orq/addq REG, imm8
1181 [(set GR64:$dst, (or_is_add GR64:$src1,
1182 i64immSExt8:$src2))]>;
1183 def ADD64ri32_DB : I<0, Pseudo,
1184 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1185 "", // orq/addq REG, imm
1186 [(set GR64:$dst, (or_is_add GR64:$src1,
1187 i64immSExt32:$src2))]>;
1189 } // AddedComplexity, SchedRW
1192 //===----------------------------------------------------------------------===//
1194 //===----------------------------------------------------------------------===//
1196 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1197 // +128 doesn't, so in this special case use a sub instead of an add.
1198 def : Pat<(add GR16:$src1, 128),
1199 (SUB16ri8 GR16:$src1, -128)>;
1200 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1201 (SUB16mi8 addr:$dst, -128)>;
1203 def : Pat<(add GR32:$src1, 128),
1204 (SUB32ri8 GR32:$src1, -128)>;
1205 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1206 (SUB32mi8 addr:$dst, -128)>;
1208 def : Pat<(add GR64:$src1, 128),
1209 (SUB64ri8 GR64:$src1, -128)>;
1210 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1211 (SUB64mi8 addr:$dst, -128)>;
1213 // The same trick applies for 32-bit immediate fields in 64-bit
1215 def : Pat<(add GR64:$src1, 0x0000000080000000),
1216 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1217 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1218 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1220 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1221 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1222 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1223 // represented with a sign extension of a 8 bit constant, use that.
1225 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1229 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1230 (i32 (GetLo8XForm imm:$imm))),
1233 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1237 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1238 (i32 (GetLo32XForm imm:$imm))),
1242 // r & (2^16-1) ==> movz
1243 def : Pat<(and GR32:$src1, 0xffff),
1244 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1245 // r & (2^8-1) ==> movz
1246 def : Pat<(and GR32:$src1, 0xff),
1247 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1250 Requires<[Not64BitMode]>;
1251 // r & (2^8-1) ==> movz
1252 def : Pat<(and GR16:$src1, 0xff),
1253 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1254 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1256 Requires<[Not64BitMode]>;
1258 // r & (2^32-1) ==> movz
1259 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1260 (SUBREG_TO_REG (i64 0),
1261 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)),
1263 // r & (2^16-1) ==> movz
1264 def : Pat<(and GR64:$src, 0xffff),
1265 (SUBREG_TO_REG (i64 0),
1266 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))),
1268 // r & (2^8-1) ==> movz
1269 def : Pat<(and GR64:$src, 0xff),
1270 (SUBREG_TO_REG (i64 0),
1271 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))),
1273 // r & (2^8-1) ==> movz
1274 def : Pat<(and GR32:$src1, 0xff),
1275 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1276 Requires<[In64BitMode]>;
1277 // r & (2^8-1) ==> movz
1278 def : Pat<(and GR16:$src1, 0xff),
1279 (EXTRACT_SUBREG (MOVZX32rr8 (i8
1280 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
1281 Requires<[In64BitMode]>;
1284 // sext_inreg patterns
1285 def : Pat<(sext_inreg GR32:$src, i16),
1286 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1287 def : Pat<(sext_inreg GR32:$src, i8),
1288 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1291 Requires<[Not64BitMode]>;
1293 def : Pat<(sext_inreg GR16:$src, i8),
1294 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
1295 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1297 Requires<[Not64BitMode]>;
1299 def : Pat<(sext_inreg GR64:$src, i32),
1300 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1301 def : Pat<(sext_inreg GR64:$src, i16),
1302 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1303 def : Pat<(sext_inreg GR64:$src, i8),
1304 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1305 def : Pat<(sext_inreg GR32:$src, i8),
1306 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1307 Requires<[In64BitMode]>;
1308 def : Pat<(sext_inreg GR16:$src, i8),
1309 (EXTRACT_SUBREG (MOVSX32rr8
1310 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
1311 Requires<[In64BitMode]>;
1313 // sext, sext_load, zext, zext_load
1314 def: Pat<(i16 (sext GR8:$src)),
1315 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1316 def: Pat<(sextloadi16i8 addr:$src),
1317 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1318 def: Pat<(i16 (zext GR8:$src)),
1319 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1320 def: Pat<(zextloadi16i8 addr:$src),
1321 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1324 def : Pat<(i16 (trunc GR32:$src)),
1325 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1326 def : Pat<(i8 (trunc GR32:$src)),
1327 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1329 Requires<[Not64BitMode]>;
1330 def : Pat<(i8 (trunc GR16:$src)),
1331 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1333 Requires<[Not64BitMode]>;
1334 def : Pat<(i32 (trunc GR64:$src)),
1335 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1336 def : Pat<(i16 (trunc GR64:$src)),
1337 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1338 def : Pat<(i8 (trunc GR64:$src)),
1339 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1340 def : Pat<(i8 (trunc GR32:$src)),
1341 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1342 Requires<[In64BitMode]>;
1343 def : Pat<(i8 (trunc GR16:$src)),
1344 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1345 Requires<[In64BitMode]>;
1347 // h-register tricks
1348 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1349 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1351 Requires<[Not64BitMode]>;
1352 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1353 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1355 Requires<[Not64BitMode]>;
1356 def : Pat<(srl GR16:$src, (i8 8)),
1359 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1362 Requires<[Not64BitMode]>;
1363 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1364 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1367 Requires<[Not64BitMode]>;
1368 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1369 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1372 Requires<[Not64BitMode]>;
1373 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1374 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1377 Requires<[Not64BitMode]>;
1378 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1379 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1382 Requires<[Not64BitMode]>;
1384 // h-register tricks.
1385 // For now, be conservative on x86-64 and use an h-register extract only if the
1386 // value is immediately zero-extended or stored, which are somewhat common
1387 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1388 // from being allocated in the same instruction as the h register, as there's
1389 // currently no way to describe this requirement to the register allocator.
1391 // h-register extract and zero-extend.
1392 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1396 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1399 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1401 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1403 Requires<[In64BitMode]>;
1404 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1405 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1408 Requires<[In64BitMode]>;
1409 def : Pat<(srl GR16:$src, (i8 8)),
1412 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1415 Requires<[In64BitMode]>;
1416 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1418 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1420 Requires<[In64BitMode]>;
1421 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1423 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1425 Requires<[In64BitMode]>;
1426 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1430 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1433 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1437 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1441 // h-register extract and store.
1442 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1445 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1447 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1450 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1452 Requires<[In64BitMode]>;
1453 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1456 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1458 Requires<[In64BitMode]>;
1461 // (shl x, 1) ==> (add x, x)
1462 // Note that if x is undef (immediate or otherwise), we could theoretically
1463 // end up with the two uses of x getting different values, producing a result
1464 // where the least significant bit is not 0. However, the probability of this
1465 // happening is considered low enough that this is officially not a
1467 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1468 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1469 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1470 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1472 // Helper imms that check if a mask doesn't change significant shift bits.
1473 def immShift32 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 5; }]>;
1474 def immShift64 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 6; }]>;
1476 // Shift amount is implicitly masked.
1477 multiclass MaskedShiftAmountPats<SDNode frag, string name> {
1478 // (shift x (and y, 31)) ==> (shift x, y)
1479 def : Pat<(frag GR8:$src1, (and CL, immShift32)),
1480 (!cast<Instruction>(name # "8rCL") GR8:$src1)>;
1481 def : Pat<(frag GR16:$src1, (and CL, immShift32)),
1482 (!cast<Instruction>(name # "16rCL") GR16:$src1)>;
1483 def : Pat<(frag GR32:$src1, (and CL, immShift32)),
1484 (!cast<Instruction>(name # "32rCL") GR32:$src1)>;
1485 def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1486 (!cast<Instruction>(name # "8mCL") addr:$dst)>;
1487 def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1488 (!cast<Instruction>(name # "16mCL") addr:$dst)>;
1489 def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1490 (!cast<Instruction>(name # "32mCL") addr:$dst)>;
1492 // (shift x (and y, 63)) ==> (shift x, y)
1493 def : Pat<(frag GR64:$src1, (and CL, immShift64)),
1494 (!cast<Instruction>(name # "64rCL") GR64:$src1)>;
1495 def : Pat<(store (frag (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1496 (!cast<Instruction>(name # "64mCL") addr:$dst)>;
1499 defm : MaskedShiftAmountPats<shl, "SHL">;
1500 defm : MaskedShiftAmountPats<srl, "SHR">;
1501 defm : MaskedShiftAmountPats<sra, "SAR">;
1502 defm : MaskedShiftAmountPats<rotl, "ROL">;
1503 defm : MaskedShiftAmountPats<rotr, "ROR">;
1505 // (anyext (setcc_carry)) -> (setcc_carry)
1506 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1508 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1510 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1516 //===----------------------------------------------------------------------===//
1517 // EFLAGS-defining Patterns
1518 //===----------------------------------------------------------------------===//
1521 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1522 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1523 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1526 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1527 (ADD8rm GR8:$src1, addr:$src2)>;
1528 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1529 (ADD16rm GR16:$src1, addr:$src2)>;
1530 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1531 (ADD32rm GR32:$src1, addr:$src2)>;
1534 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1535 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1536 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1537 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1538 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1539 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1540 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1543 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1544 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1545 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1548 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1549 (SUB8rm GR8:$src1, addr:$src2)>;
1550 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1551 (SUB16rm GR16:$src1, addr:$src2)>;
1552 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1553 (SUB32rm GR32:$src1, addr:$src2)>;
1556 def : Pat<(sub GR8:$src1, imm:$src2),
1557 (SUB8ri GR8:$src1, imm:$src2)>;
1558 def : Pat<(sub GR16:$src1, imm:$src2),
1559 (SUB16ri GR16:$src1, imm:$src2)>;
1560 def : Pat<(sub GR32:$src1, imm:$src2),
1561 (SUB32ri GR32:$src1, imm:$src2)>;
1562 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1563 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1564 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1565 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1568 def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>;
1569 def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>;
1570 def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
1571 def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>;
1574 def : Pat<(mul GR16:$src1, GR16:$src2),
1575 (IMUL16rr GR16:$src1, GR16:$src2)>;
1576 def : Pat<(mul GR32:$src1, GR32:$src2),
1577 (IMUL32rr GR32:$src1, GR32:$src2)>;
1580 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1581 (IMUL16rm GR16:$src1, addr:$src2)>;
1582 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1583 (IMUL32rm GR32:$src1, addr:$src2)>;
1586 def : Pat<(mul GR16:$src1, imm:$src2),
1587 (IMUL16rri GR16:$src1, imm:$src2)>;
1588 def : Pat<(mul GR32:$src1, imm:$src2),
1589 (IMUL32rri GR32:$src1, imm:$src2)>;
1590 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1591 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1592 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1593 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1595 // reg = mul mem, imm
1596 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1597 (IMUL16rmi addr:$src1, imm:$src2)>;
1598 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1599 (IMUL32rmi addr:$src1, imm:$src2)>;
1600 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1601 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1602 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1603 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1605 // Patterns for nodes that do not produce flags, for instructions that do.
1608 def : Pat<(add GR64:$src1, GR64:$src2),
1609 (ADD64rr GR64:$src1, GR64:$src2)>;
1610 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1611 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1612 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1613 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1614 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1615 (ADD64rm GR64:$src1, addr:$src2)>;
1618 def : Pat<(sub GR64:$src1, GR64:$src2),
1619 (SUB64rr GR64:$src1, GR64:$src2)>;
1620 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1621 (SUB64rm GR64:$src1, addr:$src2)>;
1622 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1623 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1624 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1625 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1628 def : Pat<(mul GR64:$src1, GR64:$src2),
1629 (IMUL64rr GR64:$src1, GR64:$src2)>;
1630 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1631 (IMUL64rm GR64:$src1, addr:$src2)>;
1632 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1633 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1634 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1635 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1636 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1637 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1638 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1639 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1642 // Do not make INC if it is slow
1643 def : Pat<(add GR8:$src, 1),
1644 (INC8r GR8:$src)>, Requires<[NotSlowIncDec]>;
1645 def : Pat<(add GR16:$src, 1),
1646 (INC16r GR16:$src)>, Requires<[NotSlowIncDec, Not64BitMode]>;
1647 def : Pat<(add GR16:$src, 1),
1648 (INC64_16r GR16:$src)>, Requires<[NotSlowIncDec, In64BitMode]>;
1649 def : Pat<(add GR32:$src, 1),
1650 (INC32r GR32:$src)>, Requires<[NotSlowIncDec, Not64BitMode]>;
1651 def : Pat<(add GR32:$src, 1),
1652 (INC64_32r GR32:$src)>, Requires<[NotSlowIncDec, In64BitMode]>;
1653 def : Pat<(add GR64:$src, 1),
1654 (INC64r GR64:$src)>, Requires<[NotSlowIncDec]>;
1657 // Do not make DEC if it is slow
1658 def : Pat<(add GR8:$src, -1),
1659 (DEC8r GR8:$src)>, Requires<[NotSlowIncDec]>;
1660 def : Pat<(add GR16:$src, -1),
1661 (DEC16r GR16:$src)>, Requires<[NotSlowIncDec, Not64BitMode]>;
1662 def : Pat<(add GR16:$src, -1),
1663 (DEC64_16r GR16:$src)>, Requires<[NotSlowIncDec, In64BitMode]>;
1664 def : Pat<(add GR32:$src, -1),
1665 (DEC32r GR32:$src)>, Requires<[NotSlowIncDec, Not64BitMode]>;
1666 def : Pat<(add GR32:$src, -1),
1667 (DEC64_32r GR32:$src)>, Requires<[NotSlowIncDec, In64BitMode]>;
1668 def : Pat<(add GR64:$src, -1),
1669 (DEC64r GR64:$src)>, Requires<[NotSlowIncDec]>;
1672 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1673 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1674 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1675 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1678 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1679 (OR8rm GR8:$src1, addr:$src2)>;
1680 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1681 (OR16rm GR16:$src1, addr:$src2)>;
1682 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1683 (OR32rm GR32:$src1, addr:$src2)>;
1684 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1685 (OR64rm GR64:$src1, addr:$src2)>;
1688 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1689 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1690 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1691 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1692 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1693 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1694 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1695 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1696 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1697 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1698 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1701 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1702 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1703 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1704 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1707 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1708 (XOR8rm GR8:$src1, addr:$src2)>;
1709 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1710 (XOR16rm GR16:$src1, addr:$src2)>;
1711 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1712 (XOR32rm GR32:$src1, addr:$src2)>;
1713 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1714 (XOR64rm GR64:$src1, addr:$src2)>;
1717 def : Pat<(xor GR8:$src1, imm:$src2),
1718 (XOR8ri GR8:$src1, imm:$src2)>;
1719 def : Pat<(xor GR16:$src1, imm:$src2),
1720 (XOR16ri GR16:$src1, imm:$src2)>;
1721 def : Pat<(xor GR32:$src1, imm:$src2),
1722 (XOR32ri GR32:$src1, imm:$src2)>;
1723 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1724 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1725 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1726 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1727 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1728 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1729 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1730 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1733 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1734 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1735 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1736 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1739 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1740 (AND8rm GR8:$src1, addr:$src2)>;
1741 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1742 (AND16rm GR16:$src1, addr:$src2)>;
1743 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1744 (AND32rm GR32:$src1, addr:$src2)>;
1745 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1746 (AND64rm GR64:$src1, addr:$src2)>;
1749 def : Pat<(and GR8:$src1, imm:$src2),
1750 (AND8ri GR8:$src1, imm:$src2)>;
1751 def : Pat<(and GR16:$src1, imm:$src2),
1752 (AND16ri GR16:$src1, imm:$src2)>;
1753 def : Pat<(and GR32:$src1, imm:$src2),
1754 (AND32ri GR32:$src1, imm:$src2)>;
1755 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1756 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1757 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1758 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1759 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1760 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1761 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1762 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
1764 // Bit scan instruction patterns to match explicit zero-undef behavior.
1765 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
1766 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
1767 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
1768 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
1769 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
1770 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;
1772 // When HasMOVBE is enabled it is possible to get a non-legalized
1773 // register-register 16 bit bswap. This maps it to a ROL instruction.
1774 let Predicates = [HasMOVBE] in {
1775 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>;