1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue());
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue());
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
48 [(X86callseq_start timm:$amt)]>,
49 Requires<[In32BitMode]>;
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
53 Requires<[In32BitMode]>;
56 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
57 // a stack adjustment and the codegen must know that they may modify the stack
58 // pointer before prolog-epilog rewriting occurs.
59 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
60 // sub / add which can clobber EFLAGS.
61 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
62 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
64 [(X86callseq_start timm:$amt)]>,
65 Requires<[In64BitMode]>;
66 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
68 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
69 Requires<[In64BitMode]>;
74 // x86-64 va_start lowering magic.
75 let usesCustomInserter = 1 in {
76 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
79 i64imm:$regsavefi, i64imm:$offset,
81 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
82 [(X86vastart_save_xmm_regs GR8:$al,
86 // The VAARG_64 pseudo-instruction takes the address of the va_list,
87 // and places the address of the next argument into a register.
88 let Defs = [EFLAGS] in
89 def VAARG_64 : I<0, Pseudo,
91 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
92 "#VAARG_64 $dst, $ap, $size, $mode, $align",
94 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
97 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
98 // targets. These calls are needed to probe the stack when allocating more than
99 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
100 // ensure that the guard pages used by the OS virtual memory manager are
101 // allocated in correct sequence.
102 // The main point of having separate instruction are extra unmodelled effects
103 // (compared to ordinary calls) like stack pointer change.
105 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
106 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
107 "# dynamic stack allocation",
110 // When using segmented stacks these are lowered into instructions which first
111 // check if the current stacklet has enough free memory. If it does, memory is
112 // allocated by bumping the stack pointer. Otherwise memory is allocated from
115 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
116 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
117 "# variable sized alloca for segmented stacks",
119 (X86SegAlloca GR32:$size))]>,
120 Requires<[In32BitMode]>;
122 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
123 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
124 "# variable sized alloca for segmented stacks",
126 (X86SegAlloca GR64:$size))]>,
127 Requires<[In64BitMode]>;
130 // The MSVC runtime contains an _ftol2 routine for converting floating-point
131 // to integer values. It has a strange calling convention: the input is
132 // popped from the x87 stack, and the return value is given in EDX:EAX. No
133 // other registers (aside from flags) are touched.
134 // Microsoft toolchains do not support 80-bit precision, so a WIN_FTOL_80
135 // variant is unnecessary.
137 let Defs = [EAX, EDX, EFLAGS], FPForm = SpecialFP in {
138 def WIN_FTOL_32 : I<0, Pseudo, (outs), (ins RFP32:$src),
140 [(X86WinFTOL RFP32:$src)]>,
141 Requires<[In32BitMode]>;
143 def WIN_FTOL_64 : I<0, Pseudo, (outs), (ins RFP64:$src),
145 [(X86WinFTOL RFP64:$src)]>,
146 Requires<[In32BitMode]>;
149 //===----------------------------------------------------------------------===//
150 // EH Pseudo Instructions
152 let isTerminator = 1, isReturn = 1, isBarrier = 1,
153 hasCtrlDep = 1, isCodeGenOnly = 1 in {
154 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
155 "ret\t#eh_return, addr: $addr",
156 [(X86ehret GR32:$addr)], IIC_RET>;
160 let isTerminator = 1, isReturn = 1, isBarrier = 1,
161 hasCtrlDep = 1, isCodeGenOnly = 1 in {
162 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
163 "ret\t#eh_return, addr: $addr",
164 [(X86ehret GR64:$addr)], IIC_RET>;
168 //===----------------------------------------------------------------------===//
169 // Pseudo instructions used by segmented stacks.
172 // This is lowered into a RET instruction by MCInstLower. We need
173 // this so that we don't have to have a MachineBasicBlock which ends
174 // with a RET and also has successors.
175 let isPseudo = 1 in {
176 def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
179 // This instruction is lowered to a RET followed by a MOV. The two
180 // instructions are not generated on a higher level since then the
181 // verifier sees a MachineBasicBlock ending with a non-terminator.
182 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
186 //===----------------------------------------------------------------------===//
187 // Alias Instructions
188 //===----------------------------------------------------------------------===//
190 // Alias instructions that map movr0 to xor.
191 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
192 // FIXME: Set encoding to pseudo.
193 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
194 isCodeGenOnly = 1 in {
195 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
196 [(set GR8:$dst, 0)], IIC_ALU_NONMEM>;
198 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
199 // encoding and avoids a partial-register update sometimes, but doing so
200 // at isel time interferes with rematerialization in the current register
201 // allocator. For now, this is rewritten when the instruction is lowered
203 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
205 [(set GR16:$dst, 0)], IIC_ALU_NONMEM>, OpSize;
207 // FIXME: Set encoding to pseudo.
208 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
209 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>;
212 // We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
213 // smaller encoding, but doing so at isel time interferes with rematerialization
214 // in the current register allocator. For now, this is rewritten when the
215 // instruction is lowered to an MCInst.
216 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
217 // when we have a better way to specify isel priority.
218 let Defs = [EFLAGS], isCodeGenOnly=1,
219 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
220 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
221 [(set GR64:$dst, 0)], IIC_ALU_NONMEM>;
223 // Materialize i64 constant where top 32-bits are zero. This could theoretically
224 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
225 // that would make it more difficult to rematerialize.
226 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
228 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
229 "", [(set GR64:$dst, i64immZExt32:$src)],
232 // Use sbb to materialize carry bit.
233 let Uses = [EFLAGS], Defs = [EFLAGS], isCodeGenOnly = 1 in {
234 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
235 // However, Pat<> can't replicate the destination reg into the inputs of the
237 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
239 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
240 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))],
242 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
243 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))],
246 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
247 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))],
249 def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
250 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))],
255 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
257 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
259 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
262 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
264 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
266 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
269 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
270 // will be eliminated and that the sbb can be extended up to a wider type. When
271 // this happens, it is great. However, if we are left with an 8-bit sbb and an
272 // and, we might as well just match it as a setb.
273 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
276 // (add OP, SETB) -> (adc OP, 0)
277 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
278 (ADC8ri GR8:$op, 0)>;
279 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
280 (ADC32ri8 GR32:$op, 0)>;
281 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
282 (ADC64ri8 GR64:$op, 0)>;
284 // (sub OP, SETB) -> (sbb OP, 0)
285 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
286 (SBB8ri GR8:$op, 0)>;
287 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
288 (SBB32ri8 GR32:$op, 0)>;
289 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
290 (SBB64ri8 GR64:$op, 0)>;
292 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
293 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
294 (ADC8ri GR8:$op, 0)>;
295 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
296 (ADC32ri8 GR32:$op, 0)>;
297 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
298 (ADC64ri8 GR64:$op, 0)>;
300 //===----------------------------------------------------------------------===//
301 // String Pseudo Instructions
303 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
304 def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
305 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
306 Requires<[In32BitMode]>;
307 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
308 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
309 Requires<[In32BitMode]>;
310 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
311 [(X86rep_movs i32)], IIC_REP_MOVS>, REP,
312 Requires<[In32BitMode]>;
315 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
316 def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
317 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
318 Requires<[In64BitMode]>;
319 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
320 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
321 Requires<[In64BitMode]>;
322 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
323 [(X86rep_movs i32)], IIC_REP_MOVS>, REP,
324 Requires<[In64BitMode]>;
325 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
326 [(X86rep_movs i64)], IIC_REP_MOVS>, REP,
327 Requires<[In64BitMode]>;
330 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
331 let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
332 let Uses = [AL,ECX,EDI] in
333 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
334 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
335 Requires<[In32BitMode]>;
336 let Uses = [AX,ECX,EDI] in
337 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
338 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize,
339 Requires<[In32BitMode]>;
340 let Uses = [EAX,ECX,EDI] in
341 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
342 [(X86rep_stos i32)], IIC_REP_STOS>, REP,
343 Requires<[In32BitMode]>;
346 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
347 let Uses = [AL,RCX,RDI] in
348 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
349 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
350 Requires<[In64BitMode]>;
351 let Uses = [AX,RCX,RDI] in
352 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
353 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize,
354 Requires<[In64BitMode]>;
355 let Uses = [RAX,RCX,RDI] in
356 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
357 [(X86rep_stos i32)], IIC_REP_STOS>, REP,
358 Requires<[In64BitMode]>;
360 let Uses = [RAX,RCX,RDI] in
361 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
362 [(X86rep_stos i64)], IIC_REP_STOS>, REP,
363 Requires<[In64BitMode]>;
366 //===----------------------------------------------------------------------===//
367 // Thread Local Storage Instructions
371 // All calls clobber the non-callee saved registers. ESP is marked as
372 // a use to prevent stack-pointer assignments that appear immediately
373 // before calls from potentially appearing dead.
374 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
375 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
376 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
377 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
379 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
381 [(X86tlsaddr tls32addr:$sym)]>,
382 Requires<[In32BitMode]>;
383 def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
385 [(X86tlsbaseaddr tls32baseaddr:$sym)]>,
386 Requires<[In32BitMode]>;
389 // All calls clobber the non-callee saved registers. RSP is marked as
390 // a use to prevent stack-pointer assignments that appear immediately
391 // before calls from potentially appearing dead.
392 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
393 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
394 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
395 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
396 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
398 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
400 [(X86tlsaddr tls64addr:$sym)]>,
401 Requires<[In64BitMode]>;
402 def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
404 [(X86tlsbaseaddr tls64baseaddr:$sym)]>,
405 Requires<[In64BitMode]>;
408 // Darwin TLS Support
409 // For i386, the address of the thunk is passed on the stack, on return the
410 // address of the variable is in %eax. %ecx is trashed during the function
411 // call. All other registers are preserved.
412 let Defs = [EAX, ECX, EFLAGS],
414 usesCustomInserter = 1 in
415 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
417 [(X86TLSCall addr:$sym)]>,
418 Requires<[In32BitMode]>;
420 // For x86_64, the address of the thunk is passed in %rdi, on return
421 // the address of the variable is in %rax. All other registers are preserved.
422 let Defs = [RAX, EFLAGS],
424 usesCustomInserter = 1 in
425 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
427 [(X86TLSCall addr:$sym)]>,
428 Requires<[In64BitMode]>;
431 //===----------------------------------------------------------------------===//
432 // Conditional Move Pseudo Instructions
434 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
435 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
436 // however that requires promoting the operands, and can induce additional
437 // i8 register pressure.
438 let usesCustomInserter = 1, Uses = [EFLAGS] in {
439 def CMOV_GR8 : I<0, Pseudo,
440 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
442 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
443 imm:$cond, EFLAGS))]>;
445 let Predicates = [NoCMov] in {
446 def CMOV_GR32 : I<0, Pseudo,
447 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
448 "#CMOV_GR32* PSEUDO!",
450 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
451 def CMOV_GR16 : I<0, Pseudo,
452 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
453 "#CMOV_GR16* PSEUDO!",
455 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
456 def CMOV_RFP32 : I<0, Pseudo,
458 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
459 "#CMOV_RFP32 PSEUDO!",
461 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
463 def CMOV_RFP64 : I<0, Pseudo,
465 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
466 "#CMOV_RFP64 PSEUDO!",
468 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
470 def CMOV_RFP80 : I<0, Pseudo,
472 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
473 "#CMOV_RFP80 PSEUDO!",
475 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
477 } // Predicates = [NoCMov]
478 } // UsesCustomInserter = 1, Uses = [EFLAGS]
481 //===----------------------------------------------------------------------===//
482 // Atomic Instruction Pseudo Instructions
483 //===----------------------------------------------------------------------===//
485 // Pseudo atomic instructions
487 multiclass PSEUDO_ATOMIC_LOAD_BINOP<string mnemonic> {
488 let usesCustomInserter = 1, mayLoad = 1, mayStore = 1 in {
489 def #NAME#8 : I<0, Pseudo, (outs GR8:$dst),
490 (ins i8mem:$ptr, GR8:$val),
491 !strconcat(mnemonic, "8 PSEUDO!"), []>;
492 def #NAME#16 : I<0, Pseudo,(outs GR16:$dst),
493 (ins i16mem:$ptr, GR16:$val),
494 !strconcat(mnemonic, "16 PSEUDO!"), []>;
495 def #NAME#32 : I<0, Pseudo, (outs GR32:$dst),
496 (ins i32mem:$ptr, GR32:$val),
497 !strconcat(mnemonic, "32 PSEUDO!"), []>;
498 def #NAME#64 : I<0, Pseudo, (outs GR64:$dst),
499 (ins i64mem:$ptr, GR64:$val),
500 !strconcat(mnemonic, "64 PSEUDO!"), []>;
504 multiclass PSEUDO_ATOMIC_LOAD_BINOP_PATS<string name, string frag> {
505 def : Pat<(!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val),
506 (!cast<Instruction>(name # "8") addr:$ptr, GR8:$val)>;
507 def : Pat<(!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val),
508 (!cast<Instruction>(name # "16") addr:$ptr, GR16:$val)>;
509 def : Pat<(!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val),
510 (!cast<Instruction>(name # "32") addr:$ptr, GR32:$val)>;
511 def : Pat<(!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val),
512 (!cast<Instruction>(name # "64") addr:$ptr, GR64:$val)>;
515 // Atomic exchange, and, or, xor
516 defm ATOMAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMAND">;
517 defm ATOMOR : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMOR">;
518 defm ATOMXOR : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMXOR">;
519 defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMNAND">;
520 defm ATOMMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMAX">;
521 defm ATOMMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMMIN">;
522 defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMAX">;
523 defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP<"#ATOMUMIN">;
525 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMAND", "atomic_load_and">;
526 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMOR", "atomic_load_or">;
527 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMXOR", "atomic_load_xor">;
528 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMNAND", "atomic_load_nand">;
529 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMAX", "atomic_load_max">;
530 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMMIN", "atomic_load_min">;
531 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMAX", "atomic_load_umax">;
532 defm : PSEUDO_ATOMIC_LOAD_BINOP_PATS<"ATOMUMIN", "atomic_load_umin">;
534 multiclass PSEUDO_ATOMIC_LOAD_BINOP6432<string mnemonic> {
535 let usesCustomInserter = 1, mayLoad = 1, mayStore = 1 in
536 def #NAME#6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
537 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
538 !strconcat(mnemonic, "6432 PSEUDO!"), []>;
541 defm ATOMAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMAND">;
542 defm ATOMOR : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMOR">;
543 defm ATOMXOR : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMXOR">;
544 defm ATOMNAND : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMNAND">;
545 defm ATOMADD : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMADD">;
546 defm ATOMSUB : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMSUB">;
547 defm ATOMMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMMAX">;
548 defm ATOMMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMMIN">;
549 defm ATOMUMAX : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMUMAX">;
550 defm ATOMUMIN : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMUMIN">;
551 defm ATOMSWAP : PSEUDO_ATOMIC_LOAD_BINOP6432<"ATOMSWAP">;
553 //===----------------------------------------------------------------------===//
554 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
555 //===----------------------------------------------------------------------===//
557 // FIXME: Use normal instructions and add lock prefix dynamically.
561 // TODO: Get this to fold the constant into the instruction.
562 let isCodeGenOnly = 1, Defs = [EFLAGS] in
563 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
565 "or{l}\t{$zero, $dst|$dst, $zero}",
566 [], IIC_ALU_MEM>, Requires<[In32BitMode]>, LOCK;
568 let hasSideEffects = 1 in
569 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
573 // RegOpc corresponds to the mr version of the instruction
574 // ImmOpc corresponds to the mi version of the instruction
575 // ImmOpc8 corresponds to the mi8 version of the instruction
576 // ImmMod corresponds to the instruction format of the mi and mi8 versions
577 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
578 Format ImmMod, string mnemonic> {
579 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {
581 def #NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
582 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
583 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
584 !strconcat("lock\n\t", mnemonic, "{b}\t",
585 "{$src2, $dst|$dst, $src2}"),
586 [], IIC_ALU_NONMEM>, LOCK;
587 def #NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
588 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
589 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
590 !strconcat("lock\n\t", mnemonic, "{w}\t",
591 "{$src2, $dst|$dst, $src2}"),
592 [], IIC_ALU_NONMEM>, OpSize, LOCK;
593 def #NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
594 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
595 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
596 !strconcat("lock\n\t", mnemonic, "{l}\t",
597 "{$src2, $dst|$dst, $src2}"),
598 [], IIC_ALU_NONMEM>, LOCK;
599 def #NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
600 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
601 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
602 !strconcat("lock\n\t", mnemonic, "{q}\t",
603 "{$src2, $dst|$dst, $src2}"),
604 [], IIC_ALU_NONMEM>, LOCK;
606 def #NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
607 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
608 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
609 !strconcat("lock\n\t", mnemonic, "{b}\t",
610 "{$src2, $dst|$dst, $src2}"),
611 [], IIC_ALU_MEM>, LOCK;
613 def #NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
614 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
615 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
616 !strconcat("lock\n\t", mnemonic, "{w}\t",
617 "{$src2, $dst|$dst, $src2}"),
618 [], IIC_ALU_MEM>, LOCK;
620 def #NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
621 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
622 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
623 !strconcat("lock\n\t", mnemonic, "{l}\t",
624 "{$src2, $dst|$dst, $src2}"),
625 [], IIC_ALU_MEM>, LOCK;
627 def #NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
628 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
629 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
630 !strconcat("lock\n\t", mnemonic, "{q}\t",
631 "{$src2, $dst|$dst, $src2}"),
632 [], IIC_ALU_MEM>, LOCK;
634 def #NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
635 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
636 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
637 !strconcat("lock\n\t", mnemonic, "{w}\t",
638 "{$src2, $dst|$dst, $src2}"),
639 [], IIC_ALU_MEM>, LOCK;
640 def #NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
641 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
642 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
643 !strconcat("lock\n\t", mnemonic, "{l}\t",
644 "{$src2, $dst|$dst, $src2}"),
645 [], IIC_ALU_MEM>, LOCK;
646 def #NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
647 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
648 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
649 !strconcat("lock\n\t", mnemonic, "{q}\t",
650 "{$src2, $dst|$dst, $src2}"),
651 [], IIC_ALU_MEM>, LOCK;
657 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
658 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
659 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
660 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
661 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
663 // Optimized codegen when the non-memory output is not used.
664 multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,
666 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in {
668 def #NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
669 !strconcat("lock\n\t", mnemonic, "{b}\t$dst"),
670 [], IIC_UNARY_MEM>, LOCK;
671 def #NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
672 !strconcat("lock\n\t", mnemonic, "{w}\t$dst"),
673 [], IIC_UNARY_MEM>, OpSize, LOCK;
674 def #NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
675 !strconcat("lock\n\t", mnemonic, "{l}\t$dst"),
676 [], IIC_UNARY_MEM>, LOCK;
677 def #NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
678 !strconcat("lock\n\t", mnemonic, "{q}\t$dst"),
679 [], IIC_UNARY_MEM>, LOCK;
683 defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">;
684 defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">;
686 // Atomic compare and swap.
687 multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,
688 SDPatternOperator frag, X86MemOperand x86memop,
689 InstrItinClass itin> {
690 let isCodeGenOnly = 1 in {
691 def #NAME# : I<Opc, Form, (outs), (ins x86memop:$ptr),
692 !strconcat("lock\n\t", mnemonic, "\t$ptr"),
693 [(frag addr:$ptr)], itin>, TB, LOCK;
697 multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
698 string mnemonic, SDPatternOperator frag,
699 InstrItinClass itin8, InstrItinClass itin> {
700 let isCodeGenOnly = 1 in {
701 let Defs = [AL, EFLAGS], Uses = [AL] in
702 def #NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
703 !strconcat("lock\n\t", mnemonic,
704 "{b}\t{$swap, $ptr|$ptr, $swap}"),
705 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK;
706 let Defs = [AX, EFLAGS], Uses = [AX] in
707 def #NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
708 !strconcat("lock\n\t", mnemonic,
709 "{w}\t{$swap, $ptr|$ptr, $swap}"),
710 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize, LOCK;
711 let Defs = [EAX, EFLAGS], Uses = [EAX] in
712 def #NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
713 !strconcat("lock\n\t", mnemonic,
714 "{l}\t{$swap, $ptr|$ptr, $swap}"),
715 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, LOCK;
716 let Defs = [RAX, EFLAGS], Uses = [RAX] in
717 def #NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
718 !strconcat("lock\n\t", mnemonic,
719 "{q}\t{$swap, $ptr|$ptr, $swap}"),
720 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK;
724 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
725 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",
730 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
731 Predicates = [HasCmpxchg16b] in {
732 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
734 IIC_CMPX_LOCK_16B>, REX_W;
737 defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg",
738 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>;
740 // Atomic exchange and add
741 multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
743 InstrItinClass itin8, InstrItinClass itin> {
744 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1 in {
745 def #NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),
746 (ins GR8:$val, i8mem:$ptr),
747 !strconcat("lock\n\t", mnemonic,
748 "{b}\t{$val, $ptr|$ptr, $val}"),
750 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
752 def #NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
753 (ins GR16:$val, i16mem:$ptr),
754 !strconcat("lock\n\t", mnemonic,
755 "{w}\t{$val, $ptr|$ptr, $val}"),
758 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
760 def #NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
761 (ins GR32:$val, i32mem:$ptr),
762 !strconcat("lock\n\t", mnemonic,
763 "{l}\t{$val, $ptr|$ptr, $val}"),
766 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
768 def #NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
769 (ins GR64:$val, i64mem:$ptr),
770 !strconcat("lock\n\t", mnemonic,
771 "{q}\t{$val, $ptr|$ptr, $val}"),
774 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
779 defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",
780 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>,
783 def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
784 "#ACQUIRE_MOV PSEUDO!",
785 [(set GR8:$dst, (atomic_load_8 addr:$src))]>;
786 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
787 "#ACQUIRE_MOV PSEUDO!",
788 [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
789 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
790 "#ACQUIRE_MOV PSEUDO!",
791 [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
792 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
793 "#ACQUIRE_MOV PSEUDO!",
794 [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
796 def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
797 "#RELEASE_MOV PSEUDO!",
798 [(atomic_store_8 addr:$dst, GR8 :$src)]>;
799 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
800 "#RELEASE_MOV PSEUDO!",
801 [(atomic_store_16 addr:$dst, GR16:$src)]>;
802 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
803 "#RELEASE_MOV PSEUDO!",
804 [(atomic_store_32 addr:$dst, GR32:$src)]>;
805 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
806 "#RELEASE_MOV PSEUDO!",
807 [(atomic_store_64 addr:$dst, GR64:$src)]>;
809 //===----------------------------------------------------------------------===//
810 // Conditional Move Pseudo Instructions.
811 //===----------------------------------------------------------------------===//
814 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
815 // instruction selection into a branch sequence.
816 let Uses = [EFLAGS], usesCustomInserter = 1 in {
817 def CMOV_FR32 : I<0, Pseudo,
818 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
819 "#CMOV_FR32 PSEUDO!",
820 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
822 def CMOV_FR64 : I<0, Pseudo,
823 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
824 "#CMOV_FR64 PSEUDO!",
825 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
827 def CMOV_V4F32 : I<0, Pseudo,
828 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
829 "#CMOV_V4F32 PSEUDO!",
831 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
833 def CMOV_V2F64 : I<0, Pseudo,
834 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
835 "#CMOV_V2F64 PSEUDO!",
837 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
839 def CMOV_V2I64 : I<0, Pseudo,
840 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
841 "#CMOV_V2I64 PSEUDO!",
843 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
845 def CMOV_V8F32 : I<0, Pseudo,
846 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
847 "#CMOV_V8F32 PSEUDO!",
849 (v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond,
851 def CMOV_V4F64 : I<0, Pseudo,
852 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
853 "#CMOV_V4F64 PSEUDO!",
855 (v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
857 def CMOV_V4I64 : I<0, Pseudo,
858 (outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
859 "#CMOV_V4I64 PSEUDO!",
861 (v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
866 //===----------------------------------------------------------------------===//
867 // DAG Pattern Matching Rules
868 //===----------------------------------------------------------------------===//
870 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
871 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
872 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
873 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
874 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
875 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
876 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
878 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
879 (ADD32ri GR32:$src1, tconstpool:$src2)>;
880 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
881 (ADD32ri GR32:$src1, tjumptable:$src2)>;
882 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
883 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
884 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
885 (ADD32ri GR32:$src1, texternalsym:$src2)>;
886 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
887 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
889 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
890 (MOV32mi addr:$dst, tglobaladdr:$src)>;
891 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
892 (MOV32mi addr:$dst, texternalsym:$src)>;
893 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
894 (MOV32mi addr:$dst, tblockaddress:$src)>;
898 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
899 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
900 // 'movabs' predicate should handle this sort of thing.
901 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
902 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
903 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
904 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
905 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
906 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
907 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
908 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
909 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
910 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
912 // In static codegen with small code model, we can get the address of a label
913 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
914 // the MOV64ri64i32 should accept these.
915 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
916 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
917 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
918 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
919 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
920 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
921 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
922 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
923 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
924 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
926 // In kernel code model, we can get the address of a label
927 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
928 // the MOV64ri32 should accept these.
929 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
930 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
931 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
932 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
933 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
934 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
935 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
936 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
937 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
938 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
940 // If we have small model and -static mode, it is safe to store global addresses
941 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
942 // for MOV64mi32 should handle this sort of thing.
943 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
944 (MOV64mi32 addr:$dst, tconstpool:$src)>,
945 Requires<[NearData, IsStatic]>;
946 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
947 (MOV64mi32 addr:$dst, tjumptable:$src)>,
948 Requires<[NearData, IsStatic]>;
949 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
950 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
951 Requires<[NearData, IsStatic]>;
952 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
953 (MOV64mi32 addr:$dst, texternalsym:$src)>,
954 Requires<[NearData, IsStatic]>;
955 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
956 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
957 Requires<[NearData, IsStatic]>;
963 // tls has some funny stuff here...
964 // This corresponds to movabs $foo@tpoff, %rax
965 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
966 (MOV64ri tglobaltlsaddr :$dst)>;
967 // This corresponds to add $foo@tpoff, %rax
968 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
969 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
970 // This corresponds to mov foo@tpoff(%rbx), %eax
971 def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))),
972 (MOV64rm tglobaltlsaddr :$dst)>;
975 // Direct PC relative function call for small code model. 32-bit displacement
976 // sign extended to 64-bit.
977 def : Pat<(X86call (i64 tglobaladdr:$dst)),
978 (CALL64pcrel32 tglobaladdr:$dst)>;
979 def : Pat<(X86call (i64 texternalsym:$dst)),
980 (CALL64pcrel32 texternalsym:$dst)>;
982 // Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
983 // can never use callee-saved registers. That is the purpose of the GR64_TC
986 // The only volatile register that is never used by the calling convention is
987 // %r11. This happens when calling a vararg function with 6 arguments.
989 // Match an X86tcret that uses less than 7 volatile registers.
990 def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
991 (X86tcret node:$ptr, node:$off), [{
992 // X86tcret args: (*chain, ptr, imm, regs..., glue)
993 unsigned NumRegs = 0;
994 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
995 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
1000 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1001 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>,
1002 Requires<[In32BitMode]>;
1004 // FIXME: This is disabled for 32-bit PIC mode because the global base
1005 // register which is part of the address mode may be assigned a
1006 // callee-saved register.
1007 def : Pat<(X86tcret (load addr:$dst), imm:$off),
1008 (TCRETURNmi addr:$dst, imm:$off)>,
1009 Requires<[In32BitMode, IsNotPIC]>;
1011 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
1012 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1013 Requires<[In32BitMode]>;
1015 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
1016 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1017 Requires<[In32BitMode]>;
1019 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1020 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
1021 Requires<[In64BitMode]>;
1023 // Don't fold loads into X86tcret requiring more than 6 regs.
1024 // There wouldn't be enough scratch registers for base+index.
1025 def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
1026 (TCRETURNmi64 addr:$dst, imm:$off)>,
1027 Requires<[In64BitMode]>;
1029 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1030 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
1031 Requires<[In64BitMode]>;
1033 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1034 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1035 Requires<[In64BitMode]>;
1037 // Normal calls, with various flavors of addresses.
1038 def : Pat<(X86call (i32 tglobaladdr:$dst)),
1039 (CALLpcrel32 tglobaladdr:$dst)>;
1040 def : Pat<(X86call (i32 texternalsym:$dst)),
1041 (CALLpcrel32 texternalsym:$dst)>;
1042 def : Pat<(X86call (i32 imm:$dst)),
1043 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
1047 // TEST R,R is smaller than CMP R,0
1048 def : Pat<(X86cmp GR8:$src1, 0),
1049 (TEST8rr GR8:$src1, GR8:$src1)>;
1050 def : Pat<(X86cmp GR16:$src1, 0),
1051 (TEST16rr GR16:$src1, GR16:$src1)>;
1052 def : Pat<(X86cmp GR32:$src1, 0),
1053 (TEST32rr GR32:$src1, GR32:$src1)>;
1054 def : Pat<(X86cmp GR64:$src1, 0),
1055 (TEST64rr GR64:$src1, GR64:$src1)>;
1057 // Conditional moves with folded loads with operands swapped and conditions
1059 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
1060 Instruction Inst64> {
1061 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
1062 (Inst16 GR16:$src2, addr:$src1)>;
1063 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
1064 (Inst32 GR32:$src2, addr:$src1)>;
1065 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
1066 (Inst64 GR64:$src2, addr:$src1)>;
1069 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
1070 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
1071 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
1072 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
1073 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
1074 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
1075 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
1076 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
1077 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
1078 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1079 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1080 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1081 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1082 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1083 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1084 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1086 // zextload bool -> zextload byte
1087 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1088 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1089 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1090 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1092 // extload bool -> extload byte
1093 // When extloading from 16-bit and smaller memory locations into 64-bit
1094 // registers, use zero-extending loads so that the entire 64-bit register is
1095 // defined, avoiding partial-register updates.
1097 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1098 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1099 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1100 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1101 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1102 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1104 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1105 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1106 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1107 // For other extloads, use subregs, since the high contents of the register are
1108 // defined after an extload.
1109 def : Pat<(extloadi64i32 addr:$src),
1110 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1113 // anyext. Define these to do an explicit zero-extend to
1114 // avoid partial-register updates.
1115 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1116 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1117 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1119 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1120 def : Pat<(i32 (anyext GR16:$src)),
1121 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1123 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1124 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1125 def : Pat<(i64 (anyext GR32:$src)),
1126 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1129 // Any instruction that defines a 32-bit result leaves the high half of the
1130 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1131 // be copying from a truncate. And x86's cmov doesn't do anything if the
1132 // condition is false. But any other 32-bit operation will zero-extend
1134 def def32 : PatLeaf<(i32 GR32:$src), [{
1135 return N->getOpcode() != ISD::TRUNCATE &&
1136 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1137 N->getOpcode() != ISD::CopyFromReg &&
1138 N->getOpcode() != X86ISD::CMOV;
1141 // In the case of a 32-bit def that is known to implicitly zero-extend,
1142 // we can use a SUBREG_TO_REG.
1143 def : Pat<(i64 (zext def32:$src)),
1144 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1146 //===----------------------------------------------------------------------===//
1147 // Pattern match OR as ADD
1148 //===----------------------------------------------------------------------===//
1150 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1151 // 3-addressified into an LEA instruction to avoid copies. However, we also
1152 // want to finally emit these instructions as an or at the end of the code
1153 // generator to make the generated code easier to read. To do this, we select
1154 // into "disjoint bits" pseudo ops.
1156 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1157 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1158 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1159 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1161 APInt KnownZero0, KnownOne0;
1162 CurDAG->ComputeMaskedBits(N->getOperand(0), KnownZero0, KnownOne0, 0);
1163 APInt KnownZero1, KnownOne1;
1164 CurDAG->ComputeMaskedBits(N->getOperand(1), KnownZero1, KnownOne1, 0);
1165 return (~KnownZero0 & ~KnownZero1) == 0;
1169 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1170 let AddedComplexity = 5 in { // Try this before the selecting to OR
1172 let isConvertibleToThreeAddress = 1,
1173 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1174 let isCommutable = 1 in {
1175 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1176 "", // orw/addw REG, REG
1177 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1178 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1179 "", // orl/addl REG, REG
1180 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1181 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1182 "", // orq/addq REG, REG
1183 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1186 // NOTE: These are order specific, we want the ri8 forms to be listed
1187 // first so that they are slightly preferred to the ri forms.
1189 def ADD16ri8_DB : I<0, Pseudo,
1190 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1191 "", // orw/addw REG, imm8
1192 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1193 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1194 "", // orw/addw REG, imm
1195 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1197 def ADD32ri8_DB : I<0, Pseudo,
1198 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1199 "", // orl/addl REG, imm8
1200 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1201 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1202 "", // orl/addl REG, imm
1203 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1206 def ADD64ri8_DB : I<0, Pseudo,
1207 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1208 "", // orq/addq REG, imm8
1209 [(set GR64:$dst, (or_is_add GR64:$src1,
1210 i64immSExt8:$src2))]>;
1211 def ADD64ri32_DB : I<0, Pseudo,
1212 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1213 "", // orq/addq REG, imm
1214 [(set GR64:$dst, (or_is_add GR64:$src1,
1215 i64immSExt32:$src2))]>;
1217 } // AddedComplexity
1220 //===----------------------------------------------------------------------===//
1222 //===----------------------------------------------------------------------===//
1224 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1225 // +128 doesn't, so in this special case use a sub instead of an add.
1226 def : Pat<(add GR16:$src1, 128),
1227 (SUB16ri8 GR16:$src1, -128)>;
1228 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1229 (SUB16mi8 addr:$dst, -128)>;
1231 def : Pat<(add GR32:$src1, 128),
1232 (SUB32ri8 GR32:$src1, -128)>;
1233 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1234 (SUB32mi8 addr:$dst, -128)>;
1236 def : Pat<(add GR64:$src1, 128),
1237 (SUB64ri8 GR64:$src1, -128)>;
1238 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1239 (SUB64mi8 addr:$dst, -128)>;
1241 // The same trick applies for 32-bit immediate fields in 64-bit
1243 def : Pat<(add GR64:$src1, 0x0000000080000000),
1244 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1245 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1246 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1248 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1249 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1250 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1251 // represented with a sign extension of a 8 bit constant, use that.
1253 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1257 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1258 (i32 (GetLo8XForm imm:$imm))),
1261 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1265 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1266 (i32 (GetLo32XForm imm:$imm))),
1270 // r & (2^16-1) ==> movz
1271 def : Pat<(and GR32:$src1, 0xffff),
1272 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1273 // r & (2^8-1) ==> movz
1274 def : Pat<(and GR32:$src1, 0xff),
1275 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1278 Requires<[In32BitMode]>;
1279 // r & (2^8-1) ==> movz
1280 def : Pat<(and GR16:$src1, 0xff),
1281 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1282 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1284 Requires<[In32BitMode]>;
1286 // r & (2^32-1) ==> movz
1287 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1288 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1289 // r & (2^16-1) ==> movz
1290 def : Pat<(and GR64:$src, 0xffff),
1291 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit)))>;
1292 // r & (2^8-1) ==> movz
1293 def : Pat<(and GR64:$src, 0xff),
1294 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit)))>;
1295 // r & (2^8-1) ==> movz
1296 def : Pat<(and GR32:$src1, 0xff),
1297 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1298 Requires<[In64BitMode]>;
1299 // r & (2^8-1) ==> movz
1300 def : Pat<(and GR16:$src1, 0xff),
1301 (EXTRACT_SUBREG (MOVZX32rr8 (i8
1302 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
1303 Requires<[In64BitMode]>;
1306 // sext_inreg patterns
1307 def : Pat<(sext_inreg GR32:$src, i16),
1308 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1309 def : Pat<(sext_inreg GR32:$src, i8),
1310 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1313 Requires<[In32BitMode]>;
1315 def : Pat<(sext_inreg GR16:$src, i8),
1316 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
1317 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1319 Requires<[In32BitMode]>;
1321 def : Pat<(sext_inreg GR64:$src, i32),
1322 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1323 def : Pat<(sext_inreg GR64:$src, i16),
1324 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1325 def : Pat<(sext_inreg GR64:$src, i8),
1326 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1327 def : Pat<(sext_inreg GR32:$src, i8),
1328 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1329 Requires<[In64BitMode]>;
1330 def : Pat<(sext_inreg GR16:$src, i8),
1331 (EXTRACT_SUBREG (MOVSX32rr8
1332 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
1333 Requires<[In64BitMode]>;
1335 // sext, sext_load, zext, zext_load
1336 def: Pat<(i16 (sext GR8:$src)),
1337 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1338 def: Pat<(sextloadi16i8 addr:$src),
1339 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1340 def: Pat<(i16 (zext GR8:$src)),
1341 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1342 def: Pat<(zextloadi16i8 addr:$src),
1343 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1346 def : Pat<(i16 (trunc GR32:$src)),
1347 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1348 def : Pat<(i8 (trunc GR32:$src)),
1349 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1351 Requires<[In32BitMode]>;
1352 def : Pat<(i8 (trunc GR16:$src)),
1353 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1355 Requires<[In32BitMode]>;
1356 def : Pat<(i32 (trunc GR64:$src)),
1357 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1358 def : Pat<(i16 (trunc GR64:$src)),
1359 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1360 def : Pat<(i8 (trunc GR64:$src)),
1361 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1362 def : Pat<(i8 (trunc GR32:$src)),
1363 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1364 Requires<[In64BitMode]>;
1365 def : Pat<(i8 (trunc GR16:$src)),
1366 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1367 Requires<[In64BitMode]>;
1369 // h-register tricks
1370 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1371 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1373 Requires<[In32BitMode]>;
1374 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1375 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1377 Requires<[In32BitMode]>;
1378 def : Pat<(srl GR16:$src, (i8 8)),
1381 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1384 Requires<[In32BitMode]>;
1385 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1386 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1389 Requires<[In32BitMode]>;
1390 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1391 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1394 Requires<[In32BitMode]>;
1395 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1396 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1399 Requires<[In32BitMode]>;
1400 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1401 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1404 Requires<[In32BitMode]>;
1406 // h-register tricks.
1407 // For now, be conservative on x86-64 and use an h-register extract only if the
1408 // value is immediately zero-extended or stored, which are somewhat common
1409 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1410 // from being allocated in the same instruction as the h register, as there's
1411 // currently no way to describe this requirement to the register allocator.
1413 // h-register extract and zero-extend.
1414 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1418 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1421 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1423 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1425 Requires<[In64BitMode]>;
1426 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1427 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1430 Requires<[In64BitMode]>;
1431 def : Pat<(srl GR16:$src, (i8 8)),
1434 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1437 Requires<[In64BitMode]>;
1438 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1440 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1442 Requires<[In64BitMode]>;
1443 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1445 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1447 Requires<[In64BitMode]>;
1448 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1452 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1455 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1459 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1463 // h-register extract and store.
1464 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1467 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1469 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1472 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1474 Requires<[In64BitMode]>;
1475 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1478 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1480 Requires<[In64BitMode]>;
1483 // (shl x, 1) ==> (add x, x)
1484 // Note that if x is undef (immediate or otherwise), we could theoretically
1485 // end up with the two uses of x getting different values, producing a result
1486 // where the least significant bit is not 0. However, the probability of this
1487 // happening is considered low enough that this is officially not a
1489 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1490 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1491 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1492 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1494 // Helper imms that check if a mask doesn't change significant shift bits.
1495 def immShift32 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 5; }]>;
1496 def immShift64 : ImmLeaf<i8, [{ return CountTrailingOnes_32(Imm) >= 6; }]>;
1498 // (shl x (and y, 31)) ==> (shl x, y)
1499 def : Pat<(shl GR8:$src1, (and CL, immShift32)),
1500 (SHL8rCL GR8:$src1)>;
1501 def : Pat<(shl GR16:$src1, (and CL, immShift32)),
1502 (SHL16rCL GR16:$src1)>;
1503 def : Pat<(shl GR32:$src1, (and CL, immShift32)),
1504 (SHL32rCL GR32:$src1)>;
1505 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1506 (SHL8mCL addr:$dst)>;
1507 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1508 (SHL16mCL addr:$dst)>;
1509 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1510 (SHL32mCL addr:$dst)>;
1512 def : Pat<(srl GR8:$src1, (and CL, immShift32)),
1513 (SHR8rCL GR8:$src1)>;
1514 def : Pat<(srl GR16:$src1, (and CL, immShift32)),
1515 (SHR16rCL GR16:$src1)>;
1516 def : Pat<(srl GR32:$src1, (and CL, immShift32)),
1517 (SHR32rCL GR32:$src1)>;
1518 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1519 (SHR8mCL addr:$dst)>;
1520 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1521 (SHR16mCL addr:$dst)>;
1522 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1523 (SHR32mCL addr:$dst)>;
1525 def : Pat<(sra GR8:$src1, (and CL, immShift32)),
1526 (SAR8rCL GR8:$src1)>;
1527 def : Pat<(sra GR16:$src1, (and CL, immShift32)),
1528 (SAR16rCL GR16:$src1)>;
1529 def : Pat<(sra GR32:$src1, (and CL, immShift32)),
1530 (SAR32rCL GR32:$src1)>;
1531 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1532 (SAR8mCL addr:$dst)>;
1533 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1534 (SAR16mCL addr:$dst)>;
1535 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1536 (SAR32mCL addr:$dst)>;
1538 // (shl x (and y, 63)) ==> (shl x, y)
1539 def : Pat<(shl GR64:$src1, (and CL, immShift64)),
1540 (SHL64rCL GR64:$src1)>;
1541 def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1542 (SHL64mCL addr:$dst)>;
1544 def : Pat<(srl GR64:$src1, (and CL, immShift64)),
1545 (SHR64rCL GR64:$src1)>;
1546 def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1547 (SHR64mCL addr:$dst)>;
1549 def : Pat<(sra GR64:$src1, (and CL, immShift64)),
1550 (SAR64rCL GR64:$src1)>;
1551 def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1552 (SAR64mCL addr:$dst)>;
1555 // (anyext (setcc_carry)) -> (setcc_carry)
1556 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1558 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1560 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1566 //===----------------------------------------------------------------------===//
1567 // EFLAGS-defining Patterns
1568 //===----------------------------------------------------------------------===//
1571 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1572 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1573 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1576 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1577 (ADD8rm GR8:$src1, addr:$src2)>;
1578 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1579 (ADD16rm GR16:$src1, addr:$src2)>;
1580 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1581 (ADD32rm GR32:$src1, addr:$src2)>;
1584 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1585 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1586 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1587 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1588 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1589 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1590 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1593 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1594 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1595 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1598 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1599 (SUB8rm GR8:$src1, addr:$src2)>;
1600 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1601 (SUB16rm GR16:$src1, addr:$src2)>;
1602 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1603 (SUB32rm GR32:$src1, addr:$src2)>;
1606 def : Pat<(sub GR8:$src1, imm:$src2),
1607 (SUB8ri GR8:$src1, imm:$src2)>;
1608 def : Pat<(sub GR16:$src1, imm:$src2),
1609 (SUB16ri GR16:$src1, imm:$src2)>;
1610 def : Pat<(sub GR32:$src1, imm:$src2),
1611 (SUB32ri GR32:$src1, imm:$src2)>;
1612 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1613 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1614 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1615 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1618 def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>;
1619 def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>;
1620 def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
1621 def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>;
1624 def : Pat<(mul GR16:$src1, GR16:$src2),
1625 (IMUL16rr GR16:$src1, GR16:$src2)>;
1626 def : Pat<(mul GR32:$src1, GR32:$src2),
1627 (IMUL32rr GR32:$src1, GR32:$src2)>;
1630 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1631 (IMUL16rm GR16:$src1, addr:$src2)>;
1632 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1633 (IMUL32rm GR32:$src1, addr:$src2)>;
1636 def : Pat<(mul GR16:$src1, imm:$src2),
1637 (IMUL16rri GR16:$src1, imm:$src2)>;
1638 def : Pat<(mul GR32:$src1, imm:$src2),
1639 (IMUL32rri GR32:$src1, imm:$src2)>;
1640 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1641 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1642 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1643 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1645 // reg = mul mem, imm
1646 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1647 (IMUL16rmi addr:$src1, imm:$src2)>;
1648 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1649 (IMUL32rmi addr:$src1, imm:$src2)>;
1650 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1651 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1652 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1653 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1655 // Patterns for nodes that do not produce flags, for instructions that do.
1658 def : Pat<(add GR64:$src1, GR64:$src2),
1659 (ADD64rr GR64:$src1, GR64:$src2)>;
1660 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1661 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1662 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1663 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1664 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1665 (ADD64rm GR64:$src1, addr:$src2)>;
1668 def : Pat<(sub GR64:$src1, GR64:$src2),
1669 (SUB64rr GR64:$src1, GR64:$src2)>;
1670 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1671 (SUB64rm GR64:$src1, addr:$src2)>;
1672 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1673 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1674 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1675 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1678 def : Pat<(mul GR64:$src1, GR64:$src2),
1679 (IMUL64rr GR64:$src1, GR64:$src2)>;
1680 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1681 (IMUL64rm GR64:$src1, addr:$src2)>;
1682 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1683 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1684 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1685 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1686 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1687 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1688 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1689 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1692 def : Pat<(add GR8 :$src, 1), (INC8r GR8 :$src)>;
1693 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
1694 def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1695 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
1696 def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1697 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1700 def : Pat<(add GR8 :$src, -1), (DEC8r GR8 :$src)>;
1701 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
1702 def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1703 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
1704 def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1705 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1708 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1709 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1710 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1711 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1714 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1715 (OR8rm GR8:$src1, addr:$src2)>;
1716 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1717 (OR16rm GR16:$src1, addr:$src2)>;
1718 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1719 (OR32rm GR32:$src1, addr:$src2)>;
1720 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1721 (OR64rm GR64:$src1, addr:$src2)>;
1724 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1725 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1726 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1727 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1728 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1729 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1730 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1731 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1732 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1733 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1734 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1737 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1738 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1739 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1740 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1743 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1744 (XOR8rm GR8:$src1, addr:$src2)>;
1745 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1746 (XOR16rm GR16:$src1, addr:$src2)>;
1747 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1748 (XOR32rm GR32:$src1, addr:$src2)>;
1749 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1750 (XOR64rm GR64:$src1, addr:$src2)>;
1753 def : Pat<(xor GR8:$src1, imm:$src2),
1754 (XOR8ri GR8:$src1, imm:$src2)>;
1755 def : Pat<(xor GR16:$src1, imm:$src2),
1756 (XOR16ri GR16:$src1, imm:$src2)>;
1757 def : Pat<(xor GR32:$src1, imm:$src2),
1758 (XOR32ri GR32:$src1, imm:$src2)>;
1759 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1760 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1761 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1762 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1763 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1764 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1765 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1766 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1769 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1770 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1771 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1772 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1775 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1776 (AND8rm GR8:$src1, addr:$src2)>;
1777 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1778 (AND16rm GR16:$src1, addr:$src2)>;
1779 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1780 (AND32rm GR32:$src1, addr:$src2)>;
1781 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1782 (AND64rm GR64:$src1, addr:$src2)>;
1785 def : Pat<(and GR8:$src1, imm:$src2),
1786 (AND8ri GR8:$src1, imm:$src2)>;
1787 def : Pat<(and GR16:$src1, imm:$src2),
1788 (AND16ri GR16:$src1, imm:$src2)>;
1789 def : Pat<(and GR32:$src1, imm:$src2),
1790 (AND32ri GR32:$src1, imm:$src2)>;
1791 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1792 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1793 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1794 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1795 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1796 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1797 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1798 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
1800 // Bit scan instruction patterns to match explicit zero-undef behavior.
1801 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
1802 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
1803 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
1804 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
1805 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
1806 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;