1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue());
24 //===----------------------------------------------------------------------===//
25 // Random Pseudo Instructions.
27 // PIC base construction. This expands to code that looks like this:
30 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
31 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
35 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
36 // a stack adjustment and the codegen must know that they may modify the stack
37 // pointer before prolog-epilog rewriting occurs.
38 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
39 // sub / add which can clobber EFLAGS.
40 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
41 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
43 [(X86callseq_start timm:$amt)]>,
44 Requires<[In32BitMode]>;
45 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
47 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
48 Requires<[In32BitMode]>;
51 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
52 // a stack adjustment and the codegen must know that they may modify the stack
53 // pointer before prolog-epilog rewriting occurs.
54 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
55 // sub / add which can clobber EFLAGS.
56 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
57 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
59 [(X86callseq_start timm:$amt)]>,
60 Requires<[In64BitMode]>;
61 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
63 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
64 Requires<[In64BitMode]>;
69 // x86-64 va_start lowering magic.
70 let usesCustomInserter = 1 in {
71 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
74 i64imm:$regsavefi, i64imm:$offset,
76 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
77 [(X86vastart_save_xmm_regs GR8:$al,
81 // Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
82 // to _alloca is needed to probe the stack when allocating more than 4k bytes in
83 // one go. Touching the stack at 4K increments is necessary to ensure that the
84 // guard pages used by the OS virtual memory manager are allocated in correct
86 // The main point of having separate instruction are extra unmodelled effects
87 // (compared to ordinary calls) like stack pointer change.
89 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
90 def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
91 "# dynamic stack allocation",
97 //===----------------------------------------------------------------------===//
98 // EH Pseudo Instructions
100 let isTerminator = 1, isReturn = 1, isBarrier = 1,
101 hasCtrlDep = 1, isCodeGenOnly = 1 in {
102 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
103 "ret\t#eh_return, addr: $addr",
104 [(X86ehret GR32:$addr)]>;
108 let isTerminator = 1, isReturn = 1, isBarrier = 1,
109 hasCtrlDep = 1, isCodeGenOnly = 1 in {
110 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
111 "ret\t#eh_return, addr: $addr",
112 [(X86ehret GR64:$addr)]>;
116 //===----------------------------------------------------------------------===//
117 // Alias Instructions
118 //===----------------------------------------------------------------------===//
120 // Alias instructions that map movr0 to xor.
121 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
122 // FIXME: Set encoding to pseudo.
123 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
124 isCodeGenOnly = 1 in {
125 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
126 [(set GR8:$dst, 0)]>;
128 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
129 // encoding and avoids a partial-register update sometimes, but doing so
130 // at isel time interferes with rematerialization in the current register
131 // allocator. For now, this is rewritten when the instruction is lowered
133 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
135 [(set GR16:$dst, 0)]>, OpSize;
137 // FIXME: Set encoding to pseudo.
138 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
139 [(set GR32:$dst, 0)]>;
142 // We want to rewrite MOV64r0 in terms of MOV32r0, because it's sometimes a
143 // smaller encoding, but doing so at isel time interferes with rematerialization
144 // in the current register allocator. For now, this is rewritten when the
145 // instruction is lowered to an MCInst.
146 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
147 // when we have a better way to specify isel priority.
149 AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
150 def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
151 [(set GR64:$dst, 0)]>;
153 // Materialize i64 constant where top 32-bits are zero. This could theoretically
154 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
155 // that would make it more difficult to rematerialize.
156 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
157 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
158 "", [(set GR64:$dst, i64immZExt32:$src)]>;
161 // Use sbb to materialize carry bit.
162 let Uses = [EFLAGS], Defs = [EFLAGS], isCodeGenOnly = 1 in {
163 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
164 // However, Pat<> can't replicate the destination reg into the inputs of the
166 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
168 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
169 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
170 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
171 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
173 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
174 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
175 def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "",
176 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
180 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
184 //===----------------------------------------------------------------------===//
185 // String Pseudo Instructions
187 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
188 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
189 [(X86rep_movs i8)]>, REP;
190 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
191 [(X86rep_movs i16)]>, REP, OpSize;
192 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
193 [(X86rep_movs i32)]>, REP;
196 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in
197 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
198 [(X86rep_movs i64)]>, REP;
201 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
202 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
203 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
204 [(X86rep_stos i8)]>, REP;
205 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
206 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
207 [(X86rep_stos i16)]>, REP, OpSize;
208 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
209 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
210 [(X86rep_stos i32)]>, REP;
212 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI], isCodeGenOnly = 1 in
213 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
214 [(X86rep_stos i64)]>, REP;
217 //===----------------------------------------------------------------------===//
218 // Thread Local Storage Instructions
222 // All calls clobber the non-callee saved registers. ESP is marked as
223 // a use to prevent stack-pointer assignments that appear immediately
224 // before calls from potentially appearing dead.
225 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
226 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
227 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
228 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
230 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
232 "call\t___tls_get_addr@PLT",
233 [(X86tlsaddr tls32addr:$sym)]>,
234 Requires<[In32BitMode]>;
236 // All calls clobber the non-callee saved registers. RSP is marked as
237 // a use to prevent stack-pointer assignments that appear immediately
238 // before calls from potentially appearing dead.
239 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
240 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
241 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
242 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
243 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
245 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
247 "leaq\t$sym(%rip), %rdi; "
250 "call\t__tls_get_addr@PLT",
251 [(X86tlsaddr tls64addr:$sym)]>,
252 Requires<[In64BitMode]>;
254 // Darwin TLS Support
255 // For i386, the address of the thunk is passed on the stack, on return the
256 // address of the variable is in %eax. %ecx is trashed during the function
257 // call. All other registers are preserved.
258 let Defs = [EAX, ECX],
260 usesCustomInserter = 1 in
261 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
263 [(X86TLSCall addr:$sym)]>,
264 Requires<[In32BitMode]>;
266 // For x86_64, the address of the thunk is passed in %rdi, on return
267 // the address of the variable is in %rax. All other registers are preserved.
270 usesCustomInserter = 1 in
271 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
273 [(X86TLSCall addr:$sym)]>,
274 Requires<[In64BitMode]>;
276 //===----------------------------------------------------------------------===//
277 // Atomic Instruction Pseudo Instructions
278 //===----------------------------------------------------------------------===//
280 // Atomic exchange, and, or, xor
281 let Constraints = "$val = $dst", Defs = [EFLAGS],
282 usesCustomInserter = 1 in {
284 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
286 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
287 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
289 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
290 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
292 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
293 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
294 "#ATOMNAND8 PSEUDO!",
295 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
297 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
298 "#ATOMAND16 PSEUDO!",
299 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
300 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
302 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
303 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
304 "#ATOMXOR16 PSEUDO!",
305 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
306 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
307 "#ATOMNAND16 PSEUDO!",
308 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
309 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
310 "#ATOMMIN16 PSEUDO!",
311 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
312 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
313 "#ATOMMAX16 PSEUDO!",
314 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
315 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
316 "#ATOMUMIN16 PSEUDO!",
317 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
318 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
319 "#ATOMUMAX16 PSEUDO!",
320 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
323 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
324 "#ATOMAND32 PSEUDO!",
325 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
326 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
328 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
329 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
330 "#ATOMXOR32 PSEUDO!",
331 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
332 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
333 "#ATOMNAND32 PSEUDO!",
334 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
335 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
336 "#ATOMMIN32 PSEUDO!",
337 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
338 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
339 "#ATOMMAX32 PSEUDO!",
340 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
341 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
342 "#ATOMUMIN32 PSEUDO!",
343 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
344 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
345 "#ATOMUMAX32 PSEUDO!",
346 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
350 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
351 "#ATOMAND64 PSEUDO!",
352 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
353 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
355 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
356 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
357 "#ATOMXOR64 PSEUDO!",
358 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
359 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
360 "#ATOMNAND64 PSEUDO!",
361 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
362 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
363 "#ATOMMIN64 PSEUDO!",
364 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
365 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
366 "#ATOMMAX64 PSEUDO!",
367 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
368 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
369 "#ATOMUMIN64 PSEUDO!",
370 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
371 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
372 "#ATOMUMAX64 PSEUDO!",
373 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
376 let Constraints = "$val1 = $dst1, $val2 = $dst2",
377 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
378 Uses = [EAX, EBX, ECX, EDX],
379 mayLoad = 1, mayStore = 1,
380 usesCustomInserter = 1 in {
381 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
382 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
383 "#ATOMAND6432 PSEUDO!", []>;
384 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
385 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
386 "#ATOMOR6432 PSEUDO!", []>;
387 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
388 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
389 "#ATOMXOR6432 PSEUDO!", []>;
390 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
391 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
392 "#ATOMNAND6432 PSEUDO!", []>;
393 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
394 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
395 "#ATOMADD6432 PSEUDO!", []>;
396 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
397 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
398 "#ATOMSUB6432 PSEUDO!", []>;
399 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
400 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
401 "#ATOMSWAP6432 PSEUDO!", []>;
404 //===----------------------------------------------------------------------===//
405 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
406 //===----------------------------------------------------------------------===//
408 // FIXME: Use normal instructions and add lock prefix dynamically.
412 // TODO: Get this to fold the constant into the instruction.
413 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
415 "or{l}\t{$zero, $dst|$dst, $zero}",
416 []>, Requires<[In32BitMode]>, LOCK;
418 let hasSideEffects = 1 in
419 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
421 [(X86MemBarrier)]>, Requires<[HasSSE2]>;
423 // TODO: Get this to fold the constant into the instruction.
424 let hasSideEffects = 1, Defs = [ESP] in
425 def Int_MemBarrierNoSSE64 : RI<0x09, MRM1r, (outs), (ins GR64:$zero),
427 "or{q}\t{$zero, (%rsp)|(%rsp), $zero}",
428 [(X86MemBarrierNoSSE GR64:$zero)]>,
429 Requires<[In64BitMode]>, LOCK;
432 // Optimized codegen when the non-memory output is not used.
433 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1 in {
434 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
436 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
437 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
439 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
440 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
442 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
443 def LOCK_ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
445 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
447 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
449 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
450 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
452 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
453 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
455 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
456 def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
457 (ins i64mem:$dst, i64i32imm :$src2),
459 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
461 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
463 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
464 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
466 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
467 def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
468 (ins i64mem:$dst, i64i8imm :$src2),
470 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
472 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
474 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
475 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
477 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
478 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
480 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
481 def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
483 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
486 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
488 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
489 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
491 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
492 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
494 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
495 def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
496 (ins i64mem:$dst, i64i32imm:$src2),
498 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
501 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
503 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
504 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
506 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
507 def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
508 (ins i64mem:$dst, i64i8imm :$src2),
510 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
512 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
514 "inc{b}\t$dst", []>, LOCK;
515 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
517 "inc{w}\t$dst", []>, OpSize, LOCK;
518 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
520 "inc{l}\t$dst", []>, LOCK;
521 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
523 "inc{q}\t$dst", []>, LOCK;
525 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
527 "dec{b}\t$dst", []>, LOCK;
528 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
530 "dec{w}\t$dst", []>, OpSize, LOCK;
531 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
533 "dec{l}\t$dst", []>, LOCK;
534 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
536 "dec{q}\t$dst", []>, LOCK;
539 // Atomic compare and swap.
540 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
541 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
544 [(X86cas8 addr:$ptr)]>, TB, LOCK;
546 let Defs = [AL, EFLAGS], Uses = [AL] in {
547 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
549 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
550 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
553 let Defs = [AX, EFLAGS], Uses = [AX] in {
554 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
556 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
557 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
560 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
561 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
563 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
564 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
567 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
568 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
570 "cmpxchgq\t$swap,$ptr",
571 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
574 // Atomic exchange and add
575 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
576 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
578 "xadd{b}\t{$val, $ptr|$ptr, $val}",
579 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
581 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
583 "xadd{w}\t{$val, $ptr|$ptr, $val}",
584 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
586 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
588 "xadd{l}\t{$val, $ptr|$ptr, $val}",
589 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
591 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins GR64:$val,i64mem:$ptr),
594 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
598 //===----------------------------------------------------------------------===//
599 // Conditional Move Pseudo Instructions.
600 //===----------------------------------------------------------------------===//
603 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
604 // instruction selection into a branch sequence.
605 let Uses = [EFLAGS], usesCustomInserter = 1 in {
606 def CMOV_FR32 : I<0, Pseudo,
607 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
608 "#CMOV_FR32 PSEUDO!",
609 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
611 def CMOV_FR64 : I<0, Pseudo,
612 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
613 "#CMOV_FR64 PSEUDO!",
614 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
616 def CMOV_V4F32 : I<0, Pseudo,
617 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
618 "#CMOV_V4F32 PSEUDO!",
620 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
622 def CMOV_V2F64 : I<0, Pseudo,
623 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
624 "#CMOV_V2F64 PSEUDO!",
626 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
628 def CMOV_V2I64 : I<0, Pseudo,
629 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
630 "#CMOV_V2I64 PSEUDO!",
632 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
637 //===----------------------------------------------------------------------===//
638 // DAG Pattern Matching Rules
639 //===----------------------------------------------------------------------===//
641 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
642 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
643 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
644 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
645 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
646 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
647 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
649 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
650 (ADD32ri GR32:$src1, tconstpool:$src2)>;
651 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
652 (ADD32ri GR32:$src1, tjumptable:$src2)>;
653 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
654 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
655 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
656 (ADD32ri GR32:$src1, texternalsym:$src2)>;
657 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
658 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
660 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
661 (MOV32mi addr:$dst, tglobaladdr:$src)>;
662 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
663 (MOV32mi addr:$dst, texternalsym:$src)>;
664 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
665 (MOV32mi addr:$dst, tblockaddress:$src)>;
669 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
670 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
671 // 'movabs' predicate should handle this sort of thing.
672 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
673 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
674 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
675 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
676 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
677 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
678 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
679 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
680 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
681 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
683 // In static codegen with small code model, we can get the address of a label
684 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
685 // the MOV64ri64i32 should accept these.
686 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
687 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
688 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
689 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
690 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
691 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
692 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
693 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
694 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
695 (MOV64ri64i32 tblockaddress:$dst)>, Requires<[SmallCode]>;
697 // In kernel code model, we can get the address of a label
698 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
699 // the MOV64ri32 should accept these.
700 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
701 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
702 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
703 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
704 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
705 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
706 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
707 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
708 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
709 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
711 // If we have small model and -static mode, it is safe to store global addresses
712 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
713 // for MOV64mi32 should handle this sort of thing.
714 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
715 (MOV64mi32 addr:$dst, tconstpool:$src)>,
716 Requires<[NearData, IsStatic]>;
717 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
718 (MOV64mi32 addr:$dst, tjumptable:$src)>,
719 Requires<[NearData, IsStatic]>;
720 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
721 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
722 Requires<[NearData, IsStatic]>;
723 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
724 (MOV64mi32 addr:$dst, texternalsym:$src)>,
725 Requires<[NearData, IsStatic]>;
726 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
727 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
728 Requires<[NearData, IsStatic]>;
734 // tls has some funny stuff here...
735 // This corresponds to movabs $foo@tpoff, %rax
736 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
737 (MOV64ri tglobaltlsaddr :$dst)>;
738 // This corresponds to add $foo@tpoff, %rax
739 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
740 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
741 // This corresponds to mov foo@tpoff(%rbx), %eax
742 def : Pat<(load (i64 (X86Wrapper tglobaltlsaddr :$dst))),
743 (MOV64rm tglobaltlsaddr :$dst)>;
746 // Direct PC relative function call for small code model. 32-bit displacement
747 // sign extended to 64-bit.
748 def : Pat<(X86call (i64 tglobaladdr:$dst)),
749 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
750 def : Pat<(X86call (i64 texternalsym:$dst)),
751 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
753 def : Pat<(X86call (i64 tglobaladdr:$dst)),
754 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
755 def : Pat<(X86call (i64 texternalsym:$dst)),
756 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
759 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
760 (TCRETURNri GR32_TC:$dst, imm:$off)>,
761 Requires<[In32BitMode]>;
763 // FIXME: This is disabled for 32-bit PIC mode because the global base
764 // register which is part of the address mode may be assigned a
765 // callee-saved register.
766 def : Pat<(X86tcret (load addr:$dst), imm:$off),
767 (TCRETURNmi addr:$dst, imm:$off)>,
768 Requires<[In32BitMode, IsNotPIC]>;
770 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
771 (TCRETURNdi texternalsym:$dst, imm:$off)>,
772 Requires<[In32BitMode]>;
774 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
775 (TCRETURNdi texternalsym:$dst, imm:$off)>,
776 Requires<[In32BitMode]>;
778 def : Pat<(X86tcret GR64_TC:$dst, imm:$off),
779 (TCRETURNri64 GR64_TC:$dst, imm:$off)>,
780 Requires<[In64BitMode]>;
782 def : Pat<(X86tcret (load addr:$dst), imm:$off),
783 (TCRETURNmi64 addr:$dst, imm:$off)>,
784 Requires<[In64BitMode]>;
786 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
787 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
788 Requires<[In64BitMode]>;
790 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
791 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
792 Requires<[In64BitMode]>;
794 // Normal calls, with various flavors of addresses.
795 def : Pat<(X86call (i32 tglobaladdr:$dst)),
796 (CALLpcrel32 tglobaladdr:$dst)>;
797 def : Pat<(X86call (i32 texternalsym:$dst)),
798 (CALLpcrel32 texternalsym:$dst)>;
799 def : Pat<(X86call (i32 imm:$dst)),
800 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
802 // X86 specific add which produces a flag.
803 def : Pat<(addc GR32:$src1, GR32:$src2),
804 (ADD32rr GR32:$src1, GR32:$src2)>;
805 def : Pat<(addc GR32:$src1, (load addr:$src2)),
806 (ADD32rm GR32:$src1, addr:$src2)>;
807 def : Pat<(addc GR32:$src1, imm:$src2),
808 (ADD32ri GR32:$src1, imm:$src2)>;
809 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
810 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
812 def : Pat<(addc GR64:$src1, GR64:$src2),
813 (ADD64rr GR64:$src1, GR64:$src2)>;
814 def : Pat<(addc GR64:$src1, (load addr:$src2)),
815 (ADD64rm GR64:$src1, addr:$src2)>;
816 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
817 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
818 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
819 (ADD64ri32 GR64:$src1, imm:$src2)>;
821 def : Pat<(subc GR32:$src1, GR32:$src2),
822 (SUB32rr GR32:$src1, GR32:$src2)>;
823 def : Pat<(subc GR32:$src1, (load addr:$src2)),
824 (SUB32rm GR32:$src1, addr:$src2)>;
825 def : Pat<(subc GR32:$src1, imm:$src2),
826 (SUB32ri GR32:$src1, imm:$src2)>;
827 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
828 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
830 def : Pat<(subc GR64:$src1, GR64:$src2),
831 (SUB64rr GR64:$src1, GR64:$src2)>;
832 def : Pat<(subc GR64:$src1, (load addr:$src2)),
833 (SUB64rm GR64:$src1, addr:$src2)>;
834 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
835 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
836 def : Pat<(subc GR64:$src1, imm:$src2),
837 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
841 // TEST R,R is smaller than CMP R,0
842 def : Pat<(X86cmp GR8:$src1, 0),
843 (TEST8rr GR8:$src1, GR8:$src1)>;
844 def : Pat<(X86cmp GR16:$src1, 0),
845 (TEST16rr GR16:$src1, GR16:$src1)>;
846 def : Pat<(X86cmp GR32:$src1, 0),
847 (TEST32rr GR32:$src1, GR32:$src1)>;
848 def : Pat<(X86cmp GR64:$src1, 0),
849 (TEST64rr GR64:$src1, GR64:$src1)>;
851 // Conditional moves with folded loads with operands swapped and conditions
853 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
854 Instruction Inst64> {
855 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
856 (Inst16 GR16:$src2, addr:$src1)>;
857 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
858 (Inst32 GR32:$src2, addr:$src1)>;
859 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
860 (Inst64 GR64:$src2, addr:$src1)>;
863 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
864 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
865 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
866 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
867 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
868 defm : CMOVmr<X86_COND_A , CMOVBErm16, CMOVBErm32, CMOVBErm64>;
869 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
870 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
871 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
872 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
873 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
874 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
875 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
876 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
877 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
878 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
880 // zextload bool -> zextload byte
881 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
882 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
883 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
884 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
886 // extload bool -> extload byte
887 // When extloading from 16-bit and smaller memory locations into 64-bit
888 // registers, use zero-extending loads so that the entire 64-bit register is
889 // defined, avoiding partial-register updates.
891 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
892 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
893 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
894 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
895 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
896 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
898 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
899 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
900 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
901 // For other extloads, use subregs, since the high contents of the register are
902 // defined after an extload.
903 def : Pat<(extloadi64i32 addr:$src),
904 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
907 // anyext. Define these to do an explicit zero-extend to
908 // avoid partial-register updates.
909 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
910 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
912 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
913 def : Pat<(i32 (anyext GR16:$src)),
914 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
916 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
917 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
918 def : Pat<(i64 (anyext GR32:$src)),
919 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
922 // Any instruction that defines a 32-bit result leaves the high half of the
923 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
924 // be copying from a truncate. And x86's cmov doesn't do anything if the
925 // condition is false. But any other 32-bit operation will zero-extend
927 def def32 : PatLeaf<(i32 GR32:$src), [{
928 return N->getOpcode() != ISD::TRUNCATE &&
929 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
930 N->getOpcode() != ISD::CopyFromReg &&
931 N->getOpcode() != X86ISD::CMOV;
934 // In the case of a 32-bit def that is known to implicitly zero-extend,
935 // we can use a SUBREG_TO_REG.
936 def : Pat<(i64 (zext def32:$src)),
937 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
939 //===----------------------------------------------------------------------===//
941 //===----------------------------------------------------------------------===//
943 // Odd encoding trick: -128 fits into an 8-bit immediate field while
944 // +128 doesn't, so in this special case use a sub instead of an add.
945 def : Pat<(add GR16:$src1, 128),
946 (SUB16ri8 GR16:$src1, -128)>;
947 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
948 (SUB16mi8 addr:$dst, -128)>;
950 def : Pat<(add GR32:$src1, 128),
951 (SUB32ri8 GR32:$src1, -128)>;
952 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
953 (SUB32mi8 addr:$dst, -128)>;
955 def : Pat<(add GR64:$src1, 128),
956 (SUB64ri8 GR64:$src1, -128)>;
957 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
958 (SUB64mi8 addr:$dst, -128)>;
960 // The same trick applies for 32-bit immediate fields in 64-bit
962 def : Pat<(add GR64:$src1, 0x0000000080000000),
963 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
964 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
965 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
967 // Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it
968 // has an immediate with at least 32 bits of leading zeros, to avoid needing to
969 // materialize that immediate in a register first.
970 def : Pat<(and GR64:$src, i64immZExt32:$imm),
974 (EXTRACT_SUBREG GR64:$src, sub_32bit),
975 (i32 (GetLo32XForm imm:$imm))),
979 // r & (2^16-1) ==> movz
980 def : Pat<(and GR32:$src1, 0xffff),
981 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
982 // r & (2^8-1) ==> movz
983 def : Pat<(and GR32:$src1, 0xff),
984 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
987 Requires<[In32BitMode]>;
988 // r & (2^8-1) ==> movz
989 def : Pat<(and GR16:$src1, 0xff),
990 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
993 Requires<[In32BitMode]>;
995 // r & (2^32-1) ==> movz
996 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
997 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
998 // r & (2^16-1) ==> movz
999 def : Pat<(and GR64:$src, 0xffff),
1000 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit)))>;
1001 // r & (2^8-1) ==> movz
1002 def : Pat<(and GR64:$src, 0xff),
1003 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit)))>;
1004 // r & (2^8-1) ==> movz
1005 def : Pat<(and GR32:$src1, 0xff),
1006 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1007 Requires<[In64BitMode]>;
1008 // r & (2^8-1) ==> movz
1009 def : Pat<(and GR16:$src1, 0xff),
1010 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)))>,
1011 Requires<[In64BitMode]>;
1014 // sext_inreg patterns
1015 def : Pat<(sext_inreg GR32:$src, i16),
1016 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1017 def : Pat<(sext_inreg GR32:$src, i8),
1018 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1021 Requires<[In32BitMode]>;
1022 def : Pat<(sext_inreg GR16:$src, i8),
1023 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1026 Requires<[In32BitMode]>;
1028 def : Pat<(sext_inreg GR64:$src, i32),
1029 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1030 def : Pat<(sext_inreg GR64:$src, i16),
1031 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1032 def : Pat<(sext_inreg GR64:$src, i8),
1033 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1034 def : Pat<(sext_inreg GR32:$src, i8),
1035 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1036 Requires<[In64BitMode]>;
1037 def : Pat<(sext_inreg GR16:$src, i8),
1038 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, sub_8bit)))>,
1039 Requires<[In64BitMode]>;
1043 def : Pat<(i16 (trunc GR32:$src)),
1044 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1045 def : Pat<(i8 (trunc GR32:$src)),
1046 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1048 Requires<[In32BitMode]>;
1049 def : Pat<(i8 (trunc GR16:$src)),
1050 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1052 Requires<[In32BitMode]>;
1053 def : Pat<(i32 (trunc GR64:$src)),
1054 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1055 def : Pat<(i16 (trunc GR64:$src)),
1056 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1057 def : Pat<(i8 (trunc GR64:$src)),
1058 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1059 def : Pat<(i8 (trunc GR32:$src)),
1060 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1061 Requires<[In64BitMode]>;
1062 def : Pat<(i8 (trunc GR16:$src)),
1063 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1064 Requires<[In64BitMode]>;
1066 // h-register tricks
1067 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1068 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1070 Requires<[In32BitMode]>;
1071 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1072 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1074 Requires<[In32BitMode]>;
1075 def : Pat<(srl GR16:$src, (i8 8)),
1078 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1081 Requires<[In32BitMode]>;
1082 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1083 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1086 Requires<[In32BitMode]>;
1087 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1088 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1091 Requires<[In32BitMode]>;
1092 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1093 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1096 Requires<[In32BitMode]>;
1097 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1098 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1101 Requires<[In32BitMode]>;
1103 // h-register tricks.
1104 // For now, be conservative on x86-64 and use an h-register extract only if the
1105 // value is immediately zero-extended or stored, which are somewhat common
1106 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1107 // from being allocated in the same instruction as the h register, as there's
1108 // currently no way to describe this requirement to the register allocator.
1110 // h-register extract and zero-extend.
1111 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1115 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1118 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1120 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1122 Requires<[In64BitMode]>;
1123 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1124 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1127 Requires<[In64BitMode]>;
1128 def : Pat<(srl GR16:$src, (i8 8)),
1131 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1134 Requires<[In64BitMode]>;
1135 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1137 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1139 Requires<[In64BitMode]>;
1140 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1142 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1144 Requires<[In64BitMode]>;
1145 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1149 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1152 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1156 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1160 // h-register extract and store.
1161 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1164 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1166 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1169 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1171 Requires<[In64BitMode]>;
1172 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1175 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1177 Requires<[In64BitMode]>;
1180 // (shl x, 1) ==> (add x, x)
1181 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1182 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1183 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1184 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1186 // (shl x (and y, 31)) ==> (shl x, y)
1187 def : Pat<(shl GR8:$src1, (and CL, 31)),
1188 (SHL8rCL GR8:$src1)>;
1189 def : Pat<(shl GR16:$src1, (and CL, 31)),
1190 (SHL16rCL GR16:$src1)>;
1191 def : Pat<(shl GR32:$src1, (and CL, 31)),
1192 (SHL32rCL GR32:$src1)>;
1193 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
1194 (SHL8mCL addr:$dst)>;
1195 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
1196 (SHL16mCL addr:$dst)>;
1197 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
1198 (SHL32mCL addr:$dst)>;
1200 def : Pat<(srl GR8:$src1, (and CL, 31)),
1201 (SHR8rCL GR8:$src1)>;
1202 def : Pat<(srl GR16:$src1, (and CL, 31)),
1203 (SHR16rCL GR16:$src1)>;
1204 def : Pat<(srl GR32:$src1, (and CL, 31)),
1205 (SHR32rCL GR32:$src1)>;
1206 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
1207 (SHR8mCL addr:$dst)>;
1208 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
1209 (SHR16mCL addr:$dst)>;
1210 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
1211 (SHR32mCL addr:$dst)>;
1213 def : Pat<(sra GR8:$src1, (and CL, 31)),
1214 (SAR8rCL GR8:$src1)>;
1215 def : Pat<(sra GR16:$src1, (and CL, 31)),
1216 (SAR16rCL GR16:$src1)>;
1217 def : Pat<(sra GR32:$src1, (and CL, 31)),
1218 (SAR32rCL GR32:$src1)>;
1219 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
1220 (SAR8mCL addr:$dst)>;
1221 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
1222 (SAR16mCL addr:$dst)>;
1223 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
1224 (SAR32mCL addr:$dst)>;
1226 // (shl x (and y, 63)) ==> (shl x, y)
1227 def : Pat<(shl GR64:$src1, (and CL, 63)),
1228 (SHL64rCL GR64:$src1)>;
1229 def : Pat<(store (shl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1230 (SHL64mCL addr:$dst)>;
1232 def : Pat<(srl GR64:$src1, (and CL, 63)),
1233 (SHR64rCL GR64:$src1)>;
1234 def : Pat<(store (srl (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1235 (SHR64mCL addr:$dst)>;
1237 def : Pat<(sra GR64:$src1, (and CL, 63)),
1238 (SAR64rCL GR64:$src1)>;
1239 def : Pat<(store (sra (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1240 (SAR64mCL addr:$dst)>;
1243 // (anyext (setcc_carry)) -> (setcc_carry)
1244 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1246 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1248 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1251 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1252 let AddedComplexity = 5 in { // Try this before the selecting to OR
1253 def : Pat<(or_is_add GR16:$src1, imm:$src2),
1254 (ADD16ri GR16:$src1, imm:$src2)>;
1255 def : Pat<(or_is_add GR32:$src1, imm:$src2),
1256 (ADD32ri GR32:$src1, imm:$src2)>;
1257 def : Pat<(or_is_add GR16:$src1, i16immSExt8:$src2),
1258 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1259 def : Pat<(or_is_add GR32:$src1, i32immSExt8:$src2),
1260 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1261 def : Pat<(or_is_add GR16:$src1, GR16:$src2),
1262 (ADD16rr GR16:$src1, GR16:$src2)>;
1263 def : Pat<(or_is_add GR32:$src1, GR32:$src2),
1264 (ADD32rr GR32:$src1, GR32:$src2)>;
1265 def : Pat<(or_is_add GR64:$src1, i64immSExt8:$src2),
1266 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1267 def : Pat<(or_is_add GR64:$src1, i64immSExt32:$src2),
1268 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1269 def : Pat<(or_is_add GR64:$src1, GR64:$src2),
1270 (ADD64rr GR64:$src1, GR64:$src2)>;
1271 } // AddedComplexity
1273 //===----------------------------------------------------------------------===//
1274 // EFLAGS-defining Patterns
1275 //===----------------------------------------------------------------------===//
1278 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1279 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1280 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1283 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1284 (ADD8rm GR8:$src1, addr:$src2)>;
1285 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1286 (ADD16rm GR16:$src1, addr:$src2)>;
1287 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1288 (ADD32rm GR32:$src1, addr:$src2)>;
1291 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1292 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1293 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1294 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1295 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1296 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1297 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1300 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1301 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1302 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1305 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1306 (SUB8rm GR8:$src1, addr:$src2)>;
1307 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1308 (SUB16rm GR16:$src1, addr:$src2)>;
1309 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1310 (SUB32rm GR32:$src1, addr:$src2)>;
1313 def : Pat<(sub GR8:$src1, imm:$src2),
1314 (SUB8ri GR8:$src1, imm:$src2)>;
1315 def : Pat<(sub GR16:$src1, imm:$src2),
1316 (SUB16ri GR16:$src1, imm:$src2)>;
1317 def : Pat<(sub GR32:$src1, imm:$src2),
1318 (SUB32ri GR32:$src1, imm:$src2)>;
1319 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1320 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1321 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1322 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1325 def : Pat<(mul GR16:$src1, GR16:$src2),
1326 (IMUL16rr GR16:$src1, GR16:$src2)>;
1327 def : Pat<(mul GR32:$src1, GR32:$src2),
1328 (IMUL32rr GR32:$src1, GR32:$src2)>;
1331 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1332 (IMUL16rm GR16:$src1, addr:$src2)>;
1333 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1334 (IMUL32rm GR32:$src1, addr:$src2)>;
1337 def : Pat<(mul GR16:$src1, imm:$src2),
1338 (IMUL16rri GR16:$src1, imm:$src2)>;
1339 def : Pat<(mul GR32:$src1, imm:$src2),
1340 (IMUL32rri GR32:$src1, imm:$src2)>;
1341 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1342 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1343 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1344 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1346 // reg = mul mem, imm
1347 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1348 (IMUL16rmi addr:$src1, imm:$src2)>;
1349 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1350 (IMUL32rmi addr:$src1, imm:$src2)>;
1351 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1352 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1353 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1354 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1356 // Optimize multiply by 2 with EFLAGS result.
1357 let AddedComplexity = 2 in {
1358 def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>;
1359 def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>;
1362 // Patterns for nodes that do not produce flags, for instructions that do.
1365 def : Pat<(add GR64:$src1, GR64:$src2),
1366 (ADD64rr GR64:$src1, GR64:$src2)>;
1367 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1368 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1369 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1370 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1371 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1372 (ADD64rm GR64:$src1, addr:$src2)>;
1375 def : Pat<(sub GR64:$src1, GR64:$src2),
1376 (SUB64rr GR64:$src1, GR64:$src2)>;
1377 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1378 (SUB64rm GR64:$src1, addr:$src2)>;
1379 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1380 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1381 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1382 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1385 def : Pat<(mul GR64:$src1, GR64:$src2),
1386 (IMUL64rr GR64:$src1, GR64:$src2)>;
1387 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1388 (IMUL64rm GR64:$src1, addr:$src2)>;
1389 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1390 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1391 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1392 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1393 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1394 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1395 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1396 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1399 def : Pat<(add GR8 :$src, 1), (INC8r GR8 :$src)>;
1400 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
1401 def : Pat<(add GR16:$src, 1), (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1402 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
1403 def : Pat<(add GR32:$src, 1), (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1404 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1407 def : Pat<(add GR8 :$src, -1), (DEC8r GR8 :$src)>;
1408 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
1409 def : Pat<(add GR16:$src, -1), (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1410 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
1411 def : Pat<(add GR32:$src, -1), (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1412 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1415 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1416 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1417 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1418 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1421 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1422 (OR8rm GR8:$src1, addr:$src2)>;
1423 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1424 (OR16rm GR16:$src1, addr:$src2)>;
1425 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1426 (OR32rm GR32:$src1, addr:$src2)>;
1427 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1428 (OR64rm GR64:$src1, addr:$src2)>;
1431 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1432 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1433 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1434 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1435 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1436 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1437 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1438 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1439 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1440 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1441 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1444 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1445 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1446 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1447 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1450 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1451 (XOR8rm GR8:$src1, addr:$src2)>;
1452 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1453 (XOR16rm GR16:$src1, addr:$src2)>;
1454 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1455 (XOR32rm GR32:$src1, addr:$src2)>;
1456 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1457 (XOR64rm GR64:$src1, addr:$src2)>;
1460 def : Pat<(xor GR8:$src1, imm:$src2),
1461 (XOR8ri GR8:$src1, imm:$src2)>;
1462 def : Pat<(xor GR16:$src1, imm:$src2),
1463 (XOR16ri GR16:$src1, imm:$src2)>;
1464 def : Pat<(xor GR32:$src1, imm:$src2),
1465 (XOR32ri GR32:$src1, imm:$src2)>;
1466 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1467 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1468 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1469 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1470 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1471 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1472 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1473 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1476 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1477 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1478 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1479 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1482 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1483 (AND8rm GR8:$src1, addr:$src2)>;
1484 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1485 (AND16rm GR16:$src1, addr:$src2)>;
1486 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1487 (AND32rm GR32:$src1, addr:$src2)>;
1488 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1489 (AND64rm GR64:$src1, addr:$src2)>;
1492 def : Pat<(and GR8:$src1, imm:$src2),
1493 (AND8ri GR8:$src1, imm:$src2)>;
1494 def : Pat<(and GR16:$src1, imm:$src2),
1495 (AND16ri GR16:$src1, imm:$src2)>;
1496 def : Pat<(and GR32:$src1, imm:$src2),
1497 (AND32ri GR32:$src1, imm:$src2)>;
1498 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1499 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1500 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1501 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1502 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1503 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1504 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1505 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;