1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue(), SDLoc(N));
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
55 def : Pat<(X86callseq_start timm:$amt1),
56 (ADJCALLSTACKDOWN32 i32imm:$amt1, 0)>, Requires<[NotLP64]>;
59 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
60 // a stack adjustment and the codegen must know that they may modify the stack
61 // pointer before prolog-epilog rewriting occurs.
62 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
63 // sub / add which can clobber EFLAGS.
64 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
65 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
69 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
71 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
74 def : Pat<(X86callseq_start timm:$amt1),
75 (ADJCALLSTACKDOWN64 i32imm:$amt1, 0)>, Requires<[IsLP64]>;
78 // x86-64 va_start lowering magic.
79 let usesCustomInserter = 1, Defs = [EFLAGS] in {
80 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
83 i64imm:$regsavefi, i64imm:$offset,
85 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
86 [(X86vastart_save_xmm_regs GR8:$al,
91 // The VAARG_64 pseudo-instruction takes the address of the va_list,
92 // and places the address of the next argument into a register.
93 let Defs = [EFLAGS] in
94 def VAARG_64 : I<0, Pseudo,
96 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
97 "#VAARG_64 $dst, $ap, $size, $mode, $align",
99 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
102 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
103 // targets. These calls are needed to probe the stack when allocating more than
104 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
105 // ensure that the guard pages used by the OS virtual memory manager are
106 // allocated in correct sequence.
107 // The main point of having separate instruction are extra unmodelled effects
108 // (compared to ordinary calls) like stack pointer change.
110 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
111 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
112 "# dynamic stack allocation",
115 // When using segmented stacks these are lowered into instructions which first
116 // check if the current stacklet has enough free memory. If it does, memory is
117 // allocated by bumping the stack pointer. Otherwise memory is allocated from
120 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
121 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
122 "# variable sized alloca for segmented stacks",
124 (X86SegAlloca GR32:$size))]>,
127 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
128 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
129 "# variable sized alloca for segmented stacks",
131 (X86SegAlloca GR64:$size))]>,
132 Requires<[In64BitMode]>;
135 //===----------------------------------------------------------------------===//
136 // EH Pseudo Instructions
138 let SchedRW = [WriteSystem] in {
139 let isTerminator = 1, isReturn = 1, isBarrier = 1,
140 hasCtrlDep = 1, isCodeGenOnly = 1 in {
141 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
142 "ret\t#eh_return, addr: $addr",
143 [(X86ehret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
147 let isTerminator = 1, isReturn = 1, isBarrier = 1,
148 hasCtrlDep = 1, isCodeGenOnly = 1 in {
149 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
150 "ret\t#eh_return, addr: $addr",
151 [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
155 let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1, isCodeGenOnly = 1, isReturn = 1 in {
156 def CATCHRET : I<0, Pseudo, (outs), (ins brtarget32:$dst, brtarget32:$from),
158 [(catchret bb:$dst, bb:$from)]>;
159 def CLEANUPRET : I<0, Pseudo, (outs), (ins), "# CLEANUPRET", [(cleanupret)]>;
162 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
163 usesCustomInserter = 1 in {
164 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
166 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
167 Requires<[Not64BitMode]>;
168 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
170 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
171 Requires<[In64BitMode]>;
172 let isTerminator = 1 in {
173 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
174 "#EH_SJLJ_LONGJMP32",
175 [(X86eh_sjlj_longjmp addr:$buf)]>,
176 Requires<[Not64BitMode]>;
177 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
178 "#EH_SJLJ_LONGJMP64",
179 [(X86eh_sjlj_longjmp addr:$buf)]>,
180 Requires<[In64BitMode]>;
185 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
186 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
187 "#EH_SjLj_Setup\t$dst", []>;
190 //===----------------------------------------------------------------------===//
191 // Pseudo instructions used by unwind info.
193 let isPseudo = 1 in {
194 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg),
195 "#SEH_PushReg $reg", []>;
196 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
197 "#SEH_SaveReg $reg, $dst", []>;
198 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
199 "#SEH_SaveXMM $reg, $dst", []>;
200 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size),
201 "#SEH_StackAlloc $size", []>;
202 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset),
203 "#SEH_SetFrame $reg, $offset", []>;
204 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode),
205 "#SEH_PushFrame $mode", []>;
206 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins),
207 "#SEH_EndPrologue", []>;
208 def SEH_Epilogue : I<0, Pseudo, (outs), (ins),
209 "#SEH_Epilogue", []>;
212 //===----------------------------------------------------------------------===//
213 // Pseudo instructions used by segmented stacks.
216 // This is lowered into a RET instruction by MCInstLower. We need
217 // this so that we don't have to have a MachineBasicBlock which ends
218 // with a RET and also has successors.
219 let isPseudo = 1 in {
220 def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
223 // This instruction is lowered to a RET followed by a MOV. The two
224 // instructions are not generated on a higher level since then the
225 // verifier sees a MachineBasicBlock ending with a non-terminator.
226 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
230 //===----------------------------------------------------------------------===//
231 // Alias Instructions
232 //===----------------------------------------------------------------------===//
234 // Alias instruction mapping movr0 to xor.
235 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
236 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
238 def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
239 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
241 // Other widths can also make use of the 32-bit xor, which may have a smaller
242 // encoding and avoid partial register updates.
243 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
244 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
245 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> {
246 let AddedComplexity = 20;
249 // Materialize i64 constant where top 32-bits are zero. This could theoretically
250 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
251 // that would make it more difficult to rematerialize.
252 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
253 isCodeGenOnly = 1, hasSideEffects = 0 in
254 def MOV32ri64 : Ii32<0xb8, AddRegFrm, (outs GR32:$dst), (ins i64i32imm:$src),
255 "", [], IIC_ALU_NONMEM>, Sched<[WriteALU]>;
257 // This 64-bit pseudo-move can be used for both a 64-bit constant that is
258 // actually the zero-extension of a 32-bit constant and for labels in the
259 // x86-64 small code model.
260 def mov64imm32 : ComplexPattern<i64, 1, "selectMOV64Imm32", [imm, X86Wrapper]>;
262 let AddedComplexity = 1 in
263 def : Pat<(i64 mov64imm32:$src),
264 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>;
266 // Use sbb to materialize carry bit.
267 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in {
268 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
269 // However, Pat<> can't replicate the destination reg into the inputs of the
271 def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "",
272 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
273 def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "",
274 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
275 def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "",
276 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
277 def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "",
278 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
282 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
284 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
286 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
289 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
291 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
293 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
296 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
297 // will be eliminated and that the sbb can be extended up to a wider type. When
298 // this happens, it is great. However, if we are left with an 8-bit sbb and an
299 // and, we might as well just match it as a setb.
300 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
303 // (add OP, SETB) -> (adc OP, 0)
304 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
305 (ADC8ri GR8:$op, 0)>;
306 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
307 (ADC32ri8 GR32:$op, 0)>;
308 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
309 (ADC64ri8 GR64:$op, 0)>;
311 // (sub OP, SETB) -> (sbb OP, 0)
312 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
313 (SBB8ri GR8:$op, 0)>;
314 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
315 (SBB32ri8 GR32:$op, 0)>;
316 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
317 (SBB64ri8 GR64:$op, 0)>;
319 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
320 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
321 (ADC8ri GR8:$op, 0)>;
322 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
323 (ADC32ri8 GR32:$op, 0)>;
324 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
325 (ADC64ri8 GR64:$op, 0)>;
327 //===----------------------------------------------------------------------===//
328 // String Pseudo Instructions
330 let SchedRW = [WriteMicrocoded] in {
331 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
332 def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
333 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
334 Requires<[Not64BitMode]>;
335 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
336 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
337 Requires<[Not64BitMode]>;
338 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
339 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
340 Requires<[Not64BitMode]>;
343 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
344 def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
345 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
346 Requires<[In64BitMode]>;
347 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
348 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
349 Requires<[In64BitMode]>;
350 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
351 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
352 Requires<[In64BitMode]>;
353 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
354 [(X86rep_movs i64)], IIC_REP_MOVS>, REP,
355 Requires<[In64BitMode]>;
358 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
359 let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
360 let Uses = [AL,ECX,EDI] in
361 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
362 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
363 Requires<[Not64BitMode]>;
364 let Uses = [AX,ECX,EDI] in
365 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
366 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
367 Requires<[Not64BitMode]>;
368 let Uses = [EAX,ECX,EDI] in
369 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
370 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
371 Requires<[Not64BitMode]>;
374 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
375 let Uses = [AL,RCX,RDI] in
376 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
377 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
378 Requires<[In64BitMode]>;
379 let Uses = [AX,RCX,RDI] in
380 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
381 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
382 Requires<[In64BitMode]>;
383 let Uses = [RAX,RCX,RDI] in
384 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
385 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
386 Requires<[In64BitMode]>;
388 let Uses = [RAX,RCX,RDI] in
389 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
390 [(X86rep_stos i64)], IIC_REP_STOS>, REP,
391 Requires<[In64BitMode]>;
395 //===----------------------------------------------------------------------===//
396 // Thread Local Storage Instructions
400 // All calls clobber the non-callee saved registers. ESP is marked as
401 // a use to prevent stack-pointer assignments that appear immediately
402 // before calls from potentially appearing dead.
403 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
404 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
405 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
406 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
407 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
409 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
411 [(X86tlsaddr tls32addr:$sym)]>,
412 Requires<[Not64BitMode]>;
413 def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
415 [(X86tlsbaseaddr tls32baseaddr:$sym)]>,
416 Requires<[Not64BitMode]>;
419 // All calls clobber the non-callee saved registers. RSP is marked as
420 // a use to prevent stack-pointer assignments that appear immediately
421 // before calls from potentially appearing dead.
422 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
423 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
424 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
425 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
426 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
427 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
429 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
431 [(X86tlsaddr tls64addr:$sym)]>,
432 Requires<[In64BitMode]>;
433 def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
435 [(X86tlsbaseaddr tls64baseaddr:$sym)]>,
436 Requires<[In64BitMode]>;
439 // Darwin TLS Support
440 // For i386, the address of the thunk is passed on the stack, on return the
441 // address of the variable is in %eax. %ecx is trashed during the function
442 // call. All other registers are preserved.
443 let Defs = [EAX, ECX, EFLAGS],
445 usesCustomInserter = 1 in
446 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
448 [(X86TLSCall addr:$sym)]>,
449 Requires<[Not64BitMode]>;
451 // For x86_64, the address of the thunk is passed in %rdi, on return
452 // the address of the variable is in %rax. All other registers are preserved.
453 let Defs = [RAX, EFLAGS],
455 usesCustomInserter = 1 in
456 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
458 [(X86TLSCall addr:$sym)]>,
459 Requires<[In64BitMode]>;
462 //===----------------------------------------------------------------------===//
463 // Conditional Move Pseudo Instructions
465 // CMOV* - Used to implement the SELECT DAG operation. Expanded after
466 // instruction selection into a branch sequence.
467 multiclass CMOVrr_PSEUDO<RegisterClass RC, ValueType VT> {
468 def CMOV#NAME : I<0, Pseudo,
469 (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond),
470 "#CMOV_"#NAME#" PSEUDO!",
471 [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, imm:$cond,
475 let usesCustomInserter = 1, Uses = [EFLAGS] in {
476 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
477 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
478 // however that requires promoting the operands, and can induce additional
479 // i8 register pressure.
480 defm _GR8 : CMOVrr_PSEUDO<GR8, i8>;
482 let Predicates = [NoCMov] in {
483 defm _GR32 : CMOVrr_PSEUDO<GR32, i32>;
484 defm _GR16 : CMOVrr_PSEUDO<GR16, i16>;
485 } // Predicates = [NoCMov]
487 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
489 let Predicates = [FPStackf32] in
490 defm _RFP32 : CMOVrr_PSEUDO<RFP32, f32>;
492 let Predicates = [FPStackf64] in
493 defm _RFP64 : CMOVrr_PSEUDO<RFP64, f64>;
495 defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>;
497 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>;
498 defm _FR64 : CMOVrr_PSEUDO<FR64, f64>;
499 defm _V4F32 : CMOVrr_PSEUDO<VR128, v4f32>;
500 defm _V2F64 : CMOVrr_PSEUDO<VR128, v2f64>;
501 defm _V2I64 : CMOVrr_PSEUDO<VR128, v2i64>;
502 defm _V8F32 : CMOVrr_PSEUDO<VR256, v8f32>;
503 defm _V4F64 : CMOVrr_PSEUDO<VR256, v4f64>;
504 defm _V4I64 : CMOVrr_PSEUDO<VR256, v4i64>;
505 defm _V8I64 : CMOVrr_PSEUDO<VR512, v8i64>;
506 defm _V8F64 : CMOVrr_PSEUDO<VR512, v8f64>;
507 defm _V16F32 : CMOVrr_PSEUDO<VR512, v16f32>;
508 defm _V8I1 : CMOVrr_PSEUDO<VK8, v8i1>;
509 defm _V16I1 : CMOVrr_PSEUDO<VK16, v16i1>;
510 defm _V32I1 : CMOVrr_PSEUDO<VK32, v32i1>;
511 defm _V64I1 : CMOVrr_PSEUDO<VK64, v64i1>;
512 } // usesCustomInserter = 1, Uses = [EFLAGS]
514 //===----------------------------------------------------------------------===//
515 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
516 //===----------------------------------------------------------------------===//
518 // FIXME: Use normal instructions and add lock prefix dynamically.
522 // TODO: Get this to fold the constant into the instruction.
523 let isCodeGenOnly = 1, Defs = [EFLAGS] in
524 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
525 "or{l}\t{$zero, $dst|$dst, $zero}",
526 [], IIC_ALU_MEM>, Requires<[Not64BitMode]>, LOCK,
527 Sched<[WriteALULd, WriteRMW]>;
529 let hasSideEffects = 1 in
530 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
532 [(X86MemBarrier)]>, Sched<[WriteLoad]>;
534 // RegOpc corresponds to the mr version of the instruction
535 // ImmOpc corresponds to the mi version of the instruction
536 // ImmOpc8 corresponds to the mi8 version of the instruction
537 // ImmMod corresponds to the instruction format of the mi and mi8 versions
538 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
539 Format ImmMod, string mnemonic> {
540 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
541 SchedRW = [WriteALULd, WriteRMW] in {
543 def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
544 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
545 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
546 !strconcat(mnemonic, "{b}\t",
547 "{$src2, $dst|$dst, $src2}"),
548 [], IIC_ALU_NONMEM>, LOCK;
549 def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
550 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
551 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
552 !strconcat(mnemonic, "{w}\t",
553 "{$src2, $dst|$dst, $src2}"),
554 [], IIC_ALU_NONMEM>, OpSize16, LOCK;
555 def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
556 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
557 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
558 !strconcat(mnemonic, "{l}\t",
559 "{$src2, $dst|$dst, $src2}"),
560 [], IIC_ALU_NONMEM>, OpSize32, LOCK;
561 def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
562 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
563 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
564 !strconcat(mnemonic, "{q}\t",
565 "{$src2, $dst|$dst, $src2}"),
566 [], IIC_ALU_NONMEM>, LOCK;
568 def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
569 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
570 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
571 !strconcat(mnemonic, "{b}\t",
572 "{$src2, $dst|$dst, $src2}"),
573 [], IIC_ALU_MEM>, LOCK;
575 def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
576 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
577 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
578 !strconcat(mnemonic, "{w}\t",
579 "{$src2, $dst|$dst, $src2}"),
580 [], IIC_ALU_MEM>, OpSize16, LOCK;
582 def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
583 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
584 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
585 !strconcat(mnemonic, "{l}\t",
586 "{$src2, $dst|$dst, $src2}"),
587 [], IIC_ALU_MEM>, OpSize32, LOCK;
589 def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
590 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
591 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
592 !strconcat(mnemonic, "{q}\t",
593 "{$src2, $dst|$dst, $src2}"),
594 [], IIC_ALU_MEM>, LOCK;
596 def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
597 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
598 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
599 !strconcat(mnemonic, "{w}\t",
600 "{$src2, $dst|$dst, $src2}"),
601 [], IIC_ALU_MEM>, OpSize16, LOCK;
602 def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
603 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
604 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
605 !strconcat(mnemonic, "{l}\t",
606 "{$src2, $dst|$dst, $src2}"),
607 [], IIC_ALU_MEM>, OpSize32, LOCK;
608 def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
609 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
610 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
611 !strconcat(mnemonic, "{q}\t",
612 "{$src2, $dst|$dst, $src2}"),
613 [], IIC_ALU_MEM>, LOCK;
619 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
620 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
621 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
622 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
623 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
625 // Optimized codegen when the non-memory output is not used.
626 multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,
628 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
629 SchedRW = [WriteALULd, WriteRMW] in {
631 def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
632 !strconcat(mnemonic, "{b}\t$dst"),
633 [], IIC_UNARY_MEM>, LOCK;
634 def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
635 !strconcat(mnemonic, "{w}\t$dst"),
636 [], IIC_UNARY_MEM>, OpSize16, LOCK;
637 def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
638 !strconcat(mnemonic, "{l}\t$dst"),
639 [], IIC_UNARY_MEM>, OpSize32, LOCK;
640 def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
641 !strconcat(mnemonic, "{q}\t$dst"),
642 [], IIC_UNARY_MEM>, LOCK;
646 defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">;
647 defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">;
649 // Atomic compare and swap.
650 multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,
651 SDPatternOperator frag, X86MemOperand x86memop,
652 InstrItinClass itin> {
653 let isCodeGenOnly = 1 in {
654 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr),
655 !strconcat(mnemonic, "\t$ptr"),
656 [(frag addr:$ptr)], itin>, TB, LOCK;
660 multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
661 string mnemonic, SDPatternOperator frag,
662 InstrItinClass itin8, InstrItinClass itin> {
663 let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
664 let Defs = [AL, EFLAGS], Uses = [AL] in
665 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
666 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"),
667 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK;
668 let Defs = [AX, EFLAGS], Uses = [AX] in
669 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
670 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
671 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK;
672 let Defs = [EAX, EFLAGS], Uses = [EAX] in
673 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
674 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
675 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK;
676 let Defs = [RAX, EFLAGS], Uses = [RAX] in
677 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
678 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
679 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK;
683 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
684 SchedRW = [WriteALULd, WriteRMW] in {
685 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",
690 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
691 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in {
692 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
694 IIC_CMPX_LOCK_16B>, REX_W;
697 defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg",
698 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>;
700 // Atomic exchange and add
701 multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
703 InstrItinClass itin8, InstrItinClass itin> {
704 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1,
705 SchedRW = [WriteALULd, WriteRMW] in {
706 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),
707 (ins GR8:$val, i8mem:$ptr),
708 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
710 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
712 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
713 (ins GR16:$val, i16mem:$ptr),
714 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
717 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
719 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
720 (ins GR32:$val, i32mem:$ptr),
721 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
724 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
726 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
727 (ins GR64:$val, i64mem:$ptr),
728 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
731 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
736 defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",
737 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>,
740 /* The following multiclass tries to make sure that in code like
741 * x.store (immediate op x.load(acquire), release)
743 * x.store (register op x.load(acquire), release)
744 * an operation directly on memory is generated instead of wasting a register.
745 * It is not automatic as atomic_store/load are only lowered to MOV instructions
746 * extremely late to prevent them from being accidentally reordered in the backend
747 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions)
749 multiclass RELEASE_BINOP_MI<SDNode op> {
750 def NAME#8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
751 "#BINOP "#NAME#"8mi PSEUDO!",
752 [(atomic_store_8 addr:$dst, (op
753 (atomic_load_8 addr:$dst), (i8 imm:$src)))]>;
754 def NAME#8mr : I<0, Pseudo, (outs), (ins i8mem:$dst, GR8:$src),
755 "#BINOP "#NAME#"8mr PSEUDO!",
756 [(atomic_store_8 addr:$dst, (op
757 (atomic_load_8 addr:$dst), GR8:$src))]>;
758 // NAME#16 is not generated as 16-bit arithmetic instructions are considered
759 // costly and avoided as far as possible by this backend anyway
760 def NAME#32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
761 "#BINOP "#NAME#"32mi PSEUDO!",
762 [(atomic_store_32 addr:$dst, (op
763 (atomic_load_32 addr:$dst), (i32 imm:$src)))]>;
764 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
765 "#BINOP "#NAME#"32mr PSEUDO!",
766 [(atomic_store_32 addr:$dst, (op
767 (atomic_load_32 addr:$dst), GR32:$src))]>;
768 def NAME#64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
769 "#BINOP "#NAME#"64mi32 PSEUDO!",
770 [(atomic_store_64 addr:$dst, (op
771 (atomic_load_64 addr:$dst), (i64immSExt32:$src)))]>;
772 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
773 "#BINOP "#NAME#"64mr PSEUDO!",
774 [(atomic_store_64 addr:$dst, (op
775 (atomic_load_64 addr:$dst), GR64:$src))]>;
777 let Defs = [EFLAGS] in {
778 defm RELEASE_ADD : RELEASE_BINOP_MI<add>;
779 defm RELEASE_AND : RELEASE_BINOP_MI<and>;
780 defm RELEASE_OR : RELEASE_BINOP_MI<or>;
781 defm RELEASE_XOR : RELEASE_BINOP_MI<xor>;
782 // Note: we don't deal with sub, because substractions of constants are
783 // optimized into additions before this code can run.
786 // Same as above, but for floating-point.
787 // FIXME: imm version.
788 // FIXME: Version that doesn't clobber $src, using AVX's VADDSS.
789 // FIXME: This could also handle SIMD operations with *ps and *pd instructions.
790 let usesCustomInserter = 1 in {
791 multiclass RELEASE_FP_BINOP_MI<SDNode op> {
792 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, FR32:$src),
793 "#BINOP "#NAME#"32mr PSEUDO!",
794 [(atomic_store_32 addr:$dst,
796 (f32 (bitconvert (i32 (atomic_load_32 addr:$dst)))),
797 FR32:$src))))]>, Requires<[HasSSE1]>;
798 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, FR64:$src),
799 "#BINOP "#NAME#"64mr PSEUDO!",
800 [(atomic_store_64 addr:$dst,
802 (f64 (bitconvert (i64 (atomic_load_64 addr:$dst)))),
803 FR64:$src))))]>, Requires<[HasSSE2]>;
805 defm RELEASE_FADD : RELEASE_FP_BINOP_MI<fadd>;
806 // FIXME: Add fsub, fmul, fdiv, ...
809 multiclass RELEASE_UNOP<dag dag8, dag dag16, dag dag32, dag dag64> {
810 def NAME#8m : I<0, Pseudo, (outs), (ins i8mem:$dst),
811 "#UNOP "#NAME#"8m PSEUDO!",
812 [(atomic_store_8 addr:$dst, dag8)]>;
813 def NAME#16m : I<0, Pseudo, (outs), (ins i16mem:$dst),
814 "#UNOP "#NAME#"16m PSEUDO!",
815 [(atomic_store_16 addr:$dst, dag16)]>;
816 def NAME#32m : I<0, Pseudo, (outs), (ins i32mem:$dst),
817 "#UNOP "#NAME#"32m PSEUDO!",
818 [(atomic_store_32 addr:$dst, dag32)]>;
819 def NAME#64m : I<0, Pseudo, (outs), (ins i64mem:$dst),
820 "#UNOP "#NAME#"64m PSEUDO!",
821 [(atomic_store_64 addr:$dst, dag64)]>;
824 let Defs = [EFLAGS] in {
825 defm RELEASE_INC : RELEASE_UNOP<
826 (add (atomic_load_8 addr:$dst), (i8 1)),
827 (add (atomic_load_16 addr:$dst), (i16 1)),
828 (add (atomic_load_32 addr:$dst), (i32 1)),
829 (add (atomic_load_64 addr:$dst), (i64 1))>, Requires<[NotSlowIncDec]>;
830 defm RELEASE_DEC : RELEASE_UNOP<
831 (add (atomic_load_8 addr:$dst), (i8 -1)),
832 (add (atomic_load_16 addr:$dst), (i16 -1)),
833 (add (atomic_load_32 addr:$dst), (i32 -1)),
834 (add (atomic_load_64 addr:$dst), (i64 -1))>, Requires<[NotSlowIncDec]>;
837 TODO: These don't work because the type inference of TableGen fails.
838 TODO: find a way to fix it.
839 let Defs = [EFLAGS] in {
840 defm RELEASE_NEG : RELEASE_UNOP<
841 (ineg (atomic_load_8 addr:$dst)),
842 (ineg (atomic_load_16 addr:$dst)),
843 (ineg (atomic_load_32 addr:$dst)),
844 (ineg (atomic_load_64 addr:$dst))>;
846 // NOT doesn't set flags.
847 defm RELEASE_NOT : RELEASE_UNOP<
848 (not (atomic_load_8 addr:$dst)),
849 (not (atomic_load_16 addr:$dst)),
850 (not (atomic_load_32 addr:$dst)),
851 (not (atomic_load_64 addr:$dst))>;
854 def RELEASE_MOV8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
855 "#RELEASE_MOV8mi PSEUDO!",
856 [(atomic_store_8 addr:$dst, (i8 imm:$src))]>;
857 def RELEASE_MOV16mi : I<0, Pseudo, (outs), (ins i16mem:$dst, i16imm:$src),
858 "#RELEASE_MOV16mi PSEUDO!",
859 [(atomic_store_16 addr:$dst, (i16 imm:$src))]>;
860 def RELEASE_MOV32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
861 "#RELEASE_MOV32mi PSEUDO!",
862 [(atomic_store_32 addr:$dst, (i32 imm:$src))]>;
863 def RELEASE_MOV64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
864 "#RELEASE_MOV64mi32 PSEUDO!",
865 [(atomic_store_64 addr:$dst, i64immSExt32:$src)]>;
867 def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
868 "#RELEASE_MOV8mr PSEUDO!",
869 [(atomic_store_8 addr:$dst, GR8 :$src)]>;
870 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
871 "#RELEASE_MOV16mr PSEUDO!",
872 [(atomic_store_16 addr:$dst, GR16:$src)]>;
873 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
874 "#RELEASE_MOV32mr PSEUDO!",
875 [(atomic_store_32 addr:$dst, GR32:$src)]>;
876 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
877 "#RELEASE_MOV64mr PSEUDO!",
878 [(atomic_store_64 addr:$dst, GR64:$src)]>;
880 def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
881 "#ACQUIRE_MOV8rm PSEUDO!",
882 [(set GR8:$dst, (atomic_load_8 addr:$src))]>;
883 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
884 "#ACQUIRE_MOV16rm PSEUDO!",
885 [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
886 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
887 "#ACQUIRE_MOV32rm PSEUDO!",
888 [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
889 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
890 "#ACQUIRE_MOV64rm PSEUDO!",
891 [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
893 //===----------------------------------------------------------------------===//
894 // DAG Pattern Matching Rules
895 //===----------------------------------------------------------------------===//
897 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
898 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
899 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
900 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
901 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
902 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
903 def : Pat<(i32 (X86Wrapper mcsym:$dst)), (MOV32ri mcsym:$dst)>;
904 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
906 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
907 (ADD32ri GR32:$src1, tconstpool:$src2)>;
908 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
909 (ADD32ri GR32:$src1, tjumptable:$src2)>;
910 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
911 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
912 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
913 (ADD32ri GR32:$src1, texternalsym:$src2)>;
914 def : Pat<(add GR32:$src1, (X86Wrapper mcsym:$src2)),
915 (ADD32ri GR32:$src1, mcsym:$src2)>;
916 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
917 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
919 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
920 (MOV32mi addr:$dst, tglobaladdr:$src)>;
921 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
922 (MOV32mi addr:$dst, texternalsym:$src)>;
923 def : Pat<(store (i32 (X86Wrapper mcsym:$src)), addr:$dst),
924 (MOV32mi addr:$dst, mcsym:$src)>;
925 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
926 (MOV32mi addr:$dst, tblockaddress:$src)>;
928 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
929 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
930 // 'movabs' predicate should handle this sort of thing.
931 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
932 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
933 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
934 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
935 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
936 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
937 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
938 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
939 def : Pat<(i64 (X86Wrapper mcsym:$dst)),
940 (MOV64ri mcsym:$dst)>, Requires<[FarData]>;
941 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
942 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
944 // In kernel code model, we can get the address of a label
945 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
946 // the MOV64ri32 should accept these.
947 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
948 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
949 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
950 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
951 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
952 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
953 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
954 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
955 def : Pat<(i64 (X86Wrapper mcsym:$dst)),
956 (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>;
957 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
958 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
960 // If we have small model and -static mode, it is safe to store global addresses
961 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
962 // for MOV64mi32 should handle this sort of thing.
963 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
964 (MOV64mi32 addr:$dst, tconstpool:$src)>,
965 Requires<[NearData, IsStatic]>;
966 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
967 (MOV64mi32 addr:$dst, tjumptable:$src)>,
968 Requires<[NearData, IsStatic]>;
969 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
970 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
971 Requires<[NearData, IsStatic]>;
972 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
973 (MOV64mi32 addr:$dst, texternalsym:$src)>,
974 Requires<[NearData, IsStatic]>;
975 def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst),
976 (MOV64mi32 addr:$dst, mcsym:$src)>,
977 Requires<[NearData, IsStatic]>;
978 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
979 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
980 Requires<[NearData, IsStatic]>;
982 def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>;
983 def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>;
987 // tls has some funny stuff here...
988 // This corresponds to movabs $foo@tpoff, %rax
989 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
990 (MOV64ri32 tglobaltlsaddr :$dst)>;
991 // This corresponds to add $foo@tpoff, %rax
992 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
993 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
996 // Direct PC relative function call for small code model. 32-bit displacement
997 // sign extended to 64-bit.
998 def : Pat<(X86call (i64 tglobaladdr:$dst)),
999 (CALL64pcrel32 tglobaladdr:$dst)>;
1000 def : Pat<(X86call (i64 texternalsym:$dst)),
1001 (CALL64pcrel32 texternalsym:$dst)>;
1003 // Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
1004 // can never use callee-saved registers. That is the purpose of the GR64_TC
1005 // register classes.
1007 // The only volatile register that is never used by the calling convention is
1008 // %r11. This happens when calling a vararg function with 6 arguments.
1010 // Match an X86tcret that uses less than 7 volatile registers.
1011 def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
1012 (X86tcret node:$ptr, node:$off), [{
1013 // X86tcret args: (*chain, ptr, imm, regs..., glue)
1014 unsigned NumRegs = 0;
1015 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
1016 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
1021 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1022 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>,
1023 Requires<[Not64BitMode]>;
1025 // FIXME: This is disabled for 32-bit PIC mode because the global base
1026 // register which is part of the address mode may be assigned a
1027 // callee-saved register.
1028 def : Pat<(X86tcret (load addr:$dst), imm:$off),
1029 (TCRETURNmi addr:$dst, imm:$off)>,
1030 Requires<[Not64BitMode, IsNotPIC]>;
1032 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
1033 (TCRETURNdi tglobaladdr:$dst, imm:$off)>,
1034 Requires<[NotLP64]>;
1036 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
1037 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1038 Requires<[NotLP64]>;
1040 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1041 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
1042 Requires<[In64BitMode]>;
1044 // Don't fold loads into X86tcret requiring more than 6 regs.
1045 // There wouldn't be enough scratch registers for base+index.
1046 def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
1047 (TCRETURNmi64 addr:$dst, imm:$off)>,
1048 Requires<[In64BitMode]>;
1050 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1051 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
1054 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1055 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1058 // Normal calls, with various flavors of addresses.
1059 def : Pat<(X86call (i32 tglobaladdr:$dst)),
1060 (CALLpcrel32 tglobaladdr:$dst)>;
1061 def : Pat<(X86call (i32 texternalsym:$dst)),
1062 (CALLpcrel32 texternalsym:$dst)>;
1063 def : Pat<(X86call (i32 imm:$dst)),
1064 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
1068 // TEST R,R is smaller than CMP R,0
1069 def : Pat<(X86cmp GR8:$src1, 0),
1070 (TEST8rr GR8:$src1, GR8:$src1)>;
1071 def : Pat<(X86cmp GR16:$src1, 0),
1072 (TEST16rr GR16:$src1, GR16:$src1)>;
1073 def : Pat<(X86cmp GR32:$src1, 0),
1074 (TEST32rr GR32:$src1, GR32:$src1)>;
1075 def : Pat<(X86cmp GR64:$src1, 0),
1076 (TEST64rr GR64:$src1, GR64:$src1)>;
1078 // Conditional moves with folded loads with operands swapped and conditions
1080 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
1081 Instruction Inst64> {
1082 let Predicates = [HasCMov] in {
1083 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
1084 (Inst16 GR16:$src2, addr:$src1)>;
1085 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
1086 (Inst32 GR32:$src2, addr:$src1)>;
1087 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
1088 (Inst64 GR64:$src2, addr:$src1)>;
1092 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
1093 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
1094 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
1095 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
1096 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
1097 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
1098 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
1099 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
1100 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
1101 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1102 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1103 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1104 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1105 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1106 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1107 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1109 // zextload bool -> zextload byte
1110 def : Pat<(zextloadi8i1 addr:$src), (AND8ri (MOV8rm addr:$src), (i8 1))>;
1111 def : Pat<(zextloadi16i1 addr:$src), (AND16ri8 (MOVZX16rm8 addr:$src), (i16 1))>;
1112 def : Pat<(zextloadi32i1 addr:$src), (AND32ri8 (MOVZX32rm8 addr:$src), (i32 1))>;
1113 def : Pat<(zextloadi64i1 addr:$src),
1114 (SUBREG_TO_REG (i64 0),
1115 (AND32ri8 (MOVZX32rm8 addr:$src), (i32 1)), sub_32bit)>;
1117 // extload bool -> extload byte
1118 // When extloading from 16-bit and smaller memory locations into 64-bit
1119 // registers, use zero-extending loads so that the entire 64-bit register is
1120 // defined, avoiding partial-register updates.
1122 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1123 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1124 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1125 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1126 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1127 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1129 // For other extloads, use subregs, since the high contents of the register are
1130 // defined after an extload.
1131 def : Pat<(extloadi64i1 addr:$src),
1132 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1133 def : Pat<(extloadi64i8 addr:$src),
1134 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1135 def : Pat<(extloadi64i16 addr:$src),
1136 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1137 def : Pat<(extloadi64i32 addr:$src),
1138 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1140 // anyext. Define these to do an explicit zero-extend to
1141 // avoid partial-register updates.
1142 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1143 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1144 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1146 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1147 def : Pat<(i32 (anyext GR16:$src)),
1148 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1150 def : Pat<(i64 (anyext GR8 :$src)),
1151 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1152 def : Pat<(i64 (anyext GR16:$src)),
1153 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
1154 def : Pat<(i64 (anyext GR32:$src)),
1155 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1158 // Any instruction that defines a 32-bit result leaves the high half of the
1159 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1160 // be copying from a truncate. And x86's cmov doesn't do anything if the
1161 // condition is false. But any other 32-bit operation will zero-extend
1163 def def32 : PatLeaf<(i32 GR32:$src), [{
1164 return N->getOpcode() != ISD::TRUNCATE &&
1165 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1166 N->getOpcode() != ISD::CopyFromReg &&
1167 N->getOpcode() != ISD::AssertSext &&
1168 N->getOpcode() != X86ISD::CMOV;
1171 // In the case of a 32-bit def that is known to implicitly zero-extend,
1172 // we can use a SUBREG_TO_REG.
1173 def : Pat<(i64 (zext def32:$src)),
1174 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1176 //===----------------------------------------------------------------------===//
1177 // Pattern match OR as ADD
1178 //===----------------------------------------------------------------------===//
1180 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1181 // 3-addressified into an LEA instruction to avoid copies. However, we also
1182 // want to finally emit these instructions as an or at the end of the code
1183 // generator to make the generated code easier to read. To do this, we select
1184 // into "disjoint bits" pseudo ops.
1186 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1187 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1188 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1189 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1191 APInt KnownZero0, KnownOne0;
1192 CurDAG->computeKnownBits(N->getOperand(0), KnownZero0, KnownOne0, 0);
1193 APInt KnownZero1, KnownOne1;
1194 CurDAG->computeKnownBits(N->getOperand(1), KnownZero1, KnownOne1, 0);
1195 return (~KnownZero0 & ~KnownZero1) == 0;
1199 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1200 // Try this before the selecting to OR.
1201 let AddedComplexity = 5, SchedRW = [WriteALU] in {
1203 let isConvertibleToThreeAddress = 1,
1204 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1205 let isCommutable = 1 in {
1206 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1207 "", // orw/addw REG, REG
1208 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1209 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1210 "", // orl/addl REG, REG
1211 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1212 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1213 "", // orq/addq REG, REG
1214 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1217 // NOTE: These are order specific, we want the ri8 forms to be listed
1218 // first so that they are slightly preferred to the ri forms.
1220 def ADD16ri8_DB : I<0, Pseudo,
1221 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1222 "", // orw/addw REG, imm8
1223 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1224 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1225 "", // orw/addw REG, imm
1226 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1228 def ADD32ri8_DB : I<0, Pseudo,
1229 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1230 "", // orl/addl REG, imm8
1231 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1232 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1233 "", // orl/addl REG, imm
1234 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1237 def ADD64ri8_DB : I<0, Pseudo,
1238 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1239 "", // orq/addq REG, imm8
1240 [(set GR64:$dst, (or_is_add GR64:$src1,
1241 i64immSExt8:$src2))]>;
1242 def ADD64ri32_DB : I<0, Pseudo,
1243 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1244 "", // orq/addq REG, imm
1245 [(set GR64:$dst, (or_is_add GR64:$src1,
1246 i64immSExt32:$src2))]>;
1248 } // AddedComplexity, SchedRW
1251 //===----------------------------------------------------------------------===//
1253 //===----------------------------------------------------------------------===//
1255 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1256 // +128 doesn't, so in this special case use a sub instead of an add.
1257 def : Pat<(add GR16:$src1, 128),
1258 (SUB16ri8 GR16:$src1, -128)>;
1259 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1260 (SUB16mi8 addr:$dst, -128)>;
1262 def : Pat<(add GR32:$src1, 128),
1263 (SUB32ri8 GR32:$src1, -128)>;
1264 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1265 (SUB32mi8 addr:$dst, -128)>;
1267 def : Pat<(add GR64:$src1, 128),
1268 (SUB64ri8 GR64:$src1, -128)>;
1269 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1270 (SUB64mi8 addr:$dst, -128)>;
1272 // The same trick applies for 32-bit immediate fields in 64-bit
1274 def : Pat<(add GR64:$src1, 0x0000000080000000),
1275 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1276 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1277 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1279 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1280 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1281 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1282 // represented with a sign extension of a 8 bit constant, use that.
1283 // This can also reduce instruction size by eliminating the need for the REX
1286 // AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32.
1287 let AddedComplexity = 1 in {
1288 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1292 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1293 (i32 (GetLo8XForm imm:$imm))),
1296 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1300 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1301 (i32 (GetLo32XForm imm:$imm))),
1303 } // AddedComplexity = 1
1306 // AddedComplexity is needed due to the increased complexity on the
1307 // i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all
1308 // the MOVZX patterns keeps thems together in DAGIsel tables.
1309 let AddedComplexity = 1 in {
1310 // r & (2^16-1) ==> movz
1311 def : Pat<(and GR32:$src1, 0xffff),
1312 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1313 // r & (2^8-1) ==> movz
1314 def : Pat<(and GR32:$src1, 0xff),
1315 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1318 Requires<[Not64BitMode]>;
1319 // r & (2^8-1) ==> movz
1320 def : Pat<(and GR16:$src1, 0xff),
1321 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1322 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1324 Requires<[Not64BitMode]>;
1326 // r & (2^32-1) ==> movz
1327 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1328 (SUBREG_TO_REG (i64 0),
1329 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)),
1331 // r & (2^16-1) ==> movz
1332 def : Pat<(and GR64:$src, 0xffff),
1333 (SUBREG_TO_REG (i64 0),
1334 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))),
1336 // r & (2^8-1) ==> movz
1337 def : Pat<(and GR64:$src, 0xff),
1338 (SUBREG_TO_REG (i64 0),
1339 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))),
1341 // r & (2^8-1) ==> movz
1342 def : Pat<(and GR32:$src1, 0xff),
1343 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1344 Requires<[In64BitMode]>;
1345 // r & (2^8-1) ==> movz
1346 def : Pat<(and GR16:$src1, 0xff),
1347 (EXTRACT_SUBREG (MOVZX32rr8 (i8
1348 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
1349 Requires<[In64BitMode]>;
1350 } // AddedComplexity = 1
1353 // sext_inreg patterns
1354 def : Pat<(sext_inreg GR32:$src, i16),
1355 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1356 def : Pat<(sext_inreg GR32:$src, i8),
1357 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1360 Requires<[Not64BitMode]>;
1362 def : Pat<(sext_inreg GR16:$src, i8),
1363 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
1364 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1366 Requires<[Not64BitMode]>;
1368 def : Pat<(sext_inreg GR64:$src, i32),
1369 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1370 def : Pat<(sext_inreg GR64:$src, i16),
1371 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1372 def : Pat<(sext_inreg GR64:$src, i8),
1373 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1374 def : Pat<(sext_inreg GR32:$src, i8),
1375 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1376 Requires<[In64BitMode]>;
1377 def : Pat<(sext_inreg GR16:$src, i8),
1378 (EXTRACT_SUBREG (MOVSX32rr8
1379 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
1380 Requires<[In64BitMode]>;
1382 // sext, sext_load, zext, zext_load
1383 def: Pat<(i16 (sext GR8:$src)),
1384 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1385 def: Pat<(sextloadi16i8 addr:$src),
1386 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1387 def: Pat<(i16 (zext GR8:$src)),
1388 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1389 def: Pat<(zextloadi16i8 addr:$src),
1390 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1393 def : Pat<(i16 (trunc GR32:$src)),
1394 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1395 def : Pat<(i8 (trunc GR32:$src)),
1396 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1398 Requires<[Not64BitMode]>;
1399 def : Pat<(i8 (trunc GR16:$src)),
1400 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1402 Requires<[Not64BitMode]>;
1403 def : Pat<(i32 (trunc GR64:$src)),
1404 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1405 def : Pat<(i16 (trunc GR64:$src)),
1406 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1407 def : Pat<(i8 (trunc GR64:$src)),
1408 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1409 def : Pat<(i8 (trunc GR32:$src)),
1410 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1411 Requires<[In64BitMode]>;
1412 def : Pat<(i8 (trunc GR16:$src)),
1413 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1414 Requires<[In64BitMode]>;
1416 // h-register tricks
1417 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1418 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1420 Requires<[Not64BitMode]>;
1421 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1422 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1424 Requires<[Not64BitMode]>;
1425 def : Pat<(srl GR16:$src, (i8 8)),
1428 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1431 Requires<[Not64BitMode]>;
1432 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1433 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1436 Requires<[Not64BitMode]>;
1437 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1438 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1441 Requires<[Not64BitMode]>;
1442 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1443 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1446 Requires<[Not64BitMode]>;
1447 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1448 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1451 Requires<[Not64BitMode]>;
1453 // h-register tricks.
1454 // For now, be conservative on x86-64 and use an h-register extract only if the
1455 // value is immediately zero-extended or stored, which are somewhat common
1456 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1457 // from being allocated in the same instruction as the h register, as there's
1458 // currently no way to describe this requirement to the register allocator.
1460 // h-register extract and zero-extend.
1461 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1465 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1468 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1470 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1472 Requires<[In64BitMode]>;
1473 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1474 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1477 Requires<[In64BitMode]>;
1478 def : Pat<(srl GR16:$src, (i8 8)),
1481 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1484 Requires<[In64BitMode]>;
1485 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1487 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1489 Requires<[In64BitMode]>;
1490 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1492 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1494 Requires<[In64BitMode]>;
1495 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1499 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1502 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1506 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1510 // h-register extract and store.
1511 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1514 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1516 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1519 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1521 Requires<[In64BitMode]>;
1522 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1525 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1527 Requires<[In64BitMode]>;
1530 // (shl x, 1) ==> (add x, x)
1531 // Note that if x is undef (immediate or otherwise), we could theoretically
1532 // end up with the two uses of x getting different values, producing a result
1533 // where the least significant bit is not 0. However, the probability of this
1534 // happening is considered low enough that this is officially not a
1536 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1537 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1538 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1539 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1541 // Helper imms that check if a mask doesn't change significant shift bits.
1542 def immShift32 : ImmLeaf<i8, [{
1543 return countTrailingOnes<uint64_t>(Imm) >= 5;
1545 def immShift64 : ImmLeaf<i8, [{
1546 return countTrailingOnes<uint64_t>(Imm) >= 6;
1549 // Shift amount is implicitly masked.
1550 multiclass MaskedShiftAmountPats<SDNode frag, string name> {
1551 // (shift x (and y, 31)) ==> (shift x, y)
1552 def : Pat<(frag GR8:$src1, (and CL, immShift32)),
1553 (!cast<Instruction>(name # "8rCL") GR8:$src1)>;
1554 def : Pat<(frag GR16:$src1, (and CL, immShift32)),
1555 (!cast<Instruction>(name # "16rCL") GR16:$src1)>;
1556 def : Pat<(frag GR32:$src1, (and CL, immShift32)),
1557 (!cast<Instruction>(name # "32rCL") GR32:$src1)>;
1558 def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1559 (!cast<Instruction>(name # "8mCL") addr:$dst)>;
1560 def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1561 (!cast<Instruction>(name # "16mCL") addr:$dst)>;
1562 def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1563 (!cast<Instruction>(name # "32mCL") addr:$dst)>;
1565 // (shift x (and y, 63)) ==> (shift x, y)
1566 def : Pat<(frag GR64:$src1, (and CL, immShift64)),
1567 (!cast<Instruction>(name # "64rCL") GR64:$src1)>;
1568 def : Pat<(store (frag (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1569 (!cast<Instruction>(name # "64mCL") addr:$dst)>;
1572 defm : MaskedShiftAmountPats<shl, "SHL">;
1573 defm : MaskedShiftAmountPats<srl, "SHR">;
1574 defm : MaskedShiftAmountPats<sra, "SAR">;
1575 defm : MaskedShiftAmountPats<rotl, "ROL">;
1576 defm : MaskedShiftAmountPats<rotr, "ROR">;
1578 // (anyext (setcc_carry)) -> (setcc_carry)
1579 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1581 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1583 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1589 //===----------------------------------------------------------------------===//
1590 // EFLAGS-defining Patterns
1591 //===----------------------------------------------------------------------===//
1594 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1595 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1596 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1599 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1600 (ADD8rm GR8:$src1, addr:$src2)>;
1601 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1602 (ADD16rm GR16:$src1, addr:$src2)>;
1603 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1604 (ADD32rm GR32:$src1, addr:$src2)>;
1607 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1608 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1609 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1610 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1611 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1612 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1613 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1616 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1617 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1618 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1621 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1622 (SUB8rm GR8:$src1, addr:$src2)>;
1623 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1624 (SUB16rm GR16:$src1, addr:$src2)>;
1625 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1626 (SUB32rm GR32:$src1, addr:$src2)>;
1629 def : Pat<(sub GR8:$src1, imm:$src2),
1630 (SUB8ri GR8:$src1, imm:$src2)>;
1631 def : Pat<(sub GR16:$src1, imm:$src2),
1632 (SUB16ri GR16:$src1, imm:$src2)>;
1633 def : Pat<(sub GR32:$src1, imm:$src2),
1634 (SUB32ri GR32:$src1, imm:$src2)>;
1635 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1636 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1637 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1638 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1641 def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>;
1642 def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>;
1643 def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
1644 def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>;
1647 def : Pat<(mul GR16:$src1, GR16:$src2),
1648 (IMUL16rr GR16:$src1, GR16:$src2)>;
1649 def : Pat<(mul GR32:$src1, GR32:$src2),
1650 (IMUL32rr GR32:$src1, GR32:$src2)>;
1653 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1654 (IMUL16rm GR16:$src1, addr:$src2)>;
1655 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1656 (IMUL32rm GR32:$src1, addr:$src2)>;
1659 def : Pat<(mul GR16:$src1, imm:$src2),
1660 (IMUL16rri GR16:$src1, imm:$src2)>;
1661 def : Pat<(mul GR32:$src1, imm:$src2),
1662 (IMUL32rri GR32:$src1, imm:$src2)>;
1663 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1664 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1665 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1666 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1668 // reg = mul mem, imm
1669 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1670 (IMUL16rmi addr:$src1, imm:$src2)>;
1671 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1672 (IMUL32rmi addr:$src1, imm:$src2)>;
1673 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1674 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1675 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1676 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1678 // Patterns for nodes that do not produce flags, for instructions that do.
1681 def : Pat<(add GR64:$src1, GR64:$src2),
1682 (ADD64rr GR64:$src1, GR64:$src2)>;
1683 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1684 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1685 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1686 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1687 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1688 (ADD64rm GR64:$src1, addr:$src2)>;
1691 def : Pat<(sub GR64:$src1, GR64:$src2),
1692 (SUB64rr GR64:$src1, GR64:$src2)>;
1693 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1694 (SUB64rm GR64:$src1, addr:$src2)>;
1695 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1696 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1697 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1698 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1701 def : Pat<(mul GR64:$src1, GR64:$src2),
1702 (IMUL64rr GR64:$src1, GR64:$src2)>;
1703 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1704 (IMUL64rm GR64:$src1, addr:$src2)>;
1705 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1706 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1707 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1708 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1709 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1710 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1711 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1712 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1714 // Increment/Decrement reg.
1715 // Do not make INC/DEC if it is slow
1716 let Predicates = [NotSlowIncDec] in {
1717 def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>;
1718 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>;
1719 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>;
1720 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1721 def : Pat<(add GR8:$src, -1), (DEC8r GR8:$src)>;
1722 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>;
1723 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>;
1724 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1728 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1729 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1730 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1731 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1734 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1735 (OR8rm GR8:$src1, addr:$src2)>;
1736 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1737 (OR16rm GR16:$src1, addr:$src2)>;
1738 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1739 (OR32rm GR32:$src1, addr:$src2)>;
1740 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1741 (OR64rm GR64:$src1, addr:$src2)>;
1744 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1745 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1746 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1747 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1748 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1749 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1750 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1751 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1752 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1753 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1754 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1757 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1758 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1759 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1760 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1763 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1764 (XOR8rm GR8:$src1, addr:$src2)>;
1765 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1766 (XOR16rm GR16:$src1, addr:$src2)>;
1767 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1768 (XOR32rm GR32:$src1, addr:$src2)>;
1769 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1770 (XOR64rm GR64:$src1, addr:$src2)>;
1773 def : Pat<(xor GR8:$src1, imm:$src2),
1774 (XOR8ri GR8:$src1, imm:$src2)>;
1775 def : Pat<(xor GR16:$src1, imm:$src2),
1776 (XOR16ri GR16:$src1, imm:$src2)>;
1777 def : Pat<(xor GR32:$src1, imm:$src2),
1778 (XOR32ri GR32:$src1, imm:$src2)>;
1779 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1780 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1781 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1782 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1783 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1784 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1785 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1786 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1789 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1790 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1791 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1792 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1795 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1796 (AND8rm GR8:$src1, addr:$src2)>;
1797 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1798 (AND16rm GR16:$src1, addr:$src2)>;
1799 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1800 (AND32rm GR32:$src1, addr:$src2)>;
1801 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1802 (AND64rm GR64:$src1, addr:$src2)>;
1805 def : Pat<(and GR8:$src1, imm:$src2),
1806 (AND8ri GR8:$src1, imm:$src2)>;
1807 def : Pat<(and GR16:$src1, imm:$src2),
1808 (AND16ri GR16:$src1, imm:$src2)>;
1809 def : Pat<(and GR32:$src1, imm:$src2),
1810 (AND32ri GR32:$src1, imm:$src2)>;
1811 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1812 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1813 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1814 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1815 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1816 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1817 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1818 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
1820 // Bit scan instruction patterns to match explicit zero-undef behavior.
1821 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
1822 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
1823 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
1824 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
1825 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
1826 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;
1828 // When HasMOVBE is enabled it is possible to get a non-legalized
1829 // register-register 16 bit bswap. This maps it to a ROL instruction.
1830 let Predicates = [HasMOVBE] in {
1831 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>;