1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue(), SDLoc(N));
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
52 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
55 def : Pat<(X86callseq_start timm:$amt1),
56 (ADJCALLSTACKDOWN32 i32imm:$amt1, 0)>, Requires<[NotLP64]>;
59 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
60 // a stack adjustment and the codegen must know that they may modify the stack
61 // pointer before prolog-epilog rewriting occurs.
62 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
63 // sub / add which can clobber EFLAGS.
64 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
65 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
69 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
71 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
74 def : Pat<(X86callseq_start timm:$amt1),
75 (ADJCALLSTACKDOWN64 i32imm:$amt1, 0)>, Requires<[IsLP64]>;
78 // x86-64 va_start lowering magic.
79 let usesCustomInserter = 1, Defs = [EFLAGS] in {
80 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
83 i64imm:$regsavefi, i64imm:$offset,
85 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
86 [(X86vastart_save_xmm_regs GR8:$al,
91 // The VAARG_64 pseudo-instruction takes the address of the va_list,
92 // and places the address of the next argument into a register.
93 let Defs = [EFLAGS] in
94 def VAARG_64 : I<0, Pseudo,
96 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
97 "#VAARG_64 $dst, $ap, $size, $mode, $align",
99 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
102 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
103 // targets. These calls are needed to probe the stack when allocating more than
104 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
105 // ensure that the guard pages used by the OS virtual memory manager are
106 // allocated in correct sequence.
107 // The main point of having separate instruction are extra unmodelled effects
108 // (compared to ordinary calls) like stack pointer change.
110 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
111 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
112 "# dynamic stack allocation",
115 // When using segmented stacks these are lowered into instructions which first
116 // check if the current stacklet has enough free memory. If it does, memory is
117 // allocated by bumping the stack pointer. Otherwise memory is allocated from
120 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
121 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
122 "# variable sized alloca for segmented stacks",
124 (X86SegAlloca GR32:$size))]>,
127 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
128 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
129 "# variable sized alloca for segmented stacks",
131 (X86SegAlloca GR64:$size))]>,
132 Requires<[In64BitMode]>;
135 //===----------------------------------------------------------------------===//
136 // EH Pseudo Instructions
138 let SchedRW = [WriteSystem] in {
139 let isTerminator = 1, isReturn = 1, isBarrier = 1,
140 hasCtrlDep = 1, isCodeGenOnly = 1 in {
141 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
142 "ret\t#eh_return, addr: $addr",
143 [(X86ehret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
147 let isTerminator = 1, isReturn = 1, isBarrier = 1,
148 hasCtrlDep = 1, isCodeGenOnly = 1 in {
149 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
150 "ret\t#eh_return, addr: $addr",
151 [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
155 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1, isCodeGenOnly = 1 in {
156 def CATCHRET : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
157 "ret{l}\t# CATCHRET",
158 [(X86catchret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
159 def CATCHRET64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
160 "ret{q}\t# CATCHRET",
161 [(X86catchret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
164 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
165 usesCustomInserter = 1 in {
166 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
168 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
169 Requires<[Not64BitMode]>;
170 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
172 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
173 Requires<[In64BitMode]>;
174 let isTerminator = 1 in {
175 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
176 "#EH_SJLJ_LONGJMP32",
177 [(X86eh_sjlj_longjmp addr:$buf)]>,
178 Requires<[Not64BitMode]>;
179 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
180 "#EH_SJLJ_LONGJMP64",
181 [(X86eh_sjlj_longjmp addr:$buf)]>,
182 Requires<[In64BitMode]>;
187 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
188 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
189 "#EH_SjLj_Setup\t$dst", []>;
192 //===----------------------------------------------------------------------===//
193 // Pseudo instructions used by unwind info.
195 let isPseudo = 1 in {
196 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg),
197 "#SEH_PushReg $reg", []>;
198 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
199 "#SEH_SaveReg $reg, $dst", []>;
200 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
201 "#SEH_SaveXMM $reg, $dst", []>;
202 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size),
203 "#SEH_StackAlloc $size", []>;
204 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset),
205 "#SEH_SetFrame $reg, $offset", []>;
206 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode),
207 "#SEH_PushFrame $mode", []>;
208 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins),
209 "#SEH_EndPrologue", []>;
210 def SEH_Epilogue : I<0, Pseudo, (outs), (ins),
211 "#SEH_Epilogue", []>;
214 //===----------------------------------------------------------------------===//
215 // Pseudo instructions used by segmented stacks.
218 // This is lowered into a RET instruction by MCInstLower. We need
219 // this so that we don't have to have a MachineBasicBlock which ends
220 // with a RET and also has successors.
221 let isPseudo = 1 in {
222 def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
225 // This instruction is lowered to a RET followed by a MOV. The two
226 // instructions are not generated on a higher level since then the
227 // verifier sees a MachineBasicBlock ending with a non-terminator.
228 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
232 //===----------------------------------------------------------------------===//
233 // Alias Instructions
234 //===----------------------------------------------------------------------===//
236 // Alias instruction mapping movr0 to xor.
237 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
238 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
240 def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
241 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
243 // Other widths can also make use of the 32-bit xor, which may have a smaller
244 // encoding and avoid partial register updates.
245 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
246 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
247 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)> {
248 let AddedComplexity = 20;
251 // Materialize i64 constant where top 32-bits are zero. This could theoretically
252 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
253 // that would make it more difficult to rematerialize.
254 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1,
255 isCodeGenOnly = 1, hasSideEffects = 0 in
256 def MOV32ri64 : Ii32<0xb8, AddRegFrm, (outs GR32:$dst), (ins i64i32imm:$src),
257 "", [], IIC_ALU_NONMEM>, Sched<[WriteALU]>;
259 // This 64-bit pseudo-move can be used for both a 64-bit constant that is
260 // actually the zero-extension of a 32-bit constant, and for labels in the
261 // x86-64 small code model.
262 def mov64imm32 : ComplexPattern<i64, 1, "SelectMOV64Imm32", [imm, X86Wrapper]>;
264 let AddedComplexity = 1 in
265 def : Pat<(i64 mov64imm32:$src),
266 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>;
268 // Use sbb to materialize carry bit.
269 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in {
270 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
271 // However, Pat<> can't replicate the destination reg into the inputs of the
273 def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "",
274 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
275 def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "",
276 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
277 def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "",
278 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
279 def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "",
280 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
284 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
286 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
288 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
291 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
293 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
295 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
298 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
299 // will be eliminated and that the sbb can be extended up to a wider type. When
300 // this happens, it is great. However, if we are left with an 8-bit sbb and an
301 // and, we might as well just match it as a setb.
302 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
305 // (add OP, SETB) -> (adc OP, 0)
306 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
307 (ADC8ri GR8:$op, 0)>;
308 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
309 (ADC32ri8 GR32:$op, 0)>;
310 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
311 (ADC64ri8 GR64:$op, 0)>;
313 // (sub OP, SETB) -> (sbb OP, 0)
314 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
315 (SBB8ri GR8:$op, 0)>;
316 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
317 (SBB32ri8 GR32:$op, 0)>;
318 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
319 (SBB64ri8 GR64:$op, 0)>;
321 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
322 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
323 (ADC8ri GR8:$op, 0)>;
324 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
325 (ADC32ri8 GR32:$op, 0)>;
326 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
327 (ADC64ri8 GR64:$op, 0)>;
329 //===----------------------------------------------------------------------===//
330 // String Pseudo Instructions
332 let SchedRW = [WriteMicrocoded] in {
333 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
334 def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
335 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
336 Requires<[Not64BitMode]>;
337 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
338 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
339 Requires<[Not64BitMode]>;
340 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
341 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
342 Requires<[Not64BitMode]>;
345 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
346 def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
347 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
348 Requires<[In64BitMode]>;
349 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
350 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
351 Requires<[In64BitMode]>;
352 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
353 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
354 Requires<[In64BitMode]>;
355 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
356 [(X86rep_movs i64)], IIC_REP_MOVS>, REP,
357 Requires<[In64BitMode]>;
360 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
361 let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
362 let Uses = [AL,ECX,EDI] in
363 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
364 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
365 Requires<[Not64BitMode]>;
366 let Uses = [AX,ECX,EDI] in
367 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
368 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
369 Requires<[Not64BitMode]>;
370 let Uses = [EAX,ECX,EDI] in
371 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
372 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
373 Requires<[Not64BitMode]>;
376 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
377 let Uses = [AL,RCX,RDI] in
378 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
379 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
380 Requires<[In64BitMode]>;
381 let Uses = [AX,RCX,RDI] in
382 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
383 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
384 Requires<[In64BitMode]>;
385 let Uses = [RAX,RCX,RDI] in
386 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
387 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
388 Requires<[In64BitMode]>;
390 let Uses = [RAX,RCX,RDI] in
391 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
392 [(X86rep_stos i64)], IIC_REP_STOS>, REP,
393 Requires<[In64BitMode]>;
397 //===----------------------------------------------------------------------===//
398 // Thread Local Storage Instructions
402 // All calls clobber the non-callee saved registers. ESP is marked as
403 // a use to prevent stack-pointer assignments that appear immediately
404 // before calls from potentially appearing dead.
405 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
406 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
407 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
408 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
409 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
411 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
413 [(X86tlsaddr tls32addr:$sym)]>,
414 Requires<[Not64BitMode]>;
415 def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
417 [(X86tlsbaseaddr tls32baseaddr:$sym)]>,
418 Requires<[Not64BitMode]>;
421 // All calls clobber the non-callee saved registers. RSP is marked as
422 // a use to prevent stack-pointer assignments that appear immediately
423 // before calls from potentially appearing dead.
424 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
425 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
426 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
427 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
428 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
429 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
431 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
433 [(X86tlsaddr tls64addr:$sym)]>,
434 Requires<[In64BitMode]>;
435 def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
437 [(X86tlsbaseaddr tls64baseaddr:$sym)]>,
438 Requires<[In64BitMode]>;
441 // Darwin TLS Support
442 // For i386, the address of the thunk is passed on the stack, on return the
443 // address of the variable is in %eax. %ecx is trashed during the function
444 // call. All other registers are preserved.
445 let Defs = [EAX, ECX, EFLAGS],
447 usesCustomInserter = 1 in
448 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
450 [(X86TLSCall addr:$sym)]>,
451 Requires<[Not64BitMode]>;
453 // For x86_64, the address of the thunk is passed in %rdi, on return
454 // the address of the variable is in %rax. All other registers are preserved.
455 let Defs = [RAX, EFLAGS],
457 usesCustomInserter = 1 in
458 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
460 [(X86TLSCall addr:$sym)]>,
461 Requires<[In64BitMode]>;
464 //===----------------------------------------------------------------------===//
465 // Conditional Move Pseudo Instructions
467 // CMOV* - Used to implement the SELECT DAG operation. Expanded after
468 // instruction selection into a branch sequence.
469 multiclass CMOVrr_PSEUDO<RegisterClass RC, ValueType VT> {
470 def CMOV#NAME : I<0, Pseudo,
471 (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond),
472 "#CMOV_"#NAME#" PSEUDO!",
473 [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, imm:$cond,
477 let usesCustomInserter = 1, Uses = [EFLAGS] in {
478 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
479 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
480 // however that requires promoting the operands, and can induce additional
481 // i8 register pressure.
482 defm _GR8 : CMOVrr_PSEUDO<GR8, i8>;
484 let Predicates = [NoCMov] in {
485 defm _GR32 : CMOVrr_PSEUDO<GR32, i32>;
486 defm _GR16 : CMOVrr_PSEUDO<GR16, i16>;
487 } // Predicates = [NoCMov]
489 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
491 let Predicates = [FPStackf32] in
492 defm _RFP32 : CMOVrr_PSEUDO<RFP32, f32>;
494 let Predicates = [FPStackf64] in
495 defm _RFP64 : CMOVrr_PSEUDO<RFP64, f64>;
497 defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>;
499 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>;
500 defm _FR64 : CMOVrr_PSEUDO<FR64, f64>;
501 defm _V4F32 : CMOVrr_PSEUDO<VR128, v4f32>;
502 defm _V2F64 : CMOVrr_PSEUDO<VR128, v2f64>;
503 defm _V2I64 : CMOVrr_PSEUDO<VR128, v2i64>;
504 defm _V8F32 : CMOVrr_PSEUDO<VR256, v8f32>;
505 defm _V4F64 : CMOVrr_PSEUDO<VR256, v4f64>;
506 defm _V4I64 : CMOVrr_PSEUDO<VR256, v4i64>;
507 defm _V8I64 : CMOVrr_PSEUDO<VR512, v8i64>;
508 defm _V8F64 : CMOVrr_PSEUDO<VR512, v8f64>;
509 defm _V16F32 : CMOVrr_PSEUDO<VR512, v16f32>;
510 defm _V8I1 : CMOVrr_PSEUDO<VK8, v8i1>;
511 defm _V16I1 : CMOVrr_PSEUDO<VK16, v16i1>;
512 defm _V32I1 : CMOVrr_PSEUDO<VK32, v32i1>;
513 defm _V64I1 : CMOVrr_PSEUDO<VK64, v64i1>;
514 } // usesCustomInserter = 1, Uses = [EFLAGS]
516 //===----------------------------------------------------------------------===//
517 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
518 //===----------------------------------------------------------------------===//
520 // FIXME: Use normal instructions and add lock prefix dynamically.
524 // TODO: Get this to fold the constant into the instruction.
525 let isCodeGenOnly = 1, Defs = [EFLAGS] in
526 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
527 "or{l}\t{$zero, $dst|$dst, $zero}",
528 [], IIC_ALU_MEM>, Requires<[Not64BitMode]>, LOCK,
529 Sched<[WriteALULd, WriteRMW]>;
531 let hasSideEffects = 1 in
532 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
534 [(X86MemBarrier)]>, Sched<[WriteLoad]>;
536 // RegOpc corresponds to the mr version of the instruction
537 // ImmOpc corresponds to the mi version of the instruction
538 // ImmOpc8 corresponds to the mi8 version of the instruction
539 // ImmMod corresponds to the instruction format of the mi and mi8 versions
540 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
541 Format ImmMod, string mnemonic> {
542 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
543 SchedRW = [WriteALULd, WriteRMW] in {
545 def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
546 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
547 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
548 !strconcat(mnemonic, "{b}\t",
549 "{$src2, $dst|$dst, $src2}"),
550 [], IIC_ALU_NONMEM>, LOCK;
551 def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
552 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
553 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
554 !strconcat(mnemonic, "{w}\t",
555 "{$src2, $dst|$dst, $src2}"),
556 [], IIC_ALU_NONMEM>, OpSize16, LOCK;
557 def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
558 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
559 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
560 !strconcat(mnemonic, "{l}\t",
561 "{$src2, $dst|$dst, $src2}"),
562 [], IIC_ALU_NONMEM>, OpSize32, LOCK;
563 def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
564 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
565 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
566 !strconcat(mnemonic, "{q}\t",
567 "{$src2, $dst|$dst, $src2}"),
568 [], IIC_ALU_NONMEM>, LOCK;
570 def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
571 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
572 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
573 !strconcat(mnemonic, "{b}\t",
574 "{$src2, $dst|$dst, $src2}"),
575 [], IIC_ALU_MEM>, LOCK;
577 def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
578 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
579 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
580 !strconcat(mnemonic, "{w}\t",
581 "{$src2, $dst|$dst, $src2}"),
582 [], IIC_ALU_MEM>, OpSize16, LOCK;
584 def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
585 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
586 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
587 !strconcat(mnemonic, "{l}\t",
588 "{$src2, $dst|$dst, $src2}"),
589 [], IIC_ALU_MEM>, OpSize32, LOCK;
591 def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
592 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
593 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
594 !strconcat(mnemonic, "{q}\t",
595 "{$src2, $dst|$dst, $src2}"),
596 [], IIC_ALU_MEM>, LOCK;
598 def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
599 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
600 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
601 !strconcat(mnemonic, "{w}\t",
602 "{$src2, $dst|$dst, $src2}"),
603 [], IIC_ALU_MEM>, OpSize16, LOCK;
604 def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
605 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
606 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
607 !strconcat(mnemonic, "{l}\t",
608 "{$src2, $dst|$dst, $src2}"),
609 [], IIC_ALU_MEM>, OpSize32, LOCK;
610 def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
611 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
612 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
613 !strconcat(mnemonic, "{q}\t",
614 "{$src2, $dst|$dst, $src2}"),
615 [], IIC_ALU_MEM>, LOCK;
621 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">;
622 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
623 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">;
624 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, "and">;
625 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, "xor">;
627 // Optimized codegen when the non-memory output is not used.
628 multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,
630 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
631 SchedRW = [WriteALULd, WriteRMW] in {
633 def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
634 !strconcat(mnemonic, "{b}\t$dst"),
635 [], IIC_UNARY_MEM>, LOCK;
636 def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
637 !strconcat(mnemonic, "{w}\t$dst"),
638 [], IIC_UNARY_MEM>, OpSize16, LOCK;
639 def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
640 !strconcat(mnemonic, "{l}\t$dst"),
641 [], IIC_UNARY_MEM>, OpSize32, LOCK;
642 def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
643 !strconcat(mnemonic, "{q}\t$dst"),
644 [], IIC_UNARY_MEM>, LOCK;
648 defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "inc">;
649 defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "dec">;
651 // Atomic compare and swap.
652 multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,
653 SDPatternOperator frag, X86MemOperand x86memop,
654 InstrItinClass itin> {
655 let isCodeGenOnly = 1 in {
656 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr),
657 !strconcat(mnemonic, "\t$ptr"),
658 [(frag addr:$ptr)], itin>, TB, LOCK;
662 multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
663 string mnemonic, SDPatternOperator frag,
664 InstrItinClass itin8, InstrItinClass itin> {
665 let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
666 let Defs = [AL, EFLAGS], Uses = [AL] in
667 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
668 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"),
669 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK;
670 let Defs = [AX, EFLAGS], Uses = [AX] in
671 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
672 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
673 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK;
674 let Defs = [EAX, EFLAGS], Uses = [EAX] in
675 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
676 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
677 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK;
678 let Defs = [RAX, EFLAGS], Uses = [RAX] in
679 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
680 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
681 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK;
685 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
686 SchedRW = [WriteALULd, WriteRMW] in {
687 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",
692 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
693 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in {
694 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
696 IIC_CMPX_LOCK_16B>, REX_W;
699 defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg",
700 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>;
702 // Atomic exchange and add
703 multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
705 InstrItinClass itin8, InstrItinClass itin> {
706 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1,
707 SchedRW = [WriteALULd, WriteRMW] in {
708 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),
709 (ins GR8:$val, i8mem:$ptr),
710 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
712 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
714 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
715 (ins GR16:$val, i16mem:$ptr),
716 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
719 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
721 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
722 (ins GR32:$val, i32mem:$ptr),
723 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
726 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
728 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
729 (ins GR64:$val, i64mem:$ptr),
730 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
733 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
738 defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",
739 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>,
742 /* The following multiclass tries to make sure that in code like
743 * x.store (immediate op x.load(acquire), release)
745 * x.store (register op x.load(acquire), release)
746 * an operation directly on memory is generated instead of wasting a register.
747 * It is not automatic as atomic_store/load are only lowered to MOV instructions
748 * extremely late to prevent them from being accidentally reordered in the backend
749 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions)
751 multiclass RELEASE_BINOP_MI<SDNode op> {
752 def NAME#8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
753 "#BINOP "#NAME#"8mi PSEUDO!",
754 [(atomic_store_8 addr:$dst, (op
755 (atomic_load_8 addr:$dst), (i8 imm:$src)))]>;
756 def NAME#8mr : I<0, Pseudo, (outs), (ins i8mem:$dst, GR8:$src),
757 "#BINOP "#NAME#"8mr PSEUDO!",
758 [(atomic_store_8 addr:$dst, (op
759 (atomic_load_8 addr:$dst), GR8:$src))]>;
760 // NAME#16 is not generated as 16-bit arithmetic instructions are considered
761 // costly and avoided as far as possible by this backend anyway
762 def NAME#32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
763 "#BINOP "#NAME#"32mi PSEUDO!",
764 [(atomic_store_32 addr:$dst, (op
765 (atomic_load_32 addr:$dst), (i32 imm:$src)))]>;
766 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
767 "#BINOP "#NAME#"32mr PSEUDO!",
768 [(atomic_store_32 addr:$dst, (op
769 (atomic_load_32 addr:$dst), GR32:$src))]>;
770 def NAME#64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
771 "#BINOP "#NAME#"64mi32 PSEUDO!",
772 [(atomic_store_64 addr:$dst, (op
773 (atomic_load_64 addr:$dst), (i64immSExt32:$src)))]>;
774 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
775 "#BINOP "#NAME#"64mr PSEUDO!",
776 [(atomic_store_64 addr:$dst, (op
777 (atomic_load_64 addr:$dst), GR64:$src))]>;
779 defm RELEASE_ADD : RELEASE_BINOP_MI<add>;
780 defm RELEASE_AND : RELEASE_BINOP_MI<and>;
781 defm RELEASE_OR : RELEASE_BINOP_MI<or>;
782 defm RELEASE_XOR : RELEASE_BINOP_MI<xor>;
783 // Note: we don't deal with sub, because substractions of constants are
784 // optimized into additions before this code can run
786 // Same as above, but for floating-point.
787 // FIXME: imm version.
788 // FIXME: Version that doesn't clobber $src, using AVX's VADDSS.
789 // FIXME: This could also handle SIMD operations with *ps and *pd instructions.
790 let usesCustomInserter = 1 in {
791 multiclass RELEASE_FP_BINOP_MI<SDNode op> {
792 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, FR32:$src),
793 "#BINOP "#NAME#"32mr PSEUDO!",
794 [(atomic_store_32 addr:$dst,
796 (f32 (bitconvert (i32 (atomic_load_32 addr:$dst)))),
797 FR32:$src))))]>, Requires<[HasSSE1]>;
798 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, FR64:$src),
799 "#BINOP "#NAME#"64mr PSEUDO!",
800 [(atomic_store_64 addr:$dst,
802 (f64 (bitconvert (i64 (atomic_load_64 addr:$dst)))),
803 FR64:$src))))]>, Requires<[HasSSE2]>;
805 defm RELEASE_FADD : RELEASE_FP_BINOP_MI<fadd>;
806 // FIXME: Add fsub, fmul, fdiv, ...
809 multiclass RELEASE_UNOP<dag dag8, dag dag16, dag dag32, dag dag64> {
810 def NAME#8m : I<0, Pseudo, (outs), (ins i8mem:$dst),
811 "#UNOP "#NAME#"8m PSEUDO!",
812 [(atomic_store_8 addr:$dst, dag8)]>;
813 def NAME#16m : I<0, Pseudo, (outs), (ins i16mem:$dst),
814 "#UNOP "#NAME#"16m PSEUDO!",
815 [(atomic_store_16 addr:$dst, dag16)]>;
816 def NAME#32m : I<0, Pseudo, (outs), (ins i32mem:$dst),
817 "#UNOP "#NAME#"32m PSEUDO!",
818 [(atomic_store_32 addr:$dst, dag32)]>;
819 def NAME#64m : I<0, Pseudo, (outs), (ins i64mem:$dst),
820 "#UNOP "#NAME#"64m PSEUDO!",
821 [(atomic_store_64 addr:$dst, dag64)]>;
824 defm RELEASE_INC : RELEASE_UNOP<
825 (add (atomic_load_8 addr:$dst), (i8 1)),
826 (add (atomic_load_16 addr:$dst), (i16 1)),
827 (add (atomic_load_32 addr:$dst), (i32 1)),
828 (add (atomic_load_64 addr:$dst), (i64 1))>, Requires<[NotSlowIncDec]>;
829 defm RELEASE_DEC : RELEASE_UNOP<
830 (add (atomic_load_8 addr:$dst), (i8 -1)),
831 (add (atomic_load_16 addr:$dst), (i16 -1)),
832 (add (atomic_load_32 addr:$dst), (i32 -1)),
833 (add (atomic_load_64 addr:$dst), (i64 -1))>, Requires<[NotSlowIncDec]>;
835 TODO: These don't work because the type inference of TableGen fails.
836 TODO: find a way to fix it.
837 defm RELEASE_NEG : RELEASE_UNOP<
838 (ineg (atomic_load_8 addr:$dst)),
839 (ineg (atomic_load_16 addr:$dst)),
840 (ineg (atomic_load_32 addr:$dst)),
841 (ineg (atomic_load_64 addr:$dst))>;
842 defm RELEASE_NOT : RELEASE_UNOP<
843 (not (atomic_load_8 addr:$dst)),
844 (not (atomic_load_16 addr:$dst)),
845 (not (atomic_load_32 addr:$dst)),
846 (not (atomic_load_64 addr:$dst))>;
849 def RELEASE_MOV8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
850 "#RELEASE_MOV8mi PSEUDO!",
851 [(atomic_store_8 addr:$dst, (i8 imm:$src))]>;
852 def RELEASE_MOV16mi : I<0, Pseudo, (outs), (ins i16mem:$dst, i16imm:$src),
853 "#RELEASE_MOV16mi PSEUDO!",
854 [(atomic_store_16 addr:$dst, (i16 imm:$src))]>;
855 def RELEASE_MOV32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
856 "#RELEASE_MOV32mi PSEUDO!",
857 [(atomic_store_32 addr:$dst, (i32 imm:$src))]>;
858 def RELEASE_MOV64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
859 "#RELEASE_MOV64mi32 PSEUDO!",
860 [(atomic_store_64 addr:$dst, i64immSExt32:$src)]>;
862 def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
863 "#RELEASE_MOV8mr PSEUDO!",
864 [(atomic_store_8 addr:$dst, GR8 :$src)]>;
865 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
866 "#RELEASE_MOV16mr PSEUDO!",
867 [(atomic_store_16 addr:$dst, GR16:$src)]>;
868 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
869 "#RELEASE_MOV32mr PSEUDO!",
870 [(atomic_store_32 addr:$dst, GR32:$src)]>;
871 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
872 "#RELEASE_MOV64mr PSEUDO!",
873 [(atomic_store_64 addr:$dst, GR64:$src)]>;
875 def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
876 "#ACQUIRE_MOV8rm PSEUDO!",
877 [(set GR8:$dst, (atomic_load_8 addr:$src))]>;
878 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
879 "#ACQUIRE_MOV16rm PSEUDO!",
880 [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
881 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
882 "#ACQUIRE_MOV32rm PSEUDO!",
883 [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
884 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
885 "#ACQUIRE_MOV64rm PSEUDO!",
886 [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
888 //===----------------------------------------------------------------------===//
889 // DAG Pattern Matching Rules
890 //===----------------------------------------------------------------------===//
892 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
893 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
894 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
895 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
896 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
897 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
898 def : Pat<(i32 (X86Wrapper mcsym:$dst)), (MOV32ri mcsym:$dst)>;
899 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
901 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
902 (ADD32ri GR32:$src1, tconstpool:$src2)>;
903 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
904 (ADD32ri GR32:$src1, tjumptable:$src2)>;
905 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
906 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
907 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
908 (ADD32ri GR32:$src1, texternalsym:$src2)>;
909 def : Pat<(add GR32:$src1, (X86Wrapper mcsym:$src2)),
910 (ADD32ri GR32:$src1, mcsym:$src2)>;
911 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
912 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
914 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
915 (MOV32mi addr:$dst, tglobaladdr:$src)>;
916 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
917 (MOV32mi addr:$dst, texternalsym:$src)>;
918 def : Pat<(store (i32 (X86Wrapper mcsym:$src)), addr:$dst),
919 (MOV32mi addr:$dst, mcsym:$src)>;
920 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
921 (MOV32mi addr:$dst, tblockaddress:$src)>;
923 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
924 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
925 // 'movabs' predicate should handle this sort of thing.
926 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
927 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
928 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
929 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
930 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
931 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
932 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
933 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
934 def : Pat<(i64 (X86Wrapper mcsym:$dst)),
935 (MOV64ri mcsym:$dst)>, Requires<[FarData]>;
936 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
937 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
939 // In kernel code model, we can get the address of a label
940 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
941 // the MOV64ri32 should accept these.
942 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
943 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
944 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
945 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
946 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
947 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
948 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
949 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
950 def : Pat<(i64 (X86Wrapper mcsym:$dst)),
951 (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>;
952 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
953 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
955 // If we have small model and -static mode, it is safe to store global addresses
956 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
957 // for MOV64mi32 should handle this sort of thing.
958 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
959 (MOV64mi32 addr:$dst, tconstpool:$src)>,
960 Requires<[NearData, IsStatic]>;
961 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
962 (MOV64mi32 addr:$dst, tjumptable:$src)>,
963 Requires<[NearData, IsStatic]>;
964 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
965 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
966 Requires<[NearData, IsStatic]>;
967 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
968 (MOV64mi32 addr:$dst, texternalsym:$src)>,
969 Requires<[NearData, IsStatic]>;
970 def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst),
971 (MOV64mi32 addr:$dst, mcsym:$src)>,
972 Requires<[NearData, IsStatic]>;
973 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
974 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
975 Requires<[NearData, IsStatic]>;
977 def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>;
978 def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>;
982 // tls has some funny stuff here...
983 // This corresponds to movabs $foo@tpoff, %rax
984 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
985 (MOV64ri32 tglobaltlsaddr :$dst)>;
986 // This corresponds to add $foo@tpoff, %rax
987 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
988 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
991 // Direct PC relative function call for small code model. 32-bit displacement
992 // sign extended to 64-bit.
993 def : Pat<(X86call (i64 tglobaladdr:$dst)),
994 (CALL64pcrel32 tglobaladdr:$dst)>;
995 def : Pat<(X86call (i64 texternalsym:$dst)),
996 (CALL64pcrel32 texternalsym:$dst)>;
998 // Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
999 // can never use callee-saved registers. That is the purpose of the GR64_TC
1000 // register classes.
1002 // The only volatile register that is never used by the calling convention is
1003 // %r11. This happens when calling a vararg function with 6 arguments.
1005 // Match an X86tcret that uses less than 7 volatile registers.
1006 def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
1007 (X86tcret node:$ptr, node:$off), [{
1008 // X86tcret args: (*chain, ptr, imm, regs..., glue)
1009 unsigned NumRegs = 0;
1010 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
1011 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
1016 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1017 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>,
1018 Requires<[Not64BitMode]>;
1020 // FIXME: This is disabled for 32-bit PIC mode because the global base
1021 // register which is part of the address mode may be assigned a
1022 // callee-saved register.
1023 def : Pat<(X86tcret (load addr:$dst), imm:$off),
1024 (TCRETURNmi addr:$dst, imm:$off)>,
1025 Requires<[Not64BitMode, IsNotPIC]>;
1027 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
1028 (TCRETURNdi tglobaladdr:$dst, imm:$off)>,
1029 Requires<[NotLP64]>;
1031 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
1032 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1033 Requires<[NotLP64]>;
1035 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1036 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
1037 Requires<[In64BitMode]>;
1039 // Don't fold loads into X86tcret requiring more than 6 regs.
1040 // There wouldn't be enough scratch registers for base+index.
1041 def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
1042 (TCRETURNmi64 addr:$dst, imm:$off)>,
1043 Requires<[In64BitMode]>;
1045 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1046 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
1049 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1050 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1053 // Normal calls, with various flavors of addresses.
1054 def : Pat<(X86call (i32 tglobaladdr:$dst)),
1055 (CALLpcrel32 tglobaladdr:$dst)>;
1056 def : Pat<(X86call (i32 texternalsym:$dst)),
1057 (CALLpcrel32 texternalsym:$dst)>;
1058 def : Pat<(X86call (i32 imm:$dst)),
1059 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
1063 // TEST R,R is smaller than CMP R,0
1064 def : Pat<(X86cmp GR8:$src1, 0),
1065 (TEST8rr GR8:$src1, GR8:$src1)>;
1066 def : Pat<(X86cmp GR16:$src1, 0),
1067 (TEST16rr GR16:$src1, GR16:$src1)>;
1068 def : Pat<(X86cmp GR32:$src1, 0),
1069 (TEST32rr GR32:$src1, GR32:$src1)>;
1070 def : Pat<(X86cmp GR64:$src1, 0),
1071 (TEST64rr GR64:$src1, GR64:$src1)>;
1073 // Conditional moves with folded loads with operands swapped and conditions
1075 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
1076 Instruction Inst64> {
1077 let Predicates = [HasCMov] in {
1078 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
1079 (Inst16 GR16:$src2, addr:$src1)>;
1080 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
1081 (Inst32 GR32:$src2, addr:$src1)>;
1082 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
1083 (Inst64 GR64:$src2, addr:$src1)>;
1087 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
1088 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
1089 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
1090 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
1091 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
1092 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
1093 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
1094 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
1095 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
1096 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1097 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1098 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1099 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1100 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1101 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1102 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1104 // zextload bool -> zextload byte
1105 def : Pat<(zextloadi8i1 addr:$src), (AND8ri (MOV8rm addr:$src), (i8 1))>;
1106 def : Pat<(zextloadi16i1 addr:$src), (AND16ri8 (MOVZX16rm8 addr:$src), (i16 1))>;
1107 def : Pat<(zextloadi32i1 addr:$src), (AND32ri8 (MOVZX32rm8 addr:$src), (i32 1))>;
1108 def : Pat<(zextloadi64i1 addr:$src),
1109 (SUBREG_TO_REG (i64 0),
1110 (AND32ri8 (MOVZX32rm8 addr:$src), (i32 1)), sub_32bit)>;
1112 // extload bool -> extload byte
1113 // When extloading from 16-bit and smaller memory locations into 64-bit
1114 // registers, use zero-extending loads so that the entire 64-bit register is
1115 // defined, avoiding partial-register updates.
1117 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1118 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1119 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1120 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1121 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1122 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1124 // For other extloads, use subregs, since the high contents of the register are
1125 // defined after an extload.
1126 def : Pat<(extloadi64i1 addr:$src),
1127 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1128 def : Pat<(extloadi64i8 addr:$src),
1129 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1130 def : Pat<(extloadi64i16 addr:$src),
1131 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1132 def : Pat<(extloadi64i32 addr:$src),
1133 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1135 // anyext. Define these to do an explicit zero-extend to
1136 // avoid partial-register updates.
1137 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1138 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1139 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1141 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1142 def : Pat<(i32 (anyext GR16:$src)),
1143 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1145 def : Pat<(i64 (anyext GR8 :$src)),
1146 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1147 def : Pat<(i64 (anyext GR16:$src)),
1148 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
1149 def : Pat<(i64 (anyext GR32:$src)),
1150 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1153 // Any instruction that defines a 32-bit result leaves the high half of the
1154 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1155 // be copying from a truncate. And x86's cmov doesn't do anything if the
1156 // condition is false. But any other 32-bit operation will zero-extend
1158 def def32 : PatLeaf<(i32 GR32:$src), [{
1159 return N->getOpcode() != ISD::TRUNCATE &&
1160 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1161 N->getOpcode() != ISD::CopyFromReg &&
1162 N->getOpcode() != ISD::AssertSext &&
1163 N->getOpcode() != X86ISD::CMOV;
1166 // In the case of a 32-bit def that is known to implicitly zero-extend,
1167 // we can use a SUBREG_TO_REG.
1168 def : Pat<(i64 (zext def32:$src)),
1169 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1171 //===----------------------------------------------------------------------===//
1172 // Pattern match OR as ADD
1173 //===----------------------------------------------------------------------===//
1175 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1176 // 3-addressified into an LEA instruction to avoid copies. However, we also
1177 // want to finally emit these instructions as an or at the end of the code
1178 // generator to make the generated code easier to read. To do this, we select
1179 // into "disjoint bits" pseudo ops.
1181 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1182 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1183 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1184 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1186 APInt KnownZero0, KnownOne0;
1187 CurDAG->computeKnownBits(N->getOperand(0), KnownZero0, KnownOne0, 0);
1188 APInt KnownZero1, KnownOne1;
1189 CurDAG->computeKnownBits(N->getOperand(1), KnownZero1, KnownOne1, 0);
1190 return (~KnownZero0 & ~KnownZero1) == 0;
1194 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1195 // Try this before the selecting to OR.
1196 let AddedComplexity = 5, SchedRW = [WriteALU] in {
1198 let isConvertibleToThreeAddress = 1,
1199 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1200 let isCommutable = 1 in {
1201 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1202 "", // orw/addw REG, REG
1203 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1204 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1205 "", // orl/addl REG, REG
1206 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1207 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1208 "", // orq/addq REG, REG
1209 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1212 // NOTE: These are order specific, we want the ri8 forms to be listed
1213 // first so that they are slightly preferred to the ri forms.
1215 def ADD16ri8_DB : I<0, Pseudo,
1216 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1217 "", // orw/addw REG, imm8
1218 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1219 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1220 "", // orw/addw REG, imm
1221 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1223 def ADD32ri8_DB : I<0, Pseudo,
1224 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1225 "", // orl/addl REG, imm8
1226 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1227 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1228 "", // orl/addl REG, imm
1229 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1232 def ADD64ri8_DB : I<0, Pseudo,
1233 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1234 "", // orq/addq REG, imm8
1235 [(set GR64:$dst, (or_is_add GR64:$src1,
1236 i64immSExt8:$src2))]>;
1237 def ADD64ri32_DB : I<0, Pseudo,
1238 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1239 "", // orq/addq REG, imm
1240 [(set GR64:$dst, (or_is_add GR64:$src1,
1241 i64immSExt32:$src2))]>;
1243 } // AddedComplexity, SchedRW
1246 //===----------------------------------------------------------------------===//
1248 //===----------------------------------------------------------------------===//
1250 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1251 // +128 doesn't, so in this special case use a sub instead of an add.
1252 def : Pat<(add GR16:$src1, 128),
1253 (SUB16ri8 GR16:$src1, -128)>;
1254 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1255 (SUB16mi8 addr:$dst, -128)>;
1257 def : Pat<(add GR32:$src1, 128),
1258 (SUB32ri8 GR32:$src1, -128)>;
1259 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1260 (SUB32mi8 addr:$dst, -128)>;
1262 def : Pat<(add GR64:$src1, 128),
1263 (SUB64ri8 GR64:$src1, -128)>;
1264 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1265 (SUB64mi8 addr:$dst, -128)>;
1267 // The same trick applies for 32-bit immediate fields in 64-bit
1269 def : Pat<(add GR64:$src1, 0x0000000080000000),
1270 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1271 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1272 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1274 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1275 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1276 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1277 // represented with a sign extension of a 8 bit constant, use that.
1278 // This can also reduce instruction size by eliminating the need for the REX
1281 // AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32.
1282 let AddedComplexity = 1 in {
1283 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1287 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1288 (i32 (GetLo8XForm imm:$imm))),
1291 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1295 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1296 (i32 (GetLo32XForm imm:$imm))),
1298 } // AddedComplexity = 1
1301 // AddedComplexity is needed due to the increased complexity on the
1302 // i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all
1303 // the MOVZX patterns keeps thems together in DAGIsel tables.
1304 let AddedComplexity = 1 in {
1305 // r & (2^16-1) ==> movz
1306 def : Pat<(and GR32:$src1, 0xffff),
1307 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1308 // r & (2^8-1) ==> movz
1309 def : Pat<(and GR32:$src1, 0xff),
1310 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1313 Requires<[Not64BitMode]>;
1314 // r & (2^8-1) ==> movz
1315 def : Pat<(and GR16:$src1, 0xff),
1316 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1317 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1319 Requires<[Not64BitMode]>;
1321 // r & (2^32-1) ==> movz
1322 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1323 (SUBREG_TO_REG (i64 0),
1324 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)),
1326 // r & (2^16-1) ==> movz
1327 let AddedComplexity = 1 in // Give priority over i64immZExt32.
1328 def : Pat<(and GR64:$src, 0xffff),
1329 (SUBREG_TO_REG (i64 0),
1330 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))),
1332 // r & (2^8-1) ==> movz
1333 def : Pat<(and GR64:$src, 0xff),
1334 (SUBREG_TO_REG (i64 0),
1335 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))),
1337 // r & (2^8-1) ==> movz
1338 def : Pat<(and GR32:$src1, 0xff),
1339 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>,
1340 Requires<[In64BitMode]>;
1341 // r & (2^8-1) ==> movz
1342 def : Pat<(and GR16:$src1, 0xff),
1343 (EXTRACT_SUBREG (MOVZX32rr8 (i8
1344 (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>,
1345 Requires<[In64BitMode]>;
1346 } // AddedComplexity = 1
1349 // sext_inreg patterns
1350 def : Pat<(sext_inreg GR32:$src, i16),
1351 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1352 def : Pat<(sext_inreg GR32:$src, i8),
1353 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1356 Requires<[Not64BitMode]>;
1358 def : Pat<(sext_inreg GR16:$src, i8),
1359 (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG
1360 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1362 Requires<[Not64BitMode]>;
1364 def : Pat<(sext_inreg GR64:$src, i32),
1365 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1366 def : Pat<(sext_inreg GR64:$src, i16),
1367 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1368 def : Pat<(sext_inreg GR64:$src, i8),
1369 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1370 def : Pat<(sext_inreg GR32:$src, i8),
1371 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>,
1372 Requires<[In64BitMode]>;
1373 def : Pat<(sext_inreg GR16:$src, i8),
1374 (EXTRACT_SUBREG (MOVSX32rr8
1375 (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>,
1376 Requires<[In64BitMode]>;
1378 // sext, sext_load, zext, zext_load
1379 def: Pat<(i16 (sext GR8:$src)),
1380 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1381 def: Pat<(sextloadi16i8 addr:$src),
1382 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1383 def: Pat<(i16 (zext GR8:$src)),
1384 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1385 def: Pat<(zextloadi16i8 addr:$src),
1386 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1389 def : Pat<(i16 (trunc GR32:$src)),
1390 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1391 def : Pat<(i8 (trunc GR32:$src)),
1392 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1394 Requires<[Not64BitMode]>;
1395 def : Pat<(i8 (trunc GR16:$src)),
1396 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1398 Requires<[Not64BitMode]>;
1399 def : Pat<(i32 (trunc GR64:$src)),
1400 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1401 def : Pat<(i16 (trunc GR64:$src)),
1402 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1403 def : Pat<(i8 (trunc GR64:$src)),
1404 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1405 def : Pat<(i8 (trunc GR32:$src)),
1406 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1407 Requires<[In64BitMode]>;
1408 def : Pat<(i8 (trunc GR16:$src)),
1409 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1410 Requires<[In64BitMode]>;
1412 // h-register tricks
1413 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1414 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1416 Requires<[Not64BitMode]>;
1417 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1418 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1420 Requires<[Not64BitMode]>;
1421 def : Pat<(srl GR16:$src, (i8 8)),
1424 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1427 Requires<[Not64BitMode]>;
1428 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1429 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1432 Requires<[Not64BitMode]>;
1433 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1434 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
1437 Requires<[Not64BitMode]>;
1438 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1439 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1442 Requires<[Not64BitMode]>;
1443 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1444 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1447 Requires<[Not64BitMode]>;
1449 // h-register tricks.
1450 // For now, be conservative on x86-64 and use an h-register extract only if the
1451 // value is immediately zero-extended or stored, which are somewhat common
1452 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1453 // from being allocated in the same instruction as the h register, as there's
1454 // currently no way to describe this requirement to the register allocator.
1456 // h-register extract and zero-extend.
1457 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1461 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1464 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1466 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1468 Requires<[In64BitMode]>;
1469 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1470 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1473 Requires<[In64BitMode]>;
1474 def : Pat<(srl GR16:$src, (i8 8)),
1477 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1480 Requires<[In64BitMode]>;
1481 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1483 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1485 Requires<[In64BitMode]>;
1486 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1488 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1490 Requires<[In64BitMode]>;
1491 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1495 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1498 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1502 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1506 // h-register extract and store.
1507 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1510 (EXTRACT_SUBREG (i64 (COPY_TO_REGCLASS GR64:$src, GR64_ABCD)),
1512 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1515 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1517 Requires<[In64BitMode]>;
1518 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1521 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1523 Requires<[In64BitMode]>;
1526 // (shl x, 1) ==> (add x, x)
1527 // Note that if x is undef (immediate or otherwise), we could theoretically
1528 // end up with the two uses of x getting different values, producing a result
1529 // where the least significant bit is not 0. However, the probability of this
1530 // happening is considered low enough that this is officially not a
1532 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1533 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1534 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1535 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1537 // Helper imms that check if a mask doesn't change significant shift bits.
1538 def immShift32 : ImmLeaf<i8, [{
1539 return countTrailingOnes<uint64_t>(Imm) >= 5;
1541 def immShift64 : ImmLeaf<i8, [{
1542 return countTrailingOnes<uint64_t>(Imm) >= 6;
1545 // Shift amount is implicitly masked.
1546 multiclass MaskedShiftAmountPats<SDNode frag, string name> {
1547 // (shift x (and y, 31)) ==> (shift x, y)
1548 def : Pat<(frag GR8:$src1, (and CL, immShift32)),
1549 (!cast<Instruction>(name # "8rCL") GR8:$src1)>;
1550 def : Pat<(frag GR16:$src1, (and CL, immShift32)),
1551 (!cast<Instruction>(name # "16rCL") GR16:$src1)>;
1552 def : Pat<(frag GR32:$src1, (and CL, immShift32)),
1553 (!cast<Instruction>(name # "32rCL") GR32:$src1)>;
1554 def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1555 (!cast<Instruction>(name # "8mCL") addr:$dst)>;
1556 def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1557 (!cast<Instruction>(name # "16mCL") addr:$dst)>;
1558 def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1559 (!cast<Instruction>(name # "32mCL") addr:$dst)>;
1561 // (shift x (and y, 63)) ==> (shift x, y)
1562 def : Pat<(frag GR64:$src1, (and CL, immShift64)),
1563 (!cast<Instruction>(name # "64rCL") GR64:$src1)>;
1564 def : Pat<(store (frag (loadi64 addr:$dst), (and CL, 63)), addr:$dst),
1565 (!cast<Instruction>(name # "64mCL") addr:$dst)>;
1568 defm : MaskedShiftAmountPats<shl, "SHL">;
1569 defm : MaskedShiftAmountPats<srl, "SHR">;
1570 defm : MaskedShiftAmountPats<sra, "SAR">;
1571 defm : MaskedShiftAmountPats<rotl, "ROL">;
1572 defm : MaskedShiftAmountPats<rotr, "ROR">;
1574 // (anyext (setcc_carry)) -> (setcc_carry)
1575 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1577 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1579 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1585 //===----------------------------------------------------------------------===//
1586 // EFLAGS-defining Patterns
1587 //===----------------------------------------------------------------------===//
1590 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1591 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1592 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1595 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1596 (ADD8rm GR8:$src1, addr:$src2)>;
1597 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1598 (ADD16rm GR16:$src1, addr:$src2)>;
1599 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1600 (ADD32rm GR32:$src1, addr:$src2)>;
1603 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1604 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1605 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1606 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1607 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1608 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1609 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1612 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1613 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1614 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1617 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1618 (SUB8rm GR8:$src1, addr:$src2)>;
1619 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1620 (SUB16rm GR16:$src1, addr:$src2)>;
1621 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1622 (SUB32rm GR32:$src1, addr:$src2)>;
1625 def : Pat<(sub GR8:$src1, imm:$src2),
1626 (SUB8ri GR8:$src1, imm:$src2)>;
1627 def : Pat<(sub GR16:$src1, imm:$src2),
1628 (SUB16ri GR16:$src1, imm:$src2)>;
1629 def : Pat<(sub GR32:$src1, imm:$src2),
1630 (SUB32ri GR32:$src1, imm:$src2)>;
1631 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1632 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1633 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1634 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1637 def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>;
1638 def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>;
1639 def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
1640 def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>;
1643 def : Pat<(mul GR16:$src1, GR16:$src2),
1644 (IMUL16rr GR16:$src1, GR16:$src2)>;
1645 def : Pat<(mul GR32:$src1, GR32:$src2),
1646 (IMUL32rr GR32:$src1, GR32:$src2)>;
1649 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1650 (IMUL16rm GR16:$src1, addr:$src2)>;
1651 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1652 (IMUL32rm GR32:$src1, addr:$src2)>;
1655 def : Pat<(mul GR16:$src1, imm:$src2),
1656 (IMUL16rri GR16:$src1, imm:$src2)>;
1657 def : Pat<(mul GR32:$src1, imm:$src2),
1658 (IMUL32rri GR32:$src1, imm:$src2)>;
1659 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1660 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1661 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1662 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1664 // reg = mul mem, imm
1665 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1666 (IMUL16rmi addr:$src1, imm:$src2)>;
1667 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1668 (IMUL32rmi addr:$src1, imm:$src2)>;
1669 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1670 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1671 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1672 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1674 // Patterns for nodes that do not produce flags, for instructions that do.
1677 def : Pat<(add GR64:$src1, GR64:$src2),
1678 (ADD64rr GR64:$src1, GR64:$src2)>;
1679 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1680 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1681 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1682 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1683 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1684 (ADD64rm GR64:$src1, addr:$src2)>;
1687 def : Pat<(sub GR64:$src1, GR64:$src2),
1688 (SUB64rr GR64:$src1, GR64:$src2)>;
1689 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1690 (SUB64rm GR64:$src1, addr:$src2)>;
1691 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1692 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1693 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1694 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1697 def : Pat<(mul GR64:$src1, GR64:$src2),
1698 (IMUL64rr GR64:$src1, GR64:$src2)>;
1699 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1700 (IMUL64rm GR64:$src1, addr:$src2)>;
1701 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1702 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1703 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1704 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1705 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1706 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1707 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1708 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1710 // Increment/Decrement reg.
1711 // Do not make INC/DEC if it is slow
1712 let Predicates = [NotSlowIncDec] in {
1713 def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>;
1714 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>;
1715 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>;
1716 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1717 def : Pat<(add GR8:$src, -1), (DEC8r GR8:$src)>;
1718 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>;
1719 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>;
1720 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1724 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1725 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1726 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1727 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1730 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1731 (OR8rm GR8:$src1, addr:$src2)>;
1732 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1733 (OR16rm GR16:$src1, addr:$src2)>;
1734 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1735 (OR32rm GR32:$src1, addr:$src2)>;
1736 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1737 (OR64rm GR64:$src1, addr:$src2)>;
1740 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1741 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1742 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1743 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1744 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1745 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1746 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1747 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1748 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1749 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1750 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1753 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1754 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1755 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1756 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1759 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1760 (XOR8rm GR8:$src1, addr:$src2)>;
1761 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1762 (XOR16rm GR16:$src1, addr:$src2)>;
1763 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1764 (XOR32rm GR32:$src1, addr:$src2)>;
1765 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1766 (XOR64rm GR64:$src1, addr:$src2)>;
1769 def : Pat<(xor GR8:$src1, imm:$src2),
1770 (XOR8ri GR8:$src1, imm:$src2)>;
1771 def : Pat<(xor GR16:$src1, imm:$src2),
1772 (XOR16ri GR16:$src1, imm:$src2)>;
1773 def : Pat<(xor GR32:$src1, imm:$src2),
1774 (XOR32ri GR32:$src1, imm:$src2)>;
1775 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1776 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1777 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1778 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1779 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1780 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1781 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1782 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1785 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1786 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1787 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1788 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1791 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1792 (AND8rm GR8:$src1, addr:$src2)>;
1793 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1794 (AND16rm GR16:$src1, addr:$src2)>;
1795 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1796 (AND32rm GR32:$src1, addr:$src2)>;
1797 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1798 (AND64rm GR64:$src1, addr:$src2)>;
1801 def : Pat<(and GR8:$src1, imm:$src2),
1802 (AND8ri GR8:$src1, imm:$src2)>;
1803 def : Pat<(and GR16:$src1, imm:$src2),
1804 (AND16ri GR16:$src1, imm:$src2)>;
1805 def : Pat<(and GR32:$src1, imm:$src2),
1806 (AND32ri GR32:$src1, imm:$src2)>;
1807 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1808 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1809 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1810 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1811 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1812 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1813 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1814 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
1816 // Bit scan instruction patterns to match explicit zero-undef behavior.
1817 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
1818 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
1819 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
1820 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
1821 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
1822 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;
1824 // When HasMOVBE is enabled it is possible to get a non-legalized
1825 // register-register 16 bit bswap. This maps it to a ROL instruction.
1826 let Predicates = [HasMOVBE] in {
1827 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>;