1 //===- X86InstrArithmetic.td - Integer Arithmetic Instrs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the integer arithmetic instructions in the X86
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // LEA - Load Effective Address
18 let neverHasSideEffects = 1 in
19 def LEA16r : I<0x8D, MRMSrcMem,
20 (outs GR16:$dst), (ins i32mem:$src),
21 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
22 let isReMaterializable = 1 in
23 def LEA32r : I<0x8D, MRMSrcMem,
24 (outs GR32:$dst), (ins i32mem:$src),
25 "lea{l}\t{$src|$dst}, {$dst|$src}",
26 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
28 def LEA64_32r : I<0x8D, MRMSrcMem,
29 (outs GR32:$dst), (ins lea64_32mem:$src),
30 "lea{l}\t{$src|$dst}, {$dst|$src}",
31 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
33 let isReMaterializable = 1 in
34 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
35 "lea{q}\t{$src|$dst}, {$dst|$src}",
36 [(set GR64:$dst, lea64addr:$src)]>;
40 //===----------------------------------------------------------------------===//
41 // Fixed-Register Multiplication and Division Instructions.
44 // Extra precision multiplication
46 // AL is really implied by AX, but the registers in Defs must match the
47 // SDNode results (i8, i32).
48 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
49 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
50 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
51 // This probably ought to be moved to a def : Pat<> if the
52 // syntax can be accepted.
53 [(set AL, (mul AL, GR8:$src)),
54 (implicit EFLAGS)]>; // AL,AH = AL*GR8
56 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
57 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
59 []>, OpSize; // AX,DX = AX*GR16
61 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
62 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
63 "mul{l}\t$src", // EAX,EDX = EAX*GR32
64 [/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/]>;
65 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
66 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
67 "mul{q}\t$src", // RAX,RDX = RAX*GR64
68 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/]>;
70 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
71 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
73 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
74 // This probably ought to be moved to a def : Pat<> if the
75 // syntax can be accepted.
76 [(set AL, (mul AL, (loadi8 addr:$src))),
77 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
79 let mayLoad = 1, neverHasSideEffects = 1 in {
80 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
81 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
83 []>, OpSize; // AX,DX = AX*[mem16]
85 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
86 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
88 []>; // EAX,EDX = EAX*[mem32]
89 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
90 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
91 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
94 let neverHasSideEffects = 1 in {
95 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
96 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
98 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
99 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
100 OpSize; // AX,DX = AX*GR16
101 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
102 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
103 // EAX,EDX = EAX*GR32
104 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
105 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", []>;
106 // RAX,RDX = RAX*GR64
109 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
110 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
111 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
112 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
113 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
114 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
115 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
116 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
117 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
118 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
119 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
120 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
122 } // neverHasSideEffects
125 let Defs = [EFLAGS] in {
126 let Constraints = "$src1 = $dst" in {
128 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
129 // Register-Register Signed Integer Multiply
130 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
131 "imul{w}\t{$src2, $dst|$dst, $src2}",
132 [(set GR16:$dst, EFLAGS,
133 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
134 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
135 "imul{l}\t{$src2, $dst|$dst, $src2}",
136 [(set GR32:$dst, EFLAGS,
137 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
138 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
139 (ins GR64:$src1, GR64:$src2),
140 "imul{q}\t{$src2, $dst|$dst, $src2}",
141 [(set GR64:$dst, EFLAGS,
142 (X86smul_flag GR64:$src1, GR64:$src2))]>, TB;
145 // Register-Memory Signed Integer Multiply
146 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
147 (ins GR16:$src1, i16mem:$src2),
148 "imul{w}\t{$src2, $dst|$dst, $src2}",
149 [(set GR16:$dst, EFLAGS,
150 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
152 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
153 (ins GR32:$src1, i32mem:$src2),
154 "imul{l}\t{$src2, $dst|$dst, $src2}",
155 [(set GR32:$dst, EFLAGS,
156 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
157 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
158 (ins GR64:$src1, i64mem:$src2),
159 "imul{q}\t{$src2, $dst|$dst, $src2}",
160 [(set GR64:$dst, EFLAGS,
161 (X86smul_flag GR64:$src1, (load addr:$src2)))]>, TB;
162 } // Constraints = "$src1 = $dst"
166 // Suprisingly enough, these are not two address instructions!
167 let Defs = [EFLAGS] in {
168 // Register-Integer Signed Integer Multiply
169 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
170 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
171 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
172 [(set GR16:$dst, EFLAGS,
173 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
174 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
175 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
176 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
177 [(set GR16:$dst, EFLAGS,
178 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
180 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
181 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
182 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
183 [(set GR32:$dst, EFLAGS,
184 (X86smul_flag GR32:$src1, imm:$src2))]>;
185 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
186 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
187 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
188 [(set GR32:$dst, EFLAGS,
189 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
190 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
191 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
192 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
193 [(set GR64:$dst, EFLAGS,
194 (X86smul_flag GR64:$src1, i64immSExt32:$src2))]>;
195 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
196 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
197 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
198 [(set GR64:$dst, EFLAGS,
199 (X86smul_flag GR64:$src1, i64immSExt8:$src2))]>;
202 // Memory-Integer Signed Integer Multiply
203 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
204 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
205 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
206 [(set GR16:$dst, EFLAGS,
207 (X86smul_flag (load addr:$src1), imm:$src2))]>,
209 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
210 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
211 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
212 [(set GR16:$dst, EFLAGS,
213 (X86smul_flag (load addr:$src1),
214 i16immSExt8:$src2))]>, OpSize;
215 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
216 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
217 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
218 [(set GR32:$dst, EFLAGS,
219 (X86smul_flag (load addr:$src1), imm:$src2))]>;
220 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
221 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
222 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
223 [(set GR32:$dst, EFLAGS,
224 (X86smul_flag (load addr:$src1),
225 i32immSExt8:$src2))]>;
226 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
227 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
228 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
229 [(set GR64:$dst, EFLAGS,
230 (X86smul_flag (load addr:$src1),
231 i64immSExt32:$src2))]>;
232 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
233 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
234 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
235 [(set GR64:$dst, EFLAGS,
236 (X86smul_flag (load addr:$src1),
237 i64immSExt8:$src2))]>;
243 // unsigned division/remainder
244 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
245 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
247 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
248 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
249 "div{w}\t$src", []>, OpSize;
250 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
251 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
253 // RDX:RAX/r64 = RAX,RDX
254 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
255 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
259 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
260 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
262 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
263 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
264 "div{w}\t$src", []>, OpSize;
265 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
266 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
268 // RDX:RAX/[mem64] = RAX,RDX
269 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
270 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
274 // Signed division/remainder.
275 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
276 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
277 "idiv{b}\t$src", []>;
278 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
279 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
280 "idiv{w}\t$src", []>, OpSize;
281 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
282 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
283 "idiv{l}\t$src", []>;
284 // RDX:RAX/r64 = RAX,RDX
285 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
286 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
287 "idiv{q}\t$src", []>;
289 let mayLoad = 1, mayLoad = 1 in {
290 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
291 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
292 "idiv{b}\t$src", []>;
293 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
294 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
295 "idiv{w}\t$src", []>, OpSize;
296 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
297 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
298 "idiv{l}\t$src", []>;
299 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX
300 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
301 "idiv{q}\t$src", []>;
304 //===----------------------------------------------------------------------===//
305 // Two address Instructions.
308 // unary instructions
309 let CodeSize = 2 in {
310 let Defs = [EFLAGS] in {
311 let Constraints = "$src1 = $dst" in {
312 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
314 [(set GR8:$dst, (ineg GR8:$src1)),
316 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
318 [(set GR16:$dst, (ineg GR16:$src1)),
319 (implicit EFLAGS)]>, OpSize;
320 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
322 [(set GR32:$dst, (ineg GR32:$src1)),
324 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
325 [(set GR64:$dst, (ineg GR64:$src1)),
327 } // Constraints = "$src1 = $dst"
329 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
331 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
333 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
335 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
336 (implicit EFLAGS)]>, OpSize;
337 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
339 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
341 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
342 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
347 // Note: NOT does not set EFLAGS!
349 let Constraints = "$src1 = $dst" in {
350 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
351 let AddedComplexity = 15 in {
352 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
354 [(set GR8:$dst, (not GR8:$src1))]>;
355 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
357 [(set GR16:$dst, (not GR16:$src1))]>, OpSize;
358 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
360 [(set GR32:$dst, (not GR32:$src1))]>;
361 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
362 [(set GR64:$dst, (not GR64:$src1))]>;
364 } // Constraints = "$src1 = $dst"
366 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
368 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
369 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
371 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
372 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
374 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
375 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
376 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
379 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
380 let Defs = [EFLAGS] in {
381 let Constraints = "$src1 = $dst" in {
383 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
385 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>;
387 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
388 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
390 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
391 OpSize, Requires<[In32BitMode]>;
392 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
394 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
395 Requires<[In32BitMode]>;
396 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
397 [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))]>;
398 } // isConvertibleToThreeAddress = 1, CodeSize = 1
401 // In 64-bit mode, single byte INC and DEC cannot be encoded.
402 let isConvertibleToThreeAddress = 1, CodeSize = 2 in {
403 // Can transform into LEA.
404 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
406 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
407 OpSize, Requires<[In64BitMode]>;
408 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
410 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
411 Requires<[In64BitMode]>;
412 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
414 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
415 OpSize, Requires<[In64BitMode]>;
416 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
418 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
419 Requires<[In64BitMode]>;
420 } // isConvertibleToThreeAddress = 1, CodeSize = 2
422 } // Constraints = "$src1 = $dst"
424 let CodeSize = 2 in {
425 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
426 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
428 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
429 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
431 OpSize, Requires<[In32BitMode]>;
432 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
433 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
435 Requires<[In32BitMode]>;
436 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
437 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
440 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
441 // how to unfold them.
442 // FIXME: What is this for??
443 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
444 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
446 OpSize, Requires<[In64BitMode]>;
447 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
448 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
450 Requires<[In64BitMode]>;
451 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
452 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
454 OpSize, Requires<[In64BitMode]>;
455 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
456 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
458 Requires<[In64BitMode]>;
461 let Constraints = "$src1 = $dst" in {
463 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
465 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>;
466 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
467 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
469 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
470 OpSize, Requires<[In32BitMode]>;
471 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
473 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
474 Requires<[In32BitMode]>;
475 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst",
476 [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))]>;
478 } // Constraints = "$src1 = $dst"
481 let CodeSize = 2 in {
482 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
483 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
485 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
486 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
488 OpSize, Requires<[In32BitMode]>;
489 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
490 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
492 Requires<[In32BitMode]>;
493 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
494 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
500 /// X86TypeInfo - This is a bunch of information that describes relevant X86
501 /// information about value types. For example, it can tell you what the
502 /// register class and preferred load to use.
503 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
504 PatFrag loadnode, X86MemOperand memoperand, ImmType immkind,
505 Operand immoperand, SDPatternOperator immoperator,
506 Operand imm8operand, SDPatternOperator imm8operator,
507 bit hasOddOpcode, bit hasOpSizePrefix, bit hasREX_WPrefix> {
508 /// VT - This is the value type itself.
511 /// InstrSuffix - This is the suffix used on instructions with this type. For
512 /// example, i8 -> "b", i16 -> "w", i32 -> "l", i64 -> "q".
513 string InstrSuffix = instrsuffix;
515 /// RegClass - This is the register class associated with this type. For
516 /// example, i8 -> GR8, i16 -> GR16, i32 -> GR32, i64 -> GR64.
517 RegisterClass RegClass = regclass;
519 /// LoadNode - This is the load node associated with this type. For
520 /// example, i8 -> loadi8, i16 -> loadi16, i32 -> loadi32, i64 -> loadi64.
521 PatFrag LoadNode = loadnode;
523 /// MemOperand - This is the memory operand associated with this type. For
524 /// example, i8 -> i8mem, i16 -> i16mem, i32 -> i32mem, i64 -> i64mem.
525 X86MemOperand MemOperand = memoperand;
527 /// ImmEncoding - This is the encoding of an immediate of this type. For
528 /// example, i8 -> Imm8, i16 -> Imm16, i32 -> Imm32. Note that i64 -> Imm32
529 /// since the immediate fields of i64 instructions is a 32-bit sign extended
531 ImmType ImmEncoding = immkind;
533 /// ImmOperand - This is the operand kind of an immediate of this type. For
534 /// example, i8 -> i8imm, i16 -> i16imm, i32 -> i32imm. Note that i64 ->
535 /// i64i32imm since the immediate fields of i64 instructions is a 32-bit sign
537 Operand ImmOperand = immoperand;
539 /// ImmOperator - This is the operator that should be used to match an
540 /// immediate of this kind in a pattern (e.g. imm, or i64immSExt32).
541 SDPatternOperator ImmOperator = immoperator;
543 /// Imm8Operand - This is the operand kind to use for an imm8 of this type.
544 /// For example, i8 -> <invalid>, i16 -> i16i8imm, i32 -> i32i8imm. This is
545 /// only used for instructions that have a sign-extended imm8 field form.
546 Operand Imm8Operand = imm8operand;
548 /// Imm8Operator - This is the operator that should be used to match an 8-bit
549 /// sign extended immediate of this kind in a pattern (e.g. imm16immSExt8).
550 SDPatternOperator Imm8Operator = imm8operator;
552 /// HasOddOpcode - This bit is true if the instruction should have an odd (as
553 /// opposed to even) opcode. Operations on i8 are usually even, operations on
554 /// other datatypes are odd.
555 bit HasOddOpcode = hasOddOpcode;
557 /// HasOpSizePrefix - This bit is set to true if the instruction should have
558 /// the 0x66 operand size prefix. This is set for i16 types.
559 bit HasOpSizePrefix = hasOpSizePrefix;
561 /// HasREX_WPrefix - This bit is set to true if the instruction should have
562 /// the 0x40 REX prefix. This is set for i64 types.
563 bit HasREX_WPrefix = hasREX_WPrefix;
566 def invalid_node : SDNode<"<<invalid_node>>", SDTIntLeaf,[],"<<invalid_node>>">;
569 def Xi8 : X86TypeInfo<i8 , "b", GR8 , loadi8 , i8mem ,
570 Imm8 , i8imm , imm, i8imm , invalid_node,
572 def Xi16 : X86TypeInfo<i16, "w", GR16, loadi16, i16mem,
573 Imm16, i16imm, imm, i16i8imm, i16immSExt8,
575 def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem,
576 Imm32, i32imm, imm, i32i8imm, i32immSExt8,
578 def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem,
579 Imm32, i64i32imm, i64immSExt32, i64i8imm, i64immSExt8,
582 /// ITy - This instruction base class takes the type info for the instruction.
584 /// 1. Concatenates together the instruction mnemonic with the appropriate
585 /// suffix letter, a tab, and the arguments.
586 /// 2. Infers whether the instruction should have a 0x66 prefix byte.
587 /// 3. Infers whether the instruction should have a 0x40 REX_W prefix.
588 /// 4. Infers whether the low bit of the opcode should be 0 (for i8 operations)
589 /// or 1 (for i16,i32,i64 operations).
590 class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins,
591 string mnemonic, string args, list<dag> pattern>
592 : I<{opcode{7}, opcode{6}, opcode{5}, opcode{4},
593 opcode{3}, opcode{2}, opcode{1}, typeinfo.HasOddOpcode },
595 !strconcat(mnemonic, "{", typeinfo.InstrSuffix, "}\t", args), pattern> {
597 // Infer instruction prefixes from type info.
598 let hasOpSizePrefix = typeinfo.HasOpSizePrefix;
599 let hasREX_WPrefix = typeinfo.HasREX_WPrefix;
602 // BinOpRR - Instructions like "add reg, reg, reg".
603 class BinOpRR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
604 dag outlist, list<dag> pattern, Format f = MRMDestReg>
605 : ITy<opcode, f, typeinfo, outlist,
606 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
607 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>;
609 // BinOpRR_R - Instructions like "add reg, reg, reg", where the pattern has
610 // just a regclass (no eflags) as a result.
611 class BinOpRR_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
613 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
614 [(set typeinfo.RegClass:$dst,
615 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
617 // BinOpRR_F - Instructions like "cmp reg, Reg", where the pattern has
618 // just a EFLAGS as a result.
619 class BinOpRR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
620 SDPatternOperator opnode, Format f = MRMDestReg>
621 : BinOpRR<opcode, mnemonic, typeinfo, (outs),
623 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
626 // BinOpRR_RF - Instructions like "add reg, reg, reg", where the pattern has
627 // both a regclass and EFLAGS as a result.
628 class BinOpRR_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
630 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
631 [(set typeinfo.RegClass:$dst, EFLAGS,
632 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
634 // BinOpRR_Rev - Instructions like "add reg, reg, reg" (reversed encoding).
635 class BinOpRR_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo>
636 : ITy<opcode, MRMSrcReg, typeinfo,
637 (outs typeinfo.RegClass:$dst),
638 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
639 mnemonic, "{$src2, $dst|$dst, $src2}", []> {
640 // The disassembler should know about this, but not the asmparser.
641 let isCodeGenOnly = 1;
644 // BinOpRM - Instructions like "add reg, reg, [mem]".
645 class BinOpRM<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
646 dag outlist, list<dag> pattern>
647 : ITy<opcode, MRMSrcMem, typeinfo, outlist,
648 (ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2),
649 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>;
651 // BinOpRM_R - Instructions like "add reg, reg, [mem]".
652 class BinOpRM_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
654 : BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
655 [(set typeinfo.RegClass:$dst,
656 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
658 // BinOpRM_F - Instructions like "cmp reg, [mem]".
659 class BinOpRM_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
660 SDPatternOperator opnode>
661 : BinOpRM<opcode, mnemonic, typeinfo, (outs),
663 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
665 // BinOpRM_RF - Instructions like "add reg, reg, [mem]".
666 class BinOpRM_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
668 : BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
669 [(set typeinfo.RegClass:$dst, EFLAGS,
670 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
672 // BinOpRI - Instructions like "add reg, reg, imm".
673 class BinOpRI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
674 Format f, dag outlist, list<dag> pattern>
675 : ITy<opcode, f, typeinfo, outlist,
676 (ins typeinfo.RegClass:$src1, typeinfo.ImmOperand:$src2),
677 mnemonic, "{$src2, $src1|$src1, $src2}", pattern> {
678 let ImmT = typeinfo.ImmEncoding;
681 // BinOpRI_R - Instructions like "add reg, reg, imm".
682 class BinOpRI_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
683 SDNode opnode, Format f>
684 : BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
685 [(set typeinfo.RegClass:$dst,
686 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
688 // BinOpRI_F - Instructions like "cmp reg, imm".
689 class BinOpRI_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
690 SDPatternOperator opnode, Format f>
691 : BinOpRI<opcode, mnemonic, typeinfo, f, (outs),
693 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
695 // BinOpRI_RF - Instructions like "add reg, reg, imm".
696 class BinOpRI_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
697 SDNode opnode, Format f>
698 : BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
699 [(set typeinfo.RegClass:$dst, EFLAGS,
700 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
702 // BinOpRI8 - Instructions like "add reg, reg, imm8".
703 class BinOpRI8<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
704 Format f, dag outlist, list<dag> pattern>
705 : ITy<opcode, f, typeinfo, outlist,
706 (ins typeinfo.RegClass:$src1, typeinfo.Imm8Operand:$src2),
707 mnemonic, "{$src2, $src1|$src1, $src2}", pattern> {
708 let ImmT = Imm8; // Always 8-bit immediate.
711 // BinOpRI8_R - Instructions like "add reg, reg, imm8".
712 class BinOpRI8_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
713 SDNode opnode, Format f>
714 : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
715 [(set typeinfo.RegClass:$dst,
716 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
718 // BinOpRI8_F - Instructions like "cmp reg, imm8".
719 class BinOpRI8_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
720 SDNode opnode, Format f>
721 : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs),
723 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
725 // BinOpRI8_RF - Instructions like "add reg, reg, imm8".
726 class BinOpRI8_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
727 SDNode opnode, Format f>
728 : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
729 [(set typeinfo.RegClass:$dst, EFLAGS,
730 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
732 // BinOpMR - Instructions like "add [mem], reg".
733 class BinOpMR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
735 : ITy<opcode, MRMDestMem, typeinfo,
736 (outs), (ins typeinfo.MemOperand:$dst, typeinfo.RegClass:$src),
737 mnemonic, "{$src, $dst|$dst, $src}", pattern>;
739 // BinOpMR_RMW - Instructions like "add [mem], reg".
740 class BinOpMR_RMW<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
742 : BinOpMR<opcode, mnemonic, typeinfo,
743 [(store (opnode (load addr:$dst), typeinfo.RegClass:$src), addr:$dst),
746 // BinOpMR_F - Instructions like "cmp [mem], reg".
747 class BinOpMR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
749 : BinOpMR<opcode, mnemonic, typeinfo,
750 [(set EFLAGS, (opnode (load addr:$dst), typeinfo.RegClass:$src))]>;
752 // BinOpMI - Instructions like "add [mem], imm".
753 class BinOpMI<string mnemonic, X86TypeInfo typeinfo,
754 Format f, list<dag> pattern, bits<8> opcode = 0x80>
755 : ITy<opcode, f, typeinfo,
756 (outs), (ins typeinfo.MemOperand:$dst, typeinfo.ImmOperand:$src),
757 mnemonic, "{$src, $dst|$dst, $src}", pattern> {
758 let ImmT = typeinfo.ImmEncoding;
761 // BinOpMI_RMW - Instructions like "add [mem], imm".
762 class BinOpMI_RMW<string mnemonic, X86TypeInfo typeinfo,
763 SDNode opnode, Format f>
764 : BinOpMI<mnemonic, typeinfo, f,
765 [(store (opnode (typeinfo.VT (load addr:$dst)),
766 typeinfo.ImmOperator:$src), addr:$dst),
769 // BinOpMI_F - Instructions like "cmp [mem], imm".
770 class BinOpMI_F<string mnemonic, X86TypeInfo typeinfo,
771 SDPatternOperator opnode, Format f, bits<8> opcode = 0x80>
772 : BinOpMI<mnemonic, typeinfo, f,
773 [(set EFLAGS, (opnode (typeinfo.VT (load addr:$dst)),
774 typeinfo.ImmOperator:$src))],
777 // BinOpMI8 - Instructions like "add [mem], imm8".
778 class BinOpMI8<string mnemonic, X86TypeInfo typeinfo,
779 Format f, list<dag> pattern>
780 : ITy<0x82, f, typeinfo,
781 (outs), (ins typeinfo.MemOperand:$dst, typeinfo.Imm8Operand:$src),
782 mnemonic, "{$src, $dst|$dst, $src}", pattern> {
783 let ImmT = Imm8; // Always 8-bit immediate.
786 // BinOpMI8_RMW - Instructions like "add [mem], imm8".
787 class BinOpMI8_RMW<string mnemonic, X86TypeInfo typeinfo,
788 SDNode opnode, Format f>
789 : BinOpMI8<mnemonic, typeinfo, f,
790 [(store (opnode (load addr:$dst),
791 typeinfo.Imm8Operator:$src), addr:$dst),
794 // BinOpMI8_F - Instructions like "cmp [mem], imm8".
795 class BinOpMI8_F<string mnemonic, X86TypeInfo typeinfo,
796 SDNode opnode, Format f>
797 : BinOpMI8<mnemonic, typeinfo, f,
798 [(set EFLAGS, (opnode (load addr:$dst),
799 typeinfo.Imm8Operator:$src))]>;
801 // BinOpAI - Instructions like "add %eax, %eax, imm".
802 class BinOpAI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
804 : ITy<opcode, RawFrm, typeinfo,
805 (outs), (ins typeinfo.ImmOperand:$src),
806 mnemonic, !strconcat("{$src, %", areg.AsmName, "|%",
807 areg.AsmName, ", $src}"), []> {
808 let ImmT = typeinfo.ImmEncoding;
813 /// ArithBinOp_RF - This is an arithmetic binary operator where the pattern is
814 /// defined with "(set GPR:$dst, EFLAGS, (...".
816 /// It would be nice to get rid of the second and third argument here, but
817 /// tblgen can't handle dependent type references aggressively enough: PR8330
818 multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
819 string mnemonic, Format RegMRM, Format MemMRM,
820 SDNode opnodeflag, SDNode opnode,
821 bit CommutableRR, bit ConvertibleToThreeAddress> {
822 let Defs = [EFLAGS] in {
823 let Constraints = "$src1 = $dst" in {
824 let isCommutable = CommutableRR,
825 isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
826 def #NAME#8rr : BinOpRR_RF<BaseOpc, mnemonic, Xi8 , opnodeflag>;
827 def #NAME#16rr : BinOpRR_RF<BaseOpc, mnemonic, Xi16, opnodeflag>;
828 def #NAME#32rr : BinOpRR_RF<BaseOpc, mnemonic, Xi32, opnodeflag>;
829 def #NAME#64rr : BinOpRR_RF<BaseOpc, mnemonic, Xi64, opnodeflag>;
832 def #NAME#8rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi8>;
833 def #NAME#16rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi16>;
834 def #NAME#32rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi32>;
835 def #NAME#64rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi64>;
837 def #NAME#8rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi8 , opnodeflag>;
838 def #NAME#16rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi16, opnodeflag>;
839 def #NAME#32rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi32, opnodeflag>;
840 def #NAME#64rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi64, opnodeflag>;
842 let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
843 // NOTE: These are order specific, we want the ri8 forms to be listed
844 // first so that they are slightly preferred to the ri forms.
845 def #NAME#16ri8 : BinOpRI8_RF<0x82, mnemonic, Xi16, opnodeflag, RegMRM>;
846 def #NAME#32ri8 : BinOpRI8_RF<0x82, mnemonic, Xi32, opnodeflag, RegMRM>;
847 def #NAME#64ri8 : BinOpRI8_RF<0x82, mnemonic, Xi64, opnodeflag, RegMRM>;
849 def #NAME#8ri : BinOpRI_RF<0x80, mnemonic, Xi8 , opnodeflag, RegMRM>;
850 def #NAME#16ri : BinOpRI_RF<0x80, mnemonic, Xi16, opnodeflag, RegMRM>;
851 def #NAME#32ri : BinOpRI_RF<0x80, mnemonic, Xi32, opnodeflag, RegMRM>;
852 def #NAME#64ri32: BinOpRI_RF<0x80, mnemonic, Xi64, opnodeflag, RegMRM>;
854 } // Constraints = "$src1 = $dst"
856 def #NAME#8mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi8 , opnode>;
857 def #NAME#16mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi16, opnode>;
858 def #NAME#32mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi32, opnode>;
859 def #NAME#64mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi64, opnode>;
861 // NOTE: These are order specific, we want the mi8 forms to be listed
862 // first so that they are slightly preferred to the mi forms.
863 def #NAME#16mi8 : BinOpMI8_RMW<mnemonic, Xi16, opnode, MemMRM>;
864 def #NAME#32mi8 : BinOpMI8_RMW<mnemonic, Xi32, opnode, MemMRM>;
865 def #NAME#64mi8 : BinOpMI8_RMW<mnemonic, Xi64, opnode, MemMRM>;
867 def #NAME#8mi : BinOpMI_RMW<mnemonic, Xi8 , opnode, MemMRM>;
868 def #NAME#16mi : BinOpMI_RMW<mnemonic, Xi16, opnode, MemMRM>;
869 def #NAME#32mi : BinOpMI_RMW<mnemonic, Xi32, opnode, MemMRM>;
870 def #NAME#64mi32 : BinOpMI_RMW<mnemonic, Xi64, opnode, MemMRM>;
872 def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL>;
873 def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX>;
874 def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX>;
875 def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX>;
879 /// ArithBinOp_R - This is an arithmetic binary operator where the pattern is
880 /// defined with "(set GPR:$dst, (...". It would be really nice to find a way
881 /// to factor this with the other ArithBinOp_*.
883 multiclass ArithBinOp_R<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
884 string mnemonic, Format RegMRM, Format MemMRM,
886 bit CommutableRR, bit ConvertibleToThreeAddress> {
887 let Defs = [EFLAGS] in {
888 let Constraints = "$src1 = $dst" in {
889 let isCommutable = CommutableRR,
890 isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
891 def #NAME#8rr : BinOpRR_R<BaseOpc, mnemonic, Xi8 , opnode>;
892 def #NAME#16rr : BinOpRR_R<BaseOpc, mnemonic, Xi16, opnode>;
893 def #NAME#32rr : BinOpRR_R<BaseOpc, mnemonic, Xi32, opnode>;
894 def #NAME#64rr : BinOpRR_R<BaseOpc, mnemonic, Xi64, opnode>;
897 def #NAME#8rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi8>;
898 def #NAME#16rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi16>;
899 def #NAME#32rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi32>;
900 def #NAME#64rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi64>;
902 def #NAME#8rm : BinOpRM_R<BaseOpc2, mnemonic, Xi8 , opnode>;
903 def #NAME#16rm : BinOpRM_R<BaseOpc2, mnemonic, Xi16, opnode>;
904 def #NAME#32rm : BinOpRM_R<BaseOpc2, mnemonic, Xi32, opnode>;
905 def #NAME#64rm : BinOpRM_R<BaseOpc2, mnemonic, Xi64, opnode>;
907 let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
908 // NOTE: These are order specific, we want the ri8 forms to be listed
909 // first so that they are slightly preferred to the ri forms.
910 def #NAME#16ri8 : BinOpRI8_R<0x82, mnemonic, Xi16, opnode, RegMRM>;
911 def #NAME#32ri8 : BinOpRI8_R<0x82, mnemonic, Xi32, opnode, RegMRM>;
912 def #NAME#64ri8 : BinOpRI8_R<0x82, mnemonic, Xi64, opnode, RegMRM>;
914 def #NAME#8ri : BinOpRI_R<0x80, mnemonic, Xi8 , opnode, RegMRM>;
915 def #NAME#16ri : BinOpRI_R<0x80, mnemonic, Xi16, opnode, RegMRM>;
916 def #NAME#32ri : BinOpRI_R<0x80, mnemonic, Xi32, opnode, RegMRM>;
917 def #NAME#64ri32: BinOpRI_R<0x80, mnemonic, Xi64, opnode, RegMRM>;
919 } // Constraints = "$src1 = $dst"
921 def #NAME#8mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi8 , opnode>;
922 def #NAME#16mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi16, opnode>;
923 def #NAME#32mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi32, opnode>;
924 def #NAME#64mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi64, opnode>;
926 // NOTE: These are order specific, we want the mi8 forms to be listed
927 // first so that they are slightly preferred to the mi forms.
928 def #NAME#16mi8 : BinOpMI8_RMW<mnemonic, Xi16, opnode, MemMRM>;
929 def #NAME#32mi8 : BinOpMI8_RMW<mnemonic, Xi32, opnode, MemMRM>;
930 def #NAME#64mi8 : BinOpMI8_RMW<mnemonic, Xi64, opnode, MemMRM>;
932 def #NAME#8mi : BinOpMI_RMW<mnemonic, Xi8 , opnode, MemMRM>;
933 def #NAME#16mi : BinOpMI_RMW<mnemonic, Xi16, opnode, MemMRM>;
934 def #NAME#32mi : BinOpMI_RMW<mnemonic, Xi32, opnode, MemMRM>;
935 def #NAME#64mi32 : BinOpMI_RMW<mnemonic, Xi64, opnode, MemMRM>;
937 def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL>;
938 def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX>;
939 def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX>;
940 def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX>;
944 /// ArithBinOp_F - This is an arithmetic binary operator where the pattern is
945 /// defined with "(set EFLAGS, (...". It would be really nice to find a way
946 /// to factor this with the other ArithBinOp_*.
948 multiclass ArithBinOp_F<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
949 string mnemonic, Format RegMRM, Format MemMRM,
951 bit CommutableRR, bit ConvertibleToThreeAddress> {
952 let Defs = [EFLAGS] in {
953 let isCommutable = CommutableRR,
954 isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
955 def #NAME#8rr : BinOpRR_F<BaseOpc, mnemonic, Xi8 , opnode>;
956 def #NAME#16rr : BinOpRR_F<BaseOpc, mnemonic, Xi16, opnode>;
957 def #NAME#32rr : BinOpRR_F<BaseOpc, mnemonic, Xi32, opnode>;
958 def #NAME#64rr : BinOpRR_F<BaseOpc, mnemonic, Xi64, opnode>;
961 def #NAME#8rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi8>;
962 def #NAME#16rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi16>;
963 def #NAME#32rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi32>;
964 def #NAME#64rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi64>;
966 def #NAME#8rm : BinOpRM_F<BaseOpc2, mnemonic, Xi8 , opnode>;
967 def #NAME#16rm : BinOpRM_F<BaseOpc2, mnemonic, Xi16, opnode>;
968 def #NAME#32rm : BinOpRM_F<BaseOpc2, mnemonic, Xi32, opnode>;
969 def #NAME#64rm : BinOpRM_F<BaseOpc2, mnemonic, Xi64, opnode>;
971 let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
972 // NOTE: These are order specific, we want the ri8 forms to be listed
973 // first so that they are slightly preferred to the ri forms.
974 def #NAME#16ri8 : BinOpRI8_F<0x82, mnemonic, Xi16, opnode, RegMRM>;
975 def #NAME#32ri8 : BinOpRI8_F<0x82, mnemonic, Xi32, opnode, RegMRM>;
976 def #NAME#64ri8 : BinOpRI8_F<0x82, mnemonic, Xi64, opnode, RegMRM>;
978 def #NAME#8ri : BinOpRI_F<0x80, mnemonic, Xi8 , opnode, RegMRM>;
979 def #NAME#16ri : BinOpRI_F<0x80, mnemonic, Xi16, opnode, RegMRM>;
980 def #NAME#32ri : BinOpRI_F<0x80, mnemonic, Xi32, opnode, RegMRM>;
981 def #NAME#64ri32: BinOpRI_F<0x80, mnemonic, Xi64, opnode, RegMRM>;
984 def #NAME#8mr : BinOpMR_F<BaseOpc, mnemonic, Xi8 , opnode>;
985 def #NAME#16mr : BinOpMR_F<BaseOpc, mnemonic, Xi16, opnode>;
986 def #NAME#32mr : BinOpMR_F<BaseOpc, mnemonic, Xi32, opnode>;
987 def #NAME#64mr : BinOpMR_F<BaseOpc, mnemonic, Xi64, opnode>;
989 // NOTE: These are order specific, we want the mi8 forms to be listed
990 // first so that they are slightly preferred to the mi forms.
991 def #NAME#16mi8 : BinOpMI8_F<mnemonic, Xi16, opnode, MemMRM>;
992 def #NAME#32mi8 : BinOpMI8_F<mnemonic, Xi32, opnode, MemMRM>;
993 def #NAME#64mi8 : BinOpMI8_F<mnemonic, Xi64, opnode, MemMRM>;
995 def #NAME#8mi : BinOpMI_F<mnemonic, Xi8 , opnode, MemMRM>;
996 def #NAME#16mi : BinOpMI_F<mnemonic, Xi16, opnode, MemMRM>;
997 def #NAME#32mi : BinOpMI_F<mnemonic, Xi32, opnode, MemMRM>;
998 def #NAME#64mi32 : BinOpMI_F<mnemonic, Xi64, opnode, MemMRM>;
1000 def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL>;
1001 def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX>;
1002 def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX>;
1003 def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX>;
1008 defm AND : ArithBinOp_RF<0x20, 0x22, 0x24, "and", MRM4r, MRM4m,
1009 X86and_flag, and, 1, 0>;
1010 defm OR : ArithBinOp_RF<0x08, 0x0A, 0x0C, "or", MRM1r, MRM1m,
1011 X86or_flag, or, 1, 0>;
1012 defm XOR : ArithBinOp_RF<0x30, 0x32, 0x34, "xor", MRM6r, MRM6m,
1013 X86xor_flag, xor, 1, 0>;
1014 defm ADD : ArithBinOp_RF<0x00, 0x02, 0x04, "add", MRM0r, MRM0m,
1015 X86add_flag, add, 1, 1>;
1016 defm SUB : ArithBinOp_RF<0x28, 0x2A, 0x2C, "sub", MRM5r, MRM5m,
1017 X86sub_flag, sub, 0, 0>;
1020 let Uses = [EFLAGS] in {
1021 // FIXME: Delete ArithBinOp_R if these switch off adde/sube.
1022 defm ADC : ArithBinOp_R<0x10, 0x12, 0x14, "adc", MRM2r, MRM2m, adde, 1, 0>;
1023 defm SBB : ArithBinOp_R<0x18, 0x1A, 0x1C, "sbb", MRM3r, MRM3m, sube, 0, 0>;
1028 defm CMP : ArithBinOp_F<0x38, 0x3A, 0x3C, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>;
1031 //===----------------------------------------------------------------------===//
1032 // Semantically, test instructions are similar like AND, except they don't
1033 // generate a result. From an encoding perspective, they are very different:
1034 // they don't have all the usual imm8 and REV forms, and are encoded into a
1036 def X86testpat : PatFrag<(ops node:$lhs, node:$rhs),
1037 (X86cmp (and_su node:$lhs, node:$rhs), 0)>;
1039 let Defs = [EFLAGS] in {
1040 let isCommutable = 1 in {
1041 def TEST8rr : BinOpRR_F<0x84, "test", Xi8 , X86testpat, MRMSrcReg>;
1042 def TEST16rr : BinOpRR_F<0x84, "test", Xi16, X86testpat, MRMSrcReg>;
1043 def TEST32rr : BinOpRR_F<0x84, "test", Xi32, X86testpat, MRMSrcReg>;
1044 def TEST64rr : BinOpRR_F<0x84, "test", Xi64, X86testpat, MRMSrcReg>;
1047 def TEST8rm : BinOpRM_F<0x84, "test", Xi8 , X86testpat>;
1048 def TEST16rm : BinOpRM_F<0x84, "test", Xi16, X86testpat>;
1049 def TEST32rm : BinOpRM_F<0x84, "test", Xi32, X86testpat>;
1050 def TEST64rm : BinOpRM_F<0x84, "test", Xi64, X86testpat>;
1052 def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>;
1053 def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>;
1054 def TEST32ri : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM0r>;
1055 def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>;
1057 def TEST8mi : BinOpMI_F<"test", Xi8 , X86testpat, MRM0m, 0xF6>;
1058 def TEST16mi : BinOpMI_F<"test", Xi16, X86testpat, MRM0m, 0xF6>;
1059 def TEST32mi : BinOpMI_F<"test", Xi32, X86testpat, MRM0m, 0xF6>;
1060 def TEST64mi32 : BinOpMI_F<"test", Xi64, X86testpat, MRM0m, 0xF6>;
1062 def TEST8i8 : BinOpAI<0xA8, "test", Xi8 , AL>;
1063 def TEST16i16 : BinOpAI<0xA8, "test", Xi16, AX>;
1064 def TEST32i32 : BinOpAI<0xA8, "test", Xi32, EAX>;
1065 def TEST64i32 : BinOpAI<0xA8, "test", Xi64, RAX>;