1 //===- X86InstrArithmetic.td - Integer Arithmetic Instrs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the integer arithmetic instructions in the X86
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // LEA - Load Effective Address
18 let neverHasSideEffects = 1 in
19 def LEA16r : I<0x8D, MRMSrcMem,
20 (outs GR16:$dst), (ins i32mem:$src),
21 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
22 let isReMaterializable = 1 in
23 def LEA32r : I<0x8D, MRMSrcMem,
24 (outs GR32:$dst), (ins i32mem:$src),
25 "lea{l}\t{$src|$dst}, {$dst|$src}",
26 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
28 def LEA64_32r : I<0x8D, MRMSrcMem,
29 (outs GR32:$dst), (ins lea64_32mem:$src),
30 "lea{l}\t{$src|$dst}, {$dst|$src}",
31 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
33 let isReMaterializable = 1 in
34 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
35 "lea{q}\t{$src|$dst}, {$dst|$src}",
36 [(set GR64:$dst, lea64addr:$src)]>;
40 //===----------------------------------------------------------------------===//
41 // Fixed-Register Multiplication and Division Instructions.
44 // Extra precision multiplication
46 // AL is really implied by AX, but the registers in Defs must match the
47 // SDNode results (i8, i32).
48 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
49 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
50 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
51 // This probably ought to be moved to a def : Pat<> if the
52 // syntax can be accepted.
53 [(set AL, (mul AL, GR8:$src)),
54 (implicit EFLAGS)]>; // AL,AH = AL*GR8
56 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
57 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
59 []>, OpSize; // AX,DX = AX*GR16
61 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
62 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
64 []>; // EAX,EDX = EAX*GR32
65 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
66 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
67 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
69 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
70 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
72 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
73 // This probably ought to be moved to a def : Pat<> if the
74 // syntax can be accepted.
75 [(set AL, (mul AL, (loadi8 addr:$src))),
76 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
78 let mayLoad = 1, neverHasSideEffects = 1 in {
79 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
80 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
82 []>, OpSize; // AX,DX = AX*[mem16]
84 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
85 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
87 []>; // EAX,EDX = EAX*[mem32]
88 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
89 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
90 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
93 let neverHasSideEffects = 1 in {
94 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
95 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
97 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
98 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
99 OpSize; // AX,DX = AX*GR16
100 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
101 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
102 // EAX,EDX = EAX*GR32
103 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
104 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", []>;
105 // RAX,RDX = RAX*GR64
108 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
109 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
110 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
111 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
112 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
113 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
114 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
115 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
116 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
117 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
118 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
119 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
121 } // neverHasSideEffects
124 let Defs = [EFLAGS] in {
125 let Constraints = "$src1 = $dst" in {
127 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
128 // Register-Register Signed Integer Multiply
129 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
130 "imul{w}\t{$src2, $dst|$dst, $src2}",
131 [(set GR16:$dst, EFLAGS,
132 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
133 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
134 "imul{l}\t{$src2, $dst|$dst, $src2}",
135 [(set GR32:$dst, EFLAGS,
136 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
137 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
138 (ins GR64:$src1, GR64:$src2),
139 "imul{q}\t{$src2, $dst|$dst, $src2}",
140 [(set GR64:$dst, EFLAGS,
141 (X86smul_flag GR64:$src1, GR64:$src2))]>, TB;
144 // Register-Memory Signed Integer Multiply
145 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
146 (ins GR16:$src1, i16mem:$src2),
147 "imul{w}\t{$src2, $dst|$dst, $src2}",
148 [(set GR16:$dst, EFLAGS,
149 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
151 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
152 (ins GR32:$src1, i32mem:$src2),
153 "imul{l}\t{$src2, $dst|$dst, $src2}",
154 [(set GR32:$dst, EFLAGS,
155 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
156 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
157 (ins GR64:$src1, i64mem:$src2),
158 "imul{q}\t{$src2, $dst|$dst, $src2}",
159 [(set GR64:$dst, EFLAGS,
160 (X86smul_flag GR64:$src1, (load addr:$src2)))]>, TB;
161 } // Constraints = "$src1 = $dst"
165 // Suprisingly enough, these are not two address instructions!
166 let Defs = [EFLAGS] in {
167 // Register-Integer Signed Integer Multiply
168 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
169 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
170 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
171 [(set GR16:$dst, EFLAGS,
172 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
173 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
174 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
175 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
176 [(set GR16:$dst, EFLAGS,
177 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
179 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
180 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
181 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
182 [(set GR32:$dst, EFLAGS,
183 (X86smul_flag GR32:$src1, imm:$src2))]>;
184 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
185 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
186 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
187 [(set GR32:$dst, EFLAGS,
188 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
189 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
190 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
191 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
192 [(set GR64:$dst, EFLAGS,
193 (X86smul_flag GR64:$src1, i64immSExt32:$src2))]>;
194 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
195 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
196 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
197 [(set GR64:$dst, EFLAGS,
198 (X86smul_flag GR64:$src1, i64immSExt8:$src2))]>;
201 // Memory-Integer Signed Integer Multiply
202 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
203 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
204 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
205 [(set GR16:$dst, EFLAGS,
206 (X86smul_flag (load addr:$src1), imm:$src2))]>,
208 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
209 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
210 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
211 [(set GR16:$dst, EFLAGS,
212 (X86smul_flag (load addr:$src1),
213 i16immSExt8:$src2))]>, OpSize;
214 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
215 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
216 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
217 [(set GR32:$dst, EFLAGS,
218 (X86smul_flag (load addr:$src1), imm:$src2))]>;
219 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
220 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
221 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
222 [(set GR32:$dst, EFLAGS,
223 (X86smul_flag (load addr:$src1),
224 i32immSExt8:$src2))]>;
225 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
226 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
227 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 [(set GR64:$dst, EFLAGS,
229 (X86smul_flag (load addr:$src1),
230 i64immSExt32:$src2))]>;
231 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
232 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
233 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
234 [(set GR64:$dst, EFLAGS,
235 (X86smul_flag (load addr:$src1),
236 i64immSExt8:$src2))]>;
242 // unsigned division/remainder
243 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
244 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
246 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
247 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
248 "div{w}\t$src", []>, OpSize;
249 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
250 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
252 // RDX:RAX/r64 = RAX,RDX
253 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
254 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
258 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
259 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
261 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
262 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
263 "div{w}\t$src", []>, OpSize;
264 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
265 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
267 // RDX:RAX/[mem64] = RAX,RDX
268 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
269 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
273 // Signed division/remainder.
274 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
275 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
276 "idiv{b}\t$src", []>;
277 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
278 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
279 "idiv{w}\t$src", []>, OpSize;
280 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
281 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
282 "idiv{l}\t$src", []>;
283 // RDX:RAX/r64 = RAX,RDX
284 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
285 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
286 "idiv{q}\t$src", []>;
288 let mayLoad = 1, mayLoad = 1 in {
289 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
290 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
291 "idiv{b}\t$src", []>;
292 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
293 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
294 "idiv{w}\t$src", []>, OpSize;
295 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
296 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
297 "idiv{l}\t$src", []>;
298 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX
299 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
300 "idiv{q}\t$src", []>;
303 //===----------------------------------------------------------------------===//
304 // Two address Instructions.
307 // unary instructions
308 let CodeSize = 2 in {
309 let Defs = [EFLAGS] in {
310 let Constraints = "$src1 = $dst" in {
311 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
313 [(set GR8:$dst, (ineg GR8:$src1)),
315 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
317 [(set GR16:$dst, (ineg GR16:$src1)),
318 (implicit EFLAGS)]>, OpSize;
319 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
321 [(set GR32:$dst, (ineg GR32:$src1)),
323 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
324 [(set GR64:$dst, (ineg GR64:$src1)),
326 } // Constraints = "$src1 = $dst"
328 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
330 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
332 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
334 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
335 (implicit EFLAGS)]>, OpSize;
336 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
338 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
340 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
341 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
346 // Note: NOT does not set EFLAGS!
348 let Constraints = "$src1 = $dst" in {
349 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
350 let AddedComplexity = 15 in {
351 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
353 [(set GR8:$dst, (not GR8:$src1))]>;
354 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
356 [(set GR16:$dst, (not GR16:$src1))]>, OpSize;
357 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
359 [(set GR32:$dst, (not GR32:$src1))]>;
360 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
361 [(set GR64:$dst, (not GR64:$src1))]>;
363 } // Constraints = "$src1 = $dst"
365 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
367 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
368 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
370 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
371 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
373 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
374 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
375 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
378 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
379 let Defs = [EFLAGS] in {
380 let Constraints = "$src1 = $dst" in {
382 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
384 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>;
386 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
387 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
389 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
390 OpSize, Requires<[In32BitMode]>;
391 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
393 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
394 Requires<[In32BitMode]>;
395 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
396 [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))]>;
397 } // isConvertibleToThreeAddress = 1, CodeSize = 1
400 // In 64-bit mode, single byte INC and DEC cannot be encoded.
401 let isConvertibleToThreeAddress = 1, CodeSize = 2 in {
402 // Can transform into LEA.
403 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
405 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
406 OpSize, Requires<[In64BitMode]>;
407 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
409 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
410 Requires<[In64BitMode]>;
411 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
413 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
414 OpSize, Requires<[In64BitMode]>;
415 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
417 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
418 Requires<[In64BitMode]>;
419 } // isConvertibleToThreeAddress = 1, CodeSize = 2
421 } // Constraints = "$src1 = $dst"
423 let CodeSize = 2 in {
424 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
425 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
427 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
428 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
430 OpSize, Requires<[In32BitMode]>;
431 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
432 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
434 Requires<[In32BitMode]>;
435 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
436 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
439 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
440 // how to unfold them.
441 // FIXME: What is this for??
442 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
443 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
445 OpSize, Requires<[In64BitMode]>;
446 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
447 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
449 Requires<[In64BitMode]>;
450 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
451 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
453 OpSize, Requires<[In64BitMode]>;
454 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
455 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
457 Requires<[In64BitMode]>;
460 let Constraints = "$src1 = $dst" in {
462 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
464 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>;
465 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
466 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
468 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
469 OpSize, Requires<[In32BitMode]>;
470 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
472 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
473 Requires<[In32BitMode]>;
474 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst",
475 [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))]>;
477 } // Constraints = "$src1 = $dst"
480 let CodeSize = 2 in {
481 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
482 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
484 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
485 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
487 OpSize, Requires<[In32BitMode]>;
488 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
489 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
491 Requires<[In32BitMode]>;
492 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
493 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
499 /// X86TypeInfo - This is a bunch of information that describes relevant X86
500 /// information about value types. For example, it can tell you what the
501 /// register class and preferred load to use.
502 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
503 PatFrag loadnode, X86MemOperand memoperand, ImmType immkind,
504 Operand immoperand, SDPatternOperator immoperator,
505 Operand imm8operand, SDPatternOperator imm8operator,
506 bit hasOddOpcode, bit hasOpSizePrefix, bit hasREX_WPrefix> {
507 /// VT - This is the value type itself.
510 /// InstrSuffix - This is the suffix used on instructions with this type. For
511 /// example, i8 -> "b", i16 -> "w", i32 -> "l", i64 -> "q".
512 string InstrSuffix = instrsuffix;
514 /// RegClass - This is the register class associated with this type. For
515 /// example, i8 -> GR8, i16 -> GR16, i32 -> GR32, i64 -> GR64.
516 RegisterClass RegClass = regclass;
518 /// LoadNode - This is the load node associated with this type. For
519 /// example, i8 -> loadi8, i16 -> loadi16, i32 -> loadi32, i64 -> loadi64.
520 PatFrag LoadNode = loadnode;
522 /// MemOperand - This is the memory operand associated with this type. For
523 /// example, i8 -> i8mem, i16 -> i16mem, i32 -> i32mem, i64 -> i64mem.
524 X86MemOperand MemOperand = memoperand;
526 /// ImmEncoding - This is the encoding of an immediate of this type. For
527 /// example, i8 -> Imm8, i16 -> Imm16, i32 -> Imm32. Note that i64 -> Imm32
528 /// since the immediate fields of i64 instructions is a 32-bit sign extended
530 ImmType ImmEncoding = immkind;
532 /// ImmOperand - This is the operand kind of an immediate of this type. For
533 /// example, i8 -> i8imm, i16 -> i16imm, i32 -> i32imm. Note that i64 ->
534 /// i64i32imm since the immediate fields of i64 instructions is a 32-bit sign
536 Operand ImmOperand = immoperand;
538 /// ImmOperator - This is the operator that should be used to match an
539 /// immediate of this kind in a pattern (e.g. imm, or i64immSExt32).
540 SDPatternOperator ImmOperator = immoperator;
542 /// Imm8Operand - This is the operand kind to use for an imm8 of this type.
543 /// For example, i8 -> <invalid>, i16 -> i16i8imm, i32 -> i32i8imm. This is
544 /// only used for instructions that have a sign-extended imm8 field form.
545 Operand Imm8Operand = imm8operand;
547 /// Imm8Operator - This is the operator that should be used to match an 8-bit
548 /// sign extended immediate of this kind in a pattern (e.g. imm16immSExt8).
549 SDPatternOperator Imm8Operator = imm8operator;
551 /// HasOddOpcode - This bit is true if the instruction should have an odd (as
552 /// opposed to even) opcode. Operations on i8 are usually even, operations on
553 /// other datatypes are odd.
554 bit HasOddOpcode = hasOddOpcode;
556 /// HasOpSizePrefix - This bit is set to true if the instruction should have
557 /// the 0x66 operand size prefix. This is set for i16 types.
558 bit HasOpSizePrefix = hasOpSizePrefix;
560 /// HasREX_WPrefix - This bit is set to true if the instruction should have
561 /// the 0x40 REX prefix. This is set for i64 types.
562 bit HasREX_WPrefix = hasREX_WPrefix;
565 def invalid_node : SDNode<"<<invalid_node>>", SDTIntLeaf,[],"<<invalid_node>>">;
568 def Xi8 : X86TypeInfo<i8 , "b", GR8 , loadi8 , i8mem ,
569 Imm8 , i8imm , imm, i8imm , invalid_node,
571 def Xi16 : X86TypeInfo<i16, "w", GR16, loadi16, i16mem,
572 Imm16, i16imm, imm, i16i8imm, i16immSExt8,
574 def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem,
575 Imm32, i32imm, imm, i32i8imm, i32immSExt8,
577 def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem,
578 Imm32, i64i32imm, i64immSExt32, i64i8imm, i64immSExt8,
581 /// ITy - This instruction base class takes the type info for the instruction.
583 /// 1. Concatenates together the instruction mnemonic with the appropriate
584 /// suffix letter, a tab, and the arguments.
585 /// 2. Infers whether the instruction should have a 0x66 prefix byte.
586 /// 3. Infers whether the instruction should have a 0x40 REX_W prefix.
587 /// 4. Infers whether the low bit of the opcode should be 0 (for i8 operations)
588 /// or 1 (for i16,i32,i64 operations).
589 class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins,
590 string mnemonic, string args, list<dag> pattern>
591 : I<{opcode{7}, opcode{6}, opcode{5}, opcode{4},
592 opcode{3}, opcode{2}, opcode{1}, typeinfo.HasOddOpcode },
594 !strconcat(mnemonic, "{", typeinfo.InstrSuffix, "}\t", args), pattern> {
596 // Infer instruction prefixes from type info.
597 let hasOpSizePrefix = typeinfo.HasOpSizePrefix;
598 let hasREX_WPrefix = typeinfo.HasREX_WPrefix;
601 // BinOpRR - Instructions like "add reg, reg, reg".
602 class BinOpRR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
604 : ITy<opcode, MRMDestReg, typeinfo,
605 (outs typeinfo.RegClass:$dst),
606 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
607 mnemonic, "{$src2, $dst|$dst, $src2}",
608 [(set typeinfo.RegClass:$dst, EFLAGS,
609 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
611 // BinOpRR_Rev - Instructions like "add reg, reg, reg" (reversed encoding).
612 class BinOpRR_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo>
613 : ITy<opcode, MRMSrcReg, typeinfo,
614 (outs typeinfo.RegClass:$dst),
615 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
616 mnemonic, "{$src2, $dst|$dst, $src2}", []> {
617 // The disassembler should know about this, but not the asmparser.
618 let isCodeGenOnly = 1;
621 // BinOpRM - Instructions like "add reg, reg, [mem]".
622 class BinOpRM<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
624 : ITy<opcode, MRMSrcMem, typeinfo,
625 (outs typeinfo.RegClass:$dst),
626 (ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2),
627 mnemonic, "{$src2, $dst|$dst, $src2}",
628 [(set typeinfo.RegClass:$dst, EFLAGS,
629 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
631 // BinOpRI - Instructions like "add reg, reg, imm".
632 class BinOpRI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
633 SDNode opnode, Format f>
634 : ITy<opcode, f, typeinfo,
635 (outs typeinfo.RegClass:$dst),
636 (ins typeinfo.RegClass:$src1, typeinfo.ImmOperand:$src2),
637 mnemonic, "{$src2, $dst|$dst, $src2}",
638 [(set typeinfo.RegClass:$dst, EFLAGS,
639 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]> {
640 let ImmT = typeinfo.ImmEncoding;
644 // BinOpRI8 - Instructions like "add reg, reg, imm8".
645 class BinOpRI8<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
646 SDNode opnode, Format f>
647 : ITy<opcode, f, typeinfo,
648 (outs typeinfo.RegClass:$dst),
649 (ins typeinfo.RegClass:$src1, typeinfo.Imm8Operand:$src2),
650 mnemonic, "{$src2, $dst|$dst, $src2}",
651 [(set typeinfo.RegClass:$dst, EFLAGS,
652 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]> {
653 let ImmT = Imm8; // Always 8-bit immediate.
656 // BinOpMR - Instructions like "add [mem], reg".
657 class BinOpMR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
659 : ITy<opcode, MRMDestMem, typeinfo,
660 (outs), (ins typeinfo.MemOperand:$dst, typeinfo.RegClass:$src),
661 mnemonic, "{$src, $dst|$dst, $src}",
662 [(store (opnode (load addr:$dst), typeinfo.RegClass:$src), addr:$dst),
665 // BinOpMI - Instructions like "add [mem], imm".
666 class BinOpMI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
667 SDNode opnode, Format f>
668 : ITy<opcode, f, typeinfo,
669 (outs), (ins typeinfo.MemOperand:$dst, typeinfo.ImmOperand:$src),
670 mnemonic, "{$src, $dst|$dst, $src}",
671 [(store (opnode (typeinfo.LoadNode addr:$dst),
672 typeinfo.ImmOperator:$src), addr:$dst),
673 (implicit EFLAGS)]> {
674 let ImmT = typeinfo.ImmEncoding;
677 // BinOpMI8 - Instructions like "add [mem], imm8".
678 class BinOpMI8<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
679 SDNode opnode, Format f>
680 : ITy<opcode, f, typeinfo,
681 (outs), (ins typeinfo.MemOperand:$dst, typeinfo.Imm8Operand:$src),
682 mnemonic, "{$src, $dst|$dst, $src}",
683 [(store (opnode (load addr:$dst),
684 typeinfo.Imm8Operator:$src), addr:$dst),
685 (implicit EFLAGS)]> {
686 let ImmT = Imm8; // Always 8-bit immediate.
689 // BinOpAI - Instructions like "add %eax, %eax, imm".
690 class BinOpAI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
692 : ITy<opcode, RawFrm, typeinfo,
693 (outs), (ins typeinfo.ImmOperand:$src),
694 mnemonic, !strconcat("{$src, %", areg.AsmName, "|%",
695 areg.AsmName, ", $src}"), []> {
696 let ImmT = typeinfo.ImmEncoding;
701 class Or2<bits<8> Val> {
702 bits<8> V = {Val{7}, Val{6}, Val{5}, Val{4}, Val{3}, Val{2}, 1, Val{0} };
704 class Or4<bits<8> Val> {
705 bits<8> V = {Val{7}, Val{6}, Val{5}, Val{4}, Val{3}, 1, Val{1}, Val{0} };
708 multiclass ArithBinOpEFLAGS<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
709 string mnemonic, Format RegMRM, Format MemMRM,
710 SDNode opnodeflag, SDNode opnode,
712 let Defs = [EFLAGS] in {
713 let Constraints = "$src1 = $dst" in {
714 let isCommutable = CommutableRR in {
715 def #NAME#8rr : BinOpRR<BaseOpc, mnemonic, Xi8 , opnodeflag>;
716 def #NAME#16rr : BinOpRR<BaseOpc, mnemonic, Xi16, opnodeflag>;
717 def #NAME#32rr : BinOpRR<BaseOpc, mnemonic, Xi32, opnodeflag>;
718 def #NAME#64rr : BinOpRR<BaseOpc, mnemonic, Xi64, opnodeflag>;
721 def #NAME#8rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi8>;
722 def #NAME#16rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi16>;
723 def #NAME#32rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi32>;
724 def #NAME#64rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi64>;
726 def #NAME#8rm : BinOpRM<BaseOpc2, mnemonic, Xi8 , opnodeflag>;
727 def #NAME#16rm : BinOpRM<BaseOpc2, mnemonic, Xi16, opnodeflag>;
728 def #NAME#32rm : BinOpRM<BaseOpc2, mnemonic, Xi32, opnodeflag>;
729 def #NAME#64rm : BinOpRM<BaseOpc2, mnemonic, Xi64, opnodeflag>;
731 def #NAME#8ri : BinOpRI<0x80, mnemonic, Xi8 , opnodeflag, RegMRM>;
732 def #NAME#16ri : BinOpRI<0x80, mnemonic, Xi16, opnodeflag, RegMRM>;
733 def #NAME#32ri : BinOpRI<0x80, mnemonic, Xi32, opnodeflag, RegMRM>;
734 def #NAME#64ri32: BinOpRI<0x80, mnemonic, Xi64, opnodeflag, RegMRM>;
736 def #NAME#16ri8 : BinOpRI8<0x82, mnemonic, Xi16, opnodeflag, RegMRM>;
737 def #NAME#32ri8 : BinOpRI8<0x82, mnemonic, Xi32, opnodeflag, RegMRM>;
738 def #NAME#64ri8 : BinOpRI8<0x82, mnemonic, Xi64, opnodeflag, RegMRM>;
739 } // Constraints = "$src1 = $dst"
741 def #NAME#8mr : BinOpMR<BaseOpc, mnemonic, Xi8 , and>;
742 def #NAME#16mr : BinOpMR<BaseOpc, mnemonic, Xi16, and>;
743 def #NAME#32mr : BinOpMR<BaseOpc, mnemonic, Xi32, and>;
744 def #NAME#64mr : BinOpMR<BaseOpc, mnemonic, Xi64, and>;
746 def #NAME#8mi : BinOpMI<0x80, mnemonic, Xi8 , and, MemMRM>;
747 def #NAME#16mi : BinOpMI<0x80, mnemonic, Xi16, and, MemMRM>;
748 def #NAME#32mi : BinOpMI<0x80, mnemonic, Xi32, and, MemMRM>;
749 def #NAME#64mi32 : BinOpMI<0x80, mnemonic, Xi64, and, MemMRM>;
751 def #NAME#16mi8 : BinOpMI8<0x82, mnemonic, Xi16, and, MemMRM>;
752 def #NAME#32mi8 : BinOpMI8<0x82, mnemonic, Xi32, and, MemMRM>;
753 def #NAME#64mi8 : BinOpMI8<0x82, mnemonic, Xi64, and, MemMRM>;
755 def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL>;
756 def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX>;
757 def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX>;
758 def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX>;
762 defm AND : ArithBinOpEFLAGS<0x20, 0x22, 0x24, "and", MRM4r, MRM4m,
763 X86and_flag, and, 1>;
768 // Logical operators.
769 let Defs = [EFLAGS] in {
771 let Constraints = "$src1 = $dst" in {
773 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
774 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
775 (ins GR8 :$src1, GR8 :$src2),
776 "or{b}\t{$src2, $dst|$dst, $src2}",
777 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
778 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
779 (ins GR16:$src1, GR16:$src2),
780 "or{w}\t{$src2, $dst|$dst, $src2}",
781 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
783 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
784 (ins GR32:$src1, GR32:$src2),
785 "or{l}\t{$src2, $dst|$dst, $src2}",
786 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
787 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst),
788 (ins GR64:$src1, GR64:$src2),
789 "or{q}\t{$src2, $dst|$dst, $src2}",
790 [(set GR64:$dst, EFLAGS,
791 (X86or_flag GR64:$src1, GR64:$src2))]>;
794 // OR instructions with the destination register in REG and the source register
795 // in R/M. Included for the disassembler.
796 let isCodeGenOnly = 1 in {
797 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
798 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
799 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
800 (ins GR16:$src1, GR16:$src2),
801 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
802 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
803 (ins GR32:$src1, GR32:$src2),
804 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
805 def OR64rr_REV : RI<0x0B, MRMSrcReg, (outs GR64:$dst),
806 (ins GR64:$src1, GR64:$src2),
807 "or{q}\t{$src2, $dst|$dst, $src2}", []>;
810 def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
811 (ins GR8 :$src1, i8mem :$src2),
812 "or{b}\t{$src2, $dst|$dst, $src2}",
813 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
814 (load addr:$src2)))]>;
815 def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
816 (ins GR16:$src1, i16mem:$src2),
817 "or{w}\t{$src2, $dst|$dst, $src2}",
818 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
819 (load addr:$src2)))]>,
821 def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
822 (ins GR32:$src1, i32mem:$src2),
823 "or{l}\t{$src2, $dst|$dst, $src2}",
824 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
825 (load addr:$src2)))]>;
826 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst),
827 (ins GR64:$src1, i64mem:$src2),
828 "or{q}\t{$src2, $dst|$dst, $src2}",
829 [(set GR64:$dst, EFLAGS,
830 (X86or_flag GR64:$src1, (load addr:$src2)))]>;
832 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
833 (ins GR8 :$src1, i8imm:$src2),
834 "or{b}\t{$src2, $dst|$dst, $src2}",
835 [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
836 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
837 (ins GR16:$src1, i16imm:$src2),
838 "or{w}\t{$src2, $dst|$dst, $src2}",
839 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
840 imm:$src2))]>, OpSize;
841 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
842 (ins GR32:$src1, i32imm:$src2),
843 "or{l}\t{$src2, $dst|$dst, $src2}",
844 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
846 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst),
847 (ins GR64:$src1, i64i32imm:$src2),
848 "or{q}\t{$src2, $dst|$dst, $src2}",
849 [(set GR64:$dst, EFLAGS,
850 (X86or_flag GR64:$src1, i64immSExt32:$src2))]>;
852 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
853 (ins GR16:$src1, i16i8imm:$src2),
854 "or{w}\t{$src2, $dst|$dst, $src2}",
855 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
856 i16immSExt8:$src2))]>, OpSize;
857 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
858 (ins GR32:$src1, i32i8imm:$src2),
859 "or{l}\t{$src2, $dst|$dst, $src2}",
860 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
861 i32immSExt8:$src2))]>;
862 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst),
863 (ins GR64:$src1, i64i8imm:$src2),
864 "or{q}\t{$src2, $dst|$dst, $src2}",
865 [(set GR64:$dst, EFLAGS,
866 (X86or_flag GR64:$src1, i64immSExt8:$src2))]>;
867 } // Constraints = "$src1 = $dst"
869 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
870 "or{b}\t{$src, $dst|$dst, $src}",
871 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
873 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
874 "or{w}\t{$src, $dst|$dst, $src}",
875 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
876 (implicit EFLAGS)]>, OpSize;
877 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
878 "or{l}\t{$src, $dst|$dst, $src}",
879 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
881 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
882 "or{q}\t{$src, $dst|$dst, $src}",
883 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
886 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
887 "or{b}\t{$src, $dst|$dst, $src}",
888 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
890 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
891 "or{w}\t{$src, $dst|$dst, $src}",
892 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
895 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
896 "or{l}\t{$src, $dst|$dst, $src}",
897 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
899 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
900 "or{q}\t{$src, $dst|$dst, $src}",
901 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
904 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
905 "or{w}\t{$src, $dst|$dst, $src}",
906 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
909 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
910 "or{l}\t{$src, $dst|$dst, $src}",
911 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
913 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
914 "or{q}\t{$src, $dst|$dst, $src}",
915 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
918 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
919 "or{b}\t{$src, %al|%al, $src}", []>;
920 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
921 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
922 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
923 "or{l}\t{$src, %eax|%eax, $src}", []>;
924 def OR64i32 : RIi32<0x0D, RawFrm, (outs), (ins i64i32imm:$src),
925 "or{q}\t{$src, %rax|%rax, $src}", []>;
928 let Constraints = "$src1 = $dst" in {
930 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
931 def XOR8rr : I<0x30, MRMDestReg,
932 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
933 "xor{b}\t{$src2, $dst|$dst, $src2}",
934 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
936 def XOR16rr : I<0x31, MRMDestReg,
937 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
938 "xor{w}\t{$src2, $dst|$dst, $src2}",
939 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
940 GR16:$src2))]>, OpSize;
941 def XOR32rr : I<0x31, MRMDestReg,
942 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
943 "xor{l}\t{$src2, $dst|$dst, $src2}",
944 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
946 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst),
947 (ins GR64:$src1, GR64:$src2),
948 "xor{q}\t{$src2, $dst|$dst, $src2}",
949 [(set GR64:$dst, EFLAGS,
950 (X86xor_flag GR64:$src1, GR64:$src2))]>;
951 } // isCommutable = 1
953 // XOR instructions with the destination register in REG and the source register
954 // in R/M. Included for the disassembler.
955 let isCodeGenOnly = 1 in {
956 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
957 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
958 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
959 (ins GR16:$src1, GR16:$src2),
960 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
961 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
962 (ins GR32:$src1, GR32:$src2),
963 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
964 def XOR64rr_REV : RI<0x33, MRMSrcReg, (outs GR64:$dst),
965 (ins GR64:$src1, GR64:$src2),
966 "xor{q}\t{$src2, $dst|$dst, $src2}", []>;
969 def XOR8rm : I<0x32, MRMSrcMem,
970 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
971 "xor{b}\t{$src2, $dst|$dst, $src2}",
972 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
973 (load addr:$src2)))]>;
974 def XOR16rm : I<0x33, MRMSrcMem,
975 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
976 "xor{w}\t{$src2, $dst|$dst, $src2}",
977 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
978 (load addr:$src2)))]>,
980 def XOR32rm : I<0x33, MRMSrcMem,
981 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
982 "xor{l}\t{$src2, $dst|$dst, $src2}",
983 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
984 (load addr:$src2)))]>;
985 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst),
986 (ins GR64:$src1, i64mem:$src2),
987 "xor{q}\t{$src2, $dst|$dst, $src2}",
988 [(set GR64:$dst, EFLAGS,
989 (X86xor_flag GR64:$src1, (load addr:$src2)))]>;
991 def XOR8ri : Ii8<0x80, MRM6r,
992 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
993 "xor{b}\t{$src2, $dst|$dst, $src2}",
994 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
995 def XOR16ri : Ii16<0x81, MRM6r,
996 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
997 "xor{w}\t{$src2, $dst|$dst, $src2}",
998 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
999 imm:$src2))]>, OpSize;
1000 def XOR32ri : Ii32<0x81, MRM6r,
1001 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1002 "xor{l}\t{$src2, $dst|$dst, $src2}",
1003 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
1005 def XOR64ri32 : RIi32<0x81, MRM6r,
1006 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1007 "xor{q}\t{$src2, $dst|$dst, $src2}",
1008 [(set GR64:$dst, EFLAGS,
1009 (X86xor_flag GR64:$src1, i64immSExt32:$src2))]>;
1011 def XOR16ri8 : Ii8<0x83, MRM6r,
1012 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1013 "xor{w}\t{$src2, $dst|$dst, $src2}",
1014 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
1015 i16immSExt8:$src2))]>,
1017 def XOR32ri8 : Ii8<0x83, MRM6r,
1018 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1019 "xor{l}\t{$src2, $dst|$dst, $src2}",
1020 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
1021 i32immSExt8:$src2))]>;
1022 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst),
1023 (ins GR64:$src1, i64i8imm:$src2),
1024 "xor{q}\t{$src2, $dst|$dst, $src2}",
1025 [(set GR64:$dst, EFLAGS,
1026 (X86xor_flag GR64:$src1, i64immSExt8:$src2))]>;
1027 } // Constraints = "$src1 = $dst"
1030 def XOR8mr : I<0x30, MRMDestMem,
1031 (outs), (ins i8mem :$dst, GR8 :$src),
1032 "xor{b}\t{$src, $dst|$dst, $src}",
1033 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
1034 (implicit EFLAGS)]>;
1035 def XOR16mr : I<0x31, MRMDestMem,
1036 (outs), (ins i16mem:$dst, GR16:$src),
1037 "xor{w}\t{$src, $dst|$dst, $src}",
1038 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
1039 (implicit EFLAGS)]>,
1041 def XOR32mr : I<0x31, MRMDestMem,
1042 (outs), (ins i32mem:$dst, GR32:$src),
1043 "xor{l}\t{$src, $dst|$dst, $src}",
1044 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
1045 (implicit EFLAGS)]>;
1046 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1047 "xor{q}\t{$src, $dst|$dst, $src}",
1048 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
1049 (implicit EFLAGS)]>;
1051 def XOR8mi : Ii8<0x80, MRM6m,
1052 (outs), (ins i8mem :$dst, i8imm :$src),
1053 "xor{b}\t{$src, $dst|$dst, $src}",
1054 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
1055 (implicit EFLAGS)]>;
1056 def XOR16mi : Ii16<0x81, MRM6m,
1057 (outs), (ins i16mem:$dst, i16imm:$src),
1058 "xor{w}\t{$src, $dst|$dst, $src}",
1059 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
1060 (implicit EFLAGS)]>,
1062 def XOR32mi : Ii32<0x81, MRM6m,
1063 (outs), (ins i32mem:$dst, i32imm:$src),
1064 "xor{l}\t{$src, $dst|$dst, $src}",
1065 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
1066 (implicit EFLAGS)]>;
1067 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1068 "xor{q}\t{$src, $dst|$dst, $src}",
1069 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1070 (implicit EFLAGS)]>;
1072 def XOR16mi8 : Ii8<0x83, MRM6m,
1073 (outs), (ins i16mem:$dst, i16i8imm :$src),
1074 "xor{w}\t{$src, $dst|$dst, $src}",
1075 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
1076 (implicit EFLAGS)]>,
1078 def XOR32mi8 : Ii8<0x83, MRM6m,
1079 (outs), (ins i32mem:$dst, i32i8imm :$src),
1080 "xor{l}\t{$src, $dst|$dst, $src}",
1081 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
1082 (implicit EFLAGS)]>;
1083 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
1084 "xor{q}\t{$src, $dst|$dst, $src}",
1085 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
1086 (implicit EFLAGS)]>;
1088 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
1089 "xor{b}\t{$src, %al|%al, $src}", []>;
1090 def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
1091 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1092 def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
1093 "xor{l}\t{$src, %eax|%eax, $src}", []>;
1094 def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i64i32imm:$src),
1095 "xor{q}\t{$src, %rax|%rax, $src}", []>;
1096 } // Defs = [EFLAGS]
1100 let Defs = [EFLAGS] in {
1101 let Constraints = "$src1 = $dst" in {
1102 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1103 // Register-Register Addition
1104 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
1105 (ins GR8 :$src1, GR8 :$src2),
1106 "add{b}\t{$src2, $dst|$dst, $src2}",
1107 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
1109 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1110 // Register-Register Addition
1111 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
1112 (ins GR16:$src1, GR16:$src2),
1113 "add{w}\t{$src2, $dst|$dst, $src2}",
1114 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
1115 GR16:$src2))]>, OpSize;
1116 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
1117 (ins GR32:$src1, GR32:$src2),
1118 "add{l}\t{$src2, $dst|$dst, $src2}",
1119 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
1121 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst),
1122 (ins GR64:$src1, GR64:$src2),
1123 "add{q}\t{$src2, $dst|$dst, $src2}",
1124 [(set GR64:$dst, EFLAGS,
1125 (X86add_flag GR64:$src1, GR64:$src2))]>;
1126 } // end isConvertibleToThreeAddress
1127 } // end isCommutable
1129 // These are alternate spellings for use by the disassembler, we mark them as
1130 // code gen only to ensure they aren't matched by the assembler.
1131 let isCodeGenOnly = 1 in {
1132 def ADD8rr_alt: I<0x02, MRMSrcReg,
1133 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1134 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
1135 def ADD16rr_alt: I<0x03, MRMSrcReg,
1136 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1137 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1138 def ADD32rr_alt: I<0x03, MRMSrcReg,
1139 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1140 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
1141 def ADD64rr_alt : RI<0x03, MRMSrcReg,
1142 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1143 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
1146 // Register-Memory Addition
1147 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
1148 (ins GR8 :$src1, i8mem :$src2),
1149 "add{b}\t{$src2, $dst|$dst, $src2}",
1150 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
1151 (load addr:$src2)))]>;
1152 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
1153 (ins GR16:$src1, i16mem:$src2),
1154 "add{w}\t{$src2, $dst|$dst, $src2}",
1155 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
1156 (load addr:$src2)))]>, OpSize;
1157 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
1158 (ins GR32:$src1, i32mem:$src2),
1159 "add{l}\t{$src2, $dst|$dst, $src2}",
1160 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
1161 (load addr:$src2)))]>;
1162 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst),
1163 (ins GR64:$src1, i64mem:$src2),
1164 "add{q}\t{$src2, $dst|$dst, $src2}",
1165 [(set GR64:$dst, EFLAGS,
1166 (X86add_flag GR64:$src1, (load addr:$src2)))]>;
1168 // Register-Integer Addition
1169 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1170 "add{b}\t{$src2, $dst|$dst, $src2}",
1171 [(set GR8:$dst, EFLAGS,
1172 (X86add_flag GR8:$src1, imm:$src2))]>;
1174 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1175 // Register-Integer Addition
1176 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
1177 (ins GR16:$src1, i16imm:$src2),
1178 "add{w}\t{$src2, $dst|$dst, $src2}",
1179 [(set GR16:$dst, EFLAGS,
1180 (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
1181 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
1182 (ins GR32:$src1, i32imm:$src2),
1183 "add{l}\t{$src2, $dst|$dst, $src2}",
1184 [(set GR32:$dst, EFLAGS,
1185 (X86add_flag GR32:$src1, imm:$src2))]>;
1186 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
1187 (ins GR16:$src1, i16i8imm:$src2),
1188 "add{w}\t{$src2, $dst|$dst, $src2}",
1189 [(set GR16:$dst, EFLAGS,
1190 (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1191 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
1192 (ins GR32:$src1, i32i8imm:$src2),
1193 "add{l}\t{$src2, $dst|$dst, $src2}",
1194 [(set GR32:$dst, EFLAGS,
1195 (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
1196 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst),
1197 (ins GR64:$src1, i64i8imm:$src2),
1198 "add{q}\t{$src2, $dst|$dst, $src2}",
1199 [(set GR64:$dst, EFLAGS,
1200 (X86add_flag GR64:$src1, i64immSExt8:$src2))]>;
1201 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst),
1202 (ins GR64:$src1, i64i32imm:$src2),
1203 "add{q}\t{$src2, $dst|$dst, $src2}",
1204 [(set GR64:$dst, EFLAGS,
1205 (X86add_flag GR64:$src1, i64immSExt32:$src2))]>;
1207 } // Constraints = "$src1 = $dst"
1209 // Memory-Register Addition
1210 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
1211 "add{b}\t{$src2, $dst|$dst, $src2}",
1212 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
1213 (implicit EFLAGS)]>;
1214 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1215 "add{w}\t{$src2, $dst|$dst, $src2}",
1216 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
1217 (implicit EFLAGS)]>, OpSize;
1218 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1219 "add{l}\t{$src2, $dst|$dst, $src2}",
1220 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
1221 (implicit EFLAGS)]>;
1222 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1223 "add{q}\t{$src2, $dst|$dst, $src2}",
1224 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
1225 (implicit EFLAGS)]>;
1226 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
1227 "add{b}\t{$src2, $dst|$dst, $src2}",
1228 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
1229 (implicit EFLAGS)]>;
1230 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
1231 "add{w}\t{$src2, $dst|$dst, $src2}",
1232 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
1233 (implicit EFLAGS)]>, OpSize;
1234 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
1235 "add{l}\t{$src2, $dst|$dst, $src2}",
1236 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
1237 (implicit EFLAGS)]>;
1238 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
1239 "add{q}\t{$src2, $dst|$dst, $src2}",
1240 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
1241 (implicit EFLAGS)]>;
1242 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1243 "add{w}\t{$src2, $dst|$dst, $src2}",
1244 [(store (add (load addr:$dst), i16immSExt8:$src2),
1246 (implicit EFLAGS)]>, OpSize;
1247 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1248 "add{l}\t{$src2, $dst|$dst, $src2}",
1249 [(store (add (load addr:$dst), i32immSExt8:$src2),
1251 (implicit EFLAGS)]>;
1252 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1253 "add{q}\t{$src2, $dst|$dst, $src2}",
1254 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
1255 (implicit EFLAGS)]>;
1258 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
1259 "add{b}\t{$src, %al|%al, $src}", []>;
1260 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
1261 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1262 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
1263 "add{l}\t{$src, %eax|%eax, $src}", []>;
1264 def ADD64i32 : RIi32<0x05, RawFrm, (outs), (ins i64i32imm:$src),
1265 "add{q}\t{$src, %rax|%rax, $src}", []>;
1267 let Uses = [EFLAGS] in {
1268 let Constraints = "$src1 = $dst" in {
1269 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1270 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1271 "adc{b}\t{$src2, $dst|$dst, $src2}",
1272 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
1273 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
1274 (ins GR16:$src1, GR16:$src2),
1275 "adc{w}\t{$src2, $dst|$dst, $src2}",
1276 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
1277 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
1278 (ins GR32:$src1, GR32:$src2),
1279 "adc{l}\t{$src2, $dst|$dst, $src2}",
1280 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
1281 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst),
1282 (ins GR64:$src1, GR64:$src2),
1283 "adc{q}\t{$src2, $dst|$dst, $src2}",
1284 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
1287 let isCodeGenOnly = 1 in {
1288 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1289 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
1290 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
1291 (ins GR16:$src1, GR16:$src2),
1292 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1293 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
1294 (ins GR32:$src1, GR32:$src2),
1295 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
1296 def ADC64rr_REV : RI<0x13, MRMSrcReg , (outs GR32:$dst),
1297 (ins GR64:$src1, GR64:$src2),
1298 "adc{q}\t{$src2, $dst|$dst, $src2}", []>;
1301 def ADC8rm : I<0x12, MRMSrcMem ,
1302 (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
1303 "adc{b}\t{$src2, $dst|$dst, $src2}",
1304 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
1305 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
1306 (ins GR16:$src1, i16mem:$src2),
1307 "adc{w}\t{$src2, $dst|$dst, $src2}",
1308 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
1310 def ADC32rm : I<0x13, MRMSrcMem ,
1311 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1312 "adc{l}\t{$src2, $dst|$dst, $src2}",
1313 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
1314 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst),
1315 (ins GR64:$src1, i64mem:$src2),
1316 "adc{q}\t{$src2, $dst|$dst, $src2}",
1317 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
1318 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1319 "adc{b}\t{$src2, $dst|$dst, $src2}",
1320 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
1321 def ADC16ri : Ii16<0x81, MRM2r,
1322 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1323 "adc{w}\t{$src2, $dst|$dst, $src2}",
1324 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
1325 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
1326 (ins GR16:$src1, i16i8imm:$src2),
1327 "adc{w}\t{$src2, $dst|$dst, $src2}",
1328 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
1330 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
1331 (ins GR32:$src1, i32imm:$src2),
1332 "adc{l}\t{$src2, $dst|$dst, $src2}",
1333 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
1334 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
1335 (ins GR32:$src1, i32i8imm:$src2),
1336 "adc{l}\t{$src2, $dst|$dst, $src2}",
1337 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
1338 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst),
1339 (ins GR64:$src1, i64i32imm:$src2),
1340 "adc{q}\t{$src2, $dst|$dst, $src2}",
1341 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
1342 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst),
1343 (ins GR64:$src1, i64i8imm:$src2),
1344 "adc{q}\t{$src2, $dst|$dst, $src2}",
1345 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
1346 } // Constraints = "$src1 = $dst"
1348 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
1349 "adc{b}\t{$src2, $dst|$dst, $src2}",
1350 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
1351 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1352 "adc{w}\t{$src2, $dst|$dst, $src2}",
1353 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
1355 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1356 "adc{l}\t{$src2, $dst|$dst, $src2}",
1357 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
1358 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1359 "adc{q}\t{$src2, $dst|$dst, $src2}",
1360 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
1361 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
1362 "adc{b}\t{$src2, $dst|$dst, $src2}",
1363 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1364 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
1365 "adc{w}\t{$src2, $dst|$dst, $src2}",
1366 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1368 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1369 "adc{w}\t{$src2, $dst|$dst, $src2}",
1370 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1372 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
1373 "adc{l}\t{$src2, $dst|$dst, $src2}",
1374 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1375 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1376 "adc{l}\t{$src2, $dst|$dst, $src2}",
1377 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1379 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
1380 "adc{q}\t{$src2, $dst|$dst, $src2}",
1381 [(store (adde (load addr:$dst), i64immSExt32:$src2),
1383 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1384 "adc{q}\t{$src2, $dst|$dst, $src2}",
1385 [(store (adde (load addr:$dst), i64immSExt8:$src2),
1388 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
1389 "adc{b}\t{$src, %al|%al, $src}", []>;
1390 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
1391 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1392 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
1393 "adc{l}\t{$src, %eax|%eax, $src}", []>;
1394 def ADC64i32 : RIi32<0x15, RawFrm, (outs), (ins i64i32imm:$src),
1395 "adc{q}\t{$src, %rax|%rax, $src}", []>;
1396 } // Uses = [EFLAGS]
1398 let Constraints = "$src1 = $dst" in {
1400 // Register-Register Subtraction
1401 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1402 "sub{b}\t{$src2, $dst|$dst, $src2}",
1403 [(set GR8:$dst, EFLAGS,
1404 (X86sub_flag GR8:$src1, GR8:$src2))]>;
1405 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
1406 "sub{w}\t{$src2, $dst|$dst, $src2}",
1407 [(set GR16:$dst, EFLAGS,
1408 (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
1409 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
1410 "sub{l}\t{$src2, $dst|$dst, $src2}",
1411 [(set GR32:$dst, EFLAGS,
1412 (X86sub_flag GR32:$src1, GR32:$src2))]>;
1413 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst),
1414 (ins GR64:$src1, GR64:$src2),
1415 "sub{q}\t{$src2, $dst|$dst, $src2}",
1416 [(set GR64:$dst, EFLAGS,
1417 (X86sub_flag GR64:$src1, GR64:$src2))]>;
1419 let isCodeGenOnly = 1 in {
1420 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1421 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
1422 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
1423 (ins GR16:$src1, GR16:$src2),
1424 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1425 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
1426 (ins GR32:$src1, GR32:$src2),
1427 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
1428 def SUB64rr_REV : RI<0x2B, MRMSrcReg, (outs GR64:$dst),
1429 (ins GR64:$src1, GR64:$src2),
1430 "sub{q}\t{$src2, $dst|$dst, $src2}", []>;
1433 // Register-Memory Subtraction
1434 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
1435 (ins GR8 :$src1, i8mem :$src2),
1436 "sub{b}\t{$src2, $dst|$dst, $src2}",
1437 [(set GR8:$dst, EFLAGS,
1438 (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
1439 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
1440 (ins GR16:$src1, i16mem:$src2),
1441 "sub{w}\t{$src2, $dst|$dst, $src2}",
1442 [(set GR16:$dst, EFLAGS,
1443 (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
1444 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
1445 (ins GR32:$src1, i32mem:$src2),
1446 "sub{l}\t{$src2, $dst|$dst, $src2}",
1447 [(set GR32:$dst, EFLAGS,
1448 (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
1449 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst),
1450 (ins GR64:$src1, i64mem:$src2),
1451 "sub{q}\t{$src2, $dst|$dst, $src2}",
1452 [(set GR64:$dst, EFLAGS,
1453 (X86sub_flag GR64:$src1, (load addr:$src2)))]>;
1455 // Register-Integer Subtraction
1456 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
1457 (ins GR8:$src1, i8imm:$src2),
1458 "sub{b}\t{$src2, $dst|$dst, $src2}",
1459 [(set GR8:$dst, EFLAGS,
1460 (X86sub_flag GR8:$src1, imm:$src2))]>;
1461 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
1462 (ins GR16:$src1, i16imm:$src2),
1463 "sub{w}\t{$src2, $dst|$dst, $src2}",
1464 [(set GR16:$dst, EFLAGS,
1465 (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
1466 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
1467 (ins GR32:$src1, i32imm:$src2),
1468 "sub{l}\t{$src2, $dst|$dst, $src2}",
1469 [(set GR32:$dst, EFLAGS,
1470 (X86sub_flag GR32:$src1, imm:$src2))]>;
1471 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
1472 (ins GR64:$src1, i64i32imm:$src2),
1473 "sub{q}\t{$src2, $dst|$dst, $src2}",
1474 [(set GR64:$dst, EFLAGS,
1475 (X86sub_flag GR64:$src1, i64immSExt32:$src2))]>;
1476 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
1477 (ins GR16:$src1, i16i8imm:$src2),
1478 "sub{w}\t{$src2, $dst|$dst, $src2}",
1479 [(set GR16:$dst, EFLAGS,
1480 (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1481 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
1482 (ins GR32:$src1, i32i8imm:$src2),
1483 "sub{l}\t{$src2, $dst|$dst, $src2}",
1484 [(set GR32:$dst, EFLAGS,
1485 (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
1486 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
1487 (ins GR64:$src1, i64i8imm:$src2),
1488 "sub{q}\t{$src2, $dst|$dst, $src2}",
1489 [(set GR64:$dst, EFLAGS,
1490 (X86sub_flag GR64:$src1, i64immSExt8:$src2))]>;
1491 } // Constraints = "$src1 = $dst"
1493 // Memory-Register Subtraction
1494 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1495 "sub{b}\t{$src2, $dst|$dst, $src2}",
1496 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
1497 (implicit EFLAGS)]>;
1498 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1499 "sub{w}\t{$src2, $dst|$dst, $src2}",
1500 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
1501 (implicit EFLAGS)]>, OpSize;
1502 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1503 "sub{l}\t{$src2, $dst|$dst, $src2}",
1504 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
1505 (implicit EFLAGS)]>;
1506 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1507 "sub{q}\t{$src2, $dst|$dst, $src2}",
1508 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
1509 (implicit EFLAGS)]>;
1511 // Memory-Integer Subtraction
1512 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
1513 "sub{b}\t{$src2, $dst|$dst, $src2}",
1514 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
1515 (implicit EFLAGS)]>;
1516 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
1517 "sub{w}\t{$src2, $dst|$dst, $src2}",
1518 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
1519 (implicit EFLAGS)]>, OpSize;
1520 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
1521 "sub{l}\t{$src2, $dst|$dst, $src2}",
1522 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
1523 (implicit EFLAGS)]>;
1524 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
1525 "sub{q}\t{$src2, $dst|$dst, $src2}",
1526 [(store (sub (load addr:$dst), i64immSExt32:$src2),
1528 (implicit EFLAGS)]>;
1529 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1530 "sub{w}\t{$src2, $dst|$dst, $src2}",
1531 [(store (sub (load addr:$dst), i16immSExt8:$src2),
1533 (implicit EFLAGS)]>, OpSize;
1534 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1535 "sub{l}\t{$src2, $dst|$dst, $src2}",
1536 [(store (sub (load addr:$dst), i32immSExt8:$src2),
1538 (implicit EFLAGS)]>;
1539 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1540 "sub{q}\t{$src2, $dst|$dst, $src2}",
1541 [(store (sub (load addr:$dst), i64immSExt8:$src2),
1543 (implicit EFLAGS)]>;
1545 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
1546 "sub{b}\t{$src, %al|%al, $src}", []>;
1547 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
1548 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1549 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
1550 "sub{l}\t{$src, %eax|%eax, $src}", []>;
1551 def SUB64i32 : RIi32<0x2D, RawFrm, (outs), (ins i64i32imm:$src),
1552 "sub{q}\t{$src, %rax|%rax, $src}", []>;
1554 let Uses = [EFLAGS] in {
1555 let Constraints = "$src1 = $dst" in {
1556 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
1557 (ins GR8:$src1, GR8:$src2),
1558 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1559 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
1560 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
1561 (ins GR16:$src1, GR16:$src2),
1562 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1563 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
1564 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
1565 (ins GR32:$src1, GR32:$src2),
1566 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1567 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
1568 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst),
1569 (ins GR64:$src1, GR64:$src2),
1570 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1571 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
1572 } // Constraints = "$src1 = $dst"
1575 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
1576 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1577 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
1578 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1579 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1580 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
1582 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1583 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1584 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
1585 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1586 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1587 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
1589 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
1590 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1591 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1592 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
1593 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1594 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1596 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1597 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1598 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1600 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
1601 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1602 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1603 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1604 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1605 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1606 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
1607 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1608 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
1609 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1610 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1611 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
1613 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
1614 "sbb{b}\t{$src, %al|%al, $src}", []>;
1615 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
1616 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1617 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
1618 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
1619 def SBB64i32 : RIi32<0x1D, RawFrm, (outs), (ins i64i32imm:$src),
1620 "sbb{q}\t{$src, %rax|%rax, $src}", []>;
1622 let Constraints = "$src1 = $dst" in {
1624 let isCodeGenOnly = 1 in {
1625 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1626 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
1627 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
1628 (ins GR16:$src1, GR16:$src2),
1629 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1630 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
1631 (ins GR32:$src1, GR32:$src2),
1632 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
1633 def SBB64rr_REV : RI<0x1B, MRMSrcReg, (outs GR64:$dst),
1634 (ins GR64:$src1, GR64:$src2),
1635 "sbb{q}\t{$src2, $dst|$dst, $src2}", []>;
1638 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
1639 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1640 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
1641 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
1642 (ins GR16:$src1, i16mem:$src2),
1643 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1644 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
1646 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
1647 (ins GR32:$src1, i32mem:$src2),
1648 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1649 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
1650 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst),
1651 (ins GR64:$src1, i64mem:$src2),
1652 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1653 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
1654 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1655 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1656 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
1657 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
1658 (ins GR16:$src1, i16imm:$src2),
1659 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1660 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
1661 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
1662 (ins GR16:$src1, i16i8imm:$src2),
1663 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1664 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
1666 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
1667 (ins GR32:$src1, i32imm:$src2),
1668 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1669 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
1670 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
1671 (ins GR32:$src1, i32i8imm:$src2),
1672 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1673 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
1674 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst),
1675 (ins GR64:$src1, i64i32imm:$src2),
1676 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1677 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
1678 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst),
1679 (ins GR64:$src1, i64i8imm:$src2),
1680 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1681 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
1683 } // Constraints = "$src1 = $dst"
1684 } // Uses = [EFLAGS]
1685 } // Defs = [EFLAGS]
1687 //===----------------------------------------------------------------------===//
1688 // Test instructions are just like AND, except they don't generate a result.
1690 let Defs = [EFLAGS] in {
1691 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
1692 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
1693 "test{b}\t{$src2, $src1|$src1, $src2}",
1694 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
1695 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
1696 "test{w}\t{$src2, $src1|$src1, $src2}",
1697 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
1700 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
1701 "test{l}\t{$src2, $src1|$src1, $src2}",
1702 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
1704 def TEST64rr : RI<0x85, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1705 "test{q}\t{$src2, $src1|$src1, $src2}",
1706 [(set EFLAGS, (X86cmp (and GR64:$src1, GR64:$src2), 0))]>;
1709 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
1710 "test{b}\t{$src2, $src1|$src1, $src2}",
1711 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
1713 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
1714 "test{w}\t{$src2, $src1|$src1, $src2}",
1715 [(set EFLAGS, (X86cmp (and GR16:$src1,
1716 (loadi16 addr:$src2)), 0))]>, OpSize;
1717 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
1718 "test{l}\t{$src2, $src1|$src1, $src2}",
1719 [(set EFLAGS, (X86cmp (and GR32:$src1,
1720 (loadi32 addr:$src2)), 0))]>;
1721 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1722 "test{q}\t{$src2, $src1|$src1, $src2}",
1723 [(set EFLAGS, (X86cmp (and GR64:$src1, (loadi64 addr:$src2)),
1726 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
1727 (outs), (ins GR8:$src1, i8imm:$src2),
1728 "test{b}\t{$src2, $src1|$src1, $src2}",
1729 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
1730 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
1731 (outs), (ins GR16:$src1, i16imm:$src2),
1732 "test{w}\t{$src2, $src1|$src1, $src2}",
1733 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
1735 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
1736 (outs), (ins GR32:$src1, i32imm:$src2),
1737 "test{l}\t{$src2, $src1|$src1, $src2}",
1738 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
1739 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1740 (ins GR64:$src1, i64i32imm:$src2),
1741 "test{q}\t{$src2, $src1|$src1, $src2}",
1742 [(set EFLAGS, (X86cmp (and GR64:$src1, i64immSExt32:$src2),
1745 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
1746 (outs), (ins i8mem:$src1, i8imm:$src2),
1747 "test{b}\t{$src2, $src1|$src1, $src2}",
1748 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
1750 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
1751 (outs), (ins i16mem:$src1, i16imm:$src2),
1752 "test{w}\t{$src2, $src1|$src1, $src2}",
1753 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
1755 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
1756 (outs), (ins i32mem:$src1, i32imm:$src2),
1757 "test{l}\t{$src2, $src1|$src1, $src2}",
1758 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
1760 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1761 (ins i64mem:$src1, i64i32imm:$src2),
1762 "test{q}\t{$src2, $src1|$src1, $src2}",
1763 [(set EFLAGS, (X86cmp (and (loadi64 addr:$src1),
1764 i64immSExt32:$src2), 0))]>;
1766 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
1767 "test{b}\t{$src, %al|%al, $src}", []>;
1768 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
1769 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1770 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
1771 "test{l}\t{$src, %eax|%eax, $src}", []>;
1772 def TEST64i32 : RIi32<0xa9, RawFrm, (outs), (ins i64i32imm:$src),
1773 "test{q}\t{$src, %rax|%rax, $src}", []>;
1775 } // Defs = [EFLAGS]
1778 //===----------------------------------------------------------------------===//
1779 // Integer comparisons
1781 let Defs = [EFLAGS] in {
1783 def CMP8rr : I<0x38, MRMDestReg,
1784 (outs), (ins GR8 :$src1, GR8 :$src2),
1785 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1786 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
1787 def CMP16rr : I<0x39, MRMDestReg,
1788 (outs), (ins GR16:$src1, GR16:$src2),
1789 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1790 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
1791 def CMP32rr : I<0x39, MRMDestReg,
1792 (outs), (ins GR32:$src1, GR32:$src2),
1793 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1794 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
1795 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1796 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1797 [(set EFLAGS, (X86cmp GR64:$src1, GR64:$src2))]>;
1799 def CMP8mr : I<0x38, MRMDestMem,
1800 (outs), (ins i8mem :$src1, GR8 :$src2),
1801 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1802 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
1803 def CMP16mr : I<0x39, MRMDestMem,
1804 (outs), (ins i16mem:$src1, GR16:$src2),
1805 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1806 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
1808 def CMP32mr : I<0x39, MRMDestMem,
1809 (outs), (ins i32mem:$src1, GR32:$src2),
1810 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1811 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
1812 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1813 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1814 [(set EFLAGS, (X86cmp (loadi64 addr:$src1), GR64:$src2))]>;
1816 def CMP8rm : I<0x3A, MRMSrcMem,
1817 (outs), (ins GR8 :$src1, i8mem :$src2),
1818 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1819 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
1820 def CMP16rm : I<0x3B, MRMSrcMem,
1821 (outs), (ins GR16:$src1, i16mem:$src2),
1822 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1823 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
1825 def CMP32rm : I<0x3B, MRMSrcMem,
1826 (outs), (ins GR32:$src1, i32mem:$src2),
1827 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1828 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
1829 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1830 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1831 [(set EFLAGS, (X86cmp GR64:$src1, (loadi64 addr:$src2)))]>;
1833 // These are alternate spellings for use by the disassembler, we mark them as
1834 // code gen only to ensure they aren't matched by the assembler.
1835 let isCodeGenOnly = 1 in {
1836 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
1837 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
1838 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
1839 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
1840 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
1841 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
1842 def CMP64rr_alt : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1843 "cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
1846 def CMP8ri : Ii8<0x80, MRM7r,
1847 (outs), (ins GR8:$src1, i8imm:$src2),
1848 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1849 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
1850 def CMP16ri : Ii16<0x81, MRM7r,
1851 (outs), (ins GR16:$src1, i16imm:$src2),
1852 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1853 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
1854 def CMP32ri : Ii32<0x81, MRM7r,
1855 (outs), (ins GR32:$src1, i32imm:$src2),
1856 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1857 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
1858 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1859 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1860 [(set EFLAGS, (X86cmp GR64:$src1, i64immSExt32:$src2))]>;
1862 def CMP8mi : Ii8 <0x80, MRM7m,
1863 (outs), (ins i8mem :$src1, i8imm :$src2),
1864 "cmp{b}\t{$src2, $src1|$src1, $src2}",
1865 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
1866 def CMP16mi : Ii16<0x81, MRM7m,
1867 (outs), (ins i16mem:$src1, i16imm:$src2),
1868 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1869 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
1871 def CMP32mi : Ii32<0x81, MRM7m,
1872 (outs), (ins i32mem:$src1, i32imm:$src2),
1873 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1874 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
1875 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1876 (ins i64mem:$src1, i64i32imm:$src2),
1877 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1878 [(set EFLAGS, (X86cmp (loadi64 addr:$src1),
1879 i64immSExt32:$src2))]>;
1881 def CMP16ri8 : Ii8<0x83, MRM7r,
1882 (outs), (ins GR16:$src1, i16i8imm:$src2),
1883 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1884 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
1886 def CMP32ri8 : Ii8<0x83, MRM7r,
1887 (outs), (ins GR32:$src1, i32i8imm:$src2),
1888 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1889 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
1890 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1891 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1892 [(set EFLAGS, (X86cmp GR64:$src1, i64immSExt8:$src2))]>;
1894 def CMP16mi8 : Ii8<0x83, MRM7m,
1895 (outs), (ins i16mem:$src1, i16i8imm:$src2),
1896 "cmp{w}\t{$src2, $src1|$src1, $src2}",
1897 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
1898 i16immSExt8:$src2))]>, OpSize;
1899 def CMP32mi8 : Ii8<0x83, MRM7m,
1900 (outs), (ins i32mem:$src1, i32i8imm:$src2),
1901 "cmp{l}\t{$src2, $src1|$src1, $src2}",
1902 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
1903 i32immSExt8:$src2))]>;
1904 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1905 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1906 [(set EFLAGS, (X86cmp (loadi64 addr:$src1),
1907 i64immSExt8:$src2))]>;
1909 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
1910 "cmp{b}\t{$src, %al|%al, $src}", []>;
1911 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
1912 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1913 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
1914 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
1915 def CMP64i32 : RIi32<0x3D, RawFrm, (outs), (ins i64i32imm:$src),
1916 "cmp{q}\t{$src, %rax|%rax, $src}", []>;
1918 } // Defs = [EFLAGS]