1 //===-- X86InstrArithmetic.td - Integer Arithmetic Instrs --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the integer arithmetic instructions in the X86
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // LEA - Load Effective Address
18 let neverHasSideEffects = 1 in
19 def LEA16r : I<0x8D, MRMSrcMem,
20 (outs GR16:$dst), (ins i32mem:$src),
21 "lea{w}\t{$src|$dst}, {$dst|$src}", [], IIC_LEA_16>, OpSize;
22 let isReMaterializable = 1 in
23 def LEA32r : I<0x8D, MRMSrcMem,
24 (outs GR32:$dst), (ins i32mem:$src),
25 "lea{l}\t{$src|$dst}, {$dst|$src}",
26 [(set GR32:$dst, lea32addr:$src)], IIC_LEA>,
27 Requires<[In32BitMode]>;
29 def LEA64_32r : I<0x8D, MRMSrcMem,
30 (outs GR32:$dst), (ins lea64_32mem:$src),
31 "lea{l}\t{$src|$dst}, {$dst|$src}",
32 [(set GR32:$dst, lea32addr:$src)], IIC_LEA>,
33 Requires<[In64BitMode]>;
35 let isReMaterializable = 1 in
36 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
37 "lea{q}\t{$src|$dst}, {$dst|$src}",
38 [(set GR64:$dst, lea64addr:$src)], IIC_LEA>;
42 //===----------------------------------------------------------------------===//
43 // Fixed-Register Multiplication and Division Instructions.
46 // Extra precision multiplication
48 // AL is really implied by AX, but the registers in Defs must match the
49 // SDNode results (i8, i32).
50 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
51 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
52 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
53 // This probably ought to be moved to a def : Pat<> if the
54 // syntax can be accepted.
55 [(set AL, (mul AL, GR8:$src)),
56 (implicit EFLAGS)]>; // AL,AH = AL*GR8
58 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
59 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
61 [], IIC_MUL16_REG>, OpSize; // AX,DX = AX*GR16
63 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
64 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
65 "mul{l}\t$src", // EAX,EDX = EAX*GR32
66 [/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/],
68 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
69 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
70 "mul{q}\t$src", // RAX,RDX = RAX*GR64
71 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/],
74 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
75 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
77 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
78 // This probably ought to be moved to a def : Pat<> if the
79 // syntax can be accepted.
80 [(set AL, (mul AL, (loadi8 addr:$src))),
81 (implicit EFLAGS)], IIC_MUL8>; // AL,AH = AL*[mem8]
83 let mayLoad = 1, neverHasSideEffects = 1 in {
84 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
85 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
87 [], IIC_MUL16_MEM>, OpSize; // AX,DX = AX*[mem16]
89 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
90 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
92 [], IIC_MUL32_MEM>; // EAX,EDX = EAX*[mem32]
93 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
94 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
95 "mul{q}\t$src", [], IIC_MUL64>; // RAX,RDX = RAX*[mem64]
98 let neverHasSideEffects = 1 in {
99 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
100 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
102 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
103 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
104 OpSize; // AX,DX = AX*GR16
105 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
106 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
107 // EAX,EDX = EAX*GR32
108 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
109 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", []>;
110 // RAX,RDX = RAX*GR64
113 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
114 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
115 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
116 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
117 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
118 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
119 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
120 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
121 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
122 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
123 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
124 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
126 } // neverHasSideEffects
129 let Defs = [EFLAGS] in {
130 let Constraints = "$src1 = $dst" in {
132 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
133 // Register-Register Signed Integer Multiply
134 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
135 "imul{w}\t{$src2, $dst|$dst, $src2}",
136 [(set GR16:$dst, EFLAGS,
137 (X86smul_flag GR16:$src1, GR16:$src2))], IIC_IMUL16_RR>,
139 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
140 "imul{l}\t{$src2, $dst|$dst, $src2}",
141 [(set GR32:$dst, EFLAGS,
142 (X86smul_flag GR32:$src1, GR32:$src2))], IIC_IMUL32_RR>,
144 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
145 (ins GR64:$src1, GR64:$src2),
146 "imul{q}\t{$src2, $dst|$dst, $src2}",
147 [(set GR64:$dst, EFLAGS,
148 (X86smul_flag GR64:$src1, GR64:$src2))], IIC_IMUL64_RR>,
152 // Register-Memory Signed Integer Multiply
153 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
154 (ins GR16:$src1, i16mem:$src2),
155 "imul{w}\t{$src2, $dst|$dst, $src2}",
156 [(set GR16:$dst, EFLAGS,
157 (X86smul_flag GR16:$src1, (load addr:$src2)))],
160 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
161 (ins GR32:$src1, i32mem:$src2),
162 "imul{l}\t{$src2, $dst|$dst, $src2}",
163 [(set GR32:$dst, EFLAGS,
164 (X86smul_flag GR32:$src1, (load addr:$src2)))],
167 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
168 (ins GR64:$src1, i64mem:$src2),
169 "imul{q}\t{$src2, $dst|$dst, $src2}",
170 [(set GR64:$dst, EFLAGS,
171 (X86smul_flag GR64:$src1, (load addr:$src2)))],
174 } // Constraints = "$src1 = $dst"
178 // Surprisingly enough, these are not two address instructions!
179 let Defs = [EFLAGS] in {
180 // Register-Integer Signed Integer Multiply
181 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
182 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
183 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
184 [(set GR16:$dst, EFLAGS,
185 (X86smul_flag GR16:$src1, imm:$src2))],
186 IIC_IMUL16_RRI>, OpSize;
187 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
188 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
189 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
190 [(set GR16:$dst, EFLAGS,
191 (X86smul_flag GR16:$src1, i16immSExt8:$src2))],
194 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
195 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
196 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
197 [(set GR32:$dst, EFLAGS,
198 (X86smul_flag GR32:$src1, imm:$src2))],
200 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
201 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
202 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
203 [(set GR32:$dst, EFLAGS,
204 (X86smul_flag GR32:$src1, i32immSExt8:$src2))],
206 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
207 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
208 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
209 [(set GR64:$dst, EFLAGS,
210 (X86smul_flag GR64:$src1, i64immSExt32:$src2))],
212 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
213 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
214 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
215 [(set GR64:$dst, EFLAGS,
216 (X86smul_flag GR64:$src1, i64immSExt8:$src2))],
220 // Memory-Integer Signed Integer Multiply
221 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
222 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
223 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
224 [(set GR16:$dst, EFLAGS,
225 (X86smul_flag (load addr:$src1), imm:$src2))],
228 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
229 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
230 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
231 [(set GR16:$dst, EFLAGS,
232 (X86smul_flag (load addr:$src1),
233 i16immSExt8:$src2))], IIC_IMUL16_RMI>,
235 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
236 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
237 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 [(set GR32:$dst, EFLAGS,
239 (X86smul_flag (load addr:$src1), imm:$src2))],
241 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
242 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
243 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
244 [(set GR32:$dst, EFLAGS,
245 (X86smul_flag (load addr:$src1),
246 i32immSExt8:$src2))],
248 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
249 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
250 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 [(set GR64:$dst, EFLAGS,
252 (X86smul_flag (load addr:$src1),
253 i64immSExt32:$src2))],
255 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
256 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
257 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
258 [(set GR64:$dst, EFLAGS,
259 (X86smul_flag (load addr:$src1),
260 i64immSExt8:$src2))],
267 // unsigned division/remainder
268 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
269 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
270 "div{b}\t$src", [], IIC_DIV8_REG>;
271 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
272 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
273 "div{w}\t$src", [], IIC_DIV16>, OpSize;
274 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
275 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
276 "div{l}\t$src", [], IIC_DIV32>;
277 // RDX:RAX/r64 = RAX,RDX
278 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
279 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
280 "div{q}\t$src", [], IIC_DIV64>;
283 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
284 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
285 "div{b}\t$src", [], IIC_DIV8_MEM>;
286 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
287 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
288 "div{w}\t$src", [], IIC_DIV16>, OpSize;
289 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
290 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
291 "div{l}\t$src", [], IIC_DIV32>;
292 // RDX:RAX/[mem64] = RAX,RDX
293 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
294 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
295 "div{q}\t$src", [], IIC_DIV64>;
298 // Signed division/remainder.
299 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
300 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
301 "idiv{b}\t$src", [], IIC_IDIV8>;
302 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
303 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
304 "idiv{w}\t$src", [], IIC_IDIV16>, OpSize;
305 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
306 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
307 "idiv{l}\t$src", [], IIC_IDIV32>;
308 // RDX:RAX/r64 = RAX,RDX
309 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
310 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
311 "idiv{q}\t$src", [], IIC_IDIV64>;
314 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
315 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
316 "idiv{b}\t$src", [], IIC_IDIV8>;
317 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
318 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
319 "idiv{w}\t$src", [], IIC_IDIV16>, OpSize;
320 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
321 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
322 "idiv{l}\t$src", [], IIC_IDIV32>;
323 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX
324 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
325 "idiv{q}\t$src", [], IIC_IDIV64>;
328 //===----------------------------------------------------------------------===//
329 // Two address Instructions.
332 // unary instructions
333 let CodeSize = 2 in {
334 let Defs = [EFLAGS] in {
335 let Constraints = "$src1 = $dst" in {
336 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
338 [(set GR8:$dst, (ineg GR8:$src1)),
339 (implicit EFLAGS)], IIC_UNARY_REG>;
340 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
342 [(set GR16:$dst, (ineg GR16:$src1)),
343 (implicit EFLAGS)], IIC_UNARY_REG>, OpSize;
344 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
346 [(set GR32:$dst, (ineg GR32:$src1)),
347 (implicit EFLAGS)], IIC_UNARY_REG>;
348 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
349 [(set GR64:$dst, (ineg GR64:$src1)),
350 (implicit EFLAGS)], IIC_UNARY_REG>;
351 } // Constraints = "$src1 = $dst"
353 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
355 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
356 (implicit EFLAGS)], IIC_UNARY_MEM>;
357 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
359 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
360 (implicit EFLAGS)], IIC_UNARY_MEM>, OpSize;
361 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
363 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
364 (implicit EFLAGS)], IIC_UNARY_MEM>;
365 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
366 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
367 (implicit EFLAGS)], IIC_UNARY_MEM>;
371 // Note: NOT does not set EFLAGS!
373 let Constraints = "$src1 = $dst" in {
374 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
375 let AddedComplexity = 15 in {
376 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
378 [(set GR8:$dst, (not GR8:$src1))], IIC_UNARY_REG>;
379 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
381 [(set GR16:$dst, (not GR16:$src1))], IIC_UNARY_REG>, OpSize;
382 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
384 [(set GR32:$dst, (not GR32:$src1))], IIC_UNARY_REG>;
385 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
386 [(set GR64:$dst, (not GR64:$src1))], IIC_UNARY_REG>;
388 } // Constraints = "$src1 = $dst"
390 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
392 [(store (not (loadi8 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>;
393 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
395 [(store (not (loadi16 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>,
397 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
399 [(store (not (loadi32 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>;
400 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
401 [(store (not (loadi64 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>;
404 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
405 let Defs = [EFLAGS] in {
406 let Constraints = "$src1 = $dst" in {
408 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
410 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))],
413 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
414 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
416 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))], IIC_UNARY_REG>,
417 OpSize, Requires<[In32BitMode]>;
418 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
420 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))],
422 Requires<[In32BitMode]>;
423 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
424 [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))],
426 } // isConvertibleToThreeAddress = 1, CodeSize = 1
429 // In 64-bit mode, single byte INC and DEC cannot be encoded.
430 let isConvertibleToThreeAddress = 1, CodeSize = 2 in {
431 // Can transform into LEA.
432 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
434 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))],
436 OpSize, Requires<[In64BitMode]>;
437 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
439 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))],
441 Requires<[In64BitMode]>;
442 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
444 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))],
446 OpSize, Requires<[In64BitMode]>;
447 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
449 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))],
451 Requires<[In64BitMode]>;
452 } // isConvertibleToThreeAddress = 1, CodeSize = 2
454 } // Constraints = "$src1 = $dst"
456 let CodeSize = 2 in {
457 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
458 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
459 (implicit EFLAGS)], IIC_UNARY_MEM>;
460 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
461 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
462 (implicit EFLAGS)], IIC_UNARY_MEM>,
463 OpSize, Requires<[In32BitMode]>;
464 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
465 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
466 (implicit EFLAGS)], IIC_UNARY_MEM>,
467 Requires<[In32BitMode]>;
468 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
469 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
470 (implicit EFLAGS)], IIC_UNARY_MEM>;
472 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
473 // how to unfold them.
474 // FIXME: What is this for??
475 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
476 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
477 (implicit EFLAGS)], IIC_UNARY_MEM>,
478 OpSize, Requires<[In64BitMode]>;
479 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
480 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
481 (implicit EFLAGS)], IIC_UNARY_MEM>,
482 Requires<[In64BitMode]>;
483 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
484 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
485 (implicit EFLAGS)], IIC_UNARY_MEM>,
486 OpSize, Requires<[In64BitMode]>;
487 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
488 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
489 (implicit EFLAGS)], IIC_UNARY_MEM>,
490 Requires<[In64BitMode]>;
493 let Constraints = "$src1 = $dst" in {
495 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
497 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))],
499 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
500 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
502 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))],
504 OpSize, Requires<[In32BitMode]>;
505 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
507 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))],
509 Requires<[In32BitMode]>;
510 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst",
511 [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))],
514 } // Constraints = "$src1 = $dst"
517 let CodeSize = 2 in {
518 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
519 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
520 (implicit EFLAGS)], IIC_UNARY_MEM>;
521 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
522 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
523 (implicit EFLAGS)], IIC_UNARY_MEM>,
524 OpSize, Requires<[In32BitMode]>;
525 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
526 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
527 (implicit EFLAGS)], IIC_UNARY_MEM>,
528 Requires<[In32BitMode]>;
529 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
530 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
531 (implicit EFLAGS)], IIC_UNARY_MEM>;
536 /// X86TypeInfo - This is a bunch of information that describes relevant X86
537 /// information about value types. For example, it can tell you what the
538 /// register class and preferred load to use.
539 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
540 PatFrag loadnode, X86MemOperand memoperand, ImmType immkind,
541 Operand immoperand, SDPatternOperator immoperator,
542 Operand imm8operand, SDPatternOperator imm8operator,
543 bit hasOddOpcode, bit hasOpSizePrefix, bit hasREX_WPrefix> {
544 /// VT - This is the value type itself.
547 /// InstrSuffix - This is the suffix used on instructions with this type. For
548 /// example, i8 -> "b", i16 -> "w", i32 -> "l", i64 -> "q".
549 string InstrSuffix = instrsuffix;
551 /// RegClass - This is the register class associated with this type. For
552 /// example, i8 -> GR8, i16 -> GR16, i32 -> GR32, i64 -> GR64.
553 RegisterClass RegClass = regclass;
555 /// LoadNode - This is the load node associated with this type. For
556 /// example, i8 -> loadi8, i16 -> loadi16, i32 -> loadi32, i64 -> loadi64.
557 PatFrag LoadNode = loadnode;
559 /// MemOperand - This is the memory operand associated with this type. For
560 /// example, i8 -> i8mem, i16 -> i16mem, i32 -> i32mem, i64 -> i64mem.
561 X86MemOperand MemOperand = memoperand;
563 /// ImmEncoding - This is the encoding of an immediate of this type. For
564 /// example, i8 -> Imm8, i16 -> Imm16, i32 -> Imm32. Note that i64 -> Imm32
565 /// since the immediate fields of i64 instructions is a 32-bit sign extended
567 ImmType ImmEncoding = immkind;
569 /// ImmOperand - This is the operand kind of an immediate of this type. For
570 /// example, i8 -> i8imm, i16 -> i16imm, i32 -> i32imm. Note that i64 ->
571 /// i64i32imm since the immediate fields of i64 instructions is a 32-bit sign
573 Operand ImmOperand = immoperand;
575 /// ImmOperator - This is the operator that should be used to match an
576 /// immediate of this kind in a pattern (e.g. imm, or i64immSExt32).
577 SDPatternOperator ImmOperator = immoperator;
579 /// Imm8Operand - This is the operand kind to use for an imm8 of this type.
580 /// For example, i8 -> <invalid>, i16 -> i16i8imm, i32 -> i32i8imm. This is
581 /// only used for instructions that have a sign-extended imm8 field form.
582 Operand Imm8Operand = imm8operand;
584 /// Imm8Operator - This is the operator that should be used to match an 8-bit
585 /// sign extended immediate of this kind in a pattern (e.g. imm16immSExt8).
586 SDPatternOperator Imm8Operator = imm8operator;
588 /// HasOddOpcode - This bit is true if the instruction should have an odd (as
589 /// opposed to even) opcode. Operations on i8 are usually even, operations on
590 /// other datatypes are odd.
591 bit HasOddOpcode = hasOddOpcode;
593 /// HasOpSizePrefix - This bit is set to true if the instruction should have
594 /// the 0x66 operand size prefix. This is set for i16 types.
595 bit HasOpSizePrefix = hasOpSizePrefix;
597 /// HasREX_WPrefix - This bit is set to true if the instruction should have
598 /// the 0x40 REX prefix. This is set for i64 types.
599 bit HasREX_WPrefix = hasREX_WPrefix;
602 def invalid_node : SDNode<"<<invalid_node>>", SDTIntLeaf,[],"<<invalid_node>>">;
605 def Xi8 : X86TypeInfo<i8 , "b", GR8 , loadi8 , i8mem ,
606 Imm8 , i8imm , imm, i8imm , invalid_node,
608 def Xi16 : X86TypeInfo<i16, "w", GR16, loadi16, i16mem,
609 Imm16, i16imm, imm, i16i8imm, i16immSExt8,
611 def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem,
612 Imm32, i32imm, imm, i32i8imm, i32immSExt8,
614 def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem,
615 Imm32, i64i32imm, i64immSExt32, i64i8imm, i64immSExt8,
618 /// ITy - This instruction base class takes the type info for the instruction.
620 /// 1. Concatenates together the instruction mnemonic with the appropriate
621 /// suffix letter, a tab, and the arguments.
622 /// 2. Infers whether the instruction should have a 0x66 prefix byte.
623 /// 3. Infers whether the instruction should have a 0x40 REX_W prefix.
624 /// 4. Infers whether the low bit of the opcode should be 0 (for i8 operations)
625 /// or 1 (for i16,i32,i64 operations).
626 class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins,
627 string mnemonic, string args, list<dag> pattern,
628 InstrItinClass itin = IIC_BIN_NONMEM>
629 : I<{opcode{7}, opcode{6}, opcode{5}, opcode{4},
630 opcode{3}, opcode{2}, opcode{1}, typeinfo.HasOddOpcode },
632 !strconcat(mnemonic, "{", typeinfo.InstrSuffix, "}\t", args), pattern,
635 // Infer instruction prefixes from type info.
636 let hasOpSizePrefix = typeinfo.HasOpSizePrefix;
637 let hasREX_WPrefix = typeinfo.HasREX_WPrefix;
640 // BinOpRR - Instructions like "add reg, reg, reg".
641 class BinOpRR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
642 dag outlist, list<dag> pattern, Format f = MRMDestReg>
643 : ITy<opcode, f, typeinfo, outlist,
644 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
645 mnemonic, "{$src2, $src1|$src1, $src2}", pattern>;
647 // BinOpRR_R - Instructions like "add reg, reg, reg", where the pattern has
648 // just a regclass (no eflags) as a result.
649 class BinOpRR_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
651 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
652 [(set typeinfo.RegClass:$dst,
653 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
655 // BinOpRR_F - Instructions like "cmp reg, Reg", where the pattern has
656 // just a EFLAGS as a result.
657 class BinOpRR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
658 SDPatternOperator opnode, Format f = MRMDestReg>
659 : BinOpRR<opcode, mnemonic, typeinfo, (outs),
661 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
664 // BinOpRR_RF - Instructions like "add reg, reg, reg", where the pattern has
665 // both a regclass and EFLAGS as a result.
666 class BinOpRR_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
668 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
669 [(set typeinfo.RegClass:$dst, EFLAGS,
670 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
672 // BinOpRR_RFF - Instructions like "adc reg, reg, reg", where the pattern has
673 // both a regclass and EFLAGS as a result, and has EFLAGS as input.
674 class BinOpRR_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
676 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
677 [(set typeinfo.RegClass:$dst, EFLAGS,
678 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2,
681 // BinOpRR_Rev - Instructions like "add reg, reg, reg" (reversed encoding).
682 class BinOpRR_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo>
683 : ITy<opcode, MRMSrcReg, typeinfo,
684 (outs typeinfo.RegClass:$dst),
685 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
686 mnemonic, "{$src2, $dst|$dst, $src2}", []> {
687 // The disassembler should know about this, but not the asmparser.
688 let isCodeGenOnly = 1;
691 // BinOpRR_F_Rev - Instructions like "cmp reg, reg" (reversed encoding).
692 class BinOpRR_F_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo>
693 : ITy<opcode, MRMSrcReg, typeinfo, (outs),
694 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
695 mnemonic, "{$src2, $src1|$src1, $src2}", []> {
696 // The disassembler should know about this, but not the asmparser.
697 let isCodeGenOnly = 1;
700 // BinOpRM - Instructions like "add reg, reg, [mem]".
701 class BinOpRM<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
702 dag outlist, list<dag> pattern>
703 : ITy<opcode, MRMSrcMem, typeinfo, outlist,
704 (ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2),
705 mnemonic, "{$src2, $src1|$src1, $src2}", pattern, IIC_BIN_MEM>;
707 // BinOpRM_R - Instructions like "add reg, reg, [mem]".
708 class BinOpRM_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
710 : BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
711 [(set typeinfo.RegClass:$dst,
712 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
714 // BinOpRM_F - Instructions like "cmp reg, [mem]".
715 class BinOpRM_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
716 SDPatternOperator opnode>
717 : BinOpRM<opcode, mnemonic, typeinfo, (outs),
719 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
721 // BinOpRM_RF - Instructions like "add reg, reg, [mem]".
722 class BinOpRM_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
724 : BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
725 [(set typeinfo.RegClass:$dst, EFLAGS,
726 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>;
728 // BinOpRM_RFF - Instructions like "adc reg, reg, [mem]".
729 class BinOpRM_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
731 : BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
732 [(set typeinfo.RegClass:$dst, EFLAGS,
733 (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2),
736 // BinOpRI - Instructions like "add reg, reg, imm".
737 class BinOpRI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
738 Format f, dag outlist, list<dag> pattern>
739 : ITy<opcode, f, typeinfo, outlist,
740 (ins typeinfo.RegClass:$src1, typeinfo.ImmOperand:$src2),
741 mnemonic, "{$src2, $src1|$src1, $src2}", pattern> {
742 let ImmT = typeinfo.ImmEncoding;
745 // BinOpRI_R - Instructions like "add reg, reg, imm".
746 class BinOpRI_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
747 SDNode opnode, Format f>
748 : BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
749 [(set typeinfo.RegClass:$dst,
750 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
752 // BinOpRI_F - Instructions like "cmp reg, imm".
753 class BinOpRI_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
754 SDPatternOperator opnode, Format f>
755 : BinOpRI<opcode, mnemonic, typeinfo, f, (outs),
757 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
759 // BinOpRI_RF - Instructions like "add reg, reg, imm".
760 class BinOpRI_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
761 SDNode opnode, Format f>
762 : BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
763 [(set typeinfo.RegClass:$dst, EFLAGS,
764 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>;
766 // BinOpRI_RFF - Instructions like "adc reg, reg, imm".
767 class BinOpRI_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
768 SDNode opnode, Format f>
769 : BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
770 [(set typeinfo.RegClass:$dst, EFLAGS,
771 (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2,
774 // BinOpRI8 - Instructions like "add reg, reg, imm8".
775 class BinOpRI8<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
776 Format f, dag outlist, list<dag> pattern>
777 : ITy<opcode, f, typeinfo, outlist,
778 (ins typeinfo.RegClass:$src1, typeinfo.Imm8Operand:$src2),
779 mnemonic, "{$src2, $src1|$src1, $src2}", pattern> {
780 let ImmT = Imm8; // Always 8-bit immediate.
783 // BinOpRI8_R - Instructions like "add reg, reg, imm8".
784 class BinOpRI8_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
785 SDNode opnode, Format f>
786 : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
787 [(set typeinfo.RegClass:$dst,
788 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
790 // BinOpRI8_F - Instructions like "cmp reg, imm8".
791 class BinOpRI8_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
792 SDNode opnode, Format f>
793 : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs),
795 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
797 // BinOpRI8_RF - Instructions like "add reg, reg, imm8".
798 class BinOpRI8_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
799 SDNode opnode, Format f>
800 : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
801 [(set typeinfo.RegClass:$dst, EFLAGS,
802 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
804 // BinOpRI8_RFF - Instructions like "adc reg, reg, imm8".
805 class BinOpRI8_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
806 SDNode opnode, Format f>
807 : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst),
808 [(set typeinfo.RegClass:$dst, EFLAGS,
809 (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2,
812 // BinOpMR - Instructions like "add [mem], reg".
813 class BinOpMR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
815 : ITy<opcode, MRMDestMem, typeinfo,
816 (outs), (ins typeinfo.MemOperand:$dst, typeinfo.RegClass:$src),
817 mnemonic, "{$src, $dst|$dst, $src}", pattern, IIC_BIN_MEM>;
819 // BinOpMR_RMW - Instructions like "add [mem], reg".
820 class BinOpMR_RMW<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
822 : BinOpMR<opcode, mnemonic, typeinfo,
823 [(store (opnode (load addr:$dst), typeinfo.RegClass:$src), addr:$dst),
826 // BinOpMR_RMW_FF - Instructions like "adc [mem], reg".
827 class BinOpMR_RMW_FF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
829 : BinOpMR<opcode, mnemonic, typeinfo,
830 [(store (opnode (load addr:$dst), typeinfo.RegClass:$src, EFLAGS),
834 // BinOpMR_F - Instructions like "cmp [mem], reg".
835 class BinOpMR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
837 : BinOpMR<opcode, mnemonic, typeinfo,
838 [(set EFLAGS, (opnode (load addr:$dst), typeinfo.RegClass:$src))]>;
840 // BinOpMI - Instructions like "add [mem], imm".
841 class BinOpMI<string mnemonic, X86TypeInfo typeinfo,
842 Format f, list<dag> pattern, bits<8> opcode = 0x80>
843 : ITy<opcode, f, typeinfo,
844 (outs), (ins typeinfo.MemOperand:$dst, typeinfo.ImmOperand:$src),
845 mnemonic, "{$src, $dst|$dst, $src}", pattern, IIC_BIN_MEM> {
846 let ImmT = typeinfo.ImmEncoding;
849 // BinOpMI_RMW - Instructions like "add [mem], imm".
850 class BinOpMI_RMW<string mnemonic, X86TypeInfo typeinfo,
851 SDNode opnode, Format f>
852 : BinOpMI<mnemonic, typeinfo, f,
853 [(store (opnode (typeinfo.VT (load addr:$dst)),
854 typeinfo.ImmOperator:$src), addr:$dst),
857 // BinOpMI_RMW_FF - Instructions like "adc [mem], imm".
858 class BinOpMI_RMW_FF<string mnemonic, X86TypeInfo typeinfo,
859 SDNode opnode, Format f>
860 : BinOpMI<mnemonic, typeinfo, f,
861 [(store (opnode (typeinfo.VT (load addr:$dst)),
862 typeinfo.ImmOperator:$src, EFLAGS), addr:$dst),
865 // BinOpMI_F - Instructions like "cmp [mem], imm".
866 class BinOpMI_F<string mnemonic, X86TypeInfo typeinfo,
867 SDPatternOperator opnode, Format f, bits<8> opcode = 0x80>
868 : BinOpMI<mnemonic, typeinfo, f,
869 [(set EFLAGS, (opnode (typeinfo.VT (load addr:$dst)),
870 typeinfo.ImmOperator:$src))],
873 // BinOpMI8 - Instructions like "add [mem], imm8".
874 class BinOpMI8<string mnemonic, X86TypeInfo typeinfo,
875 Format f, list<dag> pattern>
876 : ITy<0x82, f, typeinfo,
877 (outs), (ins typeinfo.MemOperand:$dst, typeinfo.Imm8Operand:$src),
878 mnemonic, "{$src, $dst|$dst, $src}", pattern, IIC_BIN_MEM> {
879 let ImmT = Imm8; // Always 8-bit immediate.
882 // BinOpMI8_RMW - Instructions like "add [mem], imm8".
883 class BinOpMI8_RMW<string mnemonic, X86TypeInfo typeinfo,
884 SDNode opnode, Format f>
885 : BinOpMI8<mnemonic, typeinfo, f,
886 [(store (opnode (load addr:$dst),
887 typeinfo.Imm8Operator:$src), addr:$dst),
890 // BinOpMI8_RMW_FF - Instructions like "adc [mem], imm8".
891 class BinOpMI8_RMW_FF<string mnemonic, X86TypeInfo typeinfo,
892 SDNode opnode, Format f>
893 : BinOpMI8<mnemonic, typeinfo, f,
894 [(store (opnode (load addr:$dst),
895 typeinfo.Imm8Operator:$src, EFLAGS), addr:$dst),
898 // BinOpMI8_F - Instructions like "cmp [mem], imm8".
899 class BinOpMI8_F<string mnemonic, X86TypeInfo typeinfo,
900 SDNode opnode, Format f>
901 : BinOpMI8<mnemonic, typeinfo, f,
902 [(set EFLAGS, (opnode (load addr:$dst),
903 typeinfo.Imm8Operator:$src))]>;
905 // BinOpAI - Instructions like "add %eax, %eax, imm".
906 class BinOpAI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
907 Register areg, string operands>
908 : ITy<opcode, RawFrm, typeinfo,
909 (outs), (ins typeinfo.ImmOperand:$src),
910 mnemonic, operands, []> {
911 let ImmT = typeinfo.ImmEncoding;
916 /// ArithBinOp_RF - This is an arithmetic binary operator where the pattern is
917 /// defined with "(set GPR:$dst, EFLAGS, (...".
919 /// It would be nice to get rid of the second and third argument here, but
920 /// tblgen can't handle dependent type references aggressively enough: PR8330
921 multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
922 string mnemonic, Format RegMRM, Format MemMRM,
923 SDNode opnodeflag, SDNode opnode,
924 bit CommutableRR, bit ConvertibleToThreeAddress> {
925 let Defs = [EFLAGS] in {
926 let Constraints = "$src1 = $dst" in {
927 let isCommutable = CommutableRR,
928 isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
929 def #NAME#8rr : BinOpRR_RF<BaseOpc, mnemonic, Xi8 , opnodeflag>;
930 def #NAME#16rr : BinOpRR_RF<BaseOpc, mnemonic, Xi16, opnodeflag>;
931 def #NAME#32rr : BinOpRR_RF<BaseOpc, mnemonic, Xi32, opnodeflag>;
932 def #NAME#64rr : BinOpRR_RF<BaseOpc, mnemonic, Xi64, opnodeflag>;
935 def #NAME#8rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi8>;
936 def #NAME#16rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi16>;
937 def #NAME#32rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi32>;
938 def #NAME#64rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi64>;
940 def #NAME#8rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi8 , opnodeflag>;
941 def #NAME#16rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi16, opnodeflag>;
942 def #NAME#32rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi32, opnodeflag>;
943 def #NAME#64rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi64, opnodeflag>;
945 let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
946 // NOTE: These are order specific, we want the ri8 forms to be listed
947 // first so that they are slightly preferred to the ri forms.
948 def #NAME#16ri8 : BinOpRI8_RF<0x82, mnemonic, Xi16, opnodeflag, RegMRM>;
949 def #NAME#32ri8 : BinOpRI8_RF<0x82, mnemonic, Xi32, opnodeflag, RegMRM>;
950 def #NAME#64ri8 : BinOpRI8_RF<0x82, mnemonic, Xi64, opnodeflag, RegMRM>;
952 def #NAME#8ri : BinOpRI_RF<0x80, mnemonic, Xi8 , opnodeflag, RegMRM>;
953 def #NAME#16ri : BinOpRI_RF<0x80, mnemonic, Xi16, opnodeflag, RegMRM>;
954 def #NAME#32ri : BinOpRI_RF<0x80, mnemonic, Xi32, opnodeflag, RegMRM>;
955 def #NAME#64ri32: BinOpRI_RF<0x80, mnemonic, Xi64, opnodeflag, RegMRM>;
957 } // Constraints = "$src1 = $dst"
959 def #NAME#8mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi8 , opnode>;
960 def #NAME#16mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi16, opnode>;
961 def #NAME#32mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi32, opnode>;
962 def #NAME#64mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi64, opnode>;
964 // NOTE: These are order specific, we want the mi8 forms to be listed
965 // first so that they are slightly preferred to the mi forms.
966 def #NAME#16mi8 : BinOpMI8_RMW<mnemonic, Xi16, opnode, MemMRM>;
967 def #NAME#32mi8 : BinOpMI8_RMW<mnemonic, Xi32, opnode, MemMRM>;
968 def #NAME#64mi8 : BinOpMI8_RMW<mnemonic, Xi64, opnode, MemMRM>;
970 def #NAME#8mi : BinOpMI_RMW<mnemonic, Xi8 , opnode, MemMRM>;
971 def #NAME#16mi : BinOpMI_RMW<mnemonic, Xi16, opnode, MemMRM>;
972 def #NAME#32mi : BinOpMI_RMW<mnemonic, Xi32, opnode, MemMRM>;
973 def #NAME#64mi32 : BinOpMI_RMW<mnemonic, Xi64, opnode, MemMRM>;
975 def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL,
976 "{$src, %al|AL, $src}">;
977 def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX,
978 "{$src, %ax|AX, $src}">;
979 def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX,
980 "{$src, %eax|EAX, $src}">;
981 def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX,
982 "{$src, %rax|RAX, $src}">;
986 /// ArithBinOp_RFF - This is an arithmetic binary operator where the pattern is
987 /// defined with "(set GPR:$dst, EFLAGS, (node LHS, RHS, EFLAGS))" like ADC and
990 /// It would be nice to get rid of the second and third argument here, but
991 /// tblgen can't handle dependent type references aggressively enough: PR8330
992 multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
993 string mnemonic, Format RegMRM, Format MemMRM,
994 SDNode opnode, bit CommutableRR,
995 bit ConvertibleToThreeAddress> {
996 let Defs = [EFLAGS] in {
997 let Constraints = "$src1 = $dst" in {
998 let isCommutable = CommutableRR,
999 isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
1000 def #NAME#8rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi8 , opnode>;
1001 def #NAME#16rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi16, opnode>;
1002 def #NAME#32rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi32, opnode>;
1003 def #NAME#64rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi64, opnode>;
1006 def #NAME#8rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi8>;
1007 def #NAME#16rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi16>;
1008 def #NAME#32rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi32>;
1009 def #NAME#64rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi64>;
1011 def #NAME#8rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi8 , opnode>;
1012 def #NAME#16rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi16, opnode>;
1013 def #NAME#32rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi32, opnode>;
1014 def #NAME#64rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi64, opnode>;
1016 let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
1017 // NOTE: These are order specific, we want the ri8 forms to be listed
1018 // first so that they are slightly preferred to the ri forms.
1019 def #NAME#16ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi16, opnode, RegMRM>;
1020 def #NAME#32ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi32, opnode, RegMRM>;
1021 def #NAME#64ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi64, opnode, RegMRM>;
1023 def #NAME#8ri : BinOpRI_RFF<0x80, mnemonic, Xi8 , opnode, RegMRM>;
1024 def #NAME#16ri : BinOpRI_RFF<0x80, mnemonic, Xi16, opnode, RegMRM>;
1025 def #NAME#32ri : BinOpRI_RFF<0x80, mnemonic, Xi32, opnode, RegMRM>;
1026 def #NAME#64ri32: BinOpRI_RFF<0x80, mnemonic, Xi64, opnode, RegMRM>;
1028 } // Constraints = "$src1 = $dst"
1030 def #NAME#8mr : BinOpMR_RMW_FF<BaseOpc, mnemonic, Xi8 , opnode>;
1031 def #NAME#16mr : BinOpMR_RMW_FF<BaseOpc, mnemonic, Xi16, opnode>;
1032 def #NAME#32mr : BinOpMR_RMW_FF<BaseOpc, mnemonic, Xi32, opnode>;
1033 def #NAME#64mr : BinOpMR_RMW_FF<BaseOpc, mnemonic, Xi64, opnode>;
1035 // NOTE: These are order specific, we want the mi8 forms to be listed
1036 // first so that they are slightly preferred to the mi forms.
1037 def #NAME#16mi8 : BinOpMI8_RMW_FF<mnemonic, Xi16, opnode, MemMRM>;
1038 def #NAME#32mi8 : BinOpMI8_RMW_FF<mnemonic, Xi32, opnode, MemMRM>;
1039 def #NAME#64mi8 : BinOpMI8_RMW_FF<mnemonic, Xi64, opnode, MemMRM>;
1041 def #NAME#8mi : BinOpMI_RMW_FF<mnemonic, Xi8 , opnode, MemMRM>;
1042 def #NAME#16mi : BinOpMI_RMW_FF<mnemonic, Xi16, opnode, MemMRM>;
1043 def #NAME#32mi : BinOpMI_RMW_FF<mnemonic, Xi32, opnode, MemMRM>;
1044 def #NAME#64mi32 : BinOpMI_RMW_FF<mnemonic, Xi64, opnode, MemMRM>;
1046 def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL,
1047 "{$src, %al|AL, $src}">;
1048 def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX,
1049 "{$src, %ax|AX, $src}">;
1050 def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX,
1051 "{$src, %eax|EAX, $src}">;
1052 def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX,
1053 "{$src, %rax|RAX, $src}">;
1057 /// ArithBinOp_F - This is an arithmetic binary operator where the pattern is
1058 /// defined with "(set EFLAGS, (...". It would be really nice to find a way
1059 /// to factor this with the other ArithBinOp_*.
1061 multiclass ArithBinOp_F<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
1062 string mnemonic, Format RegMRM, Format MemMRM,
1064 bit CommutableRR, bit ConvertibleToThreeAddress> {
1065 let Defs = [EFLAGS] in {
1066 let isCommutable = CommutableRR,
1067 isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
1068 def #NAME#8rr : BinOpRR_F<BaseOpc, mnemonic, Xi8 , opnode>;
1069 def #NAME#16rr : BinOpRR_F<BaseOpc, mnemonic, Xi16, opnode>;
1070 def #NAME#32rr : BinOpRR_F<BaseOpc, mnemonic, Xi32, opnode>;
1071 def #NAME#64rr : BinOpRR_F<BaseOpc, mnemonic, Xi64, opnode>;
1074 def #NAME#8rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi8>;
1075 def #NAME#16rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi16>;
1076 def #NAME#32rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi32>;
1077 def #NAME#64rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi64>;
1079 def #NAME#8rm : BinOpRM_F<BaseOpc2, mnemonic, Xi8 , opnode>;
1080 def #NAME#16rm : BinOpRM_F<BaseOpc2, mnemonic, Xi16, opnode>;
1081 def #NAME#32rm : BinOpRM_F<BaseOpc2, mnemonic, Xi32, opnode>;
1082 def #NAME#64rm : BinOpRM_F<BaseOpc2, mnemonic, Xi64, opnode>;
1084 let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
1085 // NOTE: These are order specific, we want the ri8 forms to be listed
1086 // first so that they are slightly preferred to the ri forms.
1087 def #NAME#16ri8 : BinOpRI8_F<0x82, mnemonic, Xi16, opnode, RegMRM>;
1088 def #NAME#32ri8 : BinOpRI8_F<0x82, mnemonic, Xi32, opnode, RegMRM>;
1089 def #NAME#64ri8 : BinOpRI8_F<0x82, mnemonic, Xi64, opnode, RegMRM>;
1091 def #NAME#8ri : BinOpRI_F<0x80, mnemonic, Xi8 , opnode, RegMRM>;
1092 def #NAME#16ri : BinOpRI_F<0x80, mnemonic, Xi16, opnode, RegMRM>;
1093 def #NAME#32ri : BinOpRI_F<0x80, mnemonic, Xi32, opnode, RegMRM>;
1094 def #NAME#64ri32: BinOpRI_F<0x80, mnemonic, Xi64, opnode, RegMRM>;
1097 def #NAME#8mr : BinOpMR_F<BaseOpc, mnemonic, Xi8 , opnode>;
1098 def #NAME#16mr : BinOpMR_F<BaseOpc, mnemonic, Xi16, opnode>;
1099 def #NAME#32mr : BinOpMR_F<BaseOpc, mnemonic, Xi32, opnode>;
1100 def #NAME#64mr : BinOpMR_F<BaseOpc, mnemonic, Xi64, opnode>;
1102 // NOTE: These are order specific, we want the mi8 forms to be listed
1103 // first so that they are slightly preferred to the mi forms.
1104 def #NAME#16mi8 : BinOpMI8_F<mnemonic, Xi16, opnode, MemMRM>;
1105 def #NAME#32mi8 : BinOpMI8_F<mnemonic, Xi32, opnode, MemMRM>;
1106 def #NAME#64mi8 : BinOpMI8_F<mnemonic, Xi64, opnode, MemMRM>;
1108 def #NAME#8mi : BinOpMI_F<mnemonic, Xi8 , opnode, MemMRM>;
1109 def #NAME#16mi : BinOpMI_F<mnemonic, Xi16, opnode, MemMRM>;
1110 def #NAME#32mi : BinOpMI_F<mnemonic, Xi32, opnode, MemMRM>;
1111 def #NAME#64mi32 : BinOpMI_F<mnemonic, Xi64, opnode, MemMRM>;
1113 def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL,
1114 "{$src, %al|AL, $src}">;
1115 def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX,
1116 "{$src, %ax|AX, $src}">;
1117 def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX,
1118 "{$src, %eax|EAX, $src}">;
1119 def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX,
1120 "{$src, %rax|RAX, $src}">;
1125 defm AND : ArithBinOp_RF<0x20, 0x22, 0x24, "and", MRM4r, MRM4m,
1126 X86and_flag, and, 1, 0>;
1127 defm OR : ArithBinOp_RF<0x08, 0x0A, 0x0C, "or", MRM1r, MRM1m,
1128 X86or_flag, or, 1, 0>;
1129 defm XOR : ArithBinOp_RF<0x30, 0x32, 0x34, "xor", MRM6r, MRM6m,
1130 X86xor_flag, xor, 1, 0>;
1131 defm ADD : ArithBinOp_RF<0x00, 0x02, 0x04, "add", MRM0r, MRM0m,
1132 X86add_flag, add, 1, 1>;
1133 defm SUB : ArithBinOp_RF<0x28, 0x2A, 0x2C, "sub", MRM5r, MRM5m,
1134 X86sub_flag, sub, 0, 0>;
1137 let Uses = [EFLAGS] in {
1138 defm ADC : ArithBinOp_RFF<0x10, 0x12, 0x14, "adc", MRM2r, MRM2m, X86adc_flag,
1140 defm SBB : ArithBinOp_RFF<0x18, 0x1A, 0x1C, "sbb", MRM3r, MRM3m, X86sbb_flag,
1144 defm CMP : ArithBinOp_F<0x38, 0x3A, 0x3C, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>;
1147 //===----------------------------------------------------------------------===//
1148 // Semantically, test instructions are similar like AND, except they don't
1149 // generate a result. From an encoding perspective, they are very different:
1150 // they don't have all the usual imm8 and REV forms, and are encoded into a
1152 def X86testpat : PatFrag<(ops node:$lhs, node:$rhs),
1153 (X86cmp (and_su node:$lhs, node:$rhs), 0)>;
1155 let Defs = [EFLAGS] in {
1156 let isCommutable = 1 in {
1157 def TEST8rr : BinOpRR_F<0x84, "test", Xi8 , X86testpat, MRMSrcReg>;
1158 def TEST16rr : BinOpRR_F<0x84, "test", Xi16, X86testpat, MRMSrcReg>;
1159 def TEST32rr : BinOpRR_F<0x84, "test", Xi32, X86testpat, MRMSrcReg>;
1160 def TEST64rr : BinOpRR_F<0x84, "test", Xi64, X86testpat, MRMSrcReg>;
1163 def TEST8rm : BinOpRM_F<0x84, "test", Xi8 , X86testpat>;
1164 def TEST16rm : BinOpRM_F<0x84, "test", Xi16, X86testpat>;
1165 def TEST32rm : BinOpRM_F<0x84, "test", Xi32, X86testpat>;
1166 def TEST64rm : BinOpRM_F<0x84, "test", Xi64, X86testpat>;
1168 def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>;
1169 def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>;
1170 def TEST32ri : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM0r>;
1171 def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>;
1173 def TEST8mi : BinOpMI_F<"test", Xi8 , X86testpat, MRM0m, 0xF6>;
1174 def TEST16mi : BinOpMI_F<"test", Xi16, X86testpat, MRM0m, 0xF6>;
1175 def TEST32mi : BinOpMI_F<"test", Xi32, X86testpat, MRM0m, 0xF6>;
1176 def TEST64mi32 : BinOpMI_F<"test", Xi64, X86testpat, MRM0m, 0xF6>;
1178 def TEST8i8 : BinOpAI<0xA8, "test", Xi8 , AL,
1179 "{$src, %al|AL, $src}">;
1180 def TEST16i16 : BinOpAI<0xA8, "test", Xi16, AX,
1181 "{$src, %ax|AX, $src}">;
1182 def TEST32i32 : BinOpAI<0xA8, "test", Xi32, EAX,
1183 "{$src, %eax|EAX, $src}">;
1184 def TEST64i32 : BinOpAI<0xA8, "test", Xi64, RAX,
1185 "{$src, %rax|RAX, $src}">;
1187 // When testing the result of EXTRACT_SUBREG sub_8bit_hi, make sure the
1188 // register class is constrained to GR8_NOREX.
1190 def TEST8ri_NOREX : I<0, Pseudo, (outs), (ins GR8_NOREX:$src, i8imm:$mask),
1191 "", [], IIC_BIN_NONMEM>;
1194 //===----------------------------------------------------------------------===//
1197 multiclass bmi_andn<string mnemonic, RegisterClass RC, X86MemOperand x86memop,
1199 def rr : I<0xF2, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1200 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1201 [(set RC:$dst, EFLAGS, (X86andn_flag RC:$src1, RC:$src2))],
1203 def rm : I<0xF2, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1204 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1205 [(set RC:$dst, EFLAGS,
1206 (X86andn_flag RC:$src1, (ld_frag addr:$src2)))], IIC_BIN_MEM>;
1209 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1210 defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32>, T8, VEX_4V;
1211 defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64>, T8, VEX_4V, VEX_W;
1214 //===----------------------------------------------------------------------===//
1217 multiclass bmi_mulx<string mnemonic, RegisterClass RC, X86MemOperand x86memop> {
1218 let neverHasSideEffects = 1 in {
1219 let isCommutable = 1 in
1220 def rr : I<0xF6, MRMSrcReg, (outs RC:$dst1, RC:$dst2), (ins RC:$src),
1221 !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
1225 def rm : I<0xF6, MRMSrcMem, (outs RC:$dst1, RC:$dst2), (ins x86memop:$src),
1226 !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"),
1231 let Predicates = [HasBMI2] in {
1233 defm MULX32 : bmi_mulx<"mulx{l}", GR32, i32mem>;
1235 defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem>, VEX_W;