1 //===- X86InstrArithmetic.td - Integer Arithmetic Instrs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the integer arithmetic instructions in the X86
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // LEA - Load Effective Address
18 let neverHasSideEffects = 1 in
19 def LEA16r : I<0x8D, MRMSrcMem,
20 (outs GR16:$dst), (ins i32mem:$src),
21 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
22 let isReMaterializable = 1 in
23 def LEA32r : I<0x8D, MRMSrcMem,
24 (outs GR32:$dst), (ins i32mem:$src),
25 "lea{l}\t{$src|$dst}, {$dst|$src}",
26 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
28 def LEA64_32r : I<0x8D, MRMSrcMem,
29 (outs GR32:$dst), (ins lea64_32mem:$src),
30 "lea{l}\t{$src|$dst}, {$dst|$src}",
31 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
33 let isReMaterializable = 1 in
34 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
35 "lea{q}\t{$src|$dst}, {$dst|$src}",
36 [(set GR64:$dst, lea64addr:$src)]>;
40 //===----------------------------------------------------------------------===//
41 // Fixed-Register Multiplication and Division Instructions.
44 // Extra precision multiplication
46 // AL is really implied by AX, but the registers in Defs must match the
47 // SDNode results (i8, i32).
48 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
49 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
50 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
51 // This probably ought to be moved to a def : Pat<> if the
52 // syntax can be accepted.
53 [(set AL, (mul AL, GR8:$src)),
54 (implicit EFLAGS)]>; // AL,AH = AL*GR8
56 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
57 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
59 []>, OpSize; // AX,DX = AX*GR16
61 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
62 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
64 []>; // EAX,EDX = EAX*GR32
65 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
66 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
67 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
69 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
70 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
72 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
73 // This probably ought to be moved to a def : Pat<> if the
74 // syntax can be accepted.
75 [(set AL, (mul AL, (loadi8 addr:$src))),
76 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
78 let mayLoad = 1, neverHasSideEffects = 1 in {
79 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
80 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
82 []>, OpSize; // AX,DX = AX*[mem16]
84 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
85 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
87 []>; // EAX,EDX = EAX*[mem32]
88 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
89 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
90 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
93 let neverHasSideEffects = 1 in {
94 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
95 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
97 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
98 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
99 OpSize; // AX,DX = AX*GR16
100 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
101 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
102 // EAX,EDX = EAX*GR32
103 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
104 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", []>;
105 // RAX,RDX = RAX*GR64
108 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
109 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
110 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
111 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
112 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
113 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
114 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
115 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
116 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
117 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
118 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
119 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
121 } // neverHasSideEffects
124 let Defs = [EFLAGS] in {
125 let Constraints = "$src1 = $dst" in {
127 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
128 // Register-Register Signed Integer Multiply
129 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
130 "imul{w}\t{$src2, $dst|$dst, $src2}",
131 [(set GR16:$dst, EFLAGS,
132 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
133 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
134 "imul{l}\t{$src2, $dst|$dst, $src2}",
135 [(set GR32:$dst, EFLAGS,
136 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
137 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
138 (ins GR64:$src1, GR64:$src2),
139 "imul{q}\t{$src2, $dst|$dst, $src2}",
140 [(set GR64:$dst, EFLAGS,
141 (X86smul_flag GR64:$src1, GR64:$src2))]>, TB;
144 // Register-Memory Signed Integer Multiply
145 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
146 (ins GR16:$src1, i16mem:$src2),
147 "imul{w}\t{$src2, $dst|$dst, $src2}",
148 [(set GR16:$dst, EFLAGS,
149 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
151 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
152 (ins GR32:$src1, i32mem:$src2),
153 "imul{l}\t{$src2, $dst|$dst, $src2}",
154 [(set GR32:$dst, EFLAGS,
155 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
156 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
157 (ins GR64:$src1, i64mem:$src2),
158 "imul{q}\t{$src2, $dst|$dst, $src2}",
159 [(set GR64:$dst, EFLAGS,
160 (X86smul_flag GR64:$src1, (load addr:$src2)))]>, TB;
161 } // Constraints = "$src1 = $dst"
165 // Suprisingly enough, these are not two address instructions!
166 let Defs = [EFLAGS] in {
167 // Register-Integer Signed Integer Multiply
168 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
169 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
170 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
171 [(set GR16:$dst, EFLAGS,
172 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
173 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
174 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
175 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
176 [(set GR16:$dst, EFLAGS,
177 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
179 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
180 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
181 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
182 [(set GR32:$dst, EFLAGS,
183 (X86smul_flag GR32:$src1, imm:$src2))]>;
184 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
185 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
186 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
187 [(set GR32:$dst, EFLAGS,
188 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
189 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
190 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
191 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
192 [(set GR64:$dst, EFLAGS,
193 (X86smul_flag GR64:$src1, i64immSExt32:$src2))]>;
194 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
195 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
196 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
197 [(set GR64:$dst, EFLAGS,
198 (X86smul_flag GR64:$src1, i64immSExt8:$src2))]>;
201 // Memory-Integer Signed Integer Multiply
202 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
203 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
204 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
205 [(set GR16:$dst, EFLAGS,
206 (X86smul_flag (load addr:$src1), imm:$src2))]>,
208 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
209 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
210 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
211 [(set GR16:$dst, EFLAGS,
212 (X86smul_flag (load addr:$src1),
213 i16immSExt8:$src2))]>, OpSize;
214 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
215 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
216 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
217 [(set GR32:$dst, EFLAGS,
218 (X86smul_flag (load addr:$src1), imm:$src2))]>;
219 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
220 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
221 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
222 [(set GR32:$dst, EFLAGS,
223 (X86smul_flag (load addr:$src1),
224 i32immSExt8:$src2))]>;
225 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
226 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
227 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 [(set GR64:$dst, EFLAGS,
229 (X86smul_flag (load addr:$src1),
230 i64immSExt32:$src2))]>;
231 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
232 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
233 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
234 [(set GR64:$dst, EFLAGS,
235 (X86smul_flag (load addr:$src1),
236 i64immSExt8:$src2))]>;
242 // unsigned division/remainder
243 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
244 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
246 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
247 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
248 "div{w}\t$src", []>, OpSize;
249 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
250 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
252 // RDX:RAX/r64 = RAX,RDX
253 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
254 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
258 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
259 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
261 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
262 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
263 "div{w}\t$src", []>, OpSize;
264 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
265 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
267 // RDX:RAX/[mem64] = RAX,RDX
268 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
269 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
273 // Signed division/remainder.
274 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
275 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
276 "idiv{b}\t$src", []>;
277 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
278 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
279 "idiv{w}\t$src", []>, OpSize;
280 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
281 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
282 "idiv{l}\t$src", []>;
283 // RDX:RAX/r64 = RAX,RDX
284 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
285 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
286 "idiv{q}\t$src", []>;
288 let mayLoad = 1, mayLoad = 1 in {
289 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
290 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
291 "idiv{b}\t$src", []>;
292 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
293 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
294 "idiv{w}\t$src", []>, OpSize;
295 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
296 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
297 "idiv{l}\t$src", []>;
298 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX
299 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
300 "idiv{q}\t$src", []>;
303 //===----------------------------------------------------------------------===//
304 // Two address Instructions.
307 // unary instructions
308 let CodeSize = 2 in {
309 let Defs = [EFLAGS] in {
310 let Constraints = "$src1 = $dst" in {
311 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
313 [(set GR8:$dst, (ineg GR8:$src1)),
315 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
317 [(set GR16:$dst, (ineg GR16:$src1)),
318 (implicit EFLAGS)]>, OpSize;
319 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
321 [(set GR32:$dst, (ineg GR32:$src1)),
323 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
324 [(set GR64:$dst, (ineg GR64:$src1)),
326 } // Constraints = "$src1 = $dst"
328 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
330 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
332 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
334 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
335 (implicit EFLAGS)]>, OpSize;
336 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
338 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
340 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
341 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
346 // FIXME: NOT sets EFLAGS!
348 let Constraints = "$src1 = $dst" in {
349 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
350 let AddedComplexity = 15 in {
351 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
353 [(set GR8:$dst, (not GR8:$src1))]>;
354 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
356 [(set GR16:$dst, (not GR16:$src1))]>, OpSize;
357 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
359 [(set GR32:$dst, (not GR32:$src1))]>;
360 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
361 [(set GR64:$dst, (not GR64:$src1))]>;
363 } // Constraints = "$src1 = $dst"
365 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
367 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
368 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
370 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
371 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
373 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
374 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
375 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
378 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
379 let Defs = [EFLAGS] in {
380 let Constraints = "$src1 = $dst" in {
382 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
384 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>;
386 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
387 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
389 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
390 OpSize, Requires<[In32BitMode]>;
391 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
393 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
394 Requires<[In32BitMode]>;
395 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
396 [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))]>;
397 } // isConvertibleToThreeAddress = 1, CodeSize = 1
400 // In 64-bit mode, single byte INC and DEC cannot be encoded.
401 let isConvertibleToThreeAddress = 1, CodeSize = 2 in {
402 // Can transform into LEA.
403 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
405 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
406 OpSize, Requires<[In64BitMode]>;
407 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
409 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
410 Requires<[In64BitMode]>;
411 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
413 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
414 OpSize, Requires<[In64BitMode]>;
415 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
417 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
418 Requires<[In64BitMode]>;
419 } // isConvertibleToThreeAddress = 1, CodeSize = 2
421 } // Constraints = "$src1 = $dst"
423 let CodeSize = 2 in {
424 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
425 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
427 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
428 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
430 OpSize, Requires<[In32BitMode]>;
431 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
432 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
434 Requires<[In32BitMode]>;
435 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
436 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
439 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
440 // how to unfold them.
441 // FIXME: What is this for??
442 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
443 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
445 OpSize, Requires<[In64BitMode]>;
446 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
447 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
449 Requires<[In64BitMode]>;
450 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
451 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
453 OpSize, Requires<[In64BitMode]>;
454 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
455 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
457 Requires<[In64BitMode]>;
460 let Constraints = "$src1 = $dst" in {
462 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
464 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>;
465 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
466 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
468 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
469 OpSize, Requires<[In32BitMode]>;
470 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
472 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
473 Requires<[In32BitMode]>;
474 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst",
475 [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))]>;
477 } // Constraints = "$src1 = $dst"
480 let CodeSize = 2 in {
481 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
482 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
484 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
485 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
487 OpSize, Requires<[In32BitMode]>;
488 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
489 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
491 Requires<[In32BitMode]>;
492 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
493 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
498 // Logical operators.
499 let Defs = [EFLAGS] in {
500 let Constraints = "$src1 = $dst" in {
501 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
502 def AND8rr : I<0x20, MRMDestReg,
503 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
504 "and{b}\t{$src2, $dst|$dst, $src2}",
505 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, GR8:$src2))]>;
506 def AND16rr : I<0x21, MRMDestReg,
507 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
508 "and{w}\t{$src2, $dst|$dst, $src2}",
509 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
510 GR16:$src2))]>, OpSize;
511 def AND32rr : I<0x21, MRMDestReg,
512 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
513 "and{l}\t{$src2, $dst|$dst, $src2}",
514 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
516 def AND64rr : RI<0x21, MRMDestReg,
517 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
518 "and{q}\t{$src2, $dst|$dst, $src2}",
519 [(set GR64:$dst, EFLAGS,
520 (X86and_flag GR64:$src1, GR64:$src2))]>;
524 // AND instructions with the destination register in REG and the source register
525 // in R/M. Included for the disassembler.
526 let isCodeGenOnly = 1 in {
527 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
528 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
529 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
530 (ins GR16:$src1, GR16:$src2),
531 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
532 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
533 (ins GR32:$src1, GR32:$src2),
534 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
535 def AND64rr_REV : RI<0x23, MRMSrcReg, (outs GR64:$dst),
536 (ins GR64:$src1, GR64:$src2),
537 "and{q}\t{$src2, $dst|$dst, $src2}", []>;
540 def AND8rm : I<0x22, MRMSrcMem,
541 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
542 "and{b}\t{$src2, $dst|$dst, $src2}",
543 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
544 (loadi8 addr:$src2)))]>;
545 def AND16rm : I<0x23, MRMSrcMem,
546 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
547 "and{w}\t{$src2, $dst|$dst, $src2}",
548 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
549 (loadi16 addr:$src2)))]>,
551 def AND32rm : I<0x23, MRMSrcMem,
552 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
553 "and{l}\t{$src2, $dst|$dst, $src2}",
554 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
555 (loadi32 addr:$src2)))]>;
556 def AND64rm : RI<0x23, MRMSrcMem,
557 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
558 "and{q}\t{$src2, $dst|$dst, $src2}",
559 [(set GR64:$dst, EFLAGS,
560 (X86and_flag GR64:$src1, (load addr:$src2)))]>;
562 def AND8ri : Ii8<0x80, MRM4r,
563 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
564 "and{b}\t{$src2, $dst|$dst, $src2}",
565 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
567 def AND16ri : Ii16<0x81, MRM4r,
568 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
569 "and{w}\t{$src2, $dst|$dst, $src2}",
570 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
571 imm:$src2))]>, OpSize;
572 def AND32ri : Ii32<0x81, MRM4r,
573 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
574 "and{l}\t{$src2, $dst|$dst, $src2}",
575 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
577 def AND64ri32 : RIi32<0x81, MRM4r,
578 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
579 "and{q}\t{$src2, $dst|$dst, $src2}",
580 [(set GR64:$dst, EFLAGS,
581 (X86and_flag GR64:$src1, i64immSExt32:$src2))]>;
583 def AND16ri8 : Ii8<0x83, MRM4r,
584 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
585 "and{w}\t{$src2, $dst|$dst, $src2}",
586 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
587 i16immSExt8:$src2))]>,
589 def AND32ri8 : Ii8<0x83, MRM4r,
590 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
591 "and{l}\t{$src2, $dst|$dst, $src2}",
592 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
593 i32immSExt8:$src2))]>;
594 def AND64ri8 : RIi8<0x83, MRM4r,
595 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
596 "and{q}\t{$src2, $dst|$dst, $src2}",
597 [(set GR64:$dst, EFLAGS,
598 (X86and_flag GR64:$src1, i64immSExt8:$src2))]>;
599 } // Constraints = "$src1 = $dst"
601 def AND8mr : I<0x20, MRMDestMem,
602 (outs), (ins i8mem :$dst, GR8 :$src),
603 "and{b}\t{$src, $dst|$dst, $src}",
604 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
606 def AND16mr : I<0x21, MRMDestMem,
607 (outs), (ins i16mem:$dst, GR16:$src),
608 "and{w}\t{$src, $dst|$dst, $src}",
609 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
612 def AND32mr : I<0x21, MRMDestMem,
613 (outs), (ins i32mem:$dst, GR32:$src),
614 "and{l}\t{$src, $dst|$dst, $src}",
615 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
617 def AND64mr : RI<0x21, MRMDestMem,
618 (outs), (ins i64mem:$dst, GR64:$src),
619 "and{q}\t{$src, $dst|$dst, $src}",
620 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
623 def AND8mi : Ii8<0x80, MRM4m,
624 (outs), (ins i8mem :$dst, i8imm :$src),
625 "and{b}\t{$src, $dst|$dst, $src}",
626 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
628 def AND16mi : Ii16<0x81, MRM4m,
629 (outs), (ins i16mem:$dst, i16imm:$src),
630 "and{w}\t{$src, $dst|$dst, $src}",
631 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
634 def AND32mi : Ii32<0x81, MRM4m,
635 (outs), (ins i32mem:$dst, i32imm:$src),
636 "and{l}\t{$src, $dst|$dst, $src}",
637 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
639 def AND64mi32 : RIi32<0x81, MRM4m,
640 (outs), (ins i64mem:$dst, i64i32imm:$src),
641 "and{q}\t{$src, $dst|$dst, $src}",
642 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
645 def AND16mi8 : Ii8<0x83, MRM4m,
646 (outs), (ins i16mem:$dst, i16i8imm :$src),
647 "and{w}\t{$src, $dst|$dst, $src}",
648 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
651 def AND32mi8 : Ii8<0x83, MRM4m,
652 (outs), (ins i32mem:$dst, i32i8imm :$src),
653 "and{l}\t{$src, $dst|$dst, $src}",
654 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
656 def AND64mi8 : RIi8<0x83, MRM4m,
657 (outs), (ins i64mem:$dst, i64i8imm :$src),
658 "and{q}\t{$src, $dst|$dst, $src}",
659 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
662 // FIXME: Implicitly modifiers AL.
663 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
664 "and{b}\t{$src, %al|%al, $src}", []>;
665 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
666 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
667 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
668 "and{l}\t{$src, %eax|%eax, $src}", []>;
669 def AND64i32 : RIi32<0x25, RawFrm, (outs), (ins i64i32imm:$src),
670 "and{q}\t{$src, %rax|%rax, $src}", []>;
672 let Constraints = "$src1 = $dst" in {
674 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
675 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
676 (ins GR8 :$src1, GR8 :$src2),
677 "or{b}\t{$src2, $dst|$dst, $src2}",
678 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
679 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
680 (ins GR16:$src1, GR16:$src2),
681 "or{w}\t{$src2, $dst|$dst, $src2}",
682 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
684 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
685 (ins GR32:$src1, GR32:$src2),
686 "or{l}\t{$src2, $dst|$dst, $src2}",
687 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
688 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst),
689 (ins GR64:$src1, GR64:$src2),
690 "or{q}\t{$src2, $dst|$dst, $src2}",
691 [(set GR64:$dst, EFLAGS,
692 (X86or_flag GR64:$src1, GR64:$src2))]>;
695 // OR instructions with the destination register in REG and the source register
696 // in R/M. Included for the disassembler.
697 let isCodeGenOnly = 1 in {
698 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
699 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
700 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
701 (ins GR16:$src1, GR16:$src2),
702 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
703 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
704 (ins GR32:$src1, GR32:$src2),
705 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
706 def OR64rr_REV : RI<0x0B, MRMSrcReg, (outs GR64:$dst),
707 (ins GR64:$src1, GR64:$src2),
708 "or{q}\t{$src2, $dst|$dst, $src2}", []>;
711 def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
712 (ins GR8 :$src1, i8mem :$src2),
713 "or{b}\t{$src2, $dst|$dst, $src2}",
714 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
715 (load addr:$src2)))]>;
716 def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
717 (ins GR16:$src1, i16mem:$src2),
718 "or{w}\t{$src2, $dst|$dst, $src2}",
719 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
720 (load addr:$src2)))]>,
722 def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
723 (ins GR32:$src1, i32mem:$src2),
724 "or{l}\t{$src2, $dst|$dst, $src2}",
725 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
726 (load addr:$src2)))]>;
727 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst),
728 (ins GR64:$src1, i64mem:$src2),
729 "or{q}\t{$src2, $dst|$dst, $src2}",
730 [(set GR64:$dst, EFLAGS,
731 (X86or_flag GR64:$src1, (load addr:$src2)))]>;
733 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
734 (ins GR8 :$src1, i8imm:$src2),
735 "or{b}\t{$src2, $dst|$dst, $src2}",
736 [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
737 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
738 (ins GR16:$src1, i16imm:$src2),
739 "or{w}\t{$src2, $dst|$dst, $src2}",
740 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
741 imm:$src2))]>, OpSize;
742 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
743 (ins GR32:$src1, i32imm:$src2),
744 "or{l}\t{$src2, $dst|$dst, $src2}",
745 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
747 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst),
748 (ins GR64:$src1, i64i32imm:$src2),
749 "or{q}\t{$src2, $dst|$dst, $src2}",
750 [(set GR64:$dst, EFLAGS,
751 (X86or_flag GR64:$src1, i64immSExt32:$src2))]>;
753 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
754 (ins GR16:$src1, i16i8imm:$src2),
755 "or{w}\t{$src2, $dst|$dst, $src2}",
756 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
757 i16immSExt8:$src2))]>, OpSize;
758 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
759 (ins GR32:$src1, i32i8imm:$src2),
760 "or{l}\t{$src2, $dst|$dst, $src2}",
761 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
762 i32immSExt8:$src2))]>;
763 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst),
764 (ins GR64:$src1, i64i8imm:$src2),
765 "or{q}\t{$src2, $dst|$dst, $src2}",
766 [(set GR64:$dst, EFLAGS,
767 (X86or_flag GR64:$src1, i64immSExt8:$src2))]>;
768 } // Constraints = "$src1 = $dst"
770 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
771 "or{b}\t{$src, $dst|$dst, $src}",
772 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
774 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
775 "or{w}\t{$src, $dst|$dst, $src}",
776 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
777 (implicit EFLAGS)]>, OpSize;
778 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
779 "or{l}\t{$src, $dst|$dst, $src}",
780 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
782 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
783 "or{q}\t{$src, $dst|$dst, $src}",
784 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
787 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
788 "or{b}\t{$src, $dst|$dst, $src}",
789 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
791 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
792 "or{w}\t{$src, $dst|$dst, $src}",
793 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
796 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
797 "or{l}\t{$src, $dst|$dst, $src}",
798 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
800 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
801 "or{q}\t{$src, $dst|$dst, $src}",
802 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
805 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
806 "or{w}\t{$src, $dst|$dst, $src}",
807 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
810 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
811 "or{l}\t{$src, $dst|$dst, $src}",
812 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
814 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
815 "or{q}\t{$src, $dst|$dst, $src}",
816 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
819 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
820 "or{b}\t{$src, %al|%al, $src}", []>;
821 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
822 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
823 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
824 "or{l}\t{$src, %eax|%eax, $src}", []>;
825 def OR64i32 : RIi32<0x0D, RawFrm, (outs), (ins i64i32imm:$src),
826 "or{q}\t{$src, %rax|%rax, $src}", []>;
829 let Constraints = "$src1 = $dst" in {
831 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
832 def XOR8rr : I<0x30, MRMDestReg,
833 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
834 "xor{b}\t{$src2, $dst|$dst, $src2}",
835 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
837 def XOR16rr : I<0x31, MRMDestReg,
838 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
839 "xor{w}\t{$src2, $dst|$dst, $src2}",
840 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
841 GR16:$src2))]>, OpSize;
842 def XOR32rr : I<0x31, MRMDestReg,
843 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
844 "xor{l}\t{$src2, $dst|$dst, $src2}",
845 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
847 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst),
848 (ins GR64:$src1, GR64:$src2),
849 "xor{q}\t{$src2, $dst|$dst, $src2}",
850 [(set GR64:$dst, EFLAGS,
851 (X86xor_flag GR64:$src1, GR64:$src2))]>;
852 } // isCommutable = 1
854 // XOR instructions with the destination register in REG and the source register
855 // in R/M. Included for the disassembler.
856 let isCodeGenOnly = 1 in {
857 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
858 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
859 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
860 (ins GR16:$src1, GR16:$src2),
861 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
862 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
863 (ins GR32:$src1, GR32:$src2),
864 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
865 def XOR64rr_REV : RI<0x33, MRMSrcReg, (outs GR64:$dst),
866 (ins GR64:$src1, GR64:$src2),
867 "xor{q}\t{$src2, $dst|$dst, $src2}", []>;
870 def XOR8rm : I<0x32, MRMSrcMem,
871 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
872 "xor{b}\t{$src2, $dst|$dst, $src2}",
873 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
874 (load addr:$src2)))]>;
875 def XOR16rm : I<0x33, MRMSrcMem,
876 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
877 "xor{w}\t{$src2, $dst|$dst, $src2}",
878 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
879 (load addr:$src2)))]>,
881 def XOR32rm : I<0x33, MRMSrcMem,
882 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
883 "xor{l}\t{$src2, $dst|$dst, $src2}",
884 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
885 (load addr:$src2)))]>;
886 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst),
887 (ins GR64:$src1, i64mem:$src2),
888 "xor{q}\t{$src2, $dst|$dst, $src2}",
889 [(set GR64:$dst, EFLAGS,
890 (X86xor_flag GR64:$src1, (load addr:$src2)))]>;
892 def XOR8ri : Ii8<0x80, MRM6r,
893 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
894 "xor{b}\t{$src2, $dst|$dst, $src2}",
895 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
896 def XOR16ri : Ii16<0x81, MRM6r,
897 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
898 "xor{w}\t{$src2, $dst|$dst, $src2}",
899 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
900 imm:$src2))]>, OpSize;
901 def XOR32ri : Ii32<0x81, MRM6r,
902 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
903 "xor{l}\t{$src2, $dst|$dst, $src2}",
904 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
906 def XOR64ri32 : RIi32<0x81, MRM6r,
907 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
908 "xor{q}\t{$src2, $dst|$dst, $src2}",
909 [(set GR64:$dst, EFLAGS,
910 (X86xor_flag GR64:$src1, i64immSExt32:$src2))]>;
912 def XOR16ri8 : Ii8<0x83, MRM6r,
913 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
914 "xor{w}\t{$src2, $dst|$dst, $src2}",
915 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
916 i16immSExt8:$src2))]>,
918 def XOR32ri8 : Ii8<0x83, MRM6r,
919 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
920 "xor{l}\t{$src2, $dst|$dst, $src2}",
921 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
922 i32immSExt8:$src2))]>;
923 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst),
924 (ins GR64:$src1, i64i8imm:$src2),
925 "xor{q}\t{$src2, $dst|$dst, $src2}",
926 [(set GR64:$dst, EFLAGS,
927 (X86xor_flag GR64:$src1, i64immSExt8:$src2))]>;
928 } // Constraints = "$src1 = $dst"
931 def XOR8mr : I<0x30, MRMDestMem,
932 (outs), (ins i8mem :$dst, GR8 :$src),
933 "xor{b}\t{$src, $dst|$dst, $src}",
934 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
936 def XOR16mr : I<0x31, MRMDestMem,
937 (outs), (ins i16mem:$dst, GR16:$src),
938 "xor{w}\t{$src, $dst|$dst, $src}",
939 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
942 def XOR32mr : I<0x31, MRMDestMem,
943 (outs), (ins i32mem:$dst, GR32:$src),
944 "xor{l}\t{$src, $dst|$dst, $src}",
945 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
947 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
948 "xor{q}\t{$src, $dst|$dst, $src}",
949 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
952 def XOR8mi : Ii8<0x80, MRM6m,
953 (outs), (ins i8mem :$dst, i8imm :$src),
954 "xor{b}\t{$src, $dst|$dst, $src}",
955 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
957 def XOR16mi : Ii16<0x81, MRM6m,
958 (outs), (ins i16mem:$dst, i16imm:$src),
959 "xor{w}\t{$src, $dst|$dst, $src}",
960 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
963 def XOR32mi : Ii32<0x81, MRM6m,
964 (outs), (ins i32mem:$dst, i32imm:$src),
965 "xor{l}\t{$src, $dst|$dst, $src}",
966 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
968 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
969 "xor{q}\t{$src, $dst|$dst, $src}",
970 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
973 def XOR16mi8 : Ii8<0x83, MRM6m,
974 (outs), (ins i16mem:$dst, i16i8imm :$src),
975 "xor{w}\t{$src, $dst|$dst, $src}",
976 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
979 def XOR32mi8 : Ii8<0x83, MRM6m,
980 (outs), (ins i32mem:$dst, i32i8imm :$src),
981 "xor{l}\t{$src, $dst|$dst, $src}",
982 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
984 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
985 "xor{q}\t{$src, $dst|$dst, $src}",
986 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
989 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
990 "xor{b}\t{$src, %al|%al, $src}", []>;
991 def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
992 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
993 def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
994 "xor{l}\t{$src, %eax|%eax, $src}", []>;
995 def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i64i32imm:$src),
996 "xor{q}\t{$src, %rax|%rax, $src}", []>;
1001 let Defs = [EFLAGS] in {
1002 let Constraints = "$src1 = $dst" in {
1003 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1004 // Register-Register Addition
1005 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
1006 (ins GR8 :$src1, GR8 :$src2),
1007 "add{b}\t{$src2, $dst|$dst, $src2}",
1008 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
1010 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1011 // Register-Register Addition
1012 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
1013 (ins GR16:$src1, GR16:$src2),
1014 "add{w}\t{$src2, $dst|$dst, $src2}",
1015 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
1016 GR16:$src2))]>, OpSize;
1017 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
1018 (ins GR32:$src1, GR32:$src2),
1019 "add{l}\t{$src2, $dst|$dst, $src2}",
1020 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
1022 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst),
1023 (ins GR64:$src1, GR64:$src2),
1024 "add{q}\t{$src2, $dst|$dst, $src2}",
1025 [(set GR64:$dst, EFLAGS,
1026 (X86add_flag GR64:$src1, GR64:$src2))]>;
1027 } // end isConvertibleToThreeAddress
1028 } // end isCommutable
1030 // These are alternate spellings for use by the disassembler, we mark them as
1031 // code gen only to ensure they aren't matched by the assembler.
1032 let isCodeGenOnly = 1 in {
1033 def ADD8rr_alt: I<0x02, MRMSrcReg,
1034 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1035 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
1036 def ADD16rr_alt: I<0x03, MRMSrcReg,
1037 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1038 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1039 def ADD32rr_alt: I<0x03, MRMSrcReg,
1040 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1041 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
1042 def ADD64rr_alt : RI<0x03, MRMSrcReg,
1043 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1044 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
1047 // Register-Memory Addition
1048 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
1049 (ins GR8 :$src1, i8mem :$src2),
1050 "add{b}\t{$src2, $dst|$dst, $src2}",
1051 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
1052 (load addr:$src2)))]>;
1053 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
1054 (ins GR16:$src1, i16mem:$src2),
1055 "add{w}\t{$src2, $dst|$dst, $src2}",
1056 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
1057 (load addr:$src2)))]>, OpSize;
1058 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
1059 (ins GR32:$src1, i32mem:$src2),
1060 "add{l}\t{$src2, $dst|$dst, $src2}",
1061 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
1062 (load addr:$src2)))]>;
1063 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst),
1064 (ins GR64:$src1, i64mem:$src2),
1065 "add{q}\t{$src2, $dst|$dst, $src2}",
1066 [(set GR64:$dst, EFLAGS,
1067 (X86add_flag GR64:$src1, (load addr:$src2)))]>;
1069 // Register-Integer Addition
1070 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1071 "add{b}\t{$src2, $dst|$dst, $src2}",
1072 [(set GR8:$dst, EFLAGS,
1073 (X86add_flag GR8:$src1, imm:$src2))]>;
1075 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1076 // Register-Integer Addition
1077 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
1078 (ins GR16:$src1, i16imm:$src2),
1079 "add{w}\t{$src2, $dst|$dst, $src2}",
1080 [(set GR16:$dst, EFLAGS,
1081 (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
1082 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
1083 (ins GR32:$src1, i32imm:$src2),
1084 "add{l}\t{$src2, $dst|$dst, $src2}",
1085 [(set GR32:$dst, EFLAGS,
1086 (X86add_flag GR32:$src1, imm:$src2))]>;
1087 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
1088 (ins GR16:$src1, i16i8imm:$src2),
1089 "add{w}\t{$src2, $dst|$dst, $src2}",
1090 [(set GR16:$dst, EFLAGS,
1091 (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1092 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
1093 (ins GR32:$src1, i32i8imm:$src2),
1094 "add{l}\t{$src2, $dst|$dst, $src2}",
1095 [(set GR32:$dst, EFLAGS,
1096 (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
1097 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst),
1098 (ins GR64:$src1, i64i8imm:$src2),
1099 "add{q}\t{$src2, $dst|$dst, $src2}",
1100 [(set GR64:$dst, EFLAGS,
1101 (X86add_flag GR64:$src1, i64immSExt8:$src2))]>;
1102 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst),
1103 (ins GR64:$src1, i64i32imm:$src2),
1104 "add{q}\t{$src2, $dst|$dst, $src2}",
1105 [(set GR64:$dst, EFLAGS,
1106 (X86add_flag GR64:$src1, i64immSExt32:$src2))]>;
1108 } // Constraints = "$src1 = $dst"
1110 // Memory-Register Addition
1111 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
1112 "add{b}\t{$src2, $dst|$dst, $src2}",
1113 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
1114 (implicit EFLAGS)]>;
1115 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1116 "add{w}\t{$src2, $dst|$dst, $src2}",
1117 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
1118 (implicit EFLAGS)]>, OpSize;
1119 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1120 "add{l}\t{$src2, $dst|$dst, $src2}",
1121 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
1122 (implicit EFLAGS)]>;
1123 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1124 "add{q}\t{$src2, $dst|$dst, $src2}",
1125 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
1126 (implicit EFLAGS)]>;
1127 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
1128 "add{b}\t{$src2, $dst|$dst, $src2}",
1129 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
1130 (implicit EFLAGS)]>;
1131 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
1132 "add{w}\t{$src2, $dst|$dst, $src2}",
1133 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
1134 (implicit EFLAGS)]>, OpSize;
1135 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
1136 "add{l}\t{$src2, $dst|$dst, $src2}",
1137 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
1138 (implicit EFLAGS)]>;
1139 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
1140 "add{q}\t{$src2, $dst|$dst, $src2}",
1141 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
1142 (implicit EFLAGS)]>;
1143 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1144 "add{w}\t{$src2, $dst|$dst, $src2}",
1145 [(store (add (load addr:$dst), i16immSExt8:$src2),
1147 (implicit EFLAGS)]>, OpSize;
1148 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1149 "add{l}\t{$src2, $dst|$dst, $src2}",
1150 [(store (add (load addr:$dst), i32immSExt8:$src2),
1152 (implicit EFLAGS)]>;
1153 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1154 "add{q}\t{$src2, $dst|$dst, $src2}",
1155 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
1156 (implicit EFLAGS)]>;
1159 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
1160 "add{b}\t{$src, %al|%al, $src}", []>;
1161 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
1162 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1163 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
1164 "add{l}\t{$src, %eax|%eax, $src}", []>;
1165 def ADD64i32 : RIi32<0x05, RawFrm, (outs), (ins i64i32imm:$src),
1166 "add{q}\t{$src, %rax|%rax, $src}", []>;
1168 let Uses = [EFLAGS] in {
1169 let Constraints = "$src1 = $dst" in {
1170 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1171 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1172 "adc{b}\t{$src2, $dst|$dst, $src2}",
1173 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
1174 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
1175 (ins GR16:$src1, GR16:$src2),
1176 "adc{w}\t{$src2, $dst|$dst, $src2}",
1177 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
1178 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
1179 (ins GR32:$src1, GR32:$src2),
1180 "adc{l}\t{$src2, $dst|$dst, $src2}",
1181 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
1182 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst),
1183 (ins GR64:$src1, GR64:$src2),
1184 "adc{q}\t{$src2, $dst|$dst, $src2}",
1185 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
1188 let isCodeGenOnly = 1 in {
1189 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1190 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
1191 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
1192 (ins GR16:$src1, GR16:$src2),
1193 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1194 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
1195 (ins GR32:$src1, GR32:$src2),
1196 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
1197 def ADC64rr_REV : RI<0x13, MRMSrcReg , (outs GR32:$dst),
1198 (ins GR64:$src1, GR64:$src2),
1199 "adc{q}\t{$src2, $dst|$dst, $src2}", []>;
1202 def ADC8rm : I<0x12, MRMSrcMem ,
1203 (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
1204 "adc{b}\t{$src2, $dst|$dst, $src2}",
1205 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
1206 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
1207 (ins GR16:$src1, i16mem:$src2),
1208 "adc{w}\t{$src2, $dst|$dst, $src2}",
1209 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
1211 def ADC32rm : I<0x13, MRMSrcMem ,
1212 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1213 "adc{l}\t{$src2, $dst|$dst, $src2}",
1214 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
1215 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst),
1216 (ins GR64:$src1, i64mem:$src2),
1217 "adc{q}\t{$src2, $dst|$dst, $src2}",
1218 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
1219 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1220 "adc{b}\t{$src2, $dst|$dst, $src2}",
1221 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
1222 def ADC16ri : Ii16<0x81, MRM2r,
1223 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1224 "adc{w}\t{$src2, $dst|$dst, $src2}",
1225 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
1226 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
1227 (ins GR16:$src1, i16i8imm:$src2),
1228 "adc{w}\t{$src2, $dst|$dst, $src2}",
1229 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
1231 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
1232 (ins GR32:$src1, i32imm:$src2),
1233 "adc{l}\t{$src2, $dst|$dst, $src2}",
1234 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
1235 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
1236 (ins GR32:$src1, i32i8imm:$src2),
1237 "adc{l}\t{$src2, $dst|$dst, $src2}",
1238 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
1239 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst),
1240 (ins GR64:$src1, i64i32imm:$src2),
1241 "adc{q}\t{$src2, $dst|$dst, $src2}",
1242 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
1243 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst),
1244 (ins GR64:$src1, i64i8imm:$src2),
1245 "adc{q}\t{$src2, $dst|$dst, $src2}",
1246 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
1247 } // Constraints = "$src1 = $dst"
1249 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
1250 "adc{b}\t{$src2, $dst|$dst, $src2}",
1251 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
1252 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1253 "adc{w}\t{$src2, $dst|$dst, $src2}",
1254 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
1256 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1257 "adc{l}\t{$src2, $dst|$dst, $src2}",
1258 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
1259 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1260 "adc{q}\t{$src2, $dst|$dst, $src2}",
1261 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
1262 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
1263 "adc{b}\t{$src2, $dst|$dst, $src2}",
1264 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1265 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
1266 "adc{w}\t{$src2, $dst|$dst, $src2}",
1267 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1269 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1270 "adc{w}\t{$src2, $dst|$dst, $src2}",
1271 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1273 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
1274 "adc{l}\t{$src2, $dst|$dst, $src2}",
1275 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1276 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1277 "adc{l}\t{$src2, $dst|$dst, $src2}",
1278 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1280 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
1281 "adc{q}\t{$src2, $dst|$dst, $src2}",
1282 [(store (adde (load addr:$dst), i64immSExt32:$src2),
1284 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1285 "adc{q}\t{$src2, $dst|$dst, $src2}",
1286 [(store (adde (load addr:$dst), i64immSExt8:$src2),
1289 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
1290 "adc{b}\t{$src, %al|%al, $src}", []>;
1291 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
1292 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1293 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
1294 "adc{l}\t{$src, %eax|%eax, $src}", []>;
1295 def ADC64i32 : RIi32<0x15, RawFrm, (outs), (ins i64i32imm:$src),
1296 "adc{q}\t{$src, %rax|%rax, $src}", []>;
1297 } // Uses = [EFLAGS]
1299 let Constraints = "$src1 = $dst" in {
1301 // Register-Register Subtraction
1302 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1303 "sub{b}\t{$src2, $dst|$dst, $src2}",
1304 [(set GR8:$dst, EFLAGS,
1305 (X86sub_flag GR8:$src1, GR8:$src2))]>;
1306 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
1307 "sub{w}\t{$src2, $dst|$dst, $src2}",
1308 [(set GR16:$dst, EFLAGS,
1309 (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
1310 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
1311 "sub{l}\t{$src2, $dst|$dst, $src2}",
1312 [(set GR32:$dst, EFLAGS,
1313 (X86sub_flag GR32:$src1, GR32:$src2))]>;
1314 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst),
1315 (ins GR64:$src1, GR64:$src2),
1316 "sub{q}\t{$src2, $dst|$dst, $src2}",
1317 [(set GR64:$dst, EFLAGS,
1318 (X86sub_flag GR64:$src1, GR64:$src2))]>;
1320 let isCodeGenOnly = 1 in {
1321 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1322 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
1323 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
1324 (ins GR16:$src1, GR16:$src2),
1325 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1326 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
1327 (ins GR32:$src1, GR32:$src2),
1328 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
1329 def SUB64rr_REV : RI<0x2B, MRMSrcReg, (outs GR64:$dst),
1330 (ins GR64:$src1, GR64:$src2),
1331 "sub{q}\t{$src2, $dst|$dst, $src2}", []>;
1334 // Register-Memory Subtraction
1335 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
1336 (ins GR8 :$src1, i8mem :$src2),
1337 "sub{b}\t{$src2, $dst|$dst, $src2}",
1338 [(set GR8:$dst, EFLAGS,
1339 (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
1340 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
1341 (ins GR16:$src1, i16mem:$src2),
1342 "sub{w}\t{$src2, $dst|$dst, $src2}",
1343 [(set GR16:$dst, EFLAGS,
1344 (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
1345 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
1346 (ins GR32:$src1, i32mem:$src2),
1347 "sub{l}\t{$src2, $dst|$dst, $src2}",
1348 [(set GR32:$dst, EFLAGS,
1349 (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
1350 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst),
1351 (ins GR64:$src1, i64mem:$src2),
1352 "sub{q}\t{$src2, $dst|$dst, $src2}",
1353 [(set GR64:$dst, EFLAGS,
1354 (X86sub_flag GR64:$src1, (load addr:$src2)))]>;
1356 // Register-Integer Subtraction
1357 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
1358 (ins GR8:$src1, i8imm:$src2),
1359 "sub{b}\t{$src2, $dst|$dst, $src2}",
1360 [(set GR8:$dst, EFLAGS,
1361 (X86sub_flag GR8:$src1, imm:$src2))]>;
1362 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
1363 (ins GR16:$src1, i16imm:$src2),
1364 "sub{w}\t{$src2, $dst|$dst, $src2}",
1365 [(set GR16:$dst, EFLAGS,
1366 (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
1367 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
1368 (ins GR32:$src1, i32imm:$src2),
1369 "sub{l}\t{$src2, $dst|$dst, $src2}",
1370 [(set GR32:$dst, EFLAGS,
1371 (X86sub_flag GR32:$src1, imm:$src2))]>;
1372 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
1373 (ins GR64:$src1, i64i32imm:$src2),
1374 "sub{q}\t{$src2, $dst|$dst, $src2}",
1375 [(set GR64:$dst, EFLAGS,
1376 (X86sub_flag GR64:$src1, i64immSExt32:$src2))]>;
1377 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
1378 (ins GR16:$src1, i16i8imm:$src2),
1379 "sub{w}\t{$src2, $dst|$dst, $src2}",
1380 [(set GR16:$dst, EFLAGS,
1381 (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1382 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
1383 (ins GR32:$src1, i32i8imm:$src2),
1384 "sub{l}\t{$src2, $dst|$dst, $src2}",
1385 [(set GR32:$dst, EFLAGS,
1386 (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
1387 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
1388 (ins GR64:$src1, i64i8imm:$src2),
1389 "sub{q}\t{$src2, $dst|$dst, $src2}",
1390 [(set GR64:$dst, EFLAGS,
1391 (X86sub_flag GR64:$src1, i64immSExt8:$src2))]>;
1392 } // Constraints = "$src1 = $dst"
1394 // Memory-Register Subtraction
1395 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1396 "sub{b}\t{$src2, $dst|$dst, $src2}",
1397 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
1398 (implicit EFLAGS)]>;
1399 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1400 "sub{w}\t{$src2, $dst|$dst, $src2}",
1401 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
1402 (implicit EFLAGS)]>, OpSize;
1403 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1404 "sub{l}\t{$src2, $dst|$dst, $src2}",
1405 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
1406 (implicit EFLAGS)]>;
1407 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1408 "sub{q}\t{$src2, $dst|$dst, $src2}",
1409 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
1410 (implicit EFLAGS)]>;
1412 // Memory-Integer Subtraction
1413 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
1414 "sub{b}\t{$src2, $dst|$dst, $src2}",
1415 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
1416 (implicit EFLAGS)]>;
1417 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
1418 "sub{w}\t{$src2, $dst|$dst, $src2}",
1419 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
1420 (implicit EFLAGS)]>, OpSize;
1421 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
1422 "sub{l}\t{$src2, $dst|$dst, $src2}",
1423 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
1424 (implicit EFLAGS)]>;
1425 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
1426 "sub{q}\t{$src2, $dst|$dst, $src2}",
1427 [(store (sub (load addr:$dst), i64immSExt32:$src2),
1429 (implicit EFLAGS)]>;
1430 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1431 "sub{w}\t{$src2, $dst|$dst, $src2}",
1432 [(store (sub (load addr:$dst), i16immSExt8:$src2),
1434 (implicit EFLAGS)]>, OpSize;
1435 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1436 "sub{l}\t{$src2, $dst|$dst, $src2}",
1437 [(store (sub (load addr:$dst), i32immSExt8:$src2),
1439 (implicit EFLAGS)]>;
1440 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1441 "sub{q}\t{$src2, $dst|$dst, $src2}",
1442 [(store (sub (load addr:$dst), i64immSExt8:$src2),
1444 (implicit EFLAGS)]>;
1446 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
1447 "sub{b}\t{$src, %al|%al, $src}", []>;
1448 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
1449 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1450 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
1451 "sub{l}\t{$src, %eax|%eax, $src}", []>;
1452 def SUB64i32 : RIi32<0x2D, RawFrm, (outs), (ins i64i32imm:$src),
1453 "sub{q}\t{$src, %rax|%rax, $src}", []>;
1455 let Uses = [EFLAGS] in {
1456 let Constraints = "$src1 = $dst" in {
1457 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
1458 (ins GR8:$src1, GR8:$src2),
1459 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1460 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
1461 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
1462 (ins GR16:$src1, GR16:$src2),
1463 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1464 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
1465 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
1466 (ins GR32:$src1, GR32:$src2),
1467 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1468 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
1469 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst),
1470 (ins GR64:$src1, GR64:$src2),
1471 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1472 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
1473 } // Constraints = "$src1 = $dst"
1476 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
1477 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1478 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
1479 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1480 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1481 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
1483 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1484 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1485 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
1486 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1487 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1488 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
1490 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
1491 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1492 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1493 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
1494 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1495 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1497 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1498 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1499 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1501 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
1502 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1503 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1504 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1505 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1506 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1507 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
1508 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1509 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
1510 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
1511 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1512 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
1514 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
1515 "sbb{b}\t{$src, %al|%al, $src}", []>;
1516 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
1517 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1518 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
1519 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
1520 def SBB64i32 : RIi32<0x1D, RawFrm, (outs), (ins i64i32imm:$src),
1521 "sbb{q}\t{$src, %rax|%rax, $src}", []>;
1523 let Constraints = "$src1 = $dst" in {
1525 let isCodeGenOnly = 1 in {
1526 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1527 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
1528 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
1529 (ins GR16:$src1, GR16:$src2),
1530 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1531 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
1532 (ins GR32:$src1, GR32:$src2),
1533 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
1534 def SBB64rr_REV : RI<0x1B, MRMSrcReg, (outs GR64:$dst),
1535 (ins GR64:$src1, GR64:$src2),
1536 "sbb{q}\t{$src2, $dst|$dst, $src2}", []>;
1539 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
1540 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1541 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
1542 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
1543 (ins GR16:$src1, i16mem:$src2),
1544 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1545 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
1547 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
1548 (ins GR32:$src1, i32mem:$src2),
1549 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1550 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
1551 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst),
1552 (ins GR64:$src1, i64mem:$src2),
1553 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1554 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
1555 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1556 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1557 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
1558 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
1559 (ins GR16:$src1, i16imm:$src2),
1560 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1561 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
1562 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
1563 (ins GR16:$src1, i16i8imm:$src2),
1564 "sbb{w}\t{$src2, $dst|$dst, $src2}",
1565 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
1567 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
1568 (ins GR32:$src1, i32imm:$src2),
1569 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1570 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
1571 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
1572 (ins GR32:$src1, i32i8imm:$src2),
1573 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1574 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
1575 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst),
1576 (ins GR64:$src1, i64i32imm:$src2),
1577 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1578 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
1579 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst),
1580 (ins GR64:$src1, i64i8imm:$src2),
1581 "sbb{q}\t{$src2, $dst|$dst, $src2}",
1582 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
1584 } // Constraints = "$src1 = $dst"
1585 } // Uses = [EFLAGS]
1586 } // Defs = [EFLAGS]
1588 //===----------------------------------------------------------------------===//
1589 // Test instructions are just like AND, except they don't generate a result.
1591 let Defs = [EFLAGS] in {
1592 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
1593 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
1594 "test{b}\t{$src2, $src1|$src1, $src2}",
1595 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
1596 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
1597 "test{w}\t{$src2, $src1|$src1, $src2}",
1598 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
1601 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
1602 "test{l}\t{$src2, $src1|$src1, $src2}",
1603 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
1605 def TEST64rr : RI<0x85, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
1606 "test{q}\t{$src2, $src1|$src1, $src2}",
1607 [(set EFLAGS, (X86cmp (and GR64:$src1, GR64:$src2), 0))]>;
1610 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
1611 "test{b}\t{$src2, $src1|$src1, $src2}",
1612 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
1614 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
1615 "test{w}\t{$src2, $src1|$src1, $src2}",
1616 [(set EFLAGS, (X86cmp (and GR16:$src1,
1617 (loadi16 addr:$src2)), 0))]>, OpSize;
1618 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
1619 "test{l}\t{$src2, $src1|$src1, $src2}",
1620 [(set EFLAGS, (X86cmp (and GR32:$src1,
1621 (loadi32 addr:$src2)), 0))]>;
1622 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1623 "test{q}\t{$src2, $src1|$src1, $src2}",
1624 [(set EFLAGS, (X86cmp (and GR64:$src1, (loadi64 addr:$src2)),
1627 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
1628 (outs), (ins GR8:$src1, i8imm:$src2),
1629 "test{b}\t{$src2, $src1|$src1, $src2}",
1630 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
1631 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
1632 (outs), (ins GR16:$src1, i16imm:$src2),
1633 "test{w}\t{$src2, $src1|$src1, $src2}",
1634 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
1636 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
1637 (outs), (ins GR32:$src1, i32imm:$src2),
1638 "test{l}\t{$src2, $src1|$src1, $src2}",
1639 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
1640 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1641 (ins GR64:$src1, i64i32imm:$src2),
1642 "test{q}\t{$src2, $src1|$src1, $src2}",
1643 [(set EFLAGS, (X86cmp (and GR64:$src1, i64immSExt32:$src2),
1646 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
1647 (outs), (ins i8mem:$src1, i8imm:$src2),
1648 "test{b}\t{$src2, $src1|$src1, $src2}",
1649 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
1651 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
1652 (outs), (ins i16mem:$src1, i16imm:$src2),
1653 "test{w}\t{$src2, $src1|$src1, $src2}",
1654 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
1656 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
1657 (outs), (ins i32mem:$src1, i32imm:$src2),
1658 "test{l}\t{$src2, $src1|$src1, $src2}",
1659 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
1661 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1662 (ins i64mem:$src1, i64i32imm:$src2),
1663 "test{q}\t{$src2, $src1|$src1, $src2}",
1664 [(set EFLAGS, (X86cmp (and (loadi64 addr:$src1),
1665 i64immSExt32:$src2), 0))]>;
1667 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
1668 "test{b}\t{$src, %al|%al, $src}", []>;
1669 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
1670 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1671 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
1672 "test{l}\t{$src, %eax|%eax, $src}", []>;
1673 def TEST64i32 : RIi32<0xa9, RawFrm, (outs), (ins i64i32imm:$src),
1674 "test{q}\t{$src, %rax|%rax, $src}", []>;
1676 } // Defs = [EFLAGS]