1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 let Predicates = [HasAVX512] in {
94 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
99 //===----------------------------------------------------------------------===//
100 // AVX-512 - VECTOR INSERT
103 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
104 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
105 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
106 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
107 []>, EVEX_4V, EVEX_V512;
109 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
110 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
111 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
112 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
115 // -- 64x4 fp form --
116 let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
117 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
118 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
119 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
120 []>, EVEX_4V, EVEX_V512, VEX_W;
122 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
123 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
124 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
125 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
127 // -- 32x4 integer form --
128 let hasSideEffects = 0 in {
129 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
130 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
131 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
132 []>, EVEX_4V, EVEX_V512;
134 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
135 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
136 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
137 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
141 let hasSideEffects = 0 in {
143 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
144 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
145 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
146 []>, EVEX_4V, EVEX_V512, VEX_W;
148 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
149 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
150 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
151 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
154 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
155 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
156 (INSERT_get_vinsert128_imm VR512:$ins))>;
157 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
158 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
159 (INSERT_get_vinsert128_imm VR512:$ins))>;
160 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
161 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
162 (INSERT_get_vinsert128_imm VR512:$ins))>;
163 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
164 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
165 (INSERT_get_vinsert128_imm VR512:$ins))>;
167 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
168 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
169 (INSERT_get_vinsert128_imm VR512:$ins))>;
170 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
171 (bc_v4i32 (loadv2i64 addr:$src2)),
172 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
173 (INSERT_get_vinsert128_imm VR512:$ins))>;
174 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
175 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
176 (INSERT_get_vinsert128_imm VR512:$ins))>;
177 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
178 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
179 (INSERT_get_vinsert128_imm VR512:$ins))>;
181 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
182 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
183 (INSERT_get_vinsert256_imm VR512:$ins))>;
184 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
185 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
186 (INSERT_get_vinsert256_imm VR512:$ins))>;
187 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
188 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
189 (INSERT_get_vinsert256_imm VR512:$ins))>;
190 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
191 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
192 (INSERT_get_vinsert256_imm VR512:$ins))>;
194 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
195 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
196 (INSERT_get_vinsert256_imm VR512:$ins))>;
197 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
198 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
199 (INSERT_get_vinsert256_imm VR512:$ins))>;
200 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
201 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
202 (INSERT_get_vinsert256_imm VR512:$ins))>;
203 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
204 (bc_v8i32 (loadv4i64 addr:$src2)),
205 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
206 (INSERT_get_vinsert256_imm VR512:$ins))>;
208 // vinsertps - insert f32 to XMM
209 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
210 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
211 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
212 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
214 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
215 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
216 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
217 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
218 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
219 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
221 //===----------------------------------------------------------------------===//
222 // AVX-512 VECTOR EXTRACT
224 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
226 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
227 (ins VR512:$src1, i8imm:$src2),
228 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
229 []>, EVEX, EVEX_V512;
230 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
231 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
232 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
233 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
236 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
237 (ins VR512:$src1, i8imm:$src2),
238 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
239 []>, EVEX, EVEX_V512, VEX_W;
241 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
242 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
243 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
244 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
247 let hasSideEffects = 0 in {
249 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
250 (ins VR512:$src1, i8imm:$src2),
251 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
252 []>, EVEX, EVEX_V512;
253 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
254 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
255 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
256 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
259 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
260 (ins VR512:$src1, i8imm:$src2),
261 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
262 []>, EVEX, EVEX_V512, VEX_W;
264 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
265 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
266 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
267 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
270 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
271 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
272 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
274 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
275 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
276 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
278 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
279 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
280 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
282 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
283 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
284 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
287 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
288 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
289 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
291 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
292 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
293 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
295 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
296 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
297 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
299 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
300 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
301 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
303 // A 256-bit subvector extract from the first 512-bit vector position
304 // is a subregister copy that needs no instruction.
305 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
306 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
307 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
308 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
309 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
310 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
311 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
312 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
315 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
316 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
317 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
318 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
319 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
320 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
321 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
322 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
325 // A 128-bit subvector insert to the first 512-bit vector position
326 // is a subregister copy that needs no instruction.
327 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
328 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
329 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
331 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
332 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
333 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
335 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
336 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
337 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
339 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
340 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
341 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
344 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
345 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
346 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
347 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
348 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
349 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
350 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
351 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
353 // vextractps - extract 32 bits from XMM
354 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
355 (ins VR128X:$src1, u32u8imm:$src2),
356 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
357 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
360 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
361 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
362 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
363 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
364 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
366 //===---------------------------------------------------------------------===//
369 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
370 RegisterClass DestRC,
371 RegisterClass SrcRC, X86MemOperand x86memop> {
372 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
373 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
375 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
376 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
378 let ExeDomain = SSEPackedSingle in {
379 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
381 EVEX_V512, EVEX_CD8<32, CD8VT1>;
384 let ExeDomain = SSEPackedDouble in {
385 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
387 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
390 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
391 (VBROADCASTSSZrm addr:$src)>;
392 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
393 (VBROADCASTSDZrm addr:$src)>;
395 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
396 (VBROADCASTSSZrm addr:$src)>;
397 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
398 (VBROADCASTSDZrm addr:$src)>;
400 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
401 RegisterClass SrcRC, RegisterClass KRC> {
402 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
403 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
404 []>, EVEX, EVEX_V512;
405 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
406 (ins KRC:$mask, SrcRC:$src),
407 !strconcat(OpcodeStr,
408 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
409 []>, EVEX, EVEX_V512, EVEX_KZ;
412 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
413 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
416 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
417 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
419 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
420 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
422 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
423 (VPBROADCASTDrZrr GR32:$src)>;
424 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
425 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
426 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
427 (VPBROADCASTQrZrr GR64:$src)>;
428 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
429 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
431 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
432 (VPBROADCASTDrZrr GR32:$src)>;
433 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
434 (VPBROADCASTQrZrr GR64:$src)>;
436 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
437 (v16i32 immAllZerosV), (i16 GR16:$mask))),
438 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
439 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
440 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
441 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
443 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
444 X86MemOperand x86memop, PatFrag ld_frag,
445 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
447 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
448 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
450 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
451 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
453 !strconcat(OpcodeStr,
454 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
456 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
459 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
460 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
462 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
463 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
465 !strconcat(OpcodeStr,
466 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
467 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
468 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
472 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
473 loadi32, VR512, v16i32, v4i32, VK16WM>,
474 EVEX_V512, EVEX_CD8<32, CD8VT1>;
475 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
476 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
477 EVEX_CD8<64, CD8VT1>;
479 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
480 (VPBROADCASTDZrr VR128X:$src)>;
481 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
482 (VPBROADCASTQZrr VR128X:$src)>;
484 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
485 (VBROADCASTSSZrr VR128X:$src)>;
486 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
487 (VBROADCASTSDZrr VR128X:$src)>;
489 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
490 (VBROADCASTSSZrr VR128X:$src)>;
491 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
492 (VBROADCASTSDZrr VR128X:$src)>;
494 // Provide fallback in case the load node that is used in the patterns above
495 // is used by additional users, which prevents the pattern selection.
496 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
497 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
498 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
499 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
502 let Predicates = [HasAVX512] in {
503 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
505 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
506 addr:$src)), sub_ymm)>;
508 //===----------------------------------------------------------------------===//
509 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
512 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
513 RegisterClass DstRC, RegisterClass KRC,
514 ValueType OpVT, ValueType SrcVT> {
515 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
516 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
520 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
521 VK16, v16i32, v16i1>, EVEX_V512;
522 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
523 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
525 //===----------------------------------------------------------------------===//
528 // -- immediate form --
529 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
530 SDNode OpNode, PatFrag mem_frag,
531 X86MemOperand x86memop, ValueType OpVT> {
532 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
533 (ins RC:$src1, i8imm:$src2),
534 !strconcat(OpcodeStr,
535 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
537 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
539 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
540 (ins x86memop:$src1, i8imm:$src2),
541 !strconcat(OpcodeStr,
542 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
544 (OpVT (OpNode (mem_frag addr:$src1),
545 (i8 imm:$src2))))]>, EVEX;
548 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
549 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
550 let ExeDomain = SSEPackedDouble in
551 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
552 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
554 // -- VPERM - register form --
555 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
556 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
558 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
559 (ins RC:$src1, RC:$src2),
560 !strconcat(OpcodeStr,
561 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
563 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
565 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
566 (ins RC:$src1, x86memop:$src2),
567 !strconcat(OpcodeStr,
568 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
570 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
574 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
575 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
576 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
577 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
578 let ExeDomain = SSEPackedSingle in
579 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
580 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
581 let ExeDomain = SSEPackedDouble in
582 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
583 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
585 // -- VPERM2I - 3 source operands form --
586 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
587 PatFrag mem_frag, X86MemOperand x86memop,
588 SDNode OpNode, ValueType OpVT> {
589 let Constraints = "$src1 = $dst" in {
590 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
591 (ins RC:$src1, RC:$src2, RC:$src3),
592 !strconcat(OpcodeStr,
593 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
595 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
598 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
599 (ins RC:$src1, RC:$src2, x86memop:$src3),
600 !strconcat(OpcodeStr,
601 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
603 (OpVT (OpNode RC:$src1, RC:$src2,
604 (mem_frag addr:$src3))))]>, EVEX_4V;
607 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
608 X86VPermiv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
609 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
610 X86VPermiv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
611 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
612 X86VPermiv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
613 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
614 X86VPermiv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
616 defm VPERMT2D : avx512_perm_3src<0x7E, "vpermt2d", VR512, memopv16i32, i512mem,
617 X86VPermv3, v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
618 defm VPERMT2Q : avx512_perm_3src<0x7E, "vpermt2q", VR512, memopv8i64, i512mem,
619 X86VPermv3, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
620 defm VPERMT2PS : avx512_perm_3src<0x7F, "vpermt2ps", VR512, memopv16f32, i512mem,
621 X86VPermv3, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
622 defm VPERMT2PD : avx512_perm_3src<0x7F, "vpermt2pd", VR512, memopv8f64, i512mem,
623 X86VPermv3, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
624 //===----------------------------------------------------------------------===//
625 // AVX-512 - BLEND using mask
627 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
628 RegisterClass KRC, RegisterClass RC,
629 X86MemOperand x86memop, PatFrag mem_frag,
630 SDNode OpNode, ValueType vt> {
631 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
632 (ins KRC:$mask, RC:$src1, RC:$src2),
633 !strconcat(OpcodeStr,
634 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
635 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
636 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
638 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
639 (ins KRC:$mask, RC:$src1, x86memop:$src2),
640 !strconcat(OpcodeStr,
641 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
642 []>, EVEX_4V, EVEX_K;
645 let ExeDomain = SSEPackedSingle in
646 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
647 VK16WM, VR512, f512mem,
648 memopv16f32, vselect, v16f32>,
649 EVEX_CD8<32, CD8VF>, EVEX_V512;
650 let ExeDomain = SSEPackedDouble in
651 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
652 VK8WM, VR512, f512mem,
653 memopv8f64, vselect, v8f64>,
654 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
656 def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
657 (v16f32 VR512:$src2), (i16 GR16:$mask))),
658 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
659 VR512:$src1, VR512:$src2)>;
661 def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
662 (v8f64 VR512:$src2), (i8 GR8:$mask))),
663 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
664 VR512:$src1, VR512:$src2)>;
666 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
667 VK16WM, VR512, f512mem,
668 memopv16i32, vselect, v16i32>,
669 EVEX_CD8<32, CD8VF>, EVEX_V512;
671 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
672 VK8WM, VR512, f512mem,
673 memopv8i64, vselect, v8i64>,
674 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
676 def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
677 (v16i32 VR512:$src2), (i16 GR16:$mask))),
678 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
679 VR512:$src1, VR512:$src2)>;
681 def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
682 (v8i64 VR512:$src2), (i8 GR8:$mask))),
683 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
684 VR512:$src1, VR512:$src2)>;
686 let Predicates = [HasAVX512] in {
687 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
688 (v8f32 VR256X:$src2))),
690 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
691 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
692 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
694 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
695 (v8i32 VR256X:$src2))),
697 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
698 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
699 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
701 //===----------------------------------------------------------------------===//
702 // Compare Instructions
703 //===----------------------------------------------------------------------===//
705 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
706 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
707 Operand CC, SDNode OpNode, ValueType VT,
708 PatFrag ld_frag, string asm, string asm_alt> {
709 def rr : AVX512Ii8<0xC2, MRMSrcReg,
710 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
711 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
712 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
713 def rm : AVX512Ii8<0xC2, MRMSrcMem,
714 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
715 [(set VK1:$dst, (OpNode (VT RC:$src1),
716 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
717 let isAsmParserOnly = 1, hasSideEffects = 0 in {
718 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
719 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
720 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
721 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
722 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
723 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
727 let Predicates = [HasAVX512] in {
728 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
729 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
730 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
732 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
733 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
734 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
738 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
739 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
740 SDNode OpNode, ValueType vt> {
741 def rr : AVX512BI<opc, MRMSrcReg,
742 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
743 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
744 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
745 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
746 def rm : AVX512BI<opc, MRMSrcMem,
747 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
748 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
749 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
750 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
753 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
754 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512,
756 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
757 memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512,
758 VEX_W, EVEX_CD8<64, CD8VF>;
760 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
761 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512,
763 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
764 memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512,
765 VEX_W, EVEX_CD8<64, CD8VF>;
767 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
768 (COPY_TO_REGCLASS (VPCMPGTDZrr
769 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
770 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
772 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
773 (COPY_TO_REGCLASS (VPCMPEQDZrr
774 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
775 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
777 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
778 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
779 SDNode OpNode, ValueType vt, Operand CC, string asm,
781 def rri : AVX512AIi8<opc, MRMSrcReg,
782 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
783 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
784 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
785 def rmi : AVX512AIi8<opc, MRMSrcMem,
786 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
787 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
788 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
789 // Accept explicit immediate argument form instead of comparison code.
790 let isAsmParserOnly = 1, hasSideEffects = 0 in {
791 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
792 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
793 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
794 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
795 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
796 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
800 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
801 X86cmpm, v16i32, AVXCC,
802 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
803 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
804 EVEX_V512, EVEX_CD8<32, CD8VF>;
805 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
806 X86cmpmu, v16i32, AVXCC,
807 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
808 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
809 EVEX_V512, EVEX_CD8<32, CD8VF>;
811 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
812 X86cmpm, v8i64, AVXCC,
813 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
814 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
815 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
816 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
817 X86cmpmu, v8i64, AVXCC,
818 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
819 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
820 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
822 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
823 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
824 X86MemOperand x86memop, ValueType vt,
825 string suffix, Domain d> {
826 def rri : AVX512PIi8<0xC2, MRMSrcReg,
827 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
828 !strconcat("vcmp${cc}", suffix,
829 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
830 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
831 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
832 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
833 !strconcat("vcmp${cc}", suffix,
834 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
836 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
837 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
838 !strconcat("vcmp${cc}", suffix,
839 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
841 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
843 // Accept explicit immediate argument form instead of comparison code.
844 let isAsmParserOnly = 1, hasSideEffects = 0 in {
845 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
846 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
847 !strconcat("vcmp", suffix,
848 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
849 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
850 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
851 !strconcat("vcmp", suffix,
852 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
856 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
857 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
859 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
860 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
863 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
864 (COPY_TO_REGCLASS (VCMPPSZrri
865 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
866 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
868 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
869 (COPY_TO_REGCLASS (VPCMPDZrri
870 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
871 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
873 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
874 (COPY_TO_REGCLASS (VPCMPUDZrri
875 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
876 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
879 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
880 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
882 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
883 (I8Imm imm:$cc)), GR16)>;
885 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
886 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
888 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
889 (I8Imm imm:$cc)), GR8)>;
891 def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
892 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
894 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
895 (I8Imm imm:$cc)), GR16)>;
897 def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
898 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
900 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
901 (I8Imm imm:$cc)), GR8)>;
903 // Mask register copy, including
904 // - copy between mask registers
905 // - load/store mask registers
906 // - copy from GPR to mask register and vice versa
908 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
909 string OpcodeStr, RegisterClass KRC,
910 ValueType vt, X86MemOperand x86memop> {
911 let hasSideEffects = 0 in {
912 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
913 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
915 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
916 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
917 [(set KRC:$dst, (vt (load addr:$src)))]>;
919 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
920 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
924 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
926 RegisterClass KRC, RegisterClass GRC> {
927 let hasSideEffects = 0 in {
928 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
929 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
930 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
931 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
935 let Predicates = [HasAVX512] in {
936 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
938 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
942 let Predicates = [HasAVX512] in {
943 // GR16 from/to 16-bit mask
944 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
945 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
946 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
947 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
949 // Store kreg in memory
950 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
951 (KMOVWmk addr:$dst, VK16:$src)>;
953 def : Pat<(store VK8:$src, addr:$dst),
954 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
956 def : Pat<(i1 (load addr:$src)),
957 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
959 def : Pat<(v8i1 (load addr:$src)),
960 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
962 def : Pat<(i1 (trunc (i32 GR32:$src))),
963 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
965 def : Pat<(i1 (trunc (i8 GR8:$src))),
967 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
969 def : Pat<(i1 (trunc (i16 GR16:$src))),
971 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
974 def : Pat<(i32 (zext VK1:$src)),
975 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
976 def : Pat<(i8 (zext VK1:$src)),
979 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
980 def : Pat<(i64 (zext VK1:$src)),
981 (AND64ri8 (SUBREG_TO_REG (i64 0),
982 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
983 def : Pat<(i16 (zext VK1:$src)),
985 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
988 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
989 let Predicates = [HasAVX512] in {
990 // GR from/to 8-bit mask without native support
991 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
993 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
995 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
997 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1000 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1001 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1002 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1003 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1007 // Mask unary operation
1009 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1010 RegisterClass KRC, SDPatternOperator OpNode> {
1011 let Predicates = [HasAVX512] in
1012 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1013 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
1014 [(set KRC:$dst, (OpNode KRC:$src))]>;
1017 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
1018 SDPatternOperator OpNode> {
1019 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1023 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
1025 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1026 let Predicates = [HasAVX512] in
1027 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1029 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1030 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1032 defm : avx512_mask_unop_int<"knot", "KNOT">;
1034 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1035 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1036 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1038 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1039 def : Pat<(not VK8:$src),
1041 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1043 // Mask binary operation
1044 // - KAND, KANDN, KOR, KXNOR, KXOR
1045 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1046 RegisterClass KRC, SDPatternOperator OpNode> {
1047 let Predicates = [HasAVX512] in
1048 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1049 !strconcat(OpcodeStr,
1050 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1051 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1054 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
1055 SDPatternOperator OpNode> {
1056 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1060 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1061 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1063 let isCommutable = 1 in {
1064 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
1065 let isCommutable = 0 in
1066 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
1067 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
1068 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
1069 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
1072 def : Pat<(xor VK1:$src1, VK1:$src2),
1073 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1074 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1076 def : Pat<(or VK1:$src1, VK1:$src2),
1077 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1078 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1080 def : Pat<(and VK1:$src1, VK1:$src2),
1081 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1082 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1084 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1085 let Predicates = [HasAVX512] in
1086 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1087 (i16 GR16:$src1), (i16 GR16:$src2)),
1088 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1089 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1090 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1093 defm : avx512_mask_binop_int<"kand", "KAND">;
1094 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1095 defm : avx512_mask_binop_int<"kor", "KOR">;
1096 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1097 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1099 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1100 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1101 let Predicates = [HasAVX512] in
1102 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1104 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1105 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1108 defm : avx512_binop_pat<and, KANDWrr>;
1109 defm : avx512_binop_pat<andn, KANDNWrr>;
1110 defm : avx512_binop_pat<or, KORWrr>;
1111 defm : avx512_binop_pat<xnor, KXNORWrr>;
1112 defm : avx512_binop_pat<xor, KXORWrr>;
1115 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1116 RegisterClass KRC> {
1117 let Predicates = [HasAVX512] in
1118 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1119 !strconcat(OpcodeStr,
1120 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1123 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1124 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1128 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1129 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1130 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1131 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1134 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1135 let Predicates = [HasAVX512] in
1136 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1137 (i16 GR16:$src1), (i16 GR16:$src2)),
1138 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1139 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1140 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1142 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1145 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1147 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1148 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1149 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
1150 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1153 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1154 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1158 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1160 def : Pat<(X86cmp VK1:$src1, (i1 0)),
1161 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1162 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
1165 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1167 let Predicates = [HasAVX512] in
1168 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1169 !strconcat(OpcodeStr,
1170 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
1171 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1174 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1176 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1180 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1181 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1183 // Mask setting all 0s or 1s
1184 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1185 let Predicates = [HasAVX512] in
1186 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1187 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1188 [(set KRC:$dst, (VT Val))]>;
1191 multiclass avx512_mask_setop_w<PatFrag Val> {
1192 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1193 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1196 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1197 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1199 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1200 let Predicates = [HasAVX512] in {
1201 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1202 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1203 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1204 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1205 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1207 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1208 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1210 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1211 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1213 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1214 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1216 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1217 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1219 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1220 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1221 //===----------------------------------------------------------------------===//
1222 // AVX-512 - Aligned and unaligned load and store
1225 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1226 X86MemOperand x86memop, PatFrag ld_frag,
1227 string asm, Domain d, bit IsReMaterializable = 1> {
1228 let hasSideEffects = 0 in
1229 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1230 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), [], d>,
1232 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
1233 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1234 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1235 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1236 let Constraints = "$src1 = $dst" in {
1237 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1238 (ins RC:$src1, KRC:$mask, RC:$src2),
1240 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1242 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1243 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1245 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1246 [], d>, EVEX, EVEX_K;
1250 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1251 "vmovaps", SSEPackedSingle>,
1252 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1253 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1254 "vmovapd", SSEPackedDouble>,
1255 PD, EVEX_V512, VEX_W,
1256 EVEX_CD8<64, CD8VF>;
1257 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1258 "vmovups", SSEPackedSingle>,
1259 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1260 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1261 "vmovupd", SSEPackedDouble, 0>,
1262 PD, EVEX_V512, VEX_W,
1263 EVEX_CD8<64, CD8VF>;
1264 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1265 "vmovaps\t{$src, $dst|$dst, $src}",
1266 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1267 SSEPackedSingle>, EVEX, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
1268 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1269 "vmovapd\t{$src, $dst|$dst, $src}",
1270 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1271 SSEPackedDouble>, EVEX, EVEX_V512,
1272 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1273 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1274 "vmovups\t{$src, $dst|$dst, $src}",
1275 [(store (v16f32 VR512:$src), addr:$dst)],
1276 SSEPackedSingle>, EVEX, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
1277 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1278 "vmovupd\t{$src, $dst|$dst, $src}",
1279 [(store (v8f64 VR512:$src), addr:$dst)],
1280 SSEPackedDouble>, EVEX, EVEX_V512,
1281 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1283 let hasSideEffects = 0 in {
1284 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1286 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1288 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1290 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1291 EVEX, EVEX_V512, VEX_W;
1292 let mayStore = 1 in {
1293 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1294 (ins i512mem:$dst, VR512:$src),
1295 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1296 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1297 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1298 (ins i512mem:$dst, VR512:$src),
1299 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1300 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1302 let mayLoad = 1 in {
1303 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1305 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1306 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1307 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1309 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1310 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1314 // 512-bit aligned load/store
1315 def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1316 def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1318 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1319 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1320 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1321 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1323 multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1324 RegisterClass RC, RegisterClass KRC,
1325 PatFrag ld_frag, X86MemOperand x86memop> {
1326 let hasSideEffects = 0 in
1327 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1328 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), []>, EVEX;
1329 let canFoldAsLoad = 1 in
1330 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1331 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1332 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1334 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1335 (ins x86memop:$dst, VR512:$src),
1336 !strconcat(asm, " \t{$src, $dst|$dst, $src}"), []>, EVEX;
1337 let Constraints = "$src1 = $dst" in {
1338 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1339 (ins RC:$src1, KRC:$mask, RC:$src2),
1341 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1343 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
1344 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1346 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1349 def rrkz : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1350 (ins KRC:$mask, RC:$src),
1352 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"), []>,
1356 defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1357 memopv16i32, i512mem>,
1358 EVEX_V512, EVEX_CD8<32, CD8VF>;
1359 defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1360 memopv8i64, i512mem>,
1361 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1363 // 512-bit unaligned load/store
1364 def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1365 def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1367 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1368 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1369 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1370 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1372 let AddedComplexity = 20 in {
1373 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
1374 (bc_v8i64 (v16i32 immAllZerosV)))),
1375 (VMOVDQU64rrkz VK8WM:$mask, VR512:$src)>;
1377 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
1378 (v8i64 VR512:$src))),
1379 (VMOVDQU64rrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
1382 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
1383 (v16i32 immAllZerosV))),
1384 (VMOVDQU32rrkz VK16WM:$mask, VR512:$src)>;
1386 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
1387 (v16i32 VR512:$src))),
1388 (VMOVDQU32rrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
1390 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1391 (v16f32 VR512:$src2))),
1392 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1393 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1394 (v8f64 VR512:$src2))),
1395 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1396 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1397 (v16i32 VR512:$src2))),
1398 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1399 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1400 (v8i64 VR512:$src2))),
1401 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1403 // Move Int Doubleword to Packed Double Int
1405 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1406 "vmovd\t{$src, $dst|$dst, $src}",
1408 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1410 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1411 "vmovd\t{$src, $dst|$dst, $src}",
1413 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1414 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1415 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1416 "vmovq\t{$src, $dst|$dst, $src}",
1418 (v2i64 (scalar_to_vector GR64:$src)))],
1419 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1420 let isCodeGenOnly = 1 in {
1421 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1422 "vmovq\t{$src, $dst|$dst, $src}",
1423 [(set FR64:$dst, (bitconvert GR64:$src))],
1424 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1425 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1426 "vmovq\t{$src, $dst|$dst, $src}",
1427 [(set GR64:$dst, (bitconvert FR64:$src))],
1428 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1430 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1431 "vmovq\t{$src, $dst|$dst, $src}",
1432 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1433 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1434 EVEX_CD8<64, CD8VT1>;
1436 // Move Int Doubleword to Single Scalar
1438 let isCodeGenOnly = 1 in {
1439 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1440 "vmovd\t{$src, $dst|$dst, $src}",
1441 [(set FR32X:$dst, (bitconvert GR32:$src))],
1442 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1444 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1445 "vmovd\t{$src, $dst|$dst, $src}",
1446 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1447 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1450 // Move doubleword from xmm register to r/m32
1452 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1453 "vmovd\t{$src, $dst|$dst, $src}",
1454 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1455 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1457 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1458 (ins i32mem:$dst, VR128X:$src),
1459 "vmovd\t{$src, $dst|$dst, $src}",
1460 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1461 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1462 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1464 // Move quadword from xmm1 register to r/m64
1466 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1467 "vmovq\t{$src, $dst|$dst, $src}",
1468 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1470 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
1471 Requires<[HasAVX512, In64BitMode]>;
1473 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1474 (ins i64mem:$dst, VR128X:$src),
1475 "vmovq\t{$src, $dst|$dst, $src}",
1476 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1477 addr:$dst)], IIC_SSE_MOVDQ>,
1478 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
1479 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1481 // Move Scalar Single to Double Int
1483 let isCodeGenOnly = 1 in {
1484 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
1486 "vmovd\t{$src, $dst|$dst, $src}",
1487 [(set GR32:$dst, (bitconvert FR32X:$src))],
1488 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1489 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
1490 (ins i32mem:$dst, FR32X:$src),
1491 "vmovd\t{$src, $dst|$dst, $src}",
1492 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1493 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1496 // Move Quadword Int to Packed Quadword Int
1498 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1500 "vmovq\t{$src, $dst|$dst, $src}",
1502 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1503 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1505 //===----------------------------------------------------------------------===//
1506 // AVX-512 MOVSS, MOVSD
1507 //===----------------------------------------------------------------------===//
1509 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1510 SDNode OpNode, ValueType vt,
1511 X86MemOperand x86memop, PatFrag mem_pat> {
1512 let hasSideEffects = 0 in {
1513 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1514 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1515 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1516 (scalar_to_vector RC:$src2))))],
1517 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1518 let Constraints = "$src1 = $dst" in
1519 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1520 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1522 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1523 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1524 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1525 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1526 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1528 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1529 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
1530 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1532 } //hasSideEffects = 0
1535 let ExeDomain = SSEPackedSingle in
1536 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1537 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1539 let ExeDomain = SSEPackedDouble in
1540 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1541 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1543 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1544 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1545 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1547 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1548 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1549 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1551 // For the disassembler
1552 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1553 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1554 (ins VR128X:$src1, FR32X:$src2),
1555 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1557 XS, EVEX_4V, VEX_LIG;
1558 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1559 (ins VR128X:$src1, FR64X:$src2),
1560 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1562 XD, EVEX_4V, VEX_LIG, VEX_W;
1565 let Predicates = [HasAVX512] in {
1566 let AddedComplexity = 15 in {
1567 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1568 // MOVS{S,D} to the lower bits.
1569 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1570 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1571 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1572 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1573 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1574 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1575 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1576 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1578 // Move low f32 and clear high bits.
1579 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1580 (SUBREG_TO_REG (i32 0),
1581 (VMOVSSZrr (v4f32 (V_SET0)),
1582 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1583 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1584 (SUBREG_TO_REG (i32 0),
1585 (VMOVSSZrr (v4i32 (V_SET0)),
1586 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1589 let AddedComplexity = 20 in {
1590 // MOVSSrm zeros the high parts of the register; represent this
1591 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1592 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1593 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1594 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1595 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1596 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1597 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1599 // MOVSDrm zeros the high parts of the register; represent this
1600 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1601 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1602 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1603 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1604 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1605 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1606 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1607 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1608 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1609 def : Pat<(v2f64 (X86vzload addr:$src)),
1610 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1612 // Represent the same patterns above but in the form they appear for
1614 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1615 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1616 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1617 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1618 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1619 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1620 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1621 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1622 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1624 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1625 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1626 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1627 FR32X:$src)), sub_xmm)>;
1628 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1629 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1630 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1631 FR64X:$src)), sub_xmm)>;
1632 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1633 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1634 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1636 // Move low f64 and clear high bits.
1637 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1638 (SUBREG_TO_REG (i32 0),
1639 (VMOVSDZrr (v2f64 (V_SET0)),
1640 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1642 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1643 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1644 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1646 // Extract and store.
1647 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1649 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1650 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1652 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1654 // Shuffle with VMOVSS
1655 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1656 (VMOVSSZrr (v4i32 VR128X:$src1),
1657 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1658 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1659 (VMOVSSZrr (v4f32 VR128X:$src1),
1660 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1663 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1664 (SUBREG_TO_REG (i32 0),
1665 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1666 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1668 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1669 (SUBREG_TO_REG (i32 0),
1670 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1671 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1674 // Shuffle with VMOVSD
1675 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1676 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1677 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1678 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1679 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1680 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1681 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1682 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1685 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1686 (SUBREG_TO_REG (i32 0),
1687 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1688 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1690 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1691 (SUBREG_TO_REG (i32 0),
1692 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1693 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1696 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1697 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1698 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1699 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1700 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1701 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1702 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1703 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1706 let AddedComplexity = 15 in
1707 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1709 "vmovq\t{$src, $dst|$dst, $src}",
1710 [(set VR128X:$dst, (v2i64 (X86vzmovl
1711 (v2i64 VR128X:$src))))],
1712 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1714 let AddedComplexity = 20 in
1715 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1717 "vmovq\t{$src, $dst|$dst, $src}",
1718 [(set VR128X:$dst, (v2i64 (X86vzmovl
1719 (loadv2i64 addr:$src))))],
1720 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1721 EVEX_CD8<8, CD8VT8>;
1723 let Predicates = [HasAVX512] in {
1724 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1725 let AddedComplexity = 20 in {
1726 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1727 (VMOVDI2PDIZrm addr:$src)>;
1728 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1729 (VMOV64toPQIZrr GR64:$src)>;
1730 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1731 (VMOVDI2PDIZrr GR32:$src)>;
1733 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1734 (VMOVDI2PDIZrm addr:$src)>;
1735 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1736 (VMOVDI2PDIZrm addr:$src)>;
1737 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1738 (VMOVZPQILo2PQIZrm addr:$src)>;
1739 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1740 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1741 def : Pat<(v2i64 (X86vzload addr:$src)),
1742 (VMOVZPQILo2PQIZrm addr:$src)>;
1745 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1746 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1747 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1748 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1749 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1750 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1751 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1754 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1755 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1757 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1758 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1760 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1761 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1763 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1764 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1766 //===----------------------------------------------------------------------===//
1767 // AVX-512 - Integer arithmetic
1769 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1770 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1771 X86MemOperand x86memop, PatFrag scalar_mfrag,
1772 X86MemOperand x86scalar_mop, string BrdcstStr,
1773 OpndItins itins, bit IsCommutable = 0> {
1774 let isCommutable = IsCommutable in
1775 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1776 (ins RC:$src1, RC:$src2),
1777 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1778 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1780 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1781 (ins RC:$src1, x86memop:$src2),
1782 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1783 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1785 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1786 (ins RC:$src1, x86scalar_mop:$src2),
1787 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
1788 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1789 [(set RC:$dst, (OpNode RC:$src1,
1790 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1791 itins.rm>, EVEX_4V, EVEX_B;
1793 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1794 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1795 PatFrag memop_frag, X86MemOperand x86memop,
1797 bit IsCommutable = 0> {
1798 let isCommutable = IsCommutable in
1799 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1800 (ins RC:$src1, RC:$src2),
1801 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1802 []>, EVEX_4V, VEX_W;
1803 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1804 (ins RC:$src1, x86memop:$src2),
1805 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1806 []>, EVEX_4V, VEX_W;
1809 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1810 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1811 EVEX_V512, EVEX_CD8<32, CD8VF>;
1813 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1814 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1815 EVEX_V512, EVEX_CD8<32, CD8VF>;
1817 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1818 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1819 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1821 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1822 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1823 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1825 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1826 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1827 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1829 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1830 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8PD,
1831 EVEX_V512, EVEX_CD8<64, CD8VF>;
1833 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1834 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1835 EVEX_CD8<64, CD8VF>;
1837 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1838 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1840 def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
1841 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1842 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1843 def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
1844 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1845 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
1847 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1848 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1849 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1850 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1851 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1852 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1854 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1855 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1856 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1857 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1858 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1859 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1861 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1862 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1863 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1864 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1865 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1866 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1868 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1869 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1870 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1871 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1872 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1873 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1875 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
1876 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1877 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
1878 def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
1879 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1880 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
1881 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
1882 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1883 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
1884 def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
1885 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1886 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
1887 def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
1888 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1889 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
1890 def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
1891 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
1892 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
1893 def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
1894 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1895 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
1896 def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
1897 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
1898 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
1899 //===----------------------------------------------------------------------===//
1900 // AVX-512 - Unpack Instructions
1901 //===----------------------------------------------------------------------===//
1903 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1904 PatFrag mem_frag, RegisterClass RC,
1905 X86MemOperand x86memop, string asm,
1907 def rr : AVX512PI<opc, MRMSrcReg,
1908 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1910 (vt (OpNode RC:$src1, RC:$src2)))],
1912 def rm : AVX512PI<opc, MRMSrcMem,
1913 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1915 (vt (OpNode RC:$src1,
1916 (bitconvert (mem_frag addr:$src2)))))],
1920 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1921 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1922 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1923 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1924 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1925 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1926 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1927 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1928 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
1929 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1930 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1931 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1933 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1934 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1935 X86MemOperand x86memop> {
1936 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1937 (ins RC:$src1, RC:$src2),
1938 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1939 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1940 IIC_SSE_UNPCK>, EVEX_4V;
1941 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1942 (ins RC:$src1, x86memop:$src2),
1943 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1944 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1945 (bitconvert (memop_frag addr:$src2)))))],
1946 IIC_SSE_UNPCK>, EVEX_4V;
1948 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1949 VR512, memopv16i32, i512mem>, EVEX_V512,
1950 EVEX_CD8<32, CD8VF>;
1951 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1952 VR512, memopv8i64, i512mem>, EVEX_V512,
1953 VEX_W, EVEX_CD8<64, CD8VF>;
1954 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1955 VR512, memopv16i32, i512mem>, EVEX_V512,
1956 EVEX_CD8<32, CD8VF>;
1957 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1958 VR512, memopv8i64, i512mem>, EVEX_V512,
1959 VEX_W, EVEX_CD8<64, CD8VF>;
1960 //===----------------------------------------------------------------------===//
1964 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1965 SDNode OpNode, PatFrag mem_frag,
1966 X86MemOperand x86memop, ValueType OpVT> {
1967 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1968 (ins RC:$src1, i8imm:$src2),
1969 !strconcat(OpcodeStr,
1970 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1972 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1974 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1975 (ins x86memop:$src1, i8imm:$src2),
1976 !strconcat(OpcodeStr,
1977 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1979 (OpVT (OpNode (mem_frag addr:$src1),
1980 (i8 imm:$src2))))]>, EVEX;
1983 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1984 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
1986 let ExeDomain = SSEPackedSingle in
1987 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1988 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
1989 EVEX_CD8<32, CD8VF>;
1990 let ExeDomain = SSEPackedDouble in
1991 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1992 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
1993 VEX_W, EVEX_CD8<32, CD8VF>;
1995 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1996 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1997 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1998 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2000 //===----------------------------------------------------------------------===//
2001 // AVX-512 Logical Instructions
2002 //===----------------------------------------------------------------------===//
2004 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
2005 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2006 EVEX_V512, EVEX_CD8<32, CD8VF>;
2007 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
2008 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2009 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2010 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
2011 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2012 EVEX_V512, EVEX_CD8<32, CD8VF>;
2013 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
2014 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2015 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2016 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
2017 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2018 EVEX_V512, EVEX_CD8<32, CD8VF>;
2019 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
2020 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2021 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2022 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
2023 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2024 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2025 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
2026 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
2027 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2029 //===----------------------------------------------------------------------===//
2030 // AVX-512 FP arithmetic
2031 //===----------------------------------------------------------------------===//
2033 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2035 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
2036 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2037 EVEX_CD8<32, CD8VT1>;
2038 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
2039 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2040 EVEX_CD8<64, CD8VT1>;
2043 let isCommutable = 1 in {
2044 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2045 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2046 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2047 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2049 let isCommutable = 0 in {
2050 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2051 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2054 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2055 RegisterClass RC, ValueType vt,
2056 X86MemOperand x86memop, PatFrag mem_frag,
2057 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2059 Domain d, OpndItins itins, bit commutable> {
2060 let isCommutable = commutable in
2061 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2062 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2063 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
2065 let mayLoad = 1 in {
2066 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2067 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2068 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
2069 itins.rm, d>, EVEX_4V;
2070 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2071 (ins RC:$src1, x86scalar_mop:$src2),
2072 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2073 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2074 [(set RC:$dst, (OpNode RC:$src1,
2075 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2076 itins.rm, d>, EVEX_4V, EVEX_B;
2080 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
2081 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2082 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2084 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
2085 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2086 SSE_ALU_ITINS_P.d, 1>,
2087 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2089 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
2090 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2091 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2092 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
2093 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2094 SSE_ALU_ITINS_P.d, 1>,
2095 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2097 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
2098 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2099 SSE_ALU_ITINS_P.s, 1>,
2100 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2101 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
2102 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2103 SSE_ALU_ITINS_P.s, 1>,
2104 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2106 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
2107 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2108 SSE_ALU_ITINS_P.d, 1>,
2109 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2110 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
2111 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2112 SSE_ALU_ITINS_P.d, 1>,
2113 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2115 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
2116 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2117 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2118 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
2119 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2120 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
2122 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
2123 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2124 SSE_ALU_ITINS_P.d, 0>,
2125 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2126 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
2127 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2128 SSE_ALU_ITINS_P.d, 0>,
2129 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2131 def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2132 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2133 (i16 -1), FROUND_CURRENT)),
2134 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2136 def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2137 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2138 (i8 -1), FROUND_CURRENT)),
2139 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2141 def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2142 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2143 (i16 -1), FROUND_CURRENT)),
2144 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2146 def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2147 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2148 (i8 -1), FROUND_CURRENT)),
2149 (VMINPDZrr VR512:$src1, VR512:$src2)>;
2150 //===----------------------------------------------------------------------===//
2151 // AVX-512 VPTESTM instructions
2152 //===----------------------------------------------------------------------===//
2154 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2155 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2156 SDNode OpNode, ValueType vt> {
2157 def rr : AVX512PI<opc, MRMSrcReg,
2158 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2159 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2160 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2161 SSEPackedInt>, EVEX_4V;
2162 def rm : AVX512PI<opc, MRMSrcMem,
2163 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2164 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2165 [(set KRC:$dst, (OpNode (vt RC:$src1),
2166 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
2169 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2170 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
2171 EVEX_CD8<32, CD8VF>;
2172 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2173 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
2174 EVEX_CD8<64, CD8VF>;
2176 let Predicates = [HasCDI] in {
2177 defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
2178 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
2179 EVEX_CD8<32, CD8VF>;
2180 defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
2181 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
2182 EVEX_CD8<64, CD8VF>;
2185 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
2186 (v16i32 VR512:$src2), (i16 -1))),
2187 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
2189 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
2190 (v8i64 VR512:$src2), (i8 -1))),
2191 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
2192 //===----------------------------------------------------------------------===//
2193 // AVX-512 Shift instructions
2194 //===----------------------------------------------------------------------===//
2195 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2196 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2197 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2198 RegisterClass KRC> {
2199 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2200 (ins RC:$src1, i8imm:$src2),
2201 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2202 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2203 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2204 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2205 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2206 !strconcat(OpcodeStr,
2207 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2208 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2209 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2210 (ins x86memop:$src1, i8imm:$src2),
2211 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2212 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2213 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2214 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2215 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2216 !strconcat(OpcodeStr,
2217 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2218 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2221 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2222 RegisterClass RC, ValueType vt, ValueType SrcVT,
2223 PatFrag bc_frag, RegisterClass KRC> {
2224 // src2 is always 128-bit
2225 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2226 (ins RC:$src1, VR128X:$src2),
2227 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2228 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2229 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2230 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2231 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2232 !strconcat(OpcodeStr,
2233 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2234 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2235 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2236 (ins RC:$src1, i128mem:$src2),
2237 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2238 [(set RC:$dst, (vt (OpNode RC:$src1,
2239 (bc_frag (memopv2i64 addr:$src2)))))],
2240 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2241 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2242 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2243 !strconcat(OpcodeStr,
2244 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2245 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2248 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2249 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2250 EVEX_V512, EVEX_CD8<32, CD8VF>;
2251 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2252 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2253 EVEX_CD8<32, CD8VQ>;
2255 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2256 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2257 EVEX_CD8<64, CD8VF>, VEX_W;
2258 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2259 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2260 EVEX_CD8<64, CD8VQ>, VEX_W;
2262 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2263 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2264 EVEX_CD8<32, CD8VF>;
2265 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2266 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2267 EVEX_CD8<32, CD8VQ>;
2269 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2270 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2271 EVEX_CD8<64, CD8VF>, VEX_W;
2272 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2273 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2274 EVEX_CD8<64, CD8VQ>, VEX_W;
2276 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2277 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2278 EVEX_V512, EVEX_CD8<32, CD8VF>;
2279 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2280 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2281 EVEX_CD8<32, CD8VQ>;
2283 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2284 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2285 EVEX_CD8<64, CD8VF>, VEX_W;
2286 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2287 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2288 EVEX_CD8<64, CD8VQ>, VEX_W;
2290 //===-------------------------------------------------------------------===//
2291 // Variable Bit Shifts
2292 //===-------------------------------------------------------------------===//
2293 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2294 RegisterClass RC, ValueType vt,
2295 X86MemOperand x86memop, PatFrag mem_frag> {
2296 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2297 (ins RC:$src1, RC:$src2),
2298 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2300 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2302 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2303 (ins RC:$src1, x86memop:$src2),
2304 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2306 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2310 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2311 i512mem, memopv16i32>, EVEX_V512,
2312 EVEX_CD8<32, CD8VF>;
2313 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2314 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2315 EVEX_CD8<64, CD8VF>;
2316 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2317 i512mem, memopv16i32>, EVEX_V512,
2318 EVEX_CD8<32, CD8VF>;
2319 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2320 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2321 EVEX_CD8<64, CD8VF>;
2322 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2323 i512mem, memopv16i32>, EVEX_V512,
2324 EVEX_CD8<32, CD8VF>;
2325 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2326 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2327 EVEX_CD8<64, CD8VF>;
2329 //===----------------------------------------------------------------------===//
2330 // AVX-512 - MOVDDUP
2331 //===----------------------------------------------------------------------===//
2333 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2334 X86MemOperand x86memop, PatFrag memop_frag> {
2335 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2336 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2337 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2338 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2339 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2341 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2344 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2345 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2346 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2347 (VMOVDDUPZrm addr:$src)>;
2349 //===---------------------------------------------------------------------===//
2350 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2351 //===---------------------------------------------------------------------===//
2352 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2353 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2354 X86MemOperand x86memop> {
2355 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2356 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2357 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2359 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2360 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
2361 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2364 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2365 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2366 EVEX_CD8<32, CD8VF>;
2367 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2368 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2369 EVEX_CD8<32, CD8VF>;
2371 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2372 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2373 (VMOVSHDUPZrm addr:$src)>;
2374 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2375 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2376 (VMOVSLDUPZrm addr:$src)>;
2378 //===----------------------------------------------------------------------===//
2379 // Move Low to High and High to Low packed FP Instructions
2380 //===----------------------------------------------------------------------===//
2381 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2382 (ins VR128X:$src1, VR128X:$src2),
2383 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2384 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2385 IIC_SSE_MOV_LH>, EVEX_4V;
2386 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2387 (ins VR128X:$src1, VR128X:$src2),
2388 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2389 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2390 IIC_SSE_MOV_LH>, EVEX_4V;
2392 let Predicates = [HasAVX512] in {
2394 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2395 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2396 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2397 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2400 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2401 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2404 //===----------------------------------------------------------------------===//
2405 // FMA - Fused Multiply Operations
2407 let Constraints = "$src1 = $dst" in {
2408 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2409 RegisterClass RC, X86MemOperand x86memop,
2410 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2411 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2412 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2413 (ins RC:$src1, RC:$src2, RC:$src3),
2414 !strconcat(OpcodeStr," \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2415 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2418 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2419 (ins RC:$src1, RC:$src2, x86memop:$src3),
2420 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2421 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2422 (mem_frag addr:$src3))))]>;
2423 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2424 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2425 !strconcat(OpcodeStr, " \t{${src3}", BrdcstStr,
2426 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2427 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2428 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2430 } // Constraints = "$src1 = $dst"
2432 let ExeDomain = SSEPackedSingle in {
2433 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2434 memopv16f32, f32mem, loadf32, "{1to16}",
2435 X86Fmadd, v16f32>, EVEX_V512,
2436 EVEX_CD8<32, CD8VF>;
2437 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2438 memopv16f32, f32mem, loadf32, "{1to16}",
2439 X86Fmsub, v16f32>, EVEX_V512,
2440 EVEX_CD8<32, CD8VF>;
2441 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2442 memopv16f32, f32mem, loadf32, "{1to16}",
2443 X86Fmaddsub, v16f32>,
2444 EVEX_V512, EVEX_CD8<32, CD8VF>;
2445 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2446 memopv16f32, f32mem, loadf32, "{1to16}",
2447 X86Fmsubadd, v16f32>,
2448 EVEX_V512, EVEX_CD8<32, CD8VF>;
2449 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2450 memopv16f32, f32mem, loadf32, "{1to16}",
2451 X86Fnmadd, v16f32>, EVEX_V512,
2452 EVEX_CD8<32, CD8VF>;
2453 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2454 memopv16f32, f32mem, loadf32, "{1to16}",
2455 X86Fnmsub, v16f32>, EVEX_V512,
2456 EVEX_CD8<32, CD8VF>;
2458 let ExeDomain = SSEPackedDouble in {
2459 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2460 memopv8f64, f64mem, loadf64, "{1to8}",
2461 X86Fmadd, v8f64>, EVEX_V512,
2462 VEX_W, EVEX_CD8<64, CD8VF>;
2463 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2464 memopv8f64, f64mem, loadf64, "{1to8}",
2465 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2466 EVEX_CD8<64, CD8VF>;
2467 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2468 memopv8f64, f64mem, loadf64, "{1to8}",
2469 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2470 EVEX_CD8<64, CD8VF>;
2471 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2472 memopv8f64, f64mem, loadf64, "{1to8}",
2473 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2474 EVEX_CD8<64, CD8VF>;
2475 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2476 memopv8f64, f64mem, loadf64, "{1to8}",
2477 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2478 EVEX_CD8<64, CD8VF>;
2479 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2480 memopv8f64, f64mem, loadf64, "{1to8}",
2481 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2482 EVEX_CD8<64, CD8VF>;
2485 let Constraints = "$src1 = $dst" in {
2486 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2487 RegisterClass RC, X86MemOperand x86memop,
2488 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2489 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2491 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2492 (ins RC:$src1, RC:$src3, x86memop:$src2),
2493 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2494 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2495 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2496 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2497 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2498 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2499 [(set RC:$dst, (OpNode RC:$src1,
2500 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2502 } // Constraints = "$src1 = $dst"
2505 let ExeDomain = SSEPackedSingle in {
2506 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2507 memopv16f32, f32mem, loadf32, "{1to16}",
2508 X86Fmadd, v16f32>, EVEX_V512,
2509 EVEX_CD8<32, CD8VF>;
2510 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2511 memopv16f32, f32mem, loadf32, "{1to16}",
2512 X86Fmsub, v16f32>, EVEX_V512,
2513 EVEX_CD8<32, CD8VF>;
2514 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2515 memopv16f32, f32mem, loadf32, "{1to16}",
2516 X86Fmaddsub, v16f32>,
2517 EVEX_V512, EVEX_CD8<32, CD8VF>;
2518 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2519 memopv16f32, f32mem, loadf32, "{1to16}",
2520 X86Fmsubadd, v16f32>,
2521 EVEX_V512, EVEX_CD8<32, CD8VF>;
2522 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2523 memopv16f32, f32mem, loadf32, "{1to16}",
2524 X86Fnmadd, v16f32>, EVEX_V512,
2525 EVEX_CD8<32, CD8VF>;
2526 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2527 memopv16f32, f32mem, loadf32, "{1to16}",
2528 X86Fnmsub, v16f32>, EVEX_V512,
2529 EVEX_CD8<32, CD8VF>;
2531 let ExeDomain = SSEPackedDouble in {
2532 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2533 memopv8f64, f64mem, loadf64, "{1to8}",
2534 X86Fmadd, v8f64>, EVEX_V512,
2535 VEX_W, EVEX_CD8<64, CD8VF>;
2536 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2537 memopv8f64, f64mem, loadf64, "{1to8}",
2538 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2539 EVEX_CD8<64, CD8VF>;
2540 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2541 memopv8f64, f64mem, loadf64, "{1to8}",
2542 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2543 EVEX_CD8<64, CD8VF>;
2544 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2545 memopv8f64, f64mem, loadf64, "{1to8}",
2546 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2547 EVEX_CD8<64, CD8VF>;
2548 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2549 memopv8f64, f64mem, loadf64, "{1to8}",
2550 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2551 EVEX_CD8<64, CD8VF>;
2552 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2553 memopv8f64, f64mem, loadf64, "{1to8}",
2554 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2555 EVEX_CD8<64, CD8VF>;
2559 let Constraints = "$src1 = $dst" in {
2560 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2561 RegisterClass RC, ValueType OpVT,
2562 X86MemOperand x86memop, Operand memop,
2564 let isCommutable = 1 in
2565 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2566 (ins RC:$src1, RC:$src2, RC:$src3),
2567 !strconcat(OpcodeStr,
2568 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2570 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2572 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2573 (ins RC:$src1, RC:$src2, f128mem:$src3),
2574 !strconcat(OpcodeStr,
2575 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2577 (OpVT (OpNode RC:$src2, RC:$src1,
2578 (mem_frag addr:$src3))))]>;
2581 } // Constraints = "$src1 = $dst"
2583 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2584 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2585 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2586 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2587 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2588 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2589 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2590 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2591 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2592 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2593 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2594 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2595 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2596 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2597 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2598 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2600 //===----------------------------------------------------------------------===//
2601 // AVX-512 Scalar convert from sign integer to float/double
2602 //===----------------------------------------------------------------------===//
2604 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2605 X86MemOperand x86memop, string asm> {
2606 let hasSideEffects = 0 in {
2607 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2608 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2611 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2612 (ins DstRC:$src1, x86memop:$src),
2613 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2615 } // hasSideEffects = 0
2617 let Predicates = [HasAVX512] in {
2618 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2619 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2620 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2621 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2622 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2623 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2624 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2625 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2627 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2628 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2629 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2630 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2631 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2632 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2633 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2634 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2636 def : Pat<(f32 (sint_to_fp GR32:$src)),
2637 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2638 def : Pat<(f32 (sint_to_fp GR64:$src)),
2639 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2640 def : Pat<(f64 (sint_to_fp GR32:$src)),
2641 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2642 def : Pat<(f64 (sint_to_fp GR64:$src)),
2643 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2645 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2646 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2647 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2648 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2649 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2650 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2651 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2652 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2654 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2655 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2656 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2657 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2658 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2659 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2660 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2661 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2663 def : Pat<(f32 (uint_to_fp GR32:$src)),
2664 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2665 def : Pat<(f32 (uint_to_fp GR64:$src)),
2666 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2667 def : Pat<(f64 (uint_to_fp GR32:$src)),
2668 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2669 def : Pat<(f64 (uint_to_fp GR64:$src)),
2670 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2673 //===----------------------------------------------------------------------===//
2674 // AVX-512 Scalar convert from float/double to integer
2675 //===----------------------------------------------------------------------===//
2676 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2677 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2679 let hasSideEffects = 0 in {
2680 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2681 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2682 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2683 Requires<[HasAVX512]>;
2685 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2686 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2687 Requires<[HasAVX512]>;
2688 } // hasSideEffects = 0
2690 let Predicates = [HasAVX512] in {
2691 // Convert float/double to signed/unsigned int 32/64
2692 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2693 ssmem, sse_load_f32, "cvtss2si">,
2694 XS, EVEX_CD8<32, CD8VT1>;
2695 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2696 ssmem, sse_load_f32, "cvtss2si">,
2697 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2698 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2699 ssmem, sse_load_f32, "cvtss2usi">,
2700 XS, EVEX_CD8<32, CD8VT1>;
2701 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2702 int_x86_avx512_cvtss2usi64, ssmem,
2703 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2704 EVEX_CD8<32, CD8VT1>;
2705 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2706 sdmem, sse_load_f64, "cvtsd2si">,
2707 XD, EVEX_CD8<64, CD8VT1>;
2708 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2709 sdmem, sse_load_f64, "cvtsd2si">,
2710 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2711 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2712 sdmem, sse_load_f64, "cvtsd2usi">,
2713 XD, EVEX_CD8<64, CD8VT1>;
2714 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2715 int_x86_avx512_cvtsd2usi64, sdmem,
2716 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2717 EVEX_CD8<64, CD8VT1>;
2719 let isCodeGenOnly = 1 in {
2720 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2721 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2722 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2723 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2724 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2725 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2726 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2727 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2728 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2729 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2730 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2731 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2733 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2734 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2735 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2736 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2737 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2738 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2739 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2740 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2741 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2742 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2743 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2744 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2745 } // isCodeGenOnly = 1
2747 // Convert float/double to signed/unsigned int 32/64 with truncation
2748 let isCodeGenOnly = 1 in {
2749 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2750 ssmem, sse_load_f32, "cvttss2si">,
2751 XS, EVEX_CD8<32, CD8VT1>;
2752 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2753 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2754 "cvttss2si">, XS, VEX_W,
2755 EVEX_CD8<32, CD8VT1>;
2756 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2757 sdmem, sse_load_f64, "cvttsd2si">, XD,
2758 EVEX_CD8<64, CD8VT1>;
2759 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2760 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2761 "cvttsd2si">, XD, VEX_W,
2762 EVEX_CD8<64, CD8VT1>;
2763 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2764 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2765 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2766 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2767 int_x86_avx512_cvttss2usi64, ssmem,
2768 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2769 EVEX_CD8<32, CD8VT1>;
2770 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2771 int_x86_avx512_cvttsd2usi,
2772 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2773 EVEX_CD8<64, CD8VT1>;
2774 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2775 int_x86_avx512_cvttsd2usi64, sdmem,
2776 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2777 EVEX_CD8<64, CD8VT1>;
2778 } // isCodeGenOnly = 1
2780 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2781 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2783 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2784 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2785 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2786 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2787 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2788 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2791 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2792 loadf32, "cvttss2si">, XS,
2793 EVEX_CD8<32, CD8VT1>;
2794 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2795 loadf32, "cvttss2usi">, XS,
2796 EVEX_CD8<32, CD8VT1>;
2797 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2798 loadf32, "cvttss2si">, XS, VEX_W,
2799 EVEX_CD8<32, CD8VT1>;
2800 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2801 loadf32, "cvttss2usi">, XS, VEX_W,
2802 EVEX_CD8<32, CD8VT1>;
2803 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2804 loadf64, "cvttsd2si">, XD,
2805 EVEX_CD8<64, CD8VT1>;
2806 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2807 loadf64, "cvttsd2usi">, XD,
2808 EVEX_CD8<64, CD8VT1>;
2809 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2810 loadf64, "cvttsd2si">, XD, VEX_W,
2811 EVEX_CD8<64, CD8VT1>;
2812 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2813 loadf64, "cvttsd2usi">, XD, VEX_W,
2814 EVEX_CD8<64, CD8VT1>;
2816 //===----------------------------------------------------------------------===//
2817 // AVX-512 Convert form float to double and back
2818 //===----------------------------------------------------------------------===//
2819 let hasSideEffects = 0 in {
2820 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2821 (ins FR32X:$src1, FR32X:$src2),
2822 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2823 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2825 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2826 (ins FR32X:$src1, f32mem:$src2),
2827 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2828 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2829 EVEX_CD8<32, CD8VT1>;
2831 // Convert scalar double to scalar single
2832 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2833 (ins FR64X:$src1, FR64X:$src2),
2834 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2835 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2837 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2838 (ins FR64X:$src1, f64mem:$src2),
2839 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2840 []>, EVEX_4V, VEX_LIG, VEX_W,
2841 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2844 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2845 Requires<[HasAVX512]>;
2846 def : Pat<(fextend (loadf32 addr:$src)),
2847 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2849 def : Pat<(extloadf32 addr:$src),
2850 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2851 Requires<[HasAVX512, OptForSize]>;
2853 def : Pat<(extloadf32 addr:$src),
2854 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2855 Requires<[HasAVX512, OptForSpeed]>;
2857 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2858 Requires<[HasAVX512]>;
2860 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
2861 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2862 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2864 let hasSideEffects = 0 in {
2865 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2866 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2868 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2869 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2870 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
2871 [], d>, EVEX, EVEX_B, EVEX_RC;
2873 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2874 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2876 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2877 } // hasSideEffects = 0
2880 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2881 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2882 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2884 let hasSideEffects = 0 in {
2885 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2886 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2888 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2890 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2891 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2893 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2894 } // hasSideEffects = 0
2897 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2898 memopv8f64, f512mem, v8f32, v8f64,
2899 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
2900 EVEX_CD8<64, CD8VF>;
2902 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2903 memopv4f64, f256mem, v8f64, v8f32,
2904 SSEPackedDouble>, EVEX_V512, PS,
2905 EVEX_CD8<32, CD8VH>;
2906 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2907 (VCVTPS2PDZrm addr:$src)>;
2909 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
2910 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
2911 (VCVTPD2PSZrr VR512:$src)>;
2913 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
2914 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
2915 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
2917 //===----------------------------------------------------------------------===//
2918 // AVX-512 Vector convert from sign integer to float/double
2919 //===----------------------------------------------------------------------===//
2921 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2922 memopv8i64, i512mem, v16f32, v16i32,
2923 SSEPackedSingle>, EVEX_V512, PS,
2924 EVEX_CD8<32, CD8VF>;
2926 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2927 memopv4i64, i256mem, v8f64, v8i32,
2928 SSEPackedDouble>, EVEX_V512, XS,
2929 EVEX_CD8<32, CD8VH>;
2931 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2932 memopv16f32, f512mem, v16i32, v16f32,
2933 SSEPackedSingle>, EVEX_V512, XS,
2934 EVEX_CD8<32, CD8VF>;
2936 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2937 memopv8f64, f512mem, v8i32, v8f64,
2938 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
2939 EVEX_CD8<64, CD8VF>;
2941 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2942 memopv16f32, f512mem, v16i32, v16f32,
2943 SSEPackedSingle>, EVEX_V512, PS,
2944 EVEX_CD8<32, CD8VF>;
2946 // cvttps2udq (src, 0, mask-all-ones, sae-current)
2947 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
2948 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
2949 (VCVTTPS2UDQZrr VR512:$src)>;
2951 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2952 memopv8f64, f512mem, v8i32, v8f64,
2953 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
2954 EVEX_CD8<64, CD8VF>;
2956 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
2957 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
2958 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
2959 (VCVTTPD2UDQZrr VR512:$src)>;
2961 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2962 memopv4i64, f256mem, v8f64, v8i32,
2963 SSEPackedDouble>, EVEX_V512, XS,
2964 EVEX_CD8<32, CD8VH>;
2966 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2967 memopv16i32, f512mem, v16f32, v16i32,
2968 SSEPackedSingle>, EVEX_V512, XD,
2969 EVEX_CD8<32, CD8VF>;
2971 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2972 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2973 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2976 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
2977 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
2978 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
2979 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
2980 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2981 (VCVTDQ2PDZrr VR256X:$src)>;
2982 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
2983 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
2984 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
2985 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
2986 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2987 (VCVTUDQ2PDZrr VR256X:$src)>;
2989 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
2990 RegisterClass DstRC, PatFrag mem_frag,
2991 X86MemOperand x86memop, Domain d> {
2992 let hasSideEffects = 0 in {
2993 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2994 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
2996 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
2997 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
2998 [], d>, EVEX, EVEX_B, EVEX_RC;
3000 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
3001 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
3003 } // hasSideEffects = 0
3006 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
3007 memopv16f32, f512mem, SSEPackedSingle>, PD,
3008 EVEX_V512, EVEX_CD8<32, CD8VF>;
3009 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3010 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3011 EVEX_V512, EVEX_CD8<64, CD8VF>;
3013 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3014 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3015 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3017 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3018 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3019 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3021 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3022 memopv16f32, f512mem, SSEPackedSingle>,
3023 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3024 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3025 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3026 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
3028 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3029 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3030 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3032 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3033 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3034 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
3036 let Predicates = [HasAVX512] in {
3037 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3038 (VCVTPD2PSZrm addr:$src)>;
3039 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3040 (VCVTPS2PDZrm addr:$src)>;
3043 //===----------------------------------------------------------------------===//
3044 // Half precision conversion instructions
3045 //===----------------------------------------------------------------------===//
3046 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3047 X86MemOperand x86memop> {
3048 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3049 "vcvtph2ps\t{$src, $dst|$dst, $src}",
3051 let hasSideEffects = 0, mayLoad = 1 in
3052 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3053 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3056 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3057 X86MemOperand x86memop> {
3058 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3059 (ins srcRC:$src1, i32i8imm:$src2),
3060 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3062 let hasSideEffects = 0, mayStore = 1 in
3063 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3064 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
3065 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
3068 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
3069 EVEX_CD8<32, CD8VH>;
3070 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
3071 EVEX_CD8<32, CD8VH>;
3073 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3074 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3075 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3077 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3078 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3079 (VCVTPH2PSZrr VR256X:$src)>;
3081 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3082 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3083 "ucomiss">, PS, EVEX, VEX_LIG,
3084 EVEX_CD8<32, CD8VT1>;
3085 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
3086 "ucomisd">, PD, EVEX,
3087 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3088 let Pattern = []<dag> in {
3089 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3090 "comiss">, PS, EVEX, VEX_LIG,
3091 EVEX_CD8<32, CD8VT1>;
3092 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
3093 "comisd">, PD, EVEX,
3094 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3096 let isCodeGenOnly = 1 in {
3097 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3098 load, "ucomiss">, PS, EVEX, VEX_LIG,
3099 EVEX_CD8<32, CD8VT1>;
3100 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
3101 load, "ucomisd">, PD, EVEX,
3102 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3104 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3105 load, "comiss">, PS, EVEX, VEX_LIG,
3106 EVEX_CD8<32, CD8VT1>;
3107 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
3108 load, "comisd">, PD, EVEX,
3109 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3113 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3114 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3115 X86MemOperand x86memop> {
3116 let hasSideEffects = 0 in {
3117 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3118 (ins RC:$src1, RC:$src2),
3119 !strconcat(OpcodeStr,
3120 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3121 let mayLoad = 1 in {
3122 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3123 (ins RC:$src1, x86memop:$src2),
3124 !strconcat(OpcodeStr,
3125 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3130 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3131 EVEX_CD8<32, CD8VT1>;
3132 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3133 VEX_W, EVEX_CD8<64, CD8VT1>;
3134 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3135 EVEX_CD8<32, CD8VT1>;
3136 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3137 VEX_W, EVEX_CD8<64, CD8VT1>;
3139 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3140 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3141 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3142 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3144 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3145 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3146 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3147 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3149 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3150 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3151 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3152 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3154 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3155 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3156 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3157 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3159 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3160 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3161 RegisterClass RC, X86MemOperand x86memop,
3162 PatFrag mem_frag, ValueType OpVt> {
3163 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3164 !strconcat(OpcodeStr,
3165 " \t{$src, $dst|$dst, $src}"),
3166 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3168 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3169 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3170 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3173 defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
3174 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3175 defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
3176 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3177 defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
3178 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3179 defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
3180 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3182 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
3183 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3184 (VRSQRT14PSZr VR512:$src)>;
3185 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
3186 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3187 (VRSQRT14PDZr VR512:$src)>;
3189 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
3190 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
3191 (VRCP14PSZr VR512:$src)>;
3192 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
3193 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3194 (VRCP14PDZr VR512:$src)>;
3196 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
3197 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3198 X86MemOperand x86memop> {
3199 let hasSideEffects = 0, Predicates = [HasERI] in {
3200 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3201 (ins RC:$src1, RC:$src2),
3202 !strconcat(OpcodeStr,
3203 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3204 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3205 (ins RC:$src1, RC:$src2),
3206 !strconcat(OpcodeStr,
3207 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
3208 []>, EVEX_4V, EVEX_B;
3209 let mayLoad = 1 in {
3210 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3211 (ins RC:$src1, x86memop:$src2),
3212 !strconcat(OpcodeStr,
3213 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
3218 defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
3219 EVEX_CD8<32, CD8VT1>;
3220 defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
3221 VEX_W, EVEX_CD8<64, CD8VT1>;
3222 defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
3223 EVEX_CD8<32, CD8VT1>;
3224 defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
3225 VEX_W, EVEX_CD8<64, CD8VT1>;
3227 def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
3228 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3230 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3231 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3233 def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
3234 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3236 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3237 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3239 def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
3240 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
3242 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3243 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
3245 def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
3246 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
3248 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3249 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
3251 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
3252 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
3253 RegisterClass RC, X86MemOperand x86memop> {
3254 let hasSideEffects = 0, Predicates = [HasERI] in {
3255 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3256 !strconcat(OpcodeStr,
3257 " \t{$src, $dst|$dst, $src}"),
3259 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3260 !strconcat(OpcodeStr,
3261 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
3263 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3264 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3268 defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
3269 EVEX_V512, EVEX_CD8<32, CD8VF>;
3270 defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
3271 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3272 defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
3273 EVEX_V512, EVEX_CD8<32, CD8VF>;
3274 defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
3275 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3277 def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
3278 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3279 (VRSQRT28PSZrb VR512:$src)>;
3280 def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
3281 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3282 (VRSQRT28PDZrb VR512:$src)>;
3284 def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
3285 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
3286 (VRCP28PSZrb VR512:$src)>;
3287 def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
3288 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
3289 (VRCP28PDZrb VR512:$src)>;
3291 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3292 Intrinsic V16F32Int, Intrinsic V8F64Int,
3293 OpndItins itins_s, OpndItins itins_d> {
3294 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3295 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3296 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
3300 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3301 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3303 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3304 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3306 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3307 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3308 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3312 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3313 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3314 [(set VR512:$dst, (OpNode
3315 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3316 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3318 let isCodeGenOnly = 1 in {
3319 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3320 !strconcat(OpcodeStr,
3321 "ps\t{$src, $dst|$dst, $src}"),
3322 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3324 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3325 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3327 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3328 EVEX_V512, EVEX_CD8<32, CD8VF>;
3329 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3330 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3331 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3332 EVEX, EVEX_V512, VEX_W;
3333 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3334 !strconcat(OpcodeStr,
3335 "pd\t{$src, $dst|$dst, $src}"),
3336 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3337 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3338 } // isCodeGenOnly = 1
3341 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3342 Intrinsic F32Int, Intrinsic F64Int,
3343 OpndItins itins_s, OpndItins itins_d> {
3344 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3345 (ins FR32X:$src1, FR32X:$src2),
3346 !strconcat(OpcodeStr,
3347 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3348 [], itins_s.rr>, XS, EVEX_4V;
3349 let isCodeGenOnly = 1 in
3350 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3351 (ins VR128X:$src1, VR128X:$src2),
3352 !strconcat(OpcodeStr,
3353 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3355 (F32Int VR128X:$src1, VR128X:$src2))],
3356 itins_s.rr>, XS, EVEX_4V;
3357 let mayLoad = 1 in {
3358 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3359 (ins FR32X:$src1, f32mem:$src2),
3360 !strconcat(OpcodeStr,
3361 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3362 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3363 let isCodeGenOnly = 1 in
3364 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3365 (ins VR128X:$src1, ssmem:$src2),
3366 !strconcat(OpcodeStr,
3367 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3369 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3370 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3372 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3373 (ins FR64X:$src1, FR64X:$src2),
3374 !strconcat(OpcodeStr,
3375 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3377 let isCodeGenOnly = 1 in
3378 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3379 (ins VR128X:$src1, VR128X:$src2),
3380 !strconcat(OpcodeStr,
3381 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3383 (F64Int VR128X:$src1, VR128X:$src2))],
3384 itins_s.rr>, XD, EVEX_4V, VEX_W;
3385 let mayLoad = 1 in {
3386 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3387 (ins FR64X:$src1, f64mem:$src2),
3388 !strconcat(OpcodeStr,
3389 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3390 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3391 let isCodeGenOnly = 1 in
3392 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3393 (ins VR128X:$src1, sdmem:$src2),
3394 !strconcat(OpcodeStr,
3395 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3397 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3398 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3403 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3404 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3405 SSE_SQRTSS, SSE_SQRTSD>,
3406 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3407 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3408 SSE_SQRTPS, SSE_SQRTPD>;
3410 let Predicates = [HasAVX512] in {
3411 def : Pat<(f32 (fsqrt FR32X:$src)),
3412 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3413 def : Pat<(f32 (fsqrt (load addr:$src))),
3414 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3415 Requires<[OptForSize]>;
3416 def : Pat<(f64 (fsqrt FR64X:$src)),
3417 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3418 def : Pat<(f64 (fsqrt (load addr:$src))),
3419 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3420 Requires<[OptForSize]>;
3422 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3423 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3424 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3425 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3426 Requires<[OptForSize]>;
3428 def : Pat<(f32 (X86frcp FR32X:$src)),
3429 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3430 def : Pat<(f32 (X86frcp (load addr:$src))),
3431 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3432 Requires<[OptForSize]>;
3434 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3435 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3436 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3438 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3439 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3441 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3442 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3443 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3445 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3446 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3450 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3451 X86MemOperand x86memop, RegisterClass RC,
3452 PatFrag mem_frag32, PatFrag mem_frag64,
3453 Intrinsic V4F32Int, Intrinsic V2F64Int,
3455 let ExeDomain = SSEPackedSingle in {
3456 // Intrinsic operation, reg.
3457 // Vector intrinsic operation, reg
3458 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3459 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3460 !strconcat(OpcodeStr,
3461 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3462 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3464 // Vector intrinsic operation, mem
3465 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3466 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3467 !strconcat(OpcodeStr,
3468 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3470 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3471 EVEX_CD8<32, VForm>;
3472 } // ExeDomain = SSEPackedSingle
3474 let ExeDomain = SSEPackedDouble in {
3475 // Vector intrinsic operation, reg
3476 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3477 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3478 !strconcat(OpcodeStr,
3479 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3480 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3482 // Vector intrinsic operation, mem
3483 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3484 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3485 !strconcat(OpcodeStr,
3486 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3488 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3489 EVEX_CD8<64, VForm>;
3490 } // ExeDomain = SSEPackedDouble
3493 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3497 let ExeDomain = GenericDomain in {
3499 let hasSideEffects = 0 in
3500 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3501 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3502 !strconcat(OpcodeStr,
3503 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3506 // Intrinsic operation, reg.
3507 let isCodeGenOnly = 1 in
3508 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3509 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3510 !strconcat(OpcodeStr,
3511 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3512 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3514 // Intrinsic operation, mem.
3515 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3516 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3517 !strconcat(OpcodeStr,
3518 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3519 [(set VR128X:$dst, (F32Int VR128X:$src1,
3520 sse_load_f32:$src2, imm:$src3))]>,
3521 EVEX_CD8<32, CD8VT1>;
3524 let hasSideEffects = 0 in
3525 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3526 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3527 !strconcat(OpcodeStr,
3528 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3531 // Intrinsic operation, reg.
3532 let isCodeGenOnly = 1 in
3533 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3534 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3535 !strconcat(OpcodeStr,
3536 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3537 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3540 // Intrinsic operation, mem.
3541 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3542 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3543 !strconcat(OpcodeStr,
3544 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3546 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3547 VEX_W, EVEX_CD8<64, CD8VT1>;
3548 } // ExeDomain = GenericDomain
3551 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
3552 X86MemOperand x86memop, RegisterClass RC,
3553 PatFrag mem_frag, Domain d> {
3554 let ExeDomain = d in {
3555 // Intrinsic operation, reg.
3556 // Vector intrinsic operation, reg
3557 def r : AVX512AIi8<opc, MRMSrcReg,
3558 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3559 !strconcat(OpcodeStr,
3560 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3563 // Vector intrinsic operation, mem
3564 def m : AVX512AIi8<opc, MRMSrcMem,
3565 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3566 !strconcat(OpcodeStr,
3567 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3573 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
3574 memopv16f32, SSEPackedSingle>, EVEX_V512,
3575 EVEX_CD8<32, CD8VF>;
3577 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
3578 imm:$src2, (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1),
3580 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
3583 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
3584 memopv8f64, SSEPackedDouble>, EVEX_V512,
3585 VEX_W, EVEX_CD8<64, CD8VF>;
3587 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
3588 imm:$src2, (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1),
3590 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
3592 multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
3593 Operand x86memop, RegisterClass RC, Domain d> {
3594 let ExeDomain = d in {
3595 def r : AVX512AIi8<opc, MRMSrcReg,
3596 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
3597 !strconcat(OpcodeStr,
3598 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3601 def m : AVX512AIi8<opc, MRMSrcMem,
3602 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
3603 !strconcat(OpcodeStr,
3604 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3609 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
3610 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
3612 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
3613 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
3615 def : Pat<(ffloor FR32X:$src),
3616 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3617 def : Pat<(f64 (ffloor FR64X:$src)),
3618 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3619 def : Pat<(f32 (fnearbyint FR32X:$src)),
3620 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3621 def : Pat<(f64 (fnearbyint FR64X:$src)),
3622 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3623 def : Pat<(f32 (fceil FR32X:$src)),
3624 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3625 def : Pat<(f64 (fceil FR64X:$src)),
3626 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3627 def : Pat<(f32 (frint FR32X:$src)),
3628 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3629 def : Pat<(f64 (frint FR64X:$src)),
3630 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3631 def : Pat<(f32 (ftrunc FR32X:$src)),
3632 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3633 def : Pat<(f64 (ftrunc FR64X:$src)),
3634 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3636 def : Pat<(v16f32 (ffloor VR512:$src)),
3637 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
3638 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3639 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
3640 def : Pat<(v16f32 (fceil VR512:$src)),
3641 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
3642 def : Pat<(v16f32 (frint VR512:$src)),
3643 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
3644 def : Pat<(v16f32 (ftrunc VR512:$src)),
3645 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
3647 def : Pat<(v8f64 (ffloor VR512:$src)),
3648 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
3649 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3650 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
3651 def : Pat<(v8f64 (fceil VR512:$src)),
3652 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
3653 def : Pat<(v8f64 (frint VR512:$src)),
3654 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
3655 def : Pat<(v8f64 (ftrunc VR512:$src)),
3656 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
3658 //-------------------------------------------------
3659 // Integer truncate and extend operations
3660 //-------------------------------------------------
3662 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3663 RegisterClass dstRC, RegisterClass srcRC,
3664 RegisterClass KRC, X86MemOperand x86memop> {
3665 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3667 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3670 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3671 (ins KRC:$mask, srcRC:$src),
3672 !strconcat(OpcodeStr,
3673 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3676 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3677 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3680 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3681 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3682 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3683 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3684 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3685 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3686 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3687 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3688 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3689 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3690 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3691 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3692 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3693 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3694 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3695 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3696 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3697 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3698 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3699 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3700 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3701 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3702 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3703 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3704 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3705 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3706 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3707 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3708 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3709 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3711 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3712 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3713 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3714 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3715 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3717 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3718 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3719 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3720 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3721 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3722 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3723 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3724 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3727 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3728 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3729 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3731 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3733 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
3734 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3735 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3736 (ins x86memop:$src),
3737 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
3739 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3743 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3744 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3746 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3747 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3749 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3750 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3751 EVEX_CD8<16, CD8VH>;
3752 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3753 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3754 EVEX_CD8<16, CD8VQ>;
3755 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3756 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3757 EVEX_CD8<32, CD8VH>;
3759 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3760 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3762 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3763 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3765 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3766 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3767 EVEX_CD8<16, CD8VH>;
3768 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3769 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3770 EVEX_CD8<16, CD8VQ>;
3771 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3772 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3773 EVEX_CD8<32, CD8VH>;
3775 //===----------------------------------------------------------------------===//
3776 // GATHER - SCATTER Operations
3778 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3779 RegisterClass RC, X86MemOperand memop> {
3781 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3782 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3783 (ins RC:$src1, KRC:$mask, memop:$src2),
3784 !strconcat(OpcodeStr,
3785 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3788 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3789 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3790 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3791 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3793 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3794 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3795 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3796 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3798 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3799 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3800 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3801 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3803 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3804 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3805 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3806 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3808 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3809 RegisterClass RC, X86MemOperand memop> {
3810 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3811 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3812 (ins memop:$dst, KRC:$mask, RC:$src2),
3813 !strconcat(OpcodeStr,
3814 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3818 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3819 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3820 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3821 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3823 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3824 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3825 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3826 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3828 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3829 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3830 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3831 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3833 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3834 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3835 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3836 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3838 //===----------------------------------------------------------------------===//
3839 // VSHUFPS - VSHUFPD Operations
3841 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3842 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3844 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3845 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3846 !strconcat(OpcodeStr,
3847 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3848 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3849 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3850 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3851 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3852 (ins RC:$src1, RC:$src2, i8imm:$src3),
3853 !strconcat(OpcodeStr,
3854 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3855 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3856 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3857 EVEX_4V, Sched<[WriteShuffle]>;
3860 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3861 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3862 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3863 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3865 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3866 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3867 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3868 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3869 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3871 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3872 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3873 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3874 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3875 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3877 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3878 X86MemOperand x86memop> {
3879 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3880 (ins RC:$src1, RC:$src2, i8imm:$src3),
3881 !strconcat(OpcodeStr,
3882 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3885 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3886 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3887 !strconcat(OpcodeStr,
3888 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3891 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3892 EVEX_V512, EVEX_CD8<32, CD8VF>;
3893 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3894 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3896 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3897 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3898 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3899 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3900 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3901 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3902 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3903 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3905 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3906 X86MemOperand x86memop> {
3907 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3908 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>,
3910 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3911 (ins x86memop:$src),
3912 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>,
3916 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3917 EVEX_CD8<32, CD8VF>;
3918 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3919 EVEX_CD8<64, CD8VF>;
3921 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
3922 (v16i32 immAllZerosV), (i16 -1))),
3923 (VPABSDrr VR512:$src)>;
3924 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
3925 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
3926 (VPABSQrr VR512:$src)>;
3928 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3929 RegisterClass RC, RegisterClass KRC,
3930 X86MemOperand x86memop,
3931 X86MemOperand x86scalar_mop, string BrdcstStr> {
3932 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3934 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
3936 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3937 (ins x86memop:$src),
3938 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
3940 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3941 (ins x86scalar_mop:$src),
3942 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
3943 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3945 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3946 (ins KRC:$mask, RC:$src),
3947 !strconcat(OpcodeStr,
3948 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3950 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3951 (ins KRC:$mask, x86memop:$src),
3952 !strconcat(OpcodeStr,
3953 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3955 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3956 (ins KRC:$mask, x86scalar_mop:$src),
3957 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
3958 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3960 []>, EVEX, EVEX_KZ, EVEX_B;
3962 let Constraints = "$src1 = $dst" in {
3963 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3964 (ins RC:$src1, KRC:$mask, RC:$src2),
3965 !strconcat(OpcodeStr,
3966 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3968 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3969 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3970 !strconcat(OpcodeStr,
3971 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3973 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3974 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3975 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
3976 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
3977 []>, EVEX, EVEX_K, EVEX_B;
3981 let Predicates = [HasCDI] in {
3982 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
3983 i512mem, i32mem, "{1to16}">,
3984 EVEX_V512, EVEX_CD8<32, CD8VF>;
3987 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
3988 i512mem, i64mem, "{1to8}">,
3989 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3993 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
3995 (VPCONFLICTDrrk VR512:$src1,
3996 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
3998 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4000 (VPCONFLICTQrrk VR512:$src1,
4001 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;