1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
98 //===----------------------------------------------------------------------===//
99 // AVX-512 - VECTOR INSERT
102 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
108 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
114 // -- 64x4 fp form --
115 let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
121 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
126 // -- 32x4 integer form --
127 let neverHasSideEffects = 1 in {
128 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
133 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
140 let neverHasSideEffects = 1 in {
142 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
147 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
153 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
166 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
180 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
193 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
207 // vinsertps - insert f32 to XMM
208 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
213 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
220 //===----------------------------------------------------------------------===//
221 // AVX-512 VECTOR EXTRACT
223 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
225 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
235 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
240 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
246 let neverHasSideEffects = 1 in {
248 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
258 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
263 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
269 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
273 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
277 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
281 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
286 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
290 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
294 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
298 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
302 // A 256-bit subvector extract from the first 512-bit vector position
303 // is a subregister copy that needs no instruction.
304 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
314 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
324 // A 128-bit subvector insert to the first 512-bit vector position
325 // is a subregister copy that needs no instruction.
326 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
330 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
334 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
338 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
343 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
352 // vextractps - extract 32 bits from XMM
353 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
359 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
365 //===---------------------------------------------------------------------===//
368 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
377 let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
383 let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
389 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
394 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
395 (VBROADCASTSSZrm addr:$src)>;
396 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
397 (VBROADCASTSDZrm addr:$src)>;
399 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
400 RegisterClass SrcRC, RegisterClass KRC> {
401 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
402 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
403 []>, EVEX, EVEX_V512;
404 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
405 (ins KRC:$mask, SrcRC:$src),
406 !strconcat(OpcodeStr,
407 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
408 []>, EVEX, EVEX_V512, EVEX_KZ;
411 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
412 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
415 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
416 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
418 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
419 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
421 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
422 (VPBROADCASTDrZrr GR32:$src)>;
423 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
424 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
425 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
426 (VPBROADCASTQrZrr GR64:$src)>;
427 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
428 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
430 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
431 (VPBROADCASTDrZrr GR32:$src)>;
432 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
433 (VPBROADCASTQrZrr GR64:$src)>;
435 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
436 X86MemOperand x86memop, PatFrag ld_frag,
437 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
439 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
440 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
442 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
443 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
445 !strconcat(OpcodeStr,
446 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
448 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
451 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
452 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
454 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
455 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
457 !strconcat(OpcodeStr,
458 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
459 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
460 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
464 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
465 loadi32, VR512, v16i32, v4i32, VK16WM>,
466 EVEX_V512, EVEX_CD8<32, CD8VT1>;
467 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
468 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
469 EVEX_CD8<64, CD8VT1>;
471 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
472 (VPBROADCASTDZrr VR128X:$src)>;
473 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
474 (VPBROADCASTQZrr VR128X:$src)>;
476 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
477 (VBROADCASTSSZrr VR128X:$src)>;
478 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
479 (VBROADCASTSDZrr VR128X:$src)>;
481 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
482 (VBROADCASTSSZrr VR128X:$src)>;
483 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
484 (VBROADCASTSDZrr VR128X:$src)>;
486 // Provide fallback in case the load node that is used in the patterns above
487 // is used by additional users, which prevents the pattern selection.
488 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
489 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
490 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
491 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
494 let Predicates = [HasAVX512] in {
495 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
497 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
498 addr:$src)), sub_ymm)>;
500 //===----------------------------------------------------------------------===//
501 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
504 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
505 RegisterClass DstRC, RegisterClass KRC,
506 ValueType OpVT, ValueType SrcVT> {
507 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
508 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
512 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
513 VK16, v16i32, v16i1>, EVEX_V512;
514 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
515 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
517 //===----------------------------------------------------------------------===//
520 // -- immediate form --
521 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
522 SDNode OpNode, PatFrag mem_frag,
523 X86MemOperand x86memop, ValueType OpVT> {
524 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
525 (ins RC:$src1, i8imm:$src2),
526 !strconcat(OpcodeStr,
527 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
529 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
531 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
532 (ins x86memop:$src1, i8imm:$src2),
533 !strconcat(OpcodeStr,
534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
536 (OpVT (OpNode (mem_frag addr:$src1),
537 (i8 imm:$src2))))]>, EVEX;
540 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
541 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
542 let ExeDomain = SSEPackedDouble in
543 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
544 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
546 // -- VPERM - register form --
547 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
548 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
550 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
551 (ins RC:$src1, RC:$src2),
552 !strconcat(OpcodeStr,
553 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
555 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
557 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
558 (ins RC:$src1, x86memop:$src2),
559 !strconcat(OpcodeStr,
560 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
562 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
566 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
567 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
568 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
569 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
570 let ExeDomain = SSEPackedSingle in
571 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
572 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
573 let ExeDomain = SSEPackedDouble in
574 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
575 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
577 // -- VPERM2I - 3 source operands form --
578 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
579 PatFrag mem_frag, X86MemOperand x86memop,
581 let Constraints = "$src1 = $dst" in {
582 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
583 (ins RC:$src1, RC:$src2, RC:$src3),
584 !strconcat(OpcodeStr,
585 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
587 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
590 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
591 (ins RC:$src1, RC:$src2, x86memop:$src3),
592 !strconcat(OpcodeStr,
593 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
595 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
596 (mem_frag addr:$src3))))]>, EVEX_4V;
599 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
600 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
601 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
602 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
603 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
604 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
605 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
606 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
608 //===----------------------------------------------------------------------===//
609 // AVX-512 - BLEND using mask
611 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, Intrinsic Int,
612 RegisterClass KRC, RegisterClass RC,
613 X86MemOperand x86memop, PatFrag mem_frag,
614 SDNode OpNode, ValueType vt> {
615 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
616 (ins KRC:$mask, RC:$src1, RC:$src2),
617 !strconcat(OpcodeStr,
618 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
619 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
620 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
621 def rr_Int : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
622 (ins KRC:$mask, RC:$src1, RC:$src2),
623 !strconcat(OpcodeStr,
624 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
625 [(set RC:$dst, (Int KRC:$mask, (vt RC:$src2),
626 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
629 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
630 (ins KRC:$mask, RC:$src1, x86memop:$src2),
631 !strconcat(OpcodeStr,
632 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
636 def rm_Int : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
637 (ins KRC:$mask, RC:$src1, x86memop:$src2),
638 !strconcat(OpcodeStr,
639 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
640 [(set RC:$dst, (Int KRC:$mask, (vt RC:$src1),
641 (mem_frag addr:$src2)))]>,
646 let ExeDomain = SSEPackedSingle in
647 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
648 int_x86_avx512_mask_blend_ps_512,
649 VK16WM, VR512, f512mem,
650 memopv16f32, vselect, v16f32>,
651 EVEX_CD8<32, CD8VF>, EVEX_V512;
652 let ExeDomain = SSEPackedDouble in
653 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
654 int_x86_avx512_mask_blend_pd_512,
655 VK8WM, VR512, f512mem,
656 memopv8f64, vselect, v8f64>,
657 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
659 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
660 int_x86_avx512_mask_blend_d_512,
661 VK16WM, VR512, f512mem,
662 memopv16i32, vselect, v16i32>,
663 EVEX_CD8<32, CD8VF>, EVEX_V512;
665 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
666 int_x86_avx512_mask_blend_q_512,
667 VK8WM, VR512, f512mem,
668 memopv8i64, vselect, v8i64>,
669 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
671 let Predicates = [HasAVX512] in {
672 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
673 (v8f32 VR256X:$src2))),
675 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
676 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
677 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
679 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
680 (v8i32 VR256X:$src2))),
682 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
683 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
684 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
686 //===----------------------------------------------------------------------===//
687 // Compare Instructions
688 //===----------------------------------------------------------------------===//
690 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
691 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
692 Operand CC, SDNode OpNode, ValueType VT,
693 PatFrag ld_frag, string asm, string asm_alt> {
694 def rr : AVX512Ii8<0xC2, MRMSrcReg,
695 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
696 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
697 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
698 def rm : AVX512Ii8<0xC2, MRMSrcMem,
699 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
700 [(set VK1:$dst, (OpNode (VT RC:$src1),
701 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
702 let neverHasSideEffects = 1 in {
703 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
704 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
705 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
706 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
707 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
708 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
712 let Predicates = [HasAVX512] in {
713 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
714 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
715 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
717 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
718 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
719 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
723 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
724 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
725 SDNode OpNode, ValueType vt> {
726 def rr : AVX512BI<opc, MRMSrcReg,
727 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
728 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
729 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
730 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
731 def rm : AVX512BI<opc, MRMSrcMem,
732 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
733 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
734 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
735 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
738 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
739 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
740 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
741 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
743 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
744 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
745 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
746 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
748 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
749 (COPY_TO_REGCLASS (VPCMPGTDZrr
750 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
751 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
753 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
754 (COPY_TO_REGCLASS (VPCMPEQDZrr
755 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
756 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
758 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
759 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
760 SDNode OpNode, ValueType vt, Operand CC, string asm,
762 def rri : AVX512AIi8<opc, MRMSrcReg,
763 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
764 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
765 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
766 def rmi : AVX512AIi8<opc, MRMSrcMem,
767 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
768 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
769 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
770 // Accept explicit immediate argument form instead of comparison code.
771 let neverHasSideEffects = 1 in {
772 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
773 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
774 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
775 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
776 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
777 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
781 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
782 X86cmpm, v16i32, AVXCC,
783 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
784 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
785 EVEX_V512, EVEX_CD8<32, CD8VF>;
786 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
787 X86cmpmu, v16i32, AVXCC,
788 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
789 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
790 EVEX_V512, EVEX_CD8<32, CD8VF>;
792 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
793 X86cmpm, v8i64, AVXCC,
794 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
795 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
796 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
797 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
798 X86cmpmu, v8i64, AVXCC,
799 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
800 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
801 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
803 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
804 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
805 X86MemOperand x86memop, Operand CC,
806 SDNode OpNode, ValueType vt, string asm,
807 string asm_alt, Domain d> {
808 def rri : AVX512PIi8<0xC2, MRMSrcReg,
809 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
810 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
811 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
812 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
814 (OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
816 // Accept explicit immediate argument form instead of comparison code.
817 let neverHasSideEffects = 1 in {
818 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
819 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
821 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
822 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
827 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
828 "vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
829 "vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
830 SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
831 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
832 "vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
833 "vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
834 SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
837 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
838 (COPY_TO_REGCLASS (VCMPPSZrri
839 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
840 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
842 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
843 (COPY_TO_REGCLASS (VPCMPDZrri
844 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
845 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
847 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
848 (COPY_TO_REGCLASS (VPCMPUDZrri
849 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
850 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
853 // Mask register copy, including
854 // - copy between mask registers
855 // - load/store mask registers
856 // - copy from GPR to mask register and vice versa
858 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
859 string OpcodeStr, RegisterClass KRC,
860 ValueType vt, X86MemOperand x86memop> {
861 let neverHasSideEffects = 1 in {
862 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
863 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
865 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
866 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
867 [(set KRC:$dst, (vt (load addr:$src)))]>;
869 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
870 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
874 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
876 RegisterClass KRC, RegisterClass GRC> {
877 let neverHasSideEffects = 1 in {
878 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
879 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
880 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
881 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
885 let Predicates = [HasAVX512] in {
886 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
888 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
892 let Predicates = [HasAVX512] in {
893 // GR16 from/to 16-bit mask
894 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
895 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
896 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
897 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
899 // Store kreg in memory
900 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
901 (KMOVWmk addr:$dst, VK16:$src)>;
903 def : Pat<(store VK8:$src, addr:$dst),
904 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
906 def : Pat<(i1 (load addr:$src)),
907 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
909 def : Pat<(v8i1 (load addr:$src)),
910 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
912 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
913 let Predicates = [HasAVX512] in {
914 // GR from/to 8-bit mask without native support
915 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
917 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
919 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
921 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
924 def : Pat<(i1 (extractelt VK16:$src, (iPTR 0))),
925 (COPY_TO_REGCLASS VK16:$src, VK1)>;
926 def : Pat<(i1 (extractelt VK8:$src, (iPTR 0))),
927 (COPY_TO_REGCLASS VK8:$src, VK1)>;
931 // Mask unary operation
933 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
934 RegisterClass KRC, SDPatternOperator OpNode> {
935 let Predicates = [HasAVX512] in
936 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
937 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
938 [(set KRC:$dst, (OpNode KRC:$src))]>;
941 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
942 SDPatternOperator OpNode> {
943 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
947 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
949 multiclass avx512_mask_unop_int<string IntName, string InstName> {
950 let Predicates = [HasAVX512] in
951 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
953 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
954 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
956 defm : avx512_mask_unop_int<"knot", "KNOT">;
958 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
959 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
960 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
962 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
963 def : Pat<(not VK8:$src),
965 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
967 // Mask binary operation
968 // - KAND, KANDN, KOR, KXNOR, KXOR
969 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
970 RegisterClass KRC, SDPatternOperator OpNode> {
971 let Predicates = [HasAVX512] in
972 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
973 !strconcat(OpcodeStr,
974 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
975 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
978 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
979 SDPatternOperator OpNode> {
980 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
984 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
985 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
987 let isCommutable = 1 in {
988 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
989 let isCommutable = 0 in
990 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
991 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
992 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
993 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
996 def : Pat<(xor VK1:$src1, VK1:$src2),
997 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
998 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1000 def : Pat<(or VK1:$src1, VK1:$src2),
1001 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1002 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1004 def : Pat<(not VK1:$src),
1005 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src, VK16),
1006 (COPY_TO_REGCLASS (VCMPSSZrr (f32 (IMPLICIT_DEF)),
1007 (f32 (IMPLICIT_DEF)), (i8 0)), VK16)), VK1)>;
1009 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1010 let Predicates = [HasAVX512] in
1011 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1012 (i16 GR16:$src1), (i16 GR16:$src2)),
1013 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1014 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1015 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1018 defm : avx512_mask_binop_int<"kand", "KAND">;
1019 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1020 defm : avx512_mask_binop_int<"kor", "KOR">;
1021 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1022 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1024 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1025 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1026 let Predicates = [HasAVX512] in
1027 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1029 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1030 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1033 defm : avx512_binop_pat<and, KANDWrr>;
1034 defm : avx512_binop_pat<andn, KANDNWrr>;
1035 defm : avx512_binop_pat<or, KORWrr>;
1036 defm : avx512_binop_pat<xnor, KXNORWrr>;
1037 defm : avx512_binop_pat<xor, KXORWrr>;
1040 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1041 RegisterClass KRC> {
1042 let Predicates = [HasAVX512] in
1043 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1044 !strconcat(OpcodeStr,
1045 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1048 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1049 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1050 VEX_4V, VEX_L, OpSize, TB;
1053 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1055 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1056 let Predicates = [HasAVX512] in
1057 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1058 (i16 GR16:$src1), (i16 GR16:$src2)),
1059 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1060 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1061 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1063 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1066 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1068 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1069 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1070 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1071 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1074 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1075 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1079 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1081 def : Pat<(X86cmp VK1:$src1, VK1:$src2),
1082 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1083 (COPY_TO_REGCLASS VK1:$src2, VK16))>;
1086 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1088 let Predicates = [HasAVX512] in
1089 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1090 !strconcat(OpcodeStr,
1091 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1092 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1095 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1097 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1098 VEX, OpSize, TA, VEX_W;
1101 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1102 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1104 // Mask setting all 0s or 1s
1105 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1106 let Predicates = [HasAVX512] in
1107 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1108 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1109 [(set KRC:$dst, (VT Val))]>;
1112 multiclass avx512_mask_setop_w<PatFrag Val> {
1113 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1114 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1117 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1118 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1120 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1121 let Predicates = [HasAVX512] in {
1122 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1123 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1125 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1126 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1128 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1129 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1131 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1132 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1134 //===----------------------------------------------------------------------===//
1135 // AVX-512 - Aligned and unaligned load and store
1138 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1139 X86MemOperand x86memop, PatFrag ld_frag,
1140 string asm, Domain d> {
1141 let neverHasSideEffects = 1 in
1142 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1143 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1145 let canFoldAsLoad = 1 in
1146 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1147 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1148 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1149 let Constraints = "$src1 = $dst" in {
1150 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1151 (ins RC:$src1, KRC:$mask, RC:$src2),
1153 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1155 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1156 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1158 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1159 [], d>, EVEX, EVEX_K;
1163 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1164 "vmovaps", SSEPackedSingle>,
1165 EVEX_V512, EVEX_CD8<32, CD8VF>;
1166 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1167 "vmovapd", SSEPackedDouble>,
1168 OpSize, EVEX_V512, VEX_W,
1169 EVEX_CD8<64, CD8VF>;
1170 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1171 "vmovups", SSEPackedSingle>,
1172 EVEX_V512, EVEX_CD8<32, CD8VF>;
1173 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1174 "vmovupd", SSEPackedDouble>,
1175 OpSize, EVEX_V512, VEX_W,
1176 EVEX_CD8<64, CD8VF>;
1177 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1178 "vmovaps\t{$src, $dst|$dst, $src}",
1179 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1180 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1181 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1182 "vmovapd\t{$src, $dst|$dst, $src}",
1183 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1184 SSEPackedDouble>, EVEX, EVEX_V512,
1185 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1186 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1187 "vmovups\t{$src, $dst|$dst, $src}",
1188 [(store (v16f32 VR512:$src), addr:$dst)],
1189 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1190 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1191 "vmovupd\t{$src, $dst|$dst, $src}",
1192 [(store (v8f64 VR512:$src), addr:$dst)],
1193 SSEPackedDouble>, EVEX, EVEX_V512,
1194 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1196 let neverHasSideEffects = 1 in {
1197 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1199 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1201 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1203 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1204 EVEX, EVEX_V512, VEX_W;
1205 let mayStore = 1 in {
1206 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1207 (ins i512mem:$dst, VR512:$src),
1208 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1209 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1210 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1211 (ins i512mem:$dst, VR512:$src),
1212 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1213 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1215 let mayLoad = 1 in {
1216 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1218 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1219 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1220 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1222 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1223 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1227 // 512-bit aligned load/store
1228 def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1229 def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1231 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1232 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1233 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1234 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1236 multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1237 RegisterClass RC, RegisterClass KRC,
1238 PatFrag ld_frag, X86MemOperand x86memop> {
1239 let neverHasSideEffects = 1 in
1240 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1241 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1242 let canFoldAsLoad = 1 in
1243 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1244 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1245 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1247 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1248 (ins x86memop:$dst, VR512:$src),
1249 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1250 let Constraints = "$src1 = $dst" in {
1251 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1252 (ins RC:$src1, KRC:$mask, RC:$src2),
1254 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1256 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
1257 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1259 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1264 defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1265 memopv16i32, i512mem>,
1266 EVEX_V512, EVEX_CD8<32, CD8VF>;
1267 defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1268 memopv8i64, i512mem>,
1269 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1271 // 512-bit unaligned load/store
1272 def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1273 def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1275 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1276 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1277 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1278 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1280 let AddedComplexity = 20 in {
1281 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1282 (v16f32 VR512:$src2))),
1283 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1284 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1285 (v8f64 VR512:$src2))),
1286 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1287 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1288 (v16i32 VR512:$src2))),
1289 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1290 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1291 (v8i64 VR512:$src2))),
1292 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1294 // Move Int Doubleword to Packed Double Int
1296 def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1297 "vmovd\t{$src, $dst|$dst, $src}",
1299 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1301 def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1302 "vmovd\t{$src, $dst|$dst, $src}",
1304 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1305 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1306 def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1307 "vmovq\t{$src, $dst|$dst, $src}",
1309 (v2i64 (scalar_to_vector GR64:$src)))],
1310 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1311 let isCodeGenOnly = 1 in {
1312 def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1313 "vmovq\t{$src, $dst|$dst, $src}",
1314 [(set FR64:$dst, (bitconvert GR64:$src))],
1315 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1316 def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1317 "vmovq\t{$src, $dst|$dst, $src}",
1318 [(set GR64:$dst, (bitconvert FR64:$src))],
1319 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1321 def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1322 "vmovq\t{$src, $dst|$dst, $src}",
1323 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1324 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1325 EVEX_CD8<64, CD8VT1>;
1327 // Move Int Doubleword to Single Scalar
1329 let isCodeGenOnly = 1 in {
1330 def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1331 "vmovd\t{$src, $dst|$dst, $src}",
1332 [(set FR32X:$dst, (bitconvert GR32:$src))],
1333 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1335 def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1336 "vmovd\t{$src, $dst|$dst, $src}",
1337 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1338 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1341 // Move Packed Doubleword Int to Packed Double Int
1343 def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1344 "vmovd\t{$src, $dst|$dst, $src}",
1345 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1346 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1348 def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1349 (ins i32mem:$dst, VR128X:$src),
1350 "vmovd\t{$src, $dst|$dst, $src}",
1351 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1352 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1353 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1355 // Move Packed Doubleword Int first element to Doubleword Int
1357 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1358 "vmovq\t{$src, $dst|$dst, $src}",
1359 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1361 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1362 Requires<[HasAVX512, In64BitMode]>;
1364 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1365 (ins i64mem:$dst, VR128X:$src),
1366 "vmovq\t{$src, $dst|$dst, $src}",
1367 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1368 addr:$dst)], IIC_SSE_MOVDQ>,
1369 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
1370 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1372 // Move Scalar Single to Double Int
1374 let isCodeGenOnly = 1 in {
1375 def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1377 "vmovd\t{$src, $dst|$dst, $src}",
1378 [(set GR32:$dst, (bitconvert FR32X:$src))],
1379 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1380 def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1381 (ins i32mem:$dst, FR32X:$src),
1382 "vmovd\t{$src, $dst|$dst, $src}",
1383 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1384 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1387 // Move Quadword Int to Packed Quadword Int
1389 def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1391 "vmovq\t{$src, $dst|$dst, $src}",
1393 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1394 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1396 //===----------------------------------------------------------------------===//
1397 // AVX-512 MOVSS, MOVSD
1398 //===----------------------------------------------------------------------===//
1400 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1401 SDNode OpNode, ValueType vt,
1402 X86MemOperand x86memop, PatFrag mem_pat> {
1403 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1404 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1405 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1406 (scalar_to_vector RC:$src2))))],
1407 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1408 let Constraints = "$src1 = $dst" in
1409 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1410 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1412 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1413 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1414 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1415 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1416 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1418 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1419 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1420 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1424 let ExeDomain = SSEPackedSingle in
1425 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1426 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1428 let ExeDomain = SSEPackedDouble in
1429 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1430 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1432 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1433 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1434 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1436 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1437 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1438 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1440 // For the disassembler
1441 let isCodeGenOnly = 1 in {
1442 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1443 (ins VR128X:$src1, FR32X:$src2),
1444 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1446 XS, EVEX_4V, VEX_LIG;
1447 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1448 (ins VR128X:$src1, FR64X:$src2),
1449 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1451 XD, EVEX_4V, VEX_LIG, VEX_W;
1454 let Predicates = [HasAVX512] in {
1455 let AddedComplexity = 15 in {
1456 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1457 // MOVS{S,D} to the lower bits.
1458 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1459 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1460 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1461 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1462 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1463 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1464 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1465 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1467 // Move low f32 and clear high bits.
1468 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1469 (SUBREG_TO_REG (i32 0),
1470 (VMOVSSZrr (v4f32 (V_SET0)),
1471 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1472 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1473 (SUBREG_TO_REG (i32 0),
1474 (VMOVSSZrr (v4i32 (V_SET0)),
1475 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1478 let AddedComplexity = 20 in {
1479 // MOVSSrm zeros the high parts of the register; represent this
1480 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1481 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1482 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1483 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1484 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1485 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1486 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1488 // MOVSDrm zeros the high parts of the register; represent this
1489 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1490 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1491 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1492 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1493 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1494 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1495 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1496 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1497 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1498 def : Pat<(v2f64 (X86vzload addr:$src)),
1499 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1501 // Represent the same patterns above but in the form they appear for
1503 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1504 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1505 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1506 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1507 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1508 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1509 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1510 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1511 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1513 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1514 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1515 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1516 FR32X:$src)), sub_xmm)>;
1517 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1518 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1519 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1520 FR64X:$src)), sub_xmm)>;
1521 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1522 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1523 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1525 // Move low f64 and clear high bits.
1526 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1527 (SUBREG_TO_REG (i32 0),
1528 (VMOVSDZrr (v2f64 (V_SET0)),
1529 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1531 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1532 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1533 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1535 // Extract and store.
1536 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1538 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1539 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1541 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1543 // Shuffle with VMOVSS
1544 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1545 (VMOVSSZrr (v4i32 VR128X:$src1),
1546 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1547 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1548 (VMOVSSZrr (v4f32 VR128X:$src1),
1549 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1552 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1553 (SUBREG_TO_REG (i32 0),
1554 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1555 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1557 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1558 (SUBREG_TO_REG (i32 0),
1559 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1560 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1563 // Shuffle with VMOVSD
1564 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1565 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1566 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1567 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1568 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1569 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1570 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1571 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1574 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1575 (SUBREG_TO_REG (i32 0),
1576 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1577 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1579 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1580 (SUBREG_TO_REG (i32 0),
1581 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1582 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1585 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1586 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1587 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1588 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1589 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1590 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1591 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1592 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1595 let AddedComplexity = 15 in
1596 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1598 "vmovq\t{$src, $dst|$dst, $src}",
1599 [(set VR128X:$dst, (v2i64 (X86vzmovl
1600 (v2i64 VR128X:$src))))],
1601 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1603 let AddedComplexity = 20 in
1604 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1606 "vmovq\t{$src, $dst|$dst, $src}",
1607 [(set VR128X:$dst, (v2i64 (X86vzmovl
1608 (loadv2i64 addr:$src))))],
1609 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1610 EVEX_CD8<8, CD8VT8>;
1612 let Predicates = [HasAVX512] in {
1613 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1614 let AddedComplexity = 20 in {
1615 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1616 (VMOVDI2PDIZrm addr:$src)>;
1617 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1618 (VMOV64toPQIZrr GR64:$src)>;
1619 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1620 (VMOVDI2PDIZrr GR32:$src)>;
1622 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1623 (VMOVDI2PDIZrm addr:$src)>;
1624 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1625 (VMOVDI2PDIZrm addr:$src)>;
1626 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1627 (VMOVZPQILo2PQIZrm addr:$src)>;
1628 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1629 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1630 def : Pat<(v2i64 (X86vzload addr:$src)),
1631 (VMOVZPQILo2PQIZrm addr:$src)>;
1634 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1635 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1636 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1637 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1638 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1639 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1640 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1643 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1644 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1646 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1647 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1649 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1650 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1652 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1653 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1655 //===----------------------------------------------------------------------===//
1656 // AVX-512 - Integer arithmetic
1658 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1659 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1660 X86MemOperand x86memop, PatFrag scalar_mfrag,
1661 X86MemOperand x86scalar_mop, string BrdcstStr,
1662 OpndItins itins, bit IsCommutable = 0> {
1663 let isCommutable = IsCommutable in
1664 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1665 (ins RC:$src1, RC:$src2),
1666 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1667 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1669 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1670 (ins RC:$src1, x86memop:$src2),
1671 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1672 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1674 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1675 (ins RC:$src1, x86scalar_mop:$src2),
1676 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1677 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1678 [(set RC:$dst, (OpNode RC:$src1,
1679 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1680 itins.rm>, EVEX_4V, EVEX_B;
1682 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1683 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1684 PatFrag memop_frag, X86MemOperand x86memop,
1686 bit IsCommutable = 0> {
1687 let isCommutable = IsCommutable in
1688 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1689 (ins RC:$src1, RC:$src2),
1690 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1691 []>, EVEX_4V, VEX_W;
1692 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1693 (ins RC:$src1, x86memop:$src2),
1694 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1695 []>, EVEX_4V, VEX_W;
1698 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1699 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1700 EVEX_V512, EVEX_CD8<32, CD8VF>;
1702 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1703 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1704 EVEX_V512, EVEX_CD8<32, CD8VF>;
1706 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1707 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1708 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1710 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1711 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1712 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1714 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1715 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1716 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1718 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1719 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1720 EVEX_V512, EVEX_CD8<64, CD8VF>;
1722 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1723 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1724 EVEX_CD8<64, CD8VF>;
1726 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1727 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1729 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1730 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1731 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1732 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1733 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1734 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1736 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1737 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1738 EVEX_V512, EVEX_CD8<32, CD8VF>;
1739 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1740 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1741 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1743 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1744 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1745 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1746 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1747 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1748 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1750 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1751 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1752 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1753 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1754 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1755 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1757 //===----------------------------------------------------------------------===//
1758 // AVX-512 - Unpack Instructions
1759 //===----------------------------------------------------------------------===//
1761 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1762 PatFrag mem_frag, RegisterClass RC,
1763 X86MemOperand x86memop, string asm,
1765 def rr : AVX512PI<opc, MRMSrcReg,
1766 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1768 (vt (OpNode RC:$src1, RC:$src2)))],
1770 def rm : AVX512PI<opc, MRMSrcMem,
1771 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1773 (vt (OpNode RC:$src1,
1774 (bitconvert (mem_frag addr:$src2)))))],
1778 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1779 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1780 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1781 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1782 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1783 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1784 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1785 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1786 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1787 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1788 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1789 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1791 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1792 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1793 X86MemOperand x86memop> {
1794 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1795 (ins RC:$src1, RC:$src2),
1796 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1797 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1798 IIC_SSE_UNPCK>, EVEX_4V;
1799 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1800 (ins RC:$src1, x86memop:$src2),
1801 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1802 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1803 (bitconvert (memop_frag addr:$src2)))))],
1804 IIC_SSE_UNPCK>, EVEX_4V;
1806 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1807 VR512, memopv16i32, i512mem>, EVEX_V512,
1808 EVEX_CD8<32, CD8VF>;
1809 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1810 VR512, memopv8i64, i512mem>, EVEX_V512,
1811 VEX_W, EVEX_CD8<64, CD8VF>;
1812 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1813 VR512, memopv16i32, i512mem>, EVEX_V512,
1814 EVEX_CD8<32, CD8VF>;
1815 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1816 VR512, memopv8i64, i512mem>, EVEX_V512,
1817 VEX_W, EVEX_CD8<64, CD8VF>;
1818 //===----------------------------------------------------------------------===//
1822 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1823 SDNode OpNode, PatFrag mem_frag,
1824 X86MemOperand x86memop, ValueType OpVT> {
1825 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1826 (ins RC:$src1, i8imm:$src2),
1827 !strconcat(OpcodeStr,
1828 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1830 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1832 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1833 (ins x86memop:$src1, i8imm:$src2),
1834 !strconcat(OpcodeStr,
1835 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1837 (OpVT (OpNode (mem_frag addr:$src1),
1838 (i8 imm:$src2))))]>, EVEX;
1841 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1842 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1844 let ExeDomain = SSEPackedSingle in
1845 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1846 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1847 EVEX_CD8<32, CD8VF>;
1848 let ExeDomain = SSEPackedDouble in
1849 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1850 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1851 VEX_W, EVEX_CD8<32, CD8VF>;
1853 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1854 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1855 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1856 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1858 //===----------------------------------------------------------------------===//
1859 // AVX-512 Logical Instructions
1860 //===----------------------------------------------------------------------===//
1862 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1863 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1864 EVEX_V512, EVEX_CD8<32, CD8VF>;
1865 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1866 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1867 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1868 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1869 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1870 EVEX_V512, EVEX_CD8<32, CD8VF>;
1871 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1872 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1873 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1874 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1875 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1876 EVEX_V512, EVEX_CD8<32, CD8VF>;
1877 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1878 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1879 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1880 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1881 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1882 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1883 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1884 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1885 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1887 //===----------------------------------------------------------------------===//
1888 // AVX-512 FP arithmetic
1889 //===----------------------------------------------------------------------===//
1891 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1893 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
1894 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1895 EVEX_CD8<32, CD8VT1>;
1896 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
1897 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1898 EVEX_CD8<64, CD8VT1>;
1901 let isCommutable = 1 in {
1902 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1903 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1904 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1905 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1907 let isCommutable = 0 in {
1908 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1909 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1912 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1913 RegisterClass RC, ValueType vt,
1914 X86MemOperand x86memop, PatFrag mem_frag,
1915 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1917 Domain d, OpndItins itins, bit commutable> {
1918 let isCommutable = commutable in
1919 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1920 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1921 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
1923 let mayLoad = 1 in {
1924 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1925 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1926 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
1927 itins.rm, d>, EVEX_4V, TB;
1928 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1929 (ins RC:$src1, x86scalar_mop:$src2),
1930 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1931 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1932 [(set RC:$dst, (OpNode RC:$src1,
1933 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1934 itins.rm, d>, EVEX_4V, EVEX_B, TB;
1938 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1939 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1940 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1942 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1943 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1944 SSE_ALU_ITINS_P.d, 1>,
1945 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1947 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
1948 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1949 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1950 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
1951 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1952 SSE_ALU_ITINS_P.d, 1>,
1953 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1955 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
1956 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1957 SSE_ALU_ITINS_P.s, 1>,
1958 EVEX_V512, EVEX_CD8<32, CD8VF>;
1959 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
1960 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1961 SSE_ALU_ITINS_P.s, 1>,
1962 EVEX_V512, EVEX_CD8<32, CD8VF>;
1964 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
1965 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1966 SSE_ALU_ITINS_P.d, 1>,
1967 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1968 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
1969 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1970 SSE_ALU_ITINS_P.d, 1>,
1971 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1973 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
1974 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1975 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1976 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
1977 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1978 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1980 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
1981 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1982 SSE_ALU_ITINS_P.d, 0>,
1983 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1984 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
1985 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1986 SSE_ALU_ITINS_P.d, 0>,
1987 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1989 //===----------------------------------------------------------------------===//
1990 // AVX-512 VPTESTM instructions
1991 //===----------------------------------------------------------------------===//
1993 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1994 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
1995 SDNode OpNode, ValueType vt> {
1996 def rr : AVX5128I<opc, MRMSrcReg,
1997 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
1998 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1999 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
2000 def rm : AVX5128I<opc, MRMSrcMem,
2001 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2002 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2003 [(set KRC:$dst, (OpNode (vt RC:$src1),
2004 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
2007 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2008 memopv16i32, X86testm, v16i32>, EVEX_V512,
2009 EVEX_CD8<32, CD8VF>;
2010 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2011 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
2012 EVEX_CD8<64, CD8VF>;
2014 //===----------------------------------------------------------------------===//
2015 // AVX-512 Shift instructions
2016 //===----------------------------------------------------------------------===//
2017 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2018 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2019 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2020 RegisterClass KRC> {
2021 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2022 (ins RC:$src1, i8imm:$src2),
2023 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2024 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2025 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2026 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2027 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2028 !strconcat(OpcodeStr,
2029 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2030 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2031 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2032 (ins x86memop:$src1, i8imm:$src2),
2033 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2034 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2035 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2036 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2037 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2038 !strconcat(OpcodeStr,
2039 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2040 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2043 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2044 RegisterClass RC, ValueType vt, ValueType SrcVT,
2045 PatFrag bc_frag, RegisterClass KRC> {
2046 // src2 is always 128-bit
2047 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2048 (ins RC:$src1, VR128X:$src2),
2049 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2050 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2051 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2052 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2053 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2054 !strconcat(OpcodeStr,
2055 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2056 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2057 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2058 (ins RC:$src1, i128mem:$src2),
2059 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2060 [(set RC:$dst, (vt (OpNode RC:$src1,
2061 (bc_frag (memopv2i64 addr:$src2)))))],
2062 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2063 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2064 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2065 !strconcat(OpcodeStr,
2066 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2067 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2070 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2071 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2072 EVEX_V512, EVEX_CD8<32, CD8VF>;
2073 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2074 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2075 EVEX_CD8<32, CD8VQ>;
2077 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2078 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2079 EVEX_CD8<64, CD8VF>, VEX_W;
2080 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2081 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2082 EVEX_CD8<64, CD8VQ>, VEX_W;
2084 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2085 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2086 EVEX_CD8<32, CD8VF>;
2087 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2088 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2089 EVEX_CD8<32, CD8VQ>;
2091 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2092 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2093 EVEX_CD8<64, CD8VF>, VEX_W;
2094 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2095 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2096 EVEX_CD8<64, CD8VQ>, VEX_W;
2098 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2099 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2100 EVEX_V512, EVEX_CD8<32, CD8VF>;
2101 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2102 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2103 EVEX_CD8<32, CD8VQ>;
2105 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2106 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2107 EVEX_CD8<64, CD8VF>, VEX_W;
2108 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2109 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2110 EVEX_CD8<64, CD8VQ>, VEX_W;
2112 //===-------------------------------------------------------------------===//
2113 // Variable Bit Shifts
2114 //===-------------------------------------------------------------------===//
2115 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2116 RegisterClass RC, ValueType vt,
2117 X86MemOperand x86memop, PatFrag mem_frag> {
2118 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2119 (ins RC:$src1, RC:$src2),
2120 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2122 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2124 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2125 (ins RC:$src1, x86memop:$src2),
2126 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2128 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2132 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2133 i512mem, memopv16i32>, EVEX_V512,
2134 EVEX_CD8<32, CD8VF>;
2135 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2136 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2137 EVEX_CD8<64, CD8VF>;
2138 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2139 i512mem, memopv16i32>, EVEX_V512,
2140 EVEX_CD8<32, CD8VF>;
2141 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2142 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2143 EVEX_CD8<64, CD8VF>;
2144 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2145 i512mem, memopv16i32>, EVEX_V512,
2146 EVEX_CD8<32, CD8VF>;
2147 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2148 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2149 EVEX_CD8<64, CD8VF>;
2151 //===----------------------------------------------------------------------===//
2152 // AVX-512 - MOVDDUP
2153 //===----------------------------------------------------------------------===//
2155 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2156 X86MemOperand x86memop, PatFrag memop_frag> {
2157 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2158 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2159 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2160 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2161 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2163 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2166 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2167 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2168 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2169 (VMOVDDUPZrm addr:$src)>;
2171 //===---------------------------------------------------------------------===//
2172 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2173 //===---------------------------------------------------------------------===//
2174 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2175 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2176 X86MemOperand x86memop> {
2177 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2178 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2179 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2181 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2182 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2183 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2186 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2187 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2188 EVEX_CD8<32, CD8VF>;
2189 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2190 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2191 EVEX_CD8<32, CD8VF>;
2193 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2194 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2195 (VMOVSHDUPZrm addr:$src)>;
2196 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2197 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2198 (VMOVSLDUPZrm addr:$src)>;
2200 //===----------------------------------------------------------------------===//
2201 // Move Low to High and High to Low packed FP Instructions
2202 //===----------------------------------------------------------------------===//
2203 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2204 (ins VR128X:$src1, VR128X:$src2),
2205 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2206 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2207 IIC_SSE_MOV_LH>, EVEX_4V;
2208 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2209 (ins VR128X:$src1, VR128X:$src2),
2210 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2211 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2212 IIC_SSE_MOV_LH>, EVEX_4V;
2214 let Predicates = [HasAVX512] in {
2216 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2217 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2218 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2219 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2222 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2223 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2226 //===----------------------------------------------------------------------===//
2227 // FMA - Fused Multiply Operations
2229 let Constraints = "$src1 = $dst" in {
2230 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2231 RegisterClass RC, X86MemOperand x86memop,
2232 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2233 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2234 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2235 (ins RC:$src1, RC:$src2, RC:$src3),
2236 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2237 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2240 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2241 (ins RC:$src1, RC:$src2, x86memop:$src3),
2242 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2243 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2244 (mem_frag addr:$src3))))]>;
2245 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2246 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2247 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2248 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2249 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2250 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2252 } // Constraints = "$src1 = $dst"
2254 let ExeDomain = SSEPackedSingle in {
2255 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2256 memopv16f32, f32mem, loadf32, "{1to16}",
2257 X86Fmadd, v16f32>, EVEX_V512,
2258 EVEX_CD8<32, CD8VF>;
2259 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2260 memopv16f32, f32mem, loadf32, "{1to16}",
2261 X86Fmsub, v16f32>, EVEX_V512,
2262 EVEX_CD8<32, CD8VF>;
2263 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2264 memopv16f32, f32mem, loadf32, "{1to16}",
2265 X86Fmaddsub, v16f32>,
2266 EVEX_V512, EVEX_CD8<32, CD8VF>;
2267 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2268 memopv16f32, f32mem, loadf32, "{1to16}",
2269 X86Fmsubadd, v16f32>,
2270 EVEX_V512, EVEX_CD8<32, CD8VF>;
2271 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2272 memopv16f32, f32mem, loadf32, "{1to16}",
2273 X86Fnmadd, v16f32>, EVEX_V512,
2274 EVEX_CD8<32, CD8VF>;
2275 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2276 memopv16f32, f32mem, loadf32, "{1to16}",
2277 X86Fnmsub, v16f32>, EVEX_V512,
2278 EVEX_CD8<32, CD8VF>;
2280 let ExeDomain = SSEPackedDouble in {
2281 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2282 memopv8f64, f64mem, loadf64, "{1to8}",
2283 X86Fmadd, v8f64>, EVEX_V512,
2284 VEX_W, EVEX_CD8<64, CD8VF>;
2285 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2286 memopv8f64, f64mem, loadf64, "{1to8}",
2287 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2288 EVEX_CD8<64, CD8VF>;
2289 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2290 memopv8f64, f64mem, loadf64, "{1to8}",
2291 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2292 EVEX_CD8<64, CD8VF>;
2293 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2294 memopv8f64, f64mem, loadf64, "{1to8}",
2295 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2296 EVEX_CD8<64, CD8VF>;
2297 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2298 memopv8f64, f64mem, loadf64, "{1to8}",
2299 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2300 EVEX_CD8<64, CD8VF>;
2301 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2302 memopv8f64, f64mem, loadf64, "{1to8}",
2303 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2304 EVEX_CD8<64, CD8VF>;
2307 let Constraints = "$src1 = $dst" in {
2308 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2309 RegisterClass RC, X86MemOperand x86memop,
2310 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2311 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2313 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2314 (ins RC:$src1, RC:$src3, x86memop:$src2),
2315 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2316 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2317 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2318 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2319 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2320 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2321 [(set RC:$dst, (OpNode RC:$src1,
2322 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2324 } // Constraints = "$src1 = $dst"
2327 let ExeDomain = SSEPackedSingle in {
2328 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2329 memopv16f32, f32mem, loadf32, "{1to16}",
2330 X86Fmadd, v16f32>, EVEX_V512,
2331 EVEX_CD8<32, CD8VF>;
2332 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2333 memopv16f32, f32mem, loadf32, "{1to16}",
2334 X86Fmsub, v16f32>, EVEX_V512,
2335 EVEX_CD8<32, CD8VF>;
2336 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2337 memopv16f32, f32mem, loadf32, "{1to16}",
2338 X86Fmaddsub, v16f32>,
2339 EVEX_V512, EVEX_CD8<32, CD8VF>;
2340 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2341 memopv16f32, f32mem, loadf32, "{1to16}",
2342 X86Fmsubadd, v16f32>,
2343 EVEX_V512, EVEX_CD8<32, CD8VF>;
2344 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2345 memopv16f32, f32mem, loadf32, "{1to16}",
2346 X86Fnmadd, v16f32>, EVEX_V512,
2347 EVEX_CD8<32, CD8VF>;
2348 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2349 memopv16f32, f32mem, loadf32, "{1to16}",
2350 X86Fnmsub, v16f32>, EVEX_V512,
2351 EVEX_CD8<32, CD8VF>;
2353 let ExeDomain = SSEPackedDouble in {
2354 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2355 memopv8f64, f64mem, loadf64, "{1to8}",
2356 X86Fmadd, v8f64>, EVEX_V512,
2357 VEX_W, EVEX_CD8<64, CD8VF>;
2358 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2359 memopv8f64, f64mem, loadf64, "{1to8}",
2360 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2361 EVEX_CD8<64, CD8VF>;
2362 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2363 memopv8f64, f64mem, loadf64, "{1to8}",
2364 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2365 EVEX_CD8<64, CD8VF>;
2366 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2367 memopv8f64, f64mem, loadf64, "{1to8}",
2368 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2369 EVEX_CD8<64, CD8VF>;
2370 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2371 memopv8f64, f64mem, loadf64, "{1to8}",
2372 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2373 EVEX_CD8<64, CD8VF>;
2374 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2375 memopv8f64, f64mem, loadf64, "{1to8}",
2376 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2377 EVEX_CD8<64, CD8VF>;
2381 let Constraints = "$src1 = $dst" in {
2382 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2383 RegisterClass RC, ValueType OpVT,
2384 X86MemOperand x86memop, Operand memop,
2386 let isCommutable = 1 in
2387 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2388 (ins RC:$src1, RC:$src2, RC:$src3),
2389 !strconcat(OpcodeStr,
2390 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2392 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2394 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2395 (ins RC:$src1, RC:$src2, f128mem:$src3),
2396 !strconcat(OpcodeStr,
2397 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2399 (OpVT (OpNode RC:$src2, RC:$src1,
2400 (mem_frag addr:$src3))))]>;
2403 } // Constraints = "$src1 = $dst"
2405 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2406 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2407 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2408 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2409 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2410 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2411 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2412 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2413 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2414 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2415 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2416 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2417 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2418 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2419 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2420 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2422 //===----------------------------------------------------------------------===//
2423 // AVX-512 Scalar convert from sign integer to float/double
2424 //===----------------------------------------------------------------------===//
2426 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2427 X86MemOperand x86memop, string asm> {
2428 let neverHasSideEffects = 1 in {
2429 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2430 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2433 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2434 (ins DstRC:$src1, x86memop:$src),
2435 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2437 } // neverHasSideEffects = 1
2439 let Predicates = [HasAVX512] in {
2440 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2441 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2442 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2443 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2444 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2445 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2446 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2447 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2449 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2450 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2451 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2452 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2453 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2454 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2455 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2456 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2458 def : Pat<(f32 (sint_to_fp GR32:$src)),
2459 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2460 def : Pat<(f32 (sint_to_fp GR64:$src)),
2461 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2462 def : Pat<(f64 (sint_to_fp GR32:$src)),
2463 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2464 def : Pat<(f64 (sint_to_fp GR64:$src)),
2465 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2467 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2468 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2469 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2470 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2471 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2472 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2473 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2474 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2476 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2477 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2478 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2479 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2480 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2481 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2482 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2483 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2485 def : Pat<(f32 (uint_to_fp GR32:$src)),
2486 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2487 def : Pat<(f32 (uint_to_fp GR64:$src)),
2488 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2489 def : Pat<(f64 (uint_to_fp GR32:$src)),
2490 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2491 def : Pat<(f64 (uint_to_fp GR64:$src)),
2492 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2495 //===----------------------------------------------------------------------===//
2496 // AVX-512 Scalar convert from float/double to integer
2497 //===----------------------------------------------------------------------===//
2498 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2499 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2501 let neverHasSideEffects = 1 in {
2502 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2503 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2504 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2505 Requires<[HasAVX512]>;
2507 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2508 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2509 Requires<[HasAVX512]>;
2510 } // neverHasSideEffects = 1
2512 let Predicates = [HasAVX512] in {
2513 // Convert float/double to signed/unsigned int 32/64
2514 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2515 ssmem, sse_load_f32, "cvtss2si">,
2516 XS, EVEX_CD8<32, CD8VT1>;
2517 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2518 ssmem, sse_load_f32, "cvtss2si">,
2519 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2520 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2521 ssmem, sse_load_f32, "cvtss2usi">,
2522 XS, EVEX_CD8<32, CD8VT1>;
2523 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2524 int_x86_avx512_cvtss2usi64, ssmem,
2525 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2526 EVEX_CD8<32, CD8VT1>;
2527 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2528 sdmem, sse_load_f64, "cvtsd2si">,
2529 XD, EVEX_CD8<64, CD8VT1>;
2530 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2531 sdmem, sse_load_f64, "cvtsd2si">,
2532 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2533 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2534 sdmem, sse_load_f64, "cvtsd2usi">,
2535 XD, EVEX_CD8<64, CD8VT1>;
2536 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2537 int_x86_avx512_cvtsd2usi64, sdmem,
2538 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2539 EVEX_CD8<64, CD8VT1>;
2541 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2542 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2543 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2544 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2545 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2546 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2547 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2548 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2549 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2550 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2551 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2552 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2554 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2555 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2556 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2557 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2558 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2559 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2560 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2561 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2562 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2563 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2564 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2565 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2567 // Convert float/double to signed/unsigned int 32/64 with truncation
2568 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2569 ssmem, sse_load_f32, "cvttss2si">,
2570 XS, EVEX_CD8<32, CD8VT1>;
2571 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2572 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2573 "cvttss2si">, XS, VEX_W,
2574 EVEX_CD8<32, CD8VT1>;
2575 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2576 sdmem, sse_load_f64, "cvttsd2si">, XD,
2577 EVEX_CD8<64, CD8VT1>;
2578 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2579 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2580 "cvttsd2si">, XD, VEX_W,
2581 EVEX_CD8<64, CD8VT1>;
2582 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2583 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2584 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2585 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2586 int_x86_avx512_cvttss2usi64, ssmem,
2587 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2588 EVEX_CD8<32, CD8VT1>;
2589 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2590 int_x86_avx512_cvttsd2usi,
2591 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2592 EVEX_CD8<64, CD8VT1>;
2593 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2594 int_x86_avx512_cvttsd2usi64, sdmem,
2595 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2596 EVEX_CD8<64, CD8VT1>;
2598 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2599 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2601 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2602 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2603 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2604 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2605 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2606 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2609 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2610 loadf32, "cvttss2si">, XS,
2611 EVEX_CD8<32, CD8VT1>;
2612 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2613 loadf32, "cvttss2usi">, XS,
2614 EVEX_CD8<32, CD8VT1>;
2615 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2616 loadf32, "cvttss2si">, XS, VEX_W,
2617 EVEX_CD8<32, CD8VT1>;
2618 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2619 loadf32, "cvttss2usi">, XS, VEX_W,
2620 EVEX_CD8<32, CD8VT1>;
2621 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2622 loadf64, "cvttsd2si">, XD,
2623 EVEX_CD8<64, CD8VT1>;
2624 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2625 loadf64, "cvttsd2usi">, XD,
2626 EVEX_CD8<64, CD8VT1>;
2627 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2628 loadf64, "cvttsd2si">, XD, VEX_W,
2629 EVEX_CD8<64, CD8VT1>;
2630 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2631 loadf64, "cvttsd2usi">, XD, VEX_W,
2632 EVEX_CD8<64, CD8VT1>;
2634 //===----------------------------------------------------------------------===//
2635 // AVX-512 Convert form float to double and back
2636 //===----------------------------------------------------------------------===//
2637 let neverHasSideEffects = 1 in {
2638 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2639 (ins FR32X:$src1, FR32X:$src2),
2640 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2641 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2643 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2644 (ins FR32X:$src1, f32mem:$src2),
2645 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2646 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2647 EVEX_CD8<32, CD8VT1>;
2649 // Convert scalar double to scalar single
2650 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2651 (ins FR64X:$src1, FR64X:$src2),
2652 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2653 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2655 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2656 (ins FR64X:$src1, f64mem:$src2),
2657 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2658 []>, EVEX_4V, VEX_LIG, VEX_W,
2659 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2662 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2663 Requires<[HasAVX512]>;
2664 def : Pat<(fextend (loadf32 addr:$src)),
2665 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2667 def : Pat<(extloadf32 addr:$src),
2668 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2669 Requires<[HasAVX512, OptForSize]>;
2671 def : Pat<(extloadf32 addr:$src),
2672 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2673 Requires<[HasAVX512, OptForSpeed]>;
2675 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2676 Requires<[HasAVX512]>;
2678 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2679 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2680 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2682 let neverHasSideEffects = 1 in {
2683 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2684 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2686 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2688 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2689 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2691 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2692 } // neverHasSideEffects = 1
2695 defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2696 memopv8f64, f512mem, v8f32, v8f64,
2697 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2698 EVEX_CD8<64, CD8VF>;
2700 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2701 memopv4f64, f256mem, v8f64, v8f32,
2702 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2703 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2704 (VCVTPS2PDZrm addr:$src)>;
2706 //===----------------------------------------------------------------------===//
2707 // AVX-512 Vector convert from sign integer to float/double
2708 //===----------------------------------------------------------------------===//
2710 defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2711 memopv8i64, i512mem, v16f32, v16i32,
2712 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2714 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2715 memopv4i64, i256mem, v8f64, v8i32,
2716 SSEPackedDouble>, EVEX_V512, XS,
2717 EVEX_CD8<32, CD8VH>;
2719 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2720 memopv16f32, f512mem, v16i32, v16f32,
2721 SSEPackedSingle>, EVEX_V512, XS,
2722 EVEX_CD8<32, CD8VF>;
2724 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2725 memopv8f64, f512mem, v8i32, v8f64,
2726 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2727 EVEX_CD8<64, CD8VF>;
2729 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2730 memopv16f32, f512mem, v16i32, v16f32,
2731 SSEPackedSingle>, EVEX_V512,
2732 EVEX_CD8<32, CD8VF>;
2734 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2735 memopv8f64, f512mem, v8i32, v8f64,
2736 SSEPackedDouble>, EVEX_V512, VEX_W,
2737 EVEX_CD8<64, CD8VF>;
2739 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2740 memopv4i64, f256mem, v8f64, v8i32,
2741 SSEPackedDouble>, EVEX_V512, XS,
2742 EVEX_CD8<32, CD8VH>;
2744 defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2745 memopv16i32, f512mem, v16f32, v16i32,
2746 SSEPackedSingle>, EVEX_V512, XD,
2747 EVEX_CD8<32, CD8VF>;
2749 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2750 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2751 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2754 def : Pat<(int_x86_avx512_cvtdq2_ps_512 VR512:$src),
2755 (VCVTDQ2PSZrr VR512:$src)>;
2756 def : Pat<(int_x86_avx512_cvtdq2_ps_512 (bitconvert (memopv8i64 addr:$src))),
2757 (VCVTDQ2PSZrm addr:$src)>;
2759 def VCVTPS2DQZrr : AVX512BI<0x5B, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2760 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2762 (int_x86_avx512_cvt_ps2dq_512 VR512:$src))],
2763 IIC_SSE_CVT_PS_RR>, EVEX, EVEX_V512;
2764 def VCVTPS2DQZrm : AVX512BI<0x5B, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2765 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2767 (int_x86_avx512_cvt_ps2dq_512 (memopv16f32 addr:$src)))],
2768 IIC_SSE_CVT_PS_RM>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2771 let Predicates = [HasAVX512] in {
2772 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2773 (VCVTPD2PSZrm addr:$src)>;
2774 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2775 (VCVTPS2PDZrm addr:$src)>;
2778 //===----------------------------------------------------------------------===//
2779 // Half precision conversion instructions
2780 //===----------------------------------------------------------------------===//
2781 multiclass avx512_f16c_ph2ps<RegisterClass destRC, RegisterClass srcRC,
2782 X86MemOperand x86memop, Intrinsic Int> {
2783 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
2784 "vcvtph2ps\t{$src, $dst|$dst, $src}",
2785 [(set destRC:$dst, (Int srcRC:$src))]>, EVEX;
2786 let neverHasSideEffects = 1, mayLoad = 1 in
2787 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
2788 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
2791 multiclass avx512_f16c_ps2ph<RegisterClass destRC, RegisterClass srcRC,
2792 X86MemOperand x86memop, Intrinsic Int> {
2793 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
2794 (ins srcRC:$src1, i32i8imm:$src2),
2795 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2796 [(set destRC:$dst, (Int srcRC:$src1, imm:$src2))]>, EVEX;
2797 let neverHasSideEffects = 1, mayStore = 1 in
2798 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
2799 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
2800 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
2803 defm VCVTPH2PSZ : avx512_f16c_ph2ps<VR512, VR256X, f256mem,
2804 int_x86_avx512_vcvtph2ps_512>, EVEX_V512,
2805 EVEX_CD8<32, CD8VH>;
2806 defm VCVTPS2PHZ : avx512_f16c_ps2ph<VR256X, VR512, f256mem,
2807 int_x86_avx512_vcvtps2ph_512>, EVEX_V512,
2808 EVEX_CD8<32, CD8VH>;
2810 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2811 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2812 "ucomiss">, TB, EVEX, VEX_LIG,
2813 EVEX_CD8<32, CD8VT1>;
2814 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
2815 "ucomisd">, TB, OpSize, EVEX,
2816 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2817 let Pattern = []<dag> in {
2818 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
2819 "comiss">, TB, EVEX, VEX_LIG,
2820 EVEX_CD8<32, CD8VT1>;
2821 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
2822 "comisd">, TB, OpSize, EVEX,
2823 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2825 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
2826 load, "ucomiss">, TB, EVEX, VEX_LIG,
2827 EVEX_CD8<32, CD8VT1>;
2828 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
2829 load, "ucomisd">, TB, OpSize, EVEX,
2830 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2832 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
2833 load, "comiss">, TB, EVEX, VEX_LIG,
2834 EVEX_CD8<32, CD8VT1>;
2835 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
2836 load, "comisd">, TB, OpSize, EVEX,
2837 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2840 /// avx512_unop_p - AVX-512 unops in packed form.
2841 multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2842 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2843 !strconcat(OpcodeStr,
2844 "ps\t{$src, $dst|$dst, $src}"),
2845 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
2847 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
2848 !strconcat(OpcodeStr,
2849 "ps\t{$src, $dst|$dst, $src}"),
2850 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2851 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2852 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2853 !strconcat(OpcodeStr,
2854 "pd\t{$src, $dst|$dst, $src}"),
2855 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
2856 EVEX, EVEX_V512, VEX_W;
2857 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2858 !strconcat(OpcodeStr,
2859 "pd\t{$src, $dst|$dst, $src}"),
2860 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2861 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2864 /// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
2865 multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2866 Intrinsic V16F32Int, Intrinsic V8F64Int> {
2867 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2868 !strconcat(OpcodeStr,
2869 "ps\t{$src, $dst|$dst, $src}"),
2870 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2872 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2873 !strconcat(OpcodeStr,
2874 "ps\t{$src, $dst|$dst, $src}"),
2876 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2877 EVEX_V512, EVEX_CD8<32, CD8VF>;
2878 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2879 !strconcat(OpcodeStr,
2880 "pd\t{$src, $dst|$dst, $src}"),
2881 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2882 EVEX, EVEX_V512, VEX_W;
2883 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2884 !strconcat(OpcodeStr,
2885 "pd\t{$src, $dst|$dst, $src}"),
2887 (V8F64Int (memopv8f64 addr:$src)))]>,
2888 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2891 /// avx512_fp_unop_s - AVX-512 unops in scalar form.
2892 multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr> {
2893 let hasSideEffects = 0 in {
2894 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
2895 (ins FR32X:$src1, FR32X:$src2),
2896 !strconcat(OpcodeStr,
2897 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2899 let mayLoad = 1 in {
2900 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
2901 (ins FR32X:$src1, f32mem:$src2),
2902 !strconcat(OpcodeStr,
2903 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2904 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2905 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2906 (ins VR128X:$src1, ssmem:$src2),
2907 !strconcat(OpcodeStr,
2908 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2909 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2911 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
2912 (ins FR64X:$src1, FR64X:$src2),
2913 !strconcat(OpcodeStr,
2914 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2916 let mayLoad = 1 in {
2917 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
2918 (ins FR64X:$src1, f64mem:$src2),
2919 !strconcat(OpcodeStr,
2920 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2921 EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2922 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2923 (ins VR128X:$src1, sdmem:$src2),
2924 !strconcat(OpcodeStr,
2925 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2926 []>, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2931 defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14">,
2932 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
2933 avx512_fp_unop_p_int<0x4C, "vrcp14",
2934 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
2936 defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14">,
2937 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
2938 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
2939 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
2941 def : Pat<(int_x86_avx512_rsqrt14_ss VR128X:$src),
2942 (COPY_TO_REGCLASS (VRSQRT14SSZr (f32 (IMPLICIT_DEF)),
2943 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2945 def : Pat<(int_x86_avx512_rsqrt14_ss sse_load_f32:$src),
2946 (VRSQRT14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2948 def : Pat<(int_x86_avx512_rcp14_ss VR128X:$src),
2949 (COPY_TO_REGCLASS (VRCP14SSZr (f32 (IMPLICIT_DEF)),
2950 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2952 def : Pat<(int_x86_avx512_rcp14_ss sse_load_f32:$src),
2953 (VRCP14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2955 let AddedComplexity = 20, Predicates = [HasERI] in {
2956 defm VRCP28 : avx512_fp_unop_s<0xCB, "vrcp28">,
2957 avx512_fp_unop_p<0xCA, "vrcp28", X86frcp>,
2958 avx512_fp_unop_p_int<0xCA, "vrcp28",
2959 int_x86_avx512_rcp28_ps_512, int_x86_avx512_rcp28_pd_512>;
2961 defm VRSQRT28 : avx512_fp_unop_s<0xCD, "vrsqrt28">,
2962 avx512_fp_unop_p<0xCC, "vrsqrt28", X86frsqrt>,
2963 avx512_fp_unop_p_int<0xCC, "vrsqrt28",
2964 int_x86_avx512_rsqrt28_ps_512, int_x86_avx512_rsqrt28_pd_512>;
2967 let Predicates = [HasERI] in {
2968 def : Pat<(int_x86_avx512_rsqrt28_ss VR128X:$src),
2969 (COPY_TO_REGCLASS (VRSQRT28SSZr (f32 (IMPLICIT_DEF)),
2970 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2972 def : Pat<(int_x86_avx512_rsqrt28_ss sse_load_f32:$src),
2973 (VRSQRT28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2975 def : Pat<(int_x86_avx512_rcp28_ss VR128X:$src),
2976 (COPY_TO_REGCLASS (VRCP28SSZr (f32 (IMPLICIT_DEF)),
2977 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2979 def : Pat<(int_x86_avx512_rcp28_ss sse_load_f32:$src),
2980 (VRCP28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2982 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2983 Intrinsic V16F32Int, Intrinsic V8F64Int,
2984 OpndItins itins_s, OpndItins itins_d> {
2985 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2986 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2987 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
2991 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2992 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2994 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
2995 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2997 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2998 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2999 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3003 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3004 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3005 [(set VR512:$dst, (OpNode
3006 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3007 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3009 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3010 !strconcat(OpcodeStr,
3011 "ps\t{$src, $dst|$dst, $src}"),
3012 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3014 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3015 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3017 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3018 EVEX_V512, EVEX_CD8<32, CD8VF>;
3019 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3020 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3021 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3022 EVEX, EVEX_V512, VEX_W;
3023 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3024 !strconcat(OpcodeStr,
3025 "pd\t{$src, $dst|$dst, $src}"),
3026 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3027 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3030 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3031 Intrinsic F32Int, Intrinsic F64Int,
3032 OpndItins itins_s, OpndItins itins_d> {
3033 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3034 (ins FR32X:$src1, FR32X:$src2),
3035 !strconcat(OpcodeStr,
3036 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3037 [], itins_s.rr>, XS, EVEX_4V;
3038 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3039 (ins VR128X:$src1, VR128X:$src2),
3040 !strconcat(OpcodeStr,
3041 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3043 (F32Int VR128X:$src1, VR128X:$src2))],
3044 itins_s.rr>, XS, EVEX_4V;
3045 let mayLoad = 1 in {
3046 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3047 (ins FR32X:$src1, f32mem:$src2),
3048 !strconcat(OpcodeStr,
3049 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3050 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3051 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3052 (ins VR128X:$src1, ssmem:$src2),
3053 !strconcat(OpcodeStr,
3054 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3056 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3057 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3059 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3060 (ins FR64X:$src1, FR64X:$src2),
3061 !strconcat(OpcodeStr,
3062 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3064 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3065 (ins VR128X:$src1, VR128X:$src2),
3066 !strconcat(OpcodeStr,
3067 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3069 (F64Int VR128X:$src1, VR128X:$src2))],
3070 itins_s.rr>, XD, EVEX_4V, VEX_W;
3071 let mayLoad = 1 in {
3072 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3073 (ins FR64X:$src1, f64mem:$src2),
3074 !strconcat(OpcodeStr,
3075 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3076 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3077 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3078 (ins VR128X:$src1, sdmem:$src2),
3079 !strconcat(OpcodeStr,
3080 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3082 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3083 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3088 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3089 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3090 SSE_SQRTSS, SSE_SQRTSD>,
3091 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3092 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3093 SSE_SQRTPS, SSE_SQRTPD>;
3095 let Predicates = [HasAVX512] in {
3096 def : Pat<(f32 (fsqrt FR32X:$src)),
3097 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3098 def : Pat<(f32 (fsqrt (load addr:$src))),
3099 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3100 Requires<[OptForSize]>;
3101 def : Pat<(f64 (fsqrt FR64X:$src)),
3102 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3103 def : Pat<(f64 (fsqrt (load addr:$src))),
3104 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3105 Requires<[OptForSize]>;
3107 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3108 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3109 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3110 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3111 Requires<[OptForSize]>;
3113 def : Pat<(f32 (X86frcp FR32X:$src)),
3114 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3115 def : Pat<(f32 (X86frcp (load addr:$src))),
3116 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3117 Requires<[OptForSize]>;
3119 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3120 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3121 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3123 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3124 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3126 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3127 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3128 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3130 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3131 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3135 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3136 X86MemOperand x86memop, RegisterClass RC,
3137 PatFrag mem_frag32, PatFrag mem_frag64,
3138 Intrinsic V4F32Int, Intrinsic V2F64Int,
3140 let ExeDomain = SSEPackedSingle in {
3141 // Intrinsic operation, reg.
3142 // Vector intrinsic operation, reg
3143 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3144 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3145 !strconcat(OpcodeStr,
3146 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3147 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3149 // Vector intrinsic operation, mem
3150 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3151 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3152 !strconcat(OpcodeStr,
3153 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3155 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3156 EVEX_CD8<32, VForm>;
3157 } // ExeDomain = SSEPackedSingle
3159 let ExeDomain = SSEPackedDouble in {
3160 // Vector intrinsic operation, reg
3161 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3162 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3163 !strconcat(OpcodeStr,
3164 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3165 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3167 // Vector intrinsic operation, mem
3168 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3169 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3170 !strconcat(OpcodeStr,
3171 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3173 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3174 EVEX_CD8<64, VForm>;
3175 } // ExeDomain = SSEPackedDouble
3178 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3182 let ExeDomain = GenericDomain in {
3184 let hasSideEffects = 0 in
3185 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3186 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3187 !strconcat(OpcodeStr,
3188 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3191 // Intrinsic operation, reg.
3192 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3193 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3194 !strconcat(OpcodeStr,
3195 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3196 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3198 // Intrinsic operation, mem.
3199 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3200 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3201 !strconcat(OpcodeStr,
3202 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3203 [(set VR128X:$dst, (F32Int VR128X:$src1,
3204 sse_load_f32:$src2, imm:$src3))]>,
3205 EVEX_CD8<32, CD8VT1>;
3208 let hasSideEffects = 0 in
3209 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3210 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3211 !strconcat(OpcodeStr,
3212 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3215 // Intrinsic operation, reg.
3216 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3217 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3218 !strconcat(OpcodeStr,
3219 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3220 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3223 // Intrinsic operation, mem.
3224 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3225 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3226 !strconcat(OpcodeStr,
3227 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3229 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3230 VEX_W, EVEX_CD8<64, CD8VT1>;
3231 } // ExeDomain = GenericDomain
3234 let Predicates = [HasAVX512] in {
3235 defm VRNDSCALE : avx512_fp_binop_rm<0x0A, 0x0B, "vrndscale",
3236 int_x86_avx512_rndscale_ss,
3237 int_x86_avx512_rndscale_sd>, EVEX_4V;
3239 defm VRNDSCALEZ : avx512_fp_unop_rm<0x08, 0x09, "vrndscale", f256mem, VR512,
3240 memopv16f32, memopv8f64,
3241 int_x86_avx512_rndscale_ps_512,
3242 int_x86_avx512_rndscale_pd_512, CD8VF>,
3246 def : Pat<(ffloor FR32X:$src),
3247 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3248 def : Pat<(f64 (ffloor FR64X:$src)),
3249 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3250 def : Pat<(f32 (fnearbyint FR32X:$src)),
3251 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3252 def : Pat<(f64 (fnearbyint FR64X:$src)),
3253 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3254 def : Pat<(f32 (fceil FR32X:$src)),
3255 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3256 def : Pat<(f64 (fceil FR64X:$src)),
3257 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3258 def : Pat<(f32 (frint FR32X:$src)),
3259 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3260 def : Pat<(f64 (frint FR64X:$src)),
3261 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3262 def : Pat<(f32 (ftrunc FR32X:$src)),
3263 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3264 def : Pat<(f64 (ftrunc FR64X:$src)),
3265 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3267 def : Pat<(v16f32 (ffloor VR512:$src)),
3268 (VRNDSCALEZPSr VR512:$src, (i32 0x1))>;
3269 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3270 (VRNDSCALEZPSr VR512:$src, (i32 0xC))>;
3271 def : Pat<(v16f32 (fceil VR512:$src)),
3272 (VRNDSCALEZPSr VR512:$src, (i32 0x2))>;
3273 def : Pat<(v16f32 (frint VR512:$src)),
3274 (VRNDSCALEZPSr VR512:$src, (i32 0x4))>;
3275 def : Pat<(v16f32 (ftrunc VR512:$src)),
3276 (VRNDSCALEZPSr VR512:$src, (i32 0x3))>;
3278 def : Pat<(v8f64 (ffloor VR512:$src)),
3279 (VRNDSCALEZPDr VR512:$src, (i32 0x1))>;
3280 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3281 (VRNDSCALEZPDr VR512:$src, (i32 0xC))>;
3282 def : Pat<(v8f64 (fceil VR512:$src)),
3283 (VRNDSCALEZPDr VR512:$src, (i32 0x2))>;
3284 def : Pat<(v8f64 (frint VR512:$src)),
3285 (VRNDSCALEZPDr VR512:$src, (i32 0x4))>;
3286 def : Pat<(v8f64 (ftrunc VR512:$src)),
3287 (VRNDSCALEZPDr VR512:$src, (i32 0x3))>;
3289 //-------------------------------------------------
3290 // Integer truncate and extend operations
3291 //-------------------------------------------------
3293 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3294 RegisterClass dstRC, RegisterClass srcRC,
3295 RegisterClass KRC, X86MemOperand x86memop> {
3296 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3298 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3301 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3302 (ins KRC:$mask, srcRC:$src),
3303 !strconcat(OpcodeStr,
3304 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3307 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3308 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3311 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3312 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3313 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3314 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3315 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3316 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3317 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3318 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3319 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3320 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3321 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3322 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3323 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3324 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3325 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3326 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3327 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3328 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3329 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3330 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3331 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3332 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3333 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3334 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3335 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3336 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3337 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3338 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3339 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3340 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3342 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3343 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3344 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3345 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3346 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3348 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3349 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3350 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3351 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3352 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3353 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3354 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3355 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3358 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3359 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3360 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3362 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3364 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3365 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3366 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3367 (ins x86memop:$src),
3368 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3370 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3374 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3375 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3377 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3378 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3380 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3381 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3382 EVEX_CD8<16, CD8VH>;
3383 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3384 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3385 EVEX_CD8<16, CD8VQ>;
3386 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3387 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3388 EVEX_CD8<32, CD8VH>;
3390 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3391 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3393 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3394 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3396 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3397 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3398 EVEX_CD8<16, CD8VH>;
3399 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3400 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3401 EVEX_CD8<16, CD8VQ>;
3402 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3403 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3404 EVEX_CD8<32, CD8VH>;
3406 //===----------------------------------------------------------------------===//
3407 // GATHER - SCATTER Operations
3409 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3410 RegisterClass RC, X86MemOperand memop> {
3412 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3413 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3414 (ins RC:$src1, KRC:$mask, memop:$src2),
3415 !strconcat(OpcodeStr,
3416 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3419 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3420 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3421 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3422 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3424 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3425 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3426 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3427 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3429 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3430 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3431 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3432 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3434 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3435 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3436 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3437 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3439 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3440 RegisterClass RC, X86MemOperand memop> {
3441 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3442 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3443 (ins memop:$dst, KRC:$mask, RC:$src2),
3444 !strconcat(OpcodeStr,
3445 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3449 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3450 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3451 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3452 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3454 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3455 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3456 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3457 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3459 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3460 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3461 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3462 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3464 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3465 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3466 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3467 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3469 //===----------------------------------------------------------------------===//
3470 // VSHUFPS - VSHUFPD Operations
3472 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3473 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3475 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3476 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3477 !strconcat(OpcodeStr,
3478 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3479 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3480 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3481 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3482 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3483 (ins RC:$src1, RC:$src2, i8imm:$src3),
3484 !strconcat(OpcodeStr,
3485 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3486 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3487 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3488 EVEX_4V, Sched<[WriteShuffle]>;
3491 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3492 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3493 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3494 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3496 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3497 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3498 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3499 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3500 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3502 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3503 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3504 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3505 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3506 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3508 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3509 X86MemOperand x86memop> {
3510 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3511 (ins RC:$src1, RC:$src2, i8imm:$src3),
3512 !strconcat(OpcodeStr,
3513 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3516 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3517 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3518 !strconcat(OpcodeStr,
3519 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3522 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3523 EVEX_V512, EVEX_CD8<32, CD8VF>;
3524 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3525 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3527 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3528 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3529 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3530 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3531 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3532 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3533 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3534 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3536 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3537 X86MemOperand x86memop> {
3538 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3539 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3541 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3542 (ins x86memop:$src),
3543 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3547 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3548 EVEX_CD8<32, CD8VF>;
3549 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3550 EVEX_CD8<64, CD8VF>;
3552 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3553 RegisterClass RC, RegisterClass KRC,
3554 X86MemOperand x86memop,
3555 X86MemOperand x86scalar_mop, string BrdcstStr> {
3556 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3558 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
3560 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3561 (ins x86memop:$src),
3562 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
3564 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3565 (ins x86scalar_mop:$src),
3566 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3567 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3569 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3570 (ins KRC:$mask, RC:$src),
3571 !strconcat(OpcodeStr,
3572 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3574 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3575 (ins KRC:$mask, x86memop:$src),
3576 !strconcat(OpcodeStr,
3577 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3579 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3580 (ins KRC:$mask, x86scalar_mop:$src),
3581 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3582 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3584 []>, EVEX, EVEX_KZ, EVEX_B;
3586 let Constraints = "$src1 = $dst" in {
3587 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3588 (ins RC:$src1, KRC:$mask, RC:$src2),
3589 !strconcat(OpcodeStr,
3590 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3592 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3593 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3594 !strconcat(OpcodeStr,
3595 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3597 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3598 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3599 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3600 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
3601 []>, EVEX, EVEX_K, EVEX_B;
3605 let Predicates = [HasCDI] in {
3606 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
3607 i512mem, i32mem, "{1to16}">,
3608 EVEX_V512, EVEX_CD8<32, CD8VF>;
3611 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
3612 i512mem, i64mem, "{1to8}">,
3613 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3617 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
3619 (VPCONFLICTDrrk VR512:$src1,
3620 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
3622 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
3624 (VPCONFLICTQrrk VR512:$src1,
3625 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;