1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
98 //===----------------------------------------------------------------------===//
99 // AVX-512 - VECTOR INSERT
102 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
108 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
114 // -- 64x4 fp form --
115 let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
121 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
126 // -- 32x4 integer form --
127 let neverHasSideEffects = 1 in {
128 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
133 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
140 let neverHasSideEffects = 1 in {
142 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
147 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
153 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
166 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
180 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
193 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
207 // vinsertps - insert f32 to XMM
208 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
213 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
220 //===----------------------------------------------------------------------===//
221 // AVX-512 VECTOR EXTRACT
223 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
225 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
235 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
240 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
246 let neverHasSideEffects = 1 in {
248 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
258 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
263 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
269 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
273 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
277 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
281 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
286 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
290 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
294 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
298 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
302 // A 256-bit subvector extract from the first 512-bit vector position
303 // is a subregister copy that needs no instruction.
304 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
314 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
324 // A 128-bit subvector insert to the first 512-bit vector position
325 // is a subregister copy that needs no instruction.
326 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
330 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
334 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
338 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
343 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
352 // vextractps - extract 32 bits from XMM
353 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
359 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
365 //===---------------------------------------------------------------------===//
368 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
377 let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss{z}", VR512,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
383 let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd{z}", VR512,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
389 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
394 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
395 (VBROADCASTSSZrm addr:$src)>;
396 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
397 (VBROADCASTSDZrm addr:$src)>;
399 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
400 RegisterClass SrcRC, RegisterClass KRC> {
401 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
402 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
403 []>, EVEX, EVEX_V512;
404 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
405 (ins KRC:$mask, SrcRC:$src),
406 !strconcat(OpcodeStr,
407 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
408 []>, EVEX, EVEX_V512, EVEX_KZ;
411 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
412 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
415 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
416 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
418 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
419 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
421 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
422 (VPBROADCASTDrZrr GR32:$src)>;
423 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
424 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
425 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
426 (VPBROADCASTQrZrr GR64:$src)>;
427 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
428 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
430 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
431 (VPBROADCASTDrZrr GR32:$src)>;
432 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
433 (VPBROADCASTQrZrr GR64:$src)>;
435 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
436 X86MemOperand x86memop, PatFrag ld_frag,
437 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
439 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
440 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
442 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
443 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
445 !strconcat(OpcodeStr,
446 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
448 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
451 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
452 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
454 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
455 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
457 !strconcat(OpcodeStr,
458 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
459 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
460 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
464 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
465 loadi32, VR512, v16i32, v4i32, VK16WM>,
466 EVEX_V512, EVEX_CD8<32, CD8VT1>;
467 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
468 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
469 EVEX_CD8<64, CD8VT1>;
471 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
472 (VPBROADCASTDZrr VR128X:$src)>;
473 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
474 (VPBROADCASTQZrr VR128X:$src)>;
476 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
477 (VBROADCASTSSZrr VR128X:$src)>;
478 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
479 (VBROADCASTSDZrr VR128X:$src)>;
481 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
482 (VBROADCASTSSZrr VR128X:$src)>;
483 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
484 (VBROADCASTSDZrr VR128X:$src)>;
486 // Provide fallback in case the load node that is used in the patterns above
487 // is used by additional users, which prevents the pattern selection.
488 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
489 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
490 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
491 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
494 let Predicates = [HasAVX512] in {
495 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
497 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
498 addr:$src)), sub_ymm)>;
500 //===----------------------------------------------------------------------===//
501 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
504 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
505 RegisterClass DstRC, RegisterClass KRC,
506 ValueType OpVT, ValueType SrcVT> {
507 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
508 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
512 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
513 VK16, v16i32, v16i1>, EVEX_V512;
514 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
515 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
517 //===----------------------------------------------------------------------===//
520 // -- immediate form --
521 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
522 SDNode OpNode, PatFrag mem_frag,
523 X86MemOperand x86memop, ValueType OpVT> {
524 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
525 (ins RC:$src1, i8imm:$src2),
526 !strconcat(OpcodeStr,
527 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
529 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
531 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
532 (ins x86memop:$src1, i8imm:$src2),
533 !strconcat(OpcodeStr,
534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
536 (OpVT (OpNode (mem_frag addr:$src1),
537 (i8 imm:$src2))))]>, EVEX;
540 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
541 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
542 let ExeDomain = SSEPackedDouble in
543 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
544 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
546 // -- VPERM - register form --
547 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
548 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
550 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
551 (ins RC:$src1, RC:$src2),
552 !strconcat(OpcodeStr,
553 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
555 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
557 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
558 (ins RC:$src1, x86memop:$src2),
559 !strconcat(OpcodeStr,
560 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
562 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
566 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
567 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
568 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
569 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
570 let ExeDomain = SSEPackedSingle in
571 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
572 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
573 let ExeDomain = SSEPackedDouble in
574 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
575 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
577 // -- VPERM2I - 3 source operands form --
578 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
579 PatFrag mem_frag, X86MemOperand x86memop,
581 let Constraints = "$src1 = $dst" in {
582 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
583 (ins RC:$src1, RC:$src2, RC:$src3),
584 !strconcat(OpcodeStr,
585 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
587 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
590 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
591 (ins RC:$src1, RC:$src2, x86memop:$src3),
592 !strconcat(OpcodeStr,
593 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
595 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
596 (mem_frag addr:$src3))))]>, EVEX_4V;
599 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
600 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
601 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
602 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
603 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
604 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
605 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
606 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
608 //===----------------------------------------------------------------------===//
609 // AVX-512 - BLEND using mask
611 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, Intrinsic Int,
612 RegisterClass KRC, RegisterClass RC,
613 X86MemOperand x86memop, PatFrag mem_frag,
614 SDNode OpNode, ValueType vt> {
615 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
616 (ins KRC:$mask, RC:$src1, RC:$src2),
617 !strconcat(OpcodeStr,
618 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
619 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
620 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
621 def rr_Int : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
622 (ins KRC:$mask, RC:$src1, RC:$src2),
623 !strconcat(OpcodeStr,
624 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
625 [(set RC:$dst, (Int KRC:$mask, (vt RC:$src2),
626 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
629 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
630 (ins KRC:$mask, RC:$src1, x86memop:$src2),
631 !strconcat(OpcodeStr,
632 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
636 def rm_Int : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
637 (ins KRC:$mask, RC:$src1, x86memop:$src2),
638 !strconcat(OpcodeStr,
639 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
640 [(set RC:$dst, (Int KRC:$mask, (vt RC:$src1),
641 (mem_frag addr:$src2)))]>,
646 let ExeDomain = SSEPackedSingle in
647 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
648 int_x86_avx512_mask_blend_ps_512,
649 VK16WM, VR512, f512mem,
650 memopv16f32, vselect, v16f32>,
651 EVEX_CD8<32, CD8VF>, EVEX_V512;
652 let ExeDomain = SSEPackedDouble in
653 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
654 int_x86_avx512_mask_blend_pd_512,
655 VK8WM, VR512, f512mem,
656 memopv8f64, vselect, v8f64>,
657 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
659 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
660 int_x86_avx512_mask_blend_d_512,
661 VK16WM, VR512, f512mem,
662 memopv16i32, vselect, v16i32>,
663 EVEX_CD8<32, CD8VF>, EVEX_V512;
665 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
666 int_x86_avx512_mask_blend_q_512,
667 VK8WM, VR512, f512mem,
668 memopv8i64, vselect, v8i64>,
669 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
671 let Predicates = [HasAVX512] in {
672 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
673 (v8f32 VR256X:$src2))),
675 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
676 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
677 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
679 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
680 (v8i32 VR256X:$src2))),
682 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
683 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
684 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
687 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
688 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
689 SDNode OpNode, ValueType vt> {
690 def rr : AVX512BI<opc, MRMSrcReg,
691 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
692 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
693 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
694 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
695 def rm : AVX512BI<opc, MRMSrcMem,
696 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
697 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
698 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
699 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
702 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
703 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
704 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
705 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
707 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
708 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
709 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
710 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
712 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
713 (COPY_TO_REGCLASS (VPCMPGTDZrr
714 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
715 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
717 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
718 (COPY_TO_REGCLASS (VPCMPEQDZrr
719 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
720 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
722 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
723 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
724 SDNode OpNode, ValueType vt, Operand CC, string asm,
726 def rri : AVX512AIi8<opc, MRMSrcReg,
727 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
728 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
729 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
730 def rmi : AVX512AIi8<opc, MRMSrcMem,
731 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
732 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
733 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
734 // Accept explicit immediate argument form instead of comparison code.
735 let neverHasSideEffects = 1 in {
736 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
737 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
738 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
739 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
740 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
741 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
745 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
746 X86cmpm, v16i32, AVXCC,
747 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
748 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
749 EVEX_V512, EVEX_CD8<32, CD8VF>;
750 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
751 X86cmpmu, v16i32, AVXCC,
752 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
753 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
754 EVEX_V512, EVEX_CD8<32, CD8VF>;
756 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
757 X86cmpm, v8i64, AVXCC,
758 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
759 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
760 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
761 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
762 X86cmpmu, v8i64, AVXCC,
763 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
764 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
765 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
767 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
768 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
769 X86MemOperand x86memop, Operand CC,
770 SDNode OpNode, ValueType vt, string asm,
771 string asm_alt, Domain d> {
772 def rri : AVX512PIi8<0xC2, MRMSrcReg,
773 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
774 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
775 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
776 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
778 (OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
780 // Accept explicit immediate argument form instead of comparison code.
781 let neverHasSideEffects = 1 in {
782 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
783 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
785 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
786 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
791 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
792 "vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
793 "vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
794 SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
795 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
796 "vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
797 "vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
798 SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
801 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
802 (COPY_TO_REGCLASS (VCMPPSZrri
803 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
804 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
806 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
807 (COPY_TO_REGCLASS (VPCMPDZrri
808 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
809 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
811 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
812 (COPY_TO_REGCLASS (VPCMPUDZrri
813 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
814 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
817 // Mask register copy, including
818 // - copy between mask registers
819 // - load/store mask registers
820 // - copy from GPR to mask register and vice versa
822 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
823 string OpcodeStr, RegisterClass KRC,
824 ValueType vt, X86MemOperand x86memop> {
825 let neverHasSideEffects = 1 in {
826 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
827 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
829 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
830 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
831 [(set KRC:$dst, (vt (load addr:$src)))]>;
833 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
834 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
838 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
840 RegisterClass KRC, RegisterClass GRC> {
841 let neverHasSideEffects = 1 in {
842 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
843 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
844 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
845 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
849 let Predicates = [HasAVX512] in {
850 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
852 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
856 let Predicates = [HasAVX512] in {
857 // GR16 from/to 16-bit mask
858 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
859 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
860 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
861 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
863 // Store kreg in memory
864 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
865 (KMOVWmk addr:$dst, VK16:$src)>;
867 def : Pat<(store (v8i1 VK8:$src), addr:$dst),
868 (KMOVWmk addr:$dst, (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16)))>;
870 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
871 let Predicates = [HasAVX512] in {
872 // GR from/to 8-bit mask without native support
873 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
875 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
877 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
879 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
883 // Mask unary operation
885 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
886 RegisterClass KRC, SDPatternOperator OpNode> {
887 let Predicates = [HasAVX512] in
888 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
889 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
890 [(set KRC:$dst, (OpNode KRC:$src))]>;
893 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
894 SDPatternOperator OpNode> {
895 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
899 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
901 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
902 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
903 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
905 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
906 def : Pat<(not VK8:$src),
908 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
910 // Mask binary operation
911 // - KADD, KAND, KANDN, KOR, KXNOR, KXOR
912 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
913 RegisterClass KRC, SDPatternOperator OpNode> {
914 let Predicates = [HasAVX512] in
915 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
916 !strconcat(OpcodeStr,
917 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
918 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
921 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
922 SDPatternOperator OpNode> {
923 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
927 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
928 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
930 let isCommutable = 1 in {
931 defm KADD : avx512_mask_binop_w<0x4a, "kadd", add>;
932 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
933 let isCommutable = 0 in
934 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
935 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
936 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
937 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
940 multiclass avx512_mask_binop_int<string IntName, string InstName> {
941 let Predicates = [HasAVX512] in
942 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
943 VK16:$src1, VK16:$src2),
944 (!cast<Instruction>(InstName##"Wrr") VK16:$src1, VK16:$src2)>;
947 defm : avx512_mask_binop_int<"kadd", "KADD">;
948 defm : avx512_mask_binop_int<"kand", "KAND">;
949 defm : avx512_mask_binop_int<"kandn", "KANDN">;
950 defm : avx512_mask_binop_int<"kor", "KOR">;
951 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
952 defm : avx512_mask_binop_int<"kxor", "KXOR">;
953 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
954 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
955 let Predicates = [HasAVX512] in
956 def : Pat<(OpNode VK8:$src1, VK8:$src2),
958 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
959 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
962 defm : avx512_binop_pat<and, KANDWrr>;
963 defm : avx512_binop_pat<andn, KANDNWrr>;
964 defm : avx512_binop_pat<or, KORWrr>;
965 defm : avx512_binop_pat<xnor, KXNORWrr>;
966 defm : avx512_binop_pat<xor, KXORWrr>;
969 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
970 RegisterClass KRC1, RegisterClass KRC2> {
971 let Predicates = [HasAVX512] in
972 def rr : I<opc, MRMSrcReg, (outs KRC1:$dst), (ins KRC2:$src1, KRC2:$src2),
973 !strconcat(OpcodeStr,
974 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
977 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
978 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16, VK8>,
979 VEX_4V, VEX_L, OpSize, TB;
982 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
984 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
985 let Predicates = [HasAVX512] in
986 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
987 VK8:$src1, VK8:$src2),
988 (!cast<Instruction>(InstName##"BWrr") VK8:$src1, VK8:$src2)>;
991 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
993 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
995 let Predicates = [HasAVX512], Defs = [EFLAGS] in
996 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
997 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
998 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1001 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1002 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1006 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1007 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest>;
1010 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1012 let Predicates = [HasAVX512] in
1013 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1014 !strconcat(OpcodeStr,
1015 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1016 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1019 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1021 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1022 VEX, OpSize, TA, VEX_W;
1025 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", shl>;
1026 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", srl>;
1028 // Mask setting all 0s or 1s
1029 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1030 let Predicates = [HasAVX512] in
1031 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1032 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1033 [(set KRC:$dst, (VT Val))]>;
1036 multiclass avx512_mask_setop_w<PatFrag Val> {
1037 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1038 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1041 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1042 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1044 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1045 let Predicates = [HasAVX512] in {
1046 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1047 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1049 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1050 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1052 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1053 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1055 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1056 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1058 //===----------------------------------------------------------------------===//
1059 // AVX-512 - Aligned and unaligned load and store
1062 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1063 X86MemOperand x86memop, PatFrag ld_frag,
1064 string asm, Domain d> {
1065 let neverHasSideEffects = 1 in
1066 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1067 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1069 let canFoldAsLoad = 1 in
1070 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1071 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1072 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1073 let Constraints = "$src1 = $dst" in {
1074 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1075 (ins RC:$src1, KRC:$mask, RC:$src2),
1077 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1079 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1080 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1082 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1083 [], d>, EVEX, EVEX_K;
1087 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1088 "vmovaps", SSEPackedSingle>,
1089 EVEX_V512, EVEX_CD8<32, CD8VF>;
1090 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1091 "vmovapd", SSEPackedDouble>,
1092 OpSize, EVEX_V512, VEX_W,
1093 EVEX_CD8<64, CD8VF>;
1094 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1095 "vmovups", SSEPackedSingle>,
1096 EVEX_V512, EVEX_CD8<32, CD8VF>;
1097 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1098 "vmovupd", SSEPackedDouble>,
1099 OpSize, EVEX_V512, VEX_W,
1100 EVEX_CD8<64, CD8VF>;
1101 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1102 "vmovaps\t{$src, $dst|$dst, $src}",
1103 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1104 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1105 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1106 "vmovapd\t{$src, $dst|$dst, $src}",
1107 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1108 SSEPackedDouble>, EVEX, EVEX_V512,
1109 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1110 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1111 "vmovups\t{$src, $dst|$dst, $src}",
1112 [(store (v16f32 VR512:$src), addr:$dst)],
1113 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1114 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1115 "vmovupd\t{$src, $dst|$dst, $src}",
1116 [(store (v8f64 VR512:$src), addr:$dst)],
1117 SSEPackedDouble>, EVEX, EVEX_V512,
1118 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1120 let neverHasSideEffects = 1 in {
1121 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1123 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1125 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1127 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1128 EVEX, EVEX_V512, VEX_W;
1129 let mayStore = 1 in {
1130 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1131 (ins i512mem:$dst, VR512:$src),
1132 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1133 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1134 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1135 (ins i512mem:$dst, VR512:$src),
1136 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1137 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1139 let mayLoad = 1 in {
1140 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1142 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1143 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1144 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1146 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1147 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1151 // 512-bit aligned load/store
1152 def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1153 def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1155 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1156 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1157 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1158 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1160 multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1161 RegisterClass RC, RegisterClass KRC,
1162 PatFrag ld_frag, X86MemOperand x86memop> {
1163 let neverHasSideEffects = 1 in
1164 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1165 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1166 let canFoldAsLoad = 1 in
1167 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1168 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1169 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1171 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1172 (ins x86memop:$dst, VR512:$src),
1173 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1174 let Constraints = "$src1 = $dst" in {
1175 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1176 (ins RC:$src1, KRC:$mask, RC:$src2),
1178 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1180 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
1181 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1183 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1188 defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1189 memopv16i32, i512mem>,
1190 EVEX_V512, EVEX_CD8<32, CD8VF>;
1191 defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1192 memopv8i64, i512mem>,
1193 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1195 // 512-bit unaligned load/store
1196 def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1197 def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1199 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1200 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1201 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1202 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1204 let AddedComplexity = 20 in {
1205 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1206 (v16f32 VR512:$src2))),
1207 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1208 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1209 (v8f64 VR512:$src2))),
1210 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1211 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1212 (v16i32 VR512:$src2))),
1213 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1214 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1215 (v8i64 VR512:$src2))),
1216 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1218 // Move Int Doubleword to Packed Double Int
1220 def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1221 "vmovd{z}\t{$src, $dst|$dst, $src}",
1223 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1225 def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1226 "vmovd{z}\t{$src, $dst|$dst, $src}",
1228 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1229 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1230 def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1231 "vmovq{z}\t{$src, $dst|$dst, $src}",
1233 (v2i64 (scalar_to_vector GR64:$src)))],
1234 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1235 let isCodeGenOnly = 1 in {
1236 def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1237 "vmovq{z}\t{$src, $dst|$dst, $src}",
1238 [(set FR64:$dst, (bitconvert GR64:$src))],
1239 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1240 def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1241 "vmovq{z}\t{$src, $dst|$dst, $src}",
1242 [(set GR64:$dst, (bitconvert FR64:$src))],
1243 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1245 def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1246 "vmovq{z}\t{$src, $dst|$dst, $src}",
1247 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1248 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1249 EVEX_CD8<64, CD8VT1>;
1251 // Move Int Doubleword to Single Scalar
1253 let isCodeGenOnly = 1 in {
1254 def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1255 "vmovd{z}\t{$src, $dst|$dst, $src}",
1256 [(set FR32X:$dst, (bitconvert GR32:$src))],
1257 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1259 def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1260 "vmovd{z}\t{$src, $dst|$dst, $src}",
1261 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1262 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1265 // Move Packed Doubleword Int to Packed Double Int
1267 def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1268 "vmovd{z}\t{$src, $dst|$dst, $src}",
1269 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1270 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1272 def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1273 (ins i32mem:$dst, VR128X:$src),
1274 "vmovd{z}\t{$src, $dst|$dst, $src}",
1275 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1276 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1277 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1279 // Move Packed Doubleword Int first element to Doubleword Int
1281 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1282 "vmovq{z}\t{$src, $dst|$dst, $src}",
1283 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1285 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1286 Requires<[HasAVX512, In64BitMode]>;
1288 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1289 (ins i64mem:$dst, VR128X:$src),
1290 "vmovq{z}\t{$src, $dst|$dst, $src}",
1291 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1292 addr:$dst)], IIC_SSE_MOVDQ>,
1293 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
1294 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1296 // Move Scalar Single to Double Int
1298 let isCodeGenOnly = 1 in {
1299 def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1301 "vmovd{z}\t{$src, $dst|$dst, $src}",
1302 [(set GR32:$dst, (bitconvert FR32X:$src))],
1303 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1304 def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1305 (ins i32mem:$dst, FR32X:$src),
1306 "vmovd{z}\t{$src, $dst|$dst, $src}",
1307 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1308 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1311 // Move Quadword Int to Packed Quadword Int
1313 def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1315 "vmovq{z}\t{$src, $dst|$dst, $src}",
1317 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1318 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1320 //===----------------------------------------------------------------------===//
1321 // AVX-512 MOVSS, MOVSD
1322 //===----------------------------------------------------------------------===//
1324 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1325 SDNode OpNode, ValueType vt,
1326 X86MemOperand x86memop, PatFrag mem_pat> {
1327 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1328 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1329 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1330 (scalar_to_vector RC:$src2))))],
1331 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1332 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1333 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1334 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1336 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1337 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1338 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1342 let ExeDomain = SSEPackedSingle in
1343 defm VMOVSSZ : avx512_move_scalar<"movss{z}", FR32X, X86Movss, v4f32, f32mem,
1344 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1346 let ExeDomain = SSEPackedDouble in
1347 defm VMOVSDZ : avx512_move_scalar<"movsd{z}", FR64X, X86Movsd, v2f64, f64mem,
1348 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1351 // For the disassembler
1352 let isCodeGenOnly = 1 in {
1353 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1354 (ins VR128X:$src1, FR32X:$src2),
1355 "movss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1357 XS, EVEX_4V, VEX_LIG;
1358 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1359 (ins VR128X:$src1, FR64X:$src2),
1360 "movsd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1362 XD, EVEX_4V, VEX_LIG, VEX_W;
1365 let Predicates = [HasAVX512] in {
1366 let AddedComplexity = 15 in {
1367 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1368 // MOVS{S,D} to the lower bits.
1369 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1370 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1371 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1372 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1373 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1374 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1375 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1376 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1378 // Move low f32 and clear high bits.
1379 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1380 (SUBREG_TO_REG (i32 0),
1381 (VMOVSSZrr (v4f32 (V_SET0)),
1382 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1383 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1384 (SUBREG_TO_REG (i32 0),
1385 (VMOVSSZrr (v4i32 (V_SET0)),
1386 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1389 let AddedComplexity = 20 in {
1390 // MOVSSrm zeros the high parts of the register; represent this
1391 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1392 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1393 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1394 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1395 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1396 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1397 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1399 // MOVSDrm zeros the high parts of the register; represent this
1400 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1401 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1402 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1403 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1404 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1405 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1406 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1407 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1408 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1409 def : Pat<(v2f64 (X86vzload addr:$src)),
1410 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1412 // Represent the same patterns above but in the form they appear for
1414 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1415 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1416 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1417 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1418 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1419 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1420 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1421 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1422 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1424 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1425 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1426 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1427 FR32X:$src)), sub_xmm)>;
1428 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1429 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1430 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1431 FR64X:$src)), sub_xmm)>;
1432 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1433 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1434 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1436 // Move low f64 and clear high bits.
1437 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1438 (SUBREG_TO_REG (i32 0),
1439 (VMOVSDZrr (v2f64 (V_SET0)),
1440 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1442 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1443 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1444 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1446 // Extract and store.
1447 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1449 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1450 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1452 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1454 // Shuffle with VMOVSS
1455 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1456 (VMOVSSZrr (v4i32 VR128X:$src1),
1457 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1458 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1459 (VMOVSSZrr (v4f32 VR128X:$src1),
1460 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1463 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1464 (SUBREG_TO_REG (i32 0),
1465 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1466 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1468 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1469 (SUBREG_TO_REG (i32 0),
1470 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1471 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1474 // Shuffle with VMOVSD
1475 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1476 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1477 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1478 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1479 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1480 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1481 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1482 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1485 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1486 (SUBREG_TO_REG (i32 0),
1487 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1488 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1490 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1491 (SUBREG_TO_REG (i32 0),
1492 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1493 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1496 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1497 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1498 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1499 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1500 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1501 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1502 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1503 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1506 let AddedComplexity = 15 in
1507 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1509 "vmovq{z}\t{$src, $dst|$dst, $src}",
1510 [(set VR128X:$dst, (v2i64 (X86vzmovl
1511 (v2i64 VR128X:$src))))],
1512 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1514 let AddedComplexity = 20 in
1515 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1517 "vmovq{z}\t{$src, $dst|$dst, $src}",
1518 [(set VR128X:$dst, (v2i64 (X86vzmovl
1519 (loadv2i64 addr:$src))))],
1520 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1521 EVEX_CD8<8, CD8VT8>;
1523 let Predicates = [HasAVX512] in {
1524 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1525 let AddedComplexity = 20 in {
1526 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1527 (VMOVDI2PDIZrm addr:$src)>;
1528 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1529 (VMOV64toPQIZrr GR64:$src)>;
1530 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1531 (VMOVDI2PDIZrr GR32:$src)>;
1533 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1534 (VMOVDI2PDIZrm addr:$src)>;
1535 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1536 (VMOVDI2PDIZrm addr:$src)>;
1537 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1538 (VMOVZPQILo2PQIZrm addr:$src)>;
1539 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1540 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1541 def : Pat<(v2i64 (X86vzload addr:$src)),
1542 (VMOVZPQILo2PQIZrm addr:$src)>;
1545 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1546 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1547 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1548 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1549 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1550 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1551 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1554 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1555 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1557 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1558 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1560 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1561 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1563 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1564 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1566 //===----------------------------------------------------------------------===//
1567 // AVX-512 - Integer arithmetic
1569 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1570 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1571 X86MemOperand x86memop, PatFrag scalar_mfrag,
1572 X86MemOperand x86scalar_mop, string BrdcstStr,
1573 OpndItins itins, bit IsCommutable = 0> {
1574 let isCommutable = IsCommutable in
1575 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1576 (ins RC:$src1, RC:$src2),
1577 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1578 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1580 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1581 (ins RC:$src1, x86memop:$src2),
1582 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1583 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1585 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1586 (ins RC:$src1, x86scalar_mop:$src2),
1587 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1588 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1589 [(set RC:$dst, (OpNode RC:$src1,
1590 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1591 itins.rm>, EVEX_4V, EVEX_B;
1593 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1594 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1595 PatFrag memop_frag, X86MemOperand x86memop,
1597 bit IsCommutable = 0> {
1598 let isCommutable = IsCommutable in
1599 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1600 (ins RC:$src1, RC:$src2),
1601 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1602 []>, EVEX_4V, VEX_W;
1603 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1604 (ins RC:$src1, x86memop:$src2),
1605 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1606 []>, EVEX_4V, VEX_W;
1609 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1610 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1611 EVEX_V512, EVEX_CD8<32, CD8VF>;
1613 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1614 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1615 EVEX_V512, EVEX_CD8<32, CD8VF>;
1617 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1618 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1619 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1621 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1622 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1623 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1625 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1626 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1627 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1629 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1630 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1631 EVEX_V512, EVEX_CD8<64, CD8VF>;
1633 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1634 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1635 EVEX_CD8<64, CD8VF>;
1637 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1638 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1640 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1641 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1642 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1643 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1644 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1645 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1647 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1648 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1649 EVEX_V512, EVEX_CD8<32, CD8VF>;
1650 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1651 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1652 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1654 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1655 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1656 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1657 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1658 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1659 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1661 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1662 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1663 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1664 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1665 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1666 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1668 //===----------------------------------------------------------------------===//
1669 // AVX-512 - Unpack Instructions
1670 //===----------------------------------------------------------------------===//
1672 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1673 PatFrag mem_frag, RegisterClass RC,
1674 X86MemOperand x86memop, string asm,
1676 def rr : AVX512PI<opc, MRMSrcReg,
1677 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1679 (vt (OpNode RC:$src1, RC:$src2)))],
1681 def rm : AVX512PI<opc, MRMSrcMem,
1682 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1684 (vt (OpNode RC:$src1,
1685 (bitconvert (mem_frag addr:$src2)))))],
1689 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1690 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1691 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1692 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1693 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1694 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1695 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1696 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1697 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1698 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1699 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1700 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1702 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1703 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1704 X86MemOperand x86memop> {
1705 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1706 (ins RC:$src1, RC:$src2),
1707 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1708 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1709 IIC_SSE_UNPCK>, EVEX_4V;
1710 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1711 (ins RC:$src1, x86memop:$src2),
1712 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1713 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1714 (bitconvert (memop_frag addr:$src2)))))],
1715 IIC_SSE_UNPCK>, EVEX_4V;
1717 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1718 VR512, memopv16i32, i512mem>, EVEX_V512,
1719 EVEX_CD8<32, CD8VF>;
1720 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1721 VR512, memopv8i64, i512mem>, EVEX_V512,
1722 VEX_W, EVEX_CD8<64, CD8VF>;
1723 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1724 VR512, memopv16i32, i512mem>, EVEX_V512,
1725 EVEX_CD8<32, CD8VF>;
1726 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1727 VR512, memopv8i64, i512mem>, EVEX_V512,
1728 VEX_W, EVEX_CD8<64, CD8VF>;
1729 //===----------------------------------------------------------------------===//
1733 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1734 SDNode OpNode, PatFrag mem_frag,
1735 X86MemOperand x86memop, ValueType OpVT> {
1736 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1737 (ins RC:$src1, i8imm:$src2),
1738 !strconcat(OpcodeStr,
1739 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1741 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1743 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1744 (ins x86memop:$src1, i8imm:$src2),
1745 !strconcat(OpcodeStr,
1746 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1748 (OpVT (OpNode (mem_frag addr:$src1),
1749 (i8 imm:$src2))))]>, EVEX;
1752 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1753 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1755 let ExeDomain = SSEPackedSingle in
1756 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1757 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1758 EVEX_CD8<32, CD8VF>;
1759 let ExeDomain = SSEPackedDouble in
1760 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1761 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1762 VEX_W, EVEX_CD8<32, CD8VF>;
1764 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1765 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1766 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1767 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1769 //===----------------------------------------------------------------------===//
1770 // AVX-512 Logical Instructions
1771 //===----------------------------------------------------------------------===//
1773 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1774 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1775 EVEX_V512, EVEX_CD8<32, CD8VF>;
1776 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1777 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1778 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1779 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1780 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1781 EVEX_V512, EVEX_CD8<32, CD8VF>;
1782 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1783 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1784 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1785 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1786 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1787 EVEX_V512, EVEX_CD8<32, CD8VF>;
1788 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1789 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1790 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1791 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1792 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1793 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1794 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1795 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1796 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1798 //===----------------------------------------------------------------------===//
1799 // AVX-512 FP arithmetic
1800 //===----------------------------------------------------------------------===//
1802 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1804 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss{z}"), OpNode, FR32X,
1805 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1806 EVEX_CD8<32, CD8VT1>;
1807 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd{z}"), OpNode, FR64X,
1808 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1809 EVEX_CD8<64, CD8VT1>;
1812 let isCommutable = 1 in {
1813 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1814 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1815 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1816 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1818 let isCommutable = 0 in {
1819 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1820 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1823 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1824 RegisterClass RC, ValueType vt,
1825 X86MemOperand x86memop, PatFrag mem_frag,
1826 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1828 Domain d, OpndItins itins, bit commutable> {
1829 let isCommutable = commutable in
1830 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1831 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1832 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
1834 let mayLoad = 1 in {
1835 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1836 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1837 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
1838 itins.rm, d>, EVEX_4V, TB;
1839 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1840 (ins RC:$src1, x86scalar_mop:$src2),
1841 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1842 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1843 [(set RC:$dst, (OpNode RC:$src1,
1844 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1845 itins.rm, d>, EVEX_4V, EVEX_B, TB;
1849 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1850 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1851 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1853 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1854 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1855 SSE_ALU_ITINS_P.d, 1>,
1856 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1858 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
1859 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1860 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1861 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
1862 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1863 SSE_ALU_ITINS_P.d, 1>,
1864 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1866 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
1867 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1868 SSE_ALU_ITINS_P.s, 1>,
1869 EVEX_V512, EVEX_CD8<32, CD8VF>;
1870 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
1871 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1872 SSE_ALU_ITINS_P.s, 1>,
1873 EVEX_V512, EVEX_CD8<32, CD8VF>;
1875 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
1876 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1877 SSE_ALU_ITINS_P.d, 1>,
1878 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1879 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
1880 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1881 SSE_ALU_ITINS_P.d, 1>,
1882 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1884 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
1885 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1886 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1887 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
1888 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1889 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1891 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
1892 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1893 SSE_ALU_ITINS_P.d, 0>,
1894 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1895 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
1896 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1897 SSE_ALU_ITINS_P.d, 0>,
1898 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1900 //===----------------------------------------------------------------------===//
1901 // AVX-512 VPTESTM instructions
1902 //===----------------------------------------------------------------------===//
1904 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1905 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
1906 SDNode OpNode, ValueType vt> {
1907 def rr : AVX5128I<opc, MRMSrcReg,
1908 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
1909 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1910 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
1911 def rm : AVX5128I<opc, MRMSrcMem,
1912 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
1913 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1914 [(set KRC:$dst, (OpNode (vt RC:$src1),
1915 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
1918 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
1919 memopv16i32, X86testm, v16i32>, EVEX_V512,
1920 EVEX_CD8<32, CD8VF>;
1921 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
1922 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
1923 EVEX_CD8<64, CD8VF>;
1925 //===----------------------------------------------------------------------===//
1926 // AVX-512 Shift instructions
1927 //===----------------------------------------------------------------------===//
1928 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
1929 string OpcodeStr, SDNode OpNode, RegisterClass RC,
1930 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
1931 RegisterClass KRC> {
1932 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
1933 (ins RC:$src1, i8imm:$src2),
1934 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1935 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
1936 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1937 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
1938 (ins KRC:$mask, RC:$src1, i8imm:$src2),
1939 !strconcat(OpcodeStr,
1940 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1941 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1942 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
1943 (ins x86memop:$src1, i8imm:$src2),
1944 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1945 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
1946 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1947 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
1948 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
1949 !strconcat(OpcodeStr,
1950 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1951 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1954 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1955 RegisterClass RC, ValueType vt, ValueType SrcVT,
1956 PatFrag bc_frag, RegisterClass KRC> {
1957 // src2 is always 128-bit
1958 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1959 (ins RC:$src1, VR128X:$src2),
1960 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1961 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
1962 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1963 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1964 (ins KRC:$mask, RC:$src1, VR128X:$src2),
1965 !strconcat(OpcodeStr,
1966 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1967 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1968 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1969 (ins RC:$src1, i128mem:$src2),
1970 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1971 [(set RC:$dst, (vt (OpNode RC:$src1,
1972 (bc_frag (memopv2i64 addr:$src2)))))],
1973 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1974 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1975 (ins KRC:$mask, RC:$src1, i128mem:$src2),
1976 !strconcat(OpcodeStr,
1977 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1978 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1981 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
1982 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1983 EVEX_V512, EVEX_CD8<32, CD8VF>;
1984 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
1985 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1986 EVEX_CD8<32, CD8VQ>;
1988 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
1989 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1990 EVEX_CD8<64, CD8VF>, VEX_W;
1991 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
1992 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1993 EVEX_CD8<64, CD8VQ>, VEX_W;
1995 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
1996 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
1997 EVEX_CD8<32, CD8VF>;
1998 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
1999 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2000 EVEX_CD8<32, CD8VQ>;
2002 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2003 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2004 EVEX_CD8<64, CD8VF>, VEX_W;
2005 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2006 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2007 EVEX_CD8<64, CD8VQ>, VEX_W;
2009 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2010 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2011 EVEX_V512, EVEX_CD8<32, CD8VF>;
2012 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2013 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2014 EVEX_CD8<32, CD8VQ>;
2016 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2017 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2018 EVEX_CD8<64, CD8VF>, VEX_W;
2019 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2020 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2021 EVEX_CD8<64, CD8VQ>, VEX_W;
2023 //===-------------------------------------------------------------------===//
2024 // Variable Bit Shifts
2025 //===-------------------------------------------------------------------===//
2026 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2027 RegisterClass RC, ValueType vt,
2028 X86MemOperand x86memop, PatFrag mem_frag> {
2029 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2030 (ins RC:$src1, RC:$src2),
2031 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2033 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2035 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2036 (ins RC:$src1, x86memop:$src2),
2037 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2039 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2043 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2044 i512mem, memopv16i32>, EVEX_V512,
2045 EVEX_CD8<32, CD8VF>;
2046 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2047 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2048 EVEX_CD8<64, CD8VF>;
2049 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2050 i512mem, memopv16i32>, EVEX_V512,
2051 EVEX_CD8<32, CD8VF>;
2052 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2053 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2054 EVEX_CD8<64, CD8VF>;
2055 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2056 i512mem, memopv16i32>, EVEX_V512,
2057 EVEX_CD8<32, CD8VF>;
2058 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2059 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2060 EVEX_CD8<64, CD8VF>;
2062 //===----------------------------------------------------------------------===//
2063 // AVX-512 - MOVDDUP
2064 //===----------------------------------------------------------------------===//
2066 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2067 X86MemOperand x86memop, PatFrag memop_frag> {
2068 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2069 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2070 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2071 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2072 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2074 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2077 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2078 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2079 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2080 (VMOVDDUPZrm addr:$src)>;
2082 //===---------------------------------------------------------------------===//
2083 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2084 //===---------------------------------------------------------------------===//
2085 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2086 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2087 X86MemOperand x86memop> {
2088 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2089 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2090 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2092 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2093 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2094 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2097 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2098 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2099 EVEX_CD8<32, CD8VF>;
2100 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2101 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2102 EVEX_CD8<32, CD8VF>;
2104 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2105 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2106 (VMOVSHDUPZrm addr:$src)>;
2107 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2108 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2109 (VMOVSLDUPZrm addr:$src)>;
2111 //===----------------------------------------------------------------------===//
2112 // Move Low to High and High to Low packed FP Instructions
2113 //===----------------------------------------------------------------------===//
2114 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2115 (ins VR128X:$src1, VR128X:$src2),
2116 "vmovlhps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2117 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2118 IIC_SSE_MOV_LH>, EVEX_4V;
2119 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2120 (ins VR128X:$src1, VR128X:$src2),
2121 "vmovhlps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2122 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2123 IIC_SSE_MOV_LH>, EVEX_4V;
2125 let Predicates = [HasAVX512] in {
2127 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2128 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2129 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2130 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2133 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2134 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2137 //===----------------------------------------------------------------------===//
2138 // FMA - Fused Multiply Operations
2140 let Constraints = "$src1 = $dst" in {
2141 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2142 RegisterClass RC, X86MemOperand x86memop,
2143 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2144 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2145 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2146 (ins RC:$src1, RC:$src2, RC:$src3),
2147 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2148 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2151 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2152 (ins RC:$src1, RC:$src2, x86memop:$src3),
2153 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2154 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2155 (mem_frag addr:$src3))))]>;
2156 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2157 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2158 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2159 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2160 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2161 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2163 } // Constraints = "$src1 = $dst"
2165 let ExeDomain = SSEPackedSingle in {
2166 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2167 memopv16f32, f32mem, loadf32, "{1to16}",
2168 X86Fmadd, v16f32>, EVEX_V512,
2169 EVEX_CD8<32, CD8VF>;
2170 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2171 memopv16f32, f32mem, loadf32, "{1to16}",
2172 X86Fmsub, v16f32>, EVEX_V512,
2173 EVEX_CD8<32, CD8VF>;
2174 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2175 memopv16f32, f32mem, loadf32, "{1to16}",
2176 X86Fmaddsub, v16f32>,
2177 EVEX_V512, EVEX_CD8<32, CD8VF>;
2178 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2179 memopv16f32, f32mem, loadf32, "{1to16}",
2180 X86Fmsubadd, v16f32>,
2181 EVEX_V512, EVEX_CD8<32, CD8VF>;
2182 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2183 memopv16f32, f32mem, loadf32, "{1to16}",
2184 X86Fnmadd, v16f32>, EVEX_V512,
2185 EVEX_CD8<32, CD8VF>;
2186 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2187 memopv16f32, f32mem, loadf32, "{1to16}",
2188 X86Fnmsub, v16f32>, EVEX_V512,
2189 EVEX_CD8<32, CD8VF>;
2191 let ExeDomain = SSEPackedDouble in {
2192 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2193 memopv8f64, f64mem, loadf64, "{1to8}",
2194 X86Fmadd, v8f64>, EVEX_V512,
2195 VEX_W, EVEX_CD8<64, CD8VF>;
2196 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2197 memopv8f64, f64mem, loadf64, "{1to8}",
2198 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2199 EVEX_CD8<64, CD8VF>;
2200 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2201 memopv8f64, f64mem, loadf64, "{1to8}",
2202 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2203 EVEX_CD8<64, CD8VF>;
2204 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2205 memopv8f64, f64mem, loadf64, "{1to8}",
2206 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2207 EVEX_CD8<64, CD8VF>;
2208 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2209 memopv8f64, f64mem, loadf64, "{1to8}",
2210 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2211 EVEX_CD8<64, CD8VF>;
2212 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2213 memopv8f64, f64mem, loadf64, "{1to8}",
2214 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2215 EVEX_CD8<64, CD8VF>;
2218 let Constraints = "$src1 = $dst" in {
2219 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2220 RegisterClass RC, X86MemOperand x86memop,
2221 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2222 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2224 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2225 (ins RC:$src1, RC:$src3, x86memop:$src2),
2226 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2227 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2228 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2229 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2230 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2231 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2232 [(set RC:$dst, (OpNode RC:$src1,
2233 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2235 } // Constraints = "$src1 = $dst"
2238 let ExeDomain = SSEPackedSingle in {
2239 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2240 memopv16f32, f32mem, loadf32, "{1to16}",
2241 X86Fmadd, v16f32>, EVEX_V512,
2242 EVEX_CD8<32, CD8VF>;
2243 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2244 memopv16f32, f32mem, loadf32, "{1to16}",
2245 X86Fmsub, v16f32>, EVEX_V512,
2246 EVEX_CD8<32, CD8VF>;
2247 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2248 memopv16f32, f32mem, loadf32, "{1to16}",
2249 X86Fmaddsub, v16f32>,
2250 EVEX_V512, EVEX_CD8<32, CD8VF>;
2251 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2252 memopv16f32, f32mem, loadf32, "{1to16}",
2253 X86Fmsubadd, v16f32>,
2254 EVEX_V512, EVEX_CD8<32, CD8VF>;
2255 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2256 memopv16f32, f32mem, loadf32, "{1to16}",
2257 X86Fnmadd, v16f32>, EVEX_V512,
2258 EVEX_CD8<32, CD8VF>;
2259 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2260 memopv16f32, f32mem, loadf32, "{1to16}",
2261 X86Fnmsub, v16f32>, EVEX_V512,
2262 EVEX_CD8<32, CD8VF>;
2264 let ExeDomain = SSEPackedDouble in {
2265 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2266 memopv8f64, f64mem, loadf64, "{1to8}",
2267 X86Fmadd, v8f64>, EVEX_V512,
2268 VEX_W, EVEX_CD8<64, CD8VF>;
2269 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2270 memopv8f64, f64mem, loadf64, "{1to8}",
2271 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2272 EVEX_CD8<64, CD8VF>;
2273 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2274 memopv8f64, f64mem, loadf64, "{1to8}",
2275 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2276 EVEX_CD8<64, CD8VF>;
2277 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2278 memopv8f64, f64mem, loadf64, "{1to8}",
2279 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2280 EVEX_CD8<64, CD8VF>;
2281 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2282 memopv8f64, f64mem, loadf64, "{1to8}",
2283 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2284 EVEX_CD8<64, CD8VF>;
2285 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2286 memopv8f64, f64mem, loadf64, "{1to8}",
2287 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2288 EVEX_CD8<64, CD8VF>;
2292 let Constraints = "$src1 = $dst" in {
2293 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2294 RegisterClass RC, ValueType OpVT,
2295 X86MemOperand x86memop, Operand memop,
2297 let isCommutable = 1 in
2298 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2299 (ins RC:$src1, RC:$src2, RC:$src3),
2300 !strconcat(OpcodeStr,
2301 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2303 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2305 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2306 (ins RC:$src1, RC:$src2, f128mem:$src3),
2307 !strconcat(OpcodeStr,
2308 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2310 (OpVT (OpNode RC:$src2, RC:$src1,
2311 (mem_frag addr:$src3))))]>;
2314 } // Constraints = "$src1 = $dst"
2316 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss{z}", X86Fmadd, FR32X,
2317 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2318 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd{z}", X86Fmadd, FR64X,
2319 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2320 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss{z}", X86Fmsub, FR32X,
2321 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2322 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd{z}", X86Fmsub, FR64X,
2323 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2324 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss{z}", X86Fnmadd, FR32X,
2325 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2326 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd{z}", X86Fnmadd, FR64X,
2327 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2328 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss{z}", X86Fnmsub, FR32X,
2329 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2330 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd{z}", X86Fnmsub, FR64X,
2331 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2333 //===----------------------------------------------------------------------===//
2334 // AVX-512 Scalar convert from sign integer to float/double
2335 //===----------------------------------------------------------------------===//
2337 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2338 X86MemOperand x86memop, string asm> {
2339 let neverHasSideEffects = 1 in {
2340 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2341 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2344 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2345 (ins DstRC:$src1, x86memop:$src),
2346 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2348 } // neverHasSideEffects = 1
2350 let Predicates = [HasAVX512] in {
2351 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}{z}">,
2352 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2353 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}{z}">,
2354 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2355 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}{z}">,
2356 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2357 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}{z}">,
2358 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2360 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2361 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2362 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2363 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2364 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2365 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2366 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2367 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2369 def : Pat<(f32 (sint_to_fp GR32:$src)),
2370 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2371 def : Pat<(f32 (sint_to_fp GR64:$src)),
2372 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2373 def : Pat<(f64 (sint_to_fp GR32:$src)),
2374 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2375 def : Pat<(f64 (sint_to_fp GR64:$src)),
2376 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2378 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}{z}">,
2379 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2380 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}{z}">,
2381 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2382 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}{z}">,
2383 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2384 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}{z}">,
2385 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2387 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2388 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2389 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2390 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2391 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2392 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2393 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2394 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2396 def : Pat<(f32 (uint_to_fp GR32:$src)),
2397 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2398 def : Pat<(f32 (uint_to_fp GR64:$src)),
2399 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2400 def : Pat<(f64 (uint_to_fp GR32:$src)),
2401 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2402 def : Pat<(f64 (uint_to_fp GR64:$src)),
2403 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2406 //===----------------------------------------------------------------------===//
2407 // AVX-512 Scalar convert from float/double to integer
2408 //===----------------------------------------------------------------------===//
2409 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2410 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2412 let neverHasSideEffects = 1 in {
2413 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2414 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2415 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
2417 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2418 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
2419 } // neverHasSideEffects = 1
2421 let Predicates = [HasAVX512] in {
2422 // Convert float/double to signed/unsigned int 32/64
2423 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2424 ssmem, sse_load_f32, "cvtss2si{z}">,
2425 XS, EVEX_CD8<32, CD8VT1>;
2426 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2427 ssmem, sse_load_f32, "cvtss2si{z}">,
2428 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2429 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2430 ssmem, sse_load_f32, "cvtss2usi{z}">,
2431 XS, EVEX_CD8<32, CD8VT1>;
2432 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2433 int_x86_avx512_cvtss2usi64, ssmem,
2434 sse_load_f32, "cvtss2usi{z}">, XS, VEX_W,
2435 EVEX_CD8<32, CD8VT1>;
2436 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2437 sdmem, sse_load_f64, "cvtsd2si{z}">,
2438 XD, EVEX_CD8<64, CD8VT1>;
2439 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2440 sdmem, sse_load_f64, "cvtsd2si{z}">,
2441 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2442 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2443 sdmem, sse_load_f64, "cvtsd2usi{z}">,
2444 XD, EVEX_CD8<64, CD8VT1>;
2445 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2446 int_x86_avx512_cvtsd2usi64, sdmem,
2447 sse_load_f64, "cvtsd2usi{z}">, XD, VEX_W,
2448 EVEX_CD8<64, CD8VT1>;
2450 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2451 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}{z}",
2452 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2453 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2454 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}{z}",
2455 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2456 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2457 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}{z}",
2458 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2459 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2460 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}{z}",
2461 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2463 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2464 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}{z}",
2465 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2466 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2467 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}{z}",
2468 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2469 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2470 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}{z}",
2471 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2472 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2473 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}{z}",
2474 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2476 // Convert float/double to signed/unsigned int 32/64 with truncation
2477 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2478 ssmem, sse_load_f32, "cvttss2si{z}">,
2479 XS, EVEX_CD8<32, CD8VT1>;
2480 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2481 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2482 "cvttss2si{z}">, XS, VEX_W,
2483 EVEX_CD8<32, CD8VT1>;
2484 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2485 sdmem, sse_load_f64, "cvttsd2si{z}">, XD,
2486 EVEX_CD8<64, CD8VT1>;
2487 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2488 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2489 "cvttsd2si{z}">, XD, VEX_W,
2490 EVEX_CD8<64, CD8VT1>;
2491 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2492 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2493 "cvttss2si{z}">, XS, EVEX_CD8<32, CD8VT1>;
2494 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2495 int_x86_avx512_cvttss2usi64, ssmem,
2496 sse_load_f32, "cvttss2usi{z}">, XS, VEX_W,
2497 EVEX_CD8<32, CD8VT1>;
2498 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2499 int_x86_avx512_cvttsd2usi,
2500 sdmem, sse_load_f64, "cvttsd2usi{z}">, XD,
2501 EVEX_CD8<64, CD8VT1>;
2502 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2503 int_x86_avx512_cvttsd2usi64, sdmem,
2504 sse_load_f64, "cvttsd2usi{z}">, XD, VEX_W,
2505 EVEX_CD8<64, CD8VT1>;
2508 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2509 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2511 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2512 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2513 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2514 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2515 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2516 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2519 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2520 loadf32, "cvttss2si{z}">, XS,
2521 EVEX_CD8<32, CD8VT1>;
2522 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2523 loadf32, "cvttss2usi{z}">, XS,
2524 EVEX_CD8<32, CD8VT1>;
2525 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2526 loadf32, "cvttss2si{z}">, XS, VEX_W,
2527 EVEX_CD8<32, CD8VT1>;
2528 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2529 loadf32, "cvttss2usi{z}">, XS, VEX_W,
2530 EVEX_CD8<32, CD8VT1>;
2531 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2532 loadf64, "cvttsd2si{z}">, XD,
2533 EVEX_CD8<64, CD8VT1>;
2534 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2535 loadf64, "cvttsd2usi{z}">, XD,
2536 EVEX_CD8<64, CD8VT1>;
2537 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2538 loadf64, "cvttsd2si{z}">, XD, VEX_W,
2539 EVEX_CD8<64, CD8VT1>;
2540 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2541 loadf64, "cvttsd2usi{z}">, XD, VEX_W,
2542 EVEX_CD8<64, CD8VT1>;
2543 //===----------------------------------------------------------------------===//
2544 // AVX-512 Convert form float to double and back
2545 //===----------------------------------------------------------------------===//
2546 let neverHasSideEffects = 1 in {
2547 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2548 (ins FR32X:$src1, FR32X:$src2),
2549 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2550 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2552 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2553 (ins FR32X:$src1, f32mem:$src2),
2554 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2555 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2556 EVEX_CD8<32, CD8VT1>;
2558 // Convert scalar double to scalar single
2559 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2560 (ins FR64X:$src1, FR64X:$src2),
2561 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2562 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2564 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2565 (ins FR64X:$src1, f64mem:$src2),
2566 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2567 []>, EVEX_4V, VEX_LIG, VEX_W,
2568 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2571 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2572 Requires<[HasAVX512]>;
2573 def : Pat<(fextend (loadf32 addr:$src)),
2574 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2576 def : Pat<(extloadf32 addr:$src),
2577 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2578 Requires<[HasAVX512, OptForSize]>;
2580 def : Pat<(extloadf32 addr:$src),
2581 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2582 Requires<[HasAVX512, OptForSpeed]>;
2584 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2585 Requires<[HasAVX512]>;
2587 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2588 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2589 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2591 let neverHasSideEffects = 1 in {
2592 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2593 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2595 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2597 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2598 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2600 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2601 } // neverHasSideEffects = 1
2604 defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2605 memopv8f64, f512mem, v8f32, v8f64,
2606 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2607 EVEX_CD8<64, CD8VF>;
2609 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2610 memopv4f64, f256mem, v8f64, v8f32,
2611 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2612 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2613 (VCVTPS2PDZrm addr:$src)>;
2615 //===----------------------------------------------------------------------===//
2616 // AVX-512 Vector convert from sign integer to float/double
2617 //===----------------------------------------------------------------------===//
2619 defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2620 memopv8i64, i512mem, v16f32, v16i32,
2621 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2623 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2624 memopv4i64, i256mem, v8f64, v8i32,
2625 SSEPackedDouble>, EVEX_V512, XS,
2626 EVEX_CD8<32, CD8VH>;
2628 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2629 memopv16f32, f512mem, v16i32, v16f32,
2630 SSEPackedSingle>, EVEX_V512, XS,
2631 EVEX_CD8<32, CD8VF>;
2633 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2634 memopv8f64, f512mem, v8i32, v8f64,
2635 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2636 EVEX_CD8<64, CD8VF>;
2638 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2639 memopv16f32, f512mem, v16i32, v16f32,
2640 SSEPackedSingle>, EVEX_V512,
2641 EVEX_CD8<32, CD8VF>;
2643 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2644 memopv8f64, f512mem, v8i32, v8f64,
2645 SSEPackedDouble>, EVEX_V512, VEX_W,
2646 EVEX_CD8<64, CD8VF>;
2648 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2649 memopv4i64, f256mem, v8f64, v8i32,
2650 SSEPackedDouble>, EVEX_V512, XS,
2651 EVEX_CD8<32, CD8VH>;
2653 defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2654 memopv16i32, f512mem, v16f32, v16i32,
2655 SSEPackedSingle>, EVEX_V512, XD,
2656 EVEX_CD8<32, CD8VF>;
2658 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2659 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2660 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2663 def : Pat<(int_x86_avx512_cvtdq2_ps_512 VR512:$src),
2664 (VCVTDQ2PSZrr VR512:$src)>;
2665 def : Pat<(int_x86_avx512_cvtdq2_ps_512 (bitconvert (memopv8i64 addr:$src))),
2666 (VCVTDQ2PSZrm addr:$src)>;
2668 def VCVTPS2DQZrr : AVX512BI<0x5B, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2669 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2671 (int_x86_avx512_cvt_ps2dq_512 VR512:$src))],
2672 IIC_SSE_CVT_PS_RR>, EVEX, EVEX_V512;
2673 def VCVTPS2DQZrm : AVX512BI<0x5B, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2674 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2676 (int_x86_avx512_cvt_ps2dq_512 (memopv16f32 addr:$src)))],
2677 IIC_SSE_CVT_PS_RM>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2680 let Predicates = [HasAVX512] in {
2681 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2682 (VCVTPD2PSZrm addr:$src)>;
2683 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2684 (VCVTPS2PDZrm addr:$src)>;
2687 //===----------------------------------------------------------------------===//
2688 // Half precision conversion instructions
2689 //===----------------------------------------------------------------------===//
2690 multiclass avx512_f16c_ph2ps<RegisterClass destRC, RegisterClass srcRC,
2691 X86MemOperand x86memop, Intrinsic Int> {
2692 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
2693 "vcvtph2ps\t{$src, $dst|$dst, $src}",
2694 [(set destRC:$dst, (Int srcRC:$src))]>, EVEX;
2695 let neverHasSideEffects = 1, mayLoad = 1 in
2696 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
2697 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
2700 multiclass avx512_f16c_ps2ph<RegisterClass destRC, RegisterClass srcRC,
2701 X86MemOperand x86memop, Intrinsic Int> {
2702 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
2703 (ins srcRC:$src1, i32i8imm:$src2),
2704 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2705 [(set destRC:$dst, (Int srcRC:$src1, imm:$src2))]>, EVEX;
2706 let neverHasSideEffects = 1, mayStore = 1 in
2707 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
2708 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
2709 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
2712 defm VCVTPH2PSZ : avx512_f16c_ph2ps<VR512, VR256X, f256mem,
2713 int_x86_avx512_vcvtph2ps_512>, EVEX_V512,
2714 EVEX_CD8<32, CD8VH>;
2715 defm VCVTPS2PHZ : avx512_f16c_ps2ph<VR256X, VR512, f256mem,
2716 int_x86_avx512_vcvtps2ph_512>, EVEX_V512,
2717 EVEX_CD8<32, CD8VH>;
2719 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2720 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2721 "ucomiss{z}">, TB, EVEX, VEX_LIG,
2722 EVEX_CD8<32, CD8VT1>;
2723 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
2724 "ucomisd{z}">, TB, OpSize, EVEX,
2725 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2726 let Pattern = []<dag> in {
2727 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
2728 "comiss{z}">, TB, EVEX, VEX_LIG,
2729 EVEX_CD8<32, CD8VT1>;
2730 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
2731 "comisd{z}">, TB, OpSize, EVEX,
2732 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2734 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
2735 load, "ucomiss">, TB, EVEX, VEX_LIG,
2736 EVEX_CD8<32, CD8VT1>;
2737 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
2738 load, "ucomisd">, TB, OpSize, EVEX,
2739 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2741 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
2742 load, "comiss">, TB, EVEX, VEX_LIG,
2743 EVEX_CD8<32, CD8VT1>;
2744 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
2745 load, "comisd">, TB, OpSize, EVEX,
2746 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2749 /// avx512_unop_p - AVX-512 unops in packed form.
2750 multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2751 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2752 !strconcat(OpcodeStr,
2753 "ps\t{$src, $dst|$dst, $src}"),
2754 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
2756 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
2757 !strconcat(OpcodeStr,
2758 "ps\t{$src, $dst|$dst, $src}"),
2759 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2760 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2761 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2762 !strconcat(OpcodeStr,
2763 "pd\t{$src, $dst|$dst, $src}"),
2764 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
2765 EVEX, EVEX_V512, VEX_W;
2766 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2767 !strconcat(OpcodeStr,
2768 "pd\t{$src, $dst|$dst, $src}"),
2769 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2770 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2773 /// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
2774 multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2775 Intrinsic V16F32Int, Intrinsic V8F64Int> {
2776 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2777 !strconcat(OpcodeStr,
2778 "ps\t{$src, $dst|$dst, $src}"),
2779 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2781 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2782 !strconcat(OpcodeStr,
2783 "ps\t{$src, $dst|$dst, $src}"),
2785 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2786 EVEX_V512, EVEX_CD8<32, CD8VF>;
2787 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2788 !strconcat(OpcodeStr,
2789 "pd\t{$src, $dst|$dst, $src}"),
2790 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2791 EVEX, EVEX_V512, VEX_W;
2792 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2793 !strconcat(OpcodeStr,
2794 "pd\t{$src, $dst|$dst, $src}"),
2796 (V8F64Int (memopv8f64 addr:$src)))]>,
2797 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2800 /// avx512_fp_unop_s - AVX-512 unops in scalar form.
2801 multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr> {
2802 let hasSideEffects = 0 in {
2803 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
2804 (ins FR32X:$src1, FR32X:$src2),
2805 !strconcat(OpcodeStr,
2806 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2808 let mayLoad = 1 in {
2809 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
2810 (ins FR32X:$src1, f32mem:$src2),
2811 !strconcat(OpcodeStr,
2812 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2813 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2814 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2815 (ins VR128X:$src1, ssmem:$src2),
2816 !strconcat(OpcodeStr,
2817 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2818 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2820 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
2821 (ins FR64X:$src1, FR64X:$src2),
2822 !strconcat(OpcodeStr,
2823 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2825 let mayLoad = 1 in {
2826 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
2827 (ins FR64X:$src1, f64mem:$src2),
2828 !strconcat(OpcodeStr,
2829 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2830 EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2831 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2832 (ins VR128X:$src1, sdmem:$src2),
2833 !strconcat(OpcodeStr,
2834 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2835 []>, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2840 defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14">,
2841 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
2842 avx512_fp_unop_p_int<0x4C, "vrcp14",
2843 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
2845 defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14">,
2846 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
2847 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
2848 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
2850 def : Pat<(int_x86_avx512_rsqrt14_ss VR128X:$src),
2851 (COPY_TO_REGCLASS (VRSQRT14SSZr (f32 (IMPLICIT_DEF)),
2852 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2854 def : Pat<(int_x86_avx512_rsqrt14_ss sse_load_f32:$src),
2855 (VRSQRT14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2857 def : Pat<(int_x86_avx512_rcp14_ss VR128X:$src),
2858 (COPY_TO_REGCLASS (VRCP14SSZr (f32 (IMPLICIT_DEF)),
2859 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2861 def : Pat<(int_x86_avx512_rcp14_ss sse_load_f32:$src),
2862 (VRCP14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2864 let AddedComplexity = 20, Predicates = [HasERI] in {
2865 defm VRCP28 : avx512_fp_unop_s<0xCB, "vrcp28">,
2866 avx512_fp_unop_p<0xCA, "vrcp28", X86frcp>,
2867 avx512_fp_unop_p_int<0xCA, "vrcp28",
2868 int_x86_avx512_rcp28_ps_512, int_x86_avx512_rcp28_pd_512>;
2870 defm VRSQRT28 : avx512_fp_unop_s<0xCD, "vrsqrt28">,
2871 avx512_fp_unop_p<0xCC, "vrsqrt28", X86frsqrt>,
2872 avx512_fp_unop_p_int<0xCC, "vrsqrt28",
2873 int_x86_avx512_rsqrt28_ps_512, int_x86_avx512_rsqrt28_pd_512>;
2876 let Predicates = [HasERI] in {
2877 def : Pat<(int_x86_avx512_rsqrt28_ss VR128X:$src),
2878 (COPY_TO_REGCLASS (VRSQRT28SSZr (f32 (IMPLICIT_DEF)),
2879 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2881 def : Pat<(int_x86_avx512_rsqrt28_ss sse_load_f32:$src),
2882 (VRSQRT28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2884 def : Pat<(int_x86_avx512_rcp28_ss VR128X:$src),
2885 (COPY_TO_REGCLASS (VRCP28SSZr (f32 (IMPLICIT_DEF)),
2886 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2888 def : Pat<(int_x86_avx512_rcp28_ss sse_load_f32:$src),
2889 (VRCP28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2891 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2892 Intrinsic V16F32Int, Intrinsic V8F64Int,
2893 OpndItins itins_s, OpndItins itins_d> {
2894 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2895 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2896 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
2900 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2901 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2903 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
2904 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2906 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2907 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2908 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
2912 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2913 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2914 [(set VR512:$dst, (OpNode
2915 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
2916 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
2918 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2919 !strconcat(OpcodeStr,
2920 "ps\t{$src, $dst|$dst, $src}"),
2921 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2923 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2924 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2926 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2927 EVEX_V512, EVEX_CD8<32, CD8VF>;
2928 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2929 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2930 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2931 EVEX, EVEX_V512, VEX_W;
2932 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2933 !strconcat(OpcodeStr,
2934 "pd\t{$src, $dst|$dst, $src}"),
2935 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
2936 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2939 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
2940 Intrinsic F32Int, Intrinsic F64Int,
2941 OpndItins itins_s, OpndItins itins_d> {
2942 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
2943 (ins FR32X:$src1, FR32X:$src2),
2944 !strconcat(OpcodeStr,
2945 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2946 [], itins_s.rr>, XS, EVEX_4V;
2947 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2948 (ins VR128X:$src1, VR128X:$src2),
2949 !strconcat(OpcodeStr,
2950 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2952 (F32Int VR128X:$src1, VR128X:$src2))],
2953 itins_s.rr>, XS, EVEX_4V;
2954 let mayLoad = 1 in {
2955 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
2956 (ins FR32X:$src1, f32mem:$src2),
2957 !strconcat(OpcodeStr,
2958 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2959 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2960 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2961 (ins VR128X:$src1, ssmem:$src2),
2962 !strconcat(OpcodeStr,
2963 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2965 (F32Int VR128X:$src1, sse_load_f32:$src2))],
2966 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2968 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
2969 (ins FR64X:$src1, FR64X:$src2),
2970 !strconcat(OpcodeStr,
2971 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2973 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2974 (ins VR128X:$src1, VR128X:$src2),
2975 !strconcat(OpcodeStr,
2976 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2978 (F64Int VR128X:$src1, VR128X:$src2))],
2979 itins_s.rr>, XD, EVEX_4V, VEX_W;
2980 let mayLoad = 1 in {
2981 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
2982 (ins FR64X:$src1, f64mem:$src2),
2983 !strconcat(OpcodeStr,
2984 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2985 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2986 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2987 (ins VR128X:$src1, sdmem:$src2),
2988 !strconcat(OpcodeStr,
2989 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2991 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
2992 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2997 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
2998 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
2999 SSE_SQRTSS, SSE_SQRTSD>,
3000 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3001 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3002 SSE_SQRTPS, SSE_SQRTPD>;
3004 let Predicates = [HasAVX512] in {
3005 def : Pat<(f32 (fsqrt FR32X:$src)),
3006 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3007 def : Pat<(f32 (fsqrt (load addr:$src))),
3008 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3009 Requires<[OptForSize]>;
3010 def : Pat<(f64 (fsqrt FR64X:$src)),
3011 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3012 def : Pat<(f64 (fsqrt (load addr:$src))),
3013 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3014 Requires<[OptForSize]>;
3016 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3017 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3018 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3019 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3020 Requires<[OptForSize]>;
3022 def : Pat<(f32 (X86frcp FR32X:$src)),
3023 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3024 def : Pat<(f32 (X86frcp (load addr:$src))),
3025 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3026 Requires<[OptForSize]>;
3028 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3029 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3030 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3032 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3033 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3035 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3036 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3037 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3039 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3040 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3044 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3045 X86MemOperand x86memop, RegisterClass RC,
3046 PatFrag mem_frag32, PatFrag mem_frag64,
3047 Intrinsic V4F32Int, Intrinsic V2F64Int,
3049 let ExeDomain = SSEPackedSingle in {
3050 // Intrinsic operation, reg.
3051 // Vector intrinsic operation, reg
3052 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3053 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3054 !strconcat(OpcodeStr,
3055 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3056 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3058 // Vector intrinsic operation, mem
3059 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3060 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3061 !strconcat(OpcodeStr,
3062 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3064 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3065 EVEX_CD8<32, VForm>;
3066 } // ExeDomain = SSEPackedSingle
3068 let ExeDomain = SSEPackedDouble in {
3069 // Vector intrinsic operation, reg
3070 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3071 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3072 !strconcat(OpcodeStr,
3073 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3074 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3076 // Vector intrinsic operation, mem
3077 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3078 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3079 !strconcat(OpcodeStr,
3080 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3082 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3083 EVEX_CD8<64, VForm>;
3084 } // ExeDomain = SSEPackedDouble
3087 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3091 let ExeDomain = GenericDomain in {
3093 let hasSideEffects = 0 in
3094 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3095 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3096 !strconcat(OpcodeStr,
3097 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3100 // Intrinsic operation, reg.
3101 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3102 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3103 !strconcat(OpcodeStr,
3104 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3105 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3107 // Intrinsic operation, mem.
3108 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3109 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3110 !strconcat(OpcodeStr,
3111 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3112 [(set VR128X:$dst, (F32Int VR128X:$src1,
3113 sse_load_f32:$src2, imm:$src3))]>,
3114 EVEX_CD8<32, CD8VT1>;
3117 let hasSideEffects = 0 in
3118 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3119 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3120 !strconcat(OpcodeStr,
3121 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3124 // Intrinsic operation, reg.
3125 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3126 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3127 !strconcat(OpcodeStr,
3128 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3129 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3132 // Intrinsic operation, mem.
3133 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3134 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3135 !strconcat(OpcodeStr,
3136 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3138 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3139 VEX_W, EVEX_CD8<64, CD8VT1>;
3140 } // ExeDomain = GenericDomain
3143 let Predicates = [HasAVX512] in {
3144 defm VRNDSCALE : avx512_fp_binop_rm<0x0A, 0x0B, "vrndscale",
3145 int_x86_avx512_rndscale_ss,
3146 int_x86_avx512_rndscale_sd>, EVEX_4V;
3148 defm VRNDSCALEZ : avx512_fp_unop_rm<0x08, 0x09, "vrndscale", f256mem, VR512,
3149 memopv16f32, memopv8f64,
3150 int_x86_avx512_rndscale_ps_512,
3151 int_x86_avx512_rndscale_pd_512, CD8VF>,
3155 def : Pat<(ffloor FR32X:$src),
3156 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3157 def : Pat<(f64 (ffloor FR64X:$src)),
3158 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3159 def : Pat<(f32 (fnearbyint FR32X:$src)),
3160 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3161 def : Pat<(f64 (fnearbyint FR64X:$src)),
3162 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3163 def : Pat<(f32 (fceil FR32X:$src)),
3164 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3165 def : Pat<(f64 (fceil FR64X:$src)),
3166 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3167 def : Pat<(f32 (frint FR32X:$src)),
3168 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3169 def : Pat<(f64 (frint FR64X:$src)),
3170 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3171 def : Pat<(f32 (ftrunc FR32X:$src)),
3172 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3173 def : Pat<(f64 (ftrunc FR64X:$src)),
3174 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3176 def : Pat<(v16f32 (ffloor VR512:$src)),
3177 (VRNDSCALEZPSr VR512:$src, (i32 0x1))>;
3178 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3179 (VRNDSCALEZPSr VR512:$src, (i32 0xC))>;
3180 def : Pat<(v16f32 (fceil VR512:$src)),
3181 (VRNDSCALEZPSr VR512:$src, (i32 0x2))>;
3182 def : Pat<(v16f32 (frint VR512:$src)),
3183 (VRNDSCALEZPSr VR512:$src, (i32 0x4))>;
3184 def : Pat<(v16f32 (ftrunc VR512:$src)),
3185 (VRNDSCALEZPSr VR512:$src, (i32 0x3))>;
3187 def : Pat<(v8f64 (ffloor VR512:$src)),
3188 (VRNDSCALEZPDr VR512:$src, (i32 0x1))>;
3189 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3190 (VRNDSCALEZPDr VR512:$src, (i32 0xC))>;
3191 def : Pat<(v8f64 (fceil VR512:$src)),
3192 (VRNDSCALEZPDr VR512:$src, (i32 0x2))>;
3193 def : Pat<(v8f64 (frint VR512:$src)),
3194 (VRNDSCALEZPDr VR512:$src, (i32 0x4))>;
3195 def : Pat<(v8f64 (ftrunc VR512:$src)),
3196 (VRNDSCALEZPDr VR512:$src, (i32 0x3))>;
3198 //-------------------------------------------------
3199 // Integer truncate and extend operations
3200 //-------------------------------------------------
3202 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3203 RegisterClass dstRC, RegisterClass srcRC,
3204 RegisterClass KRC, X86MemOperand x86memop> {
3205 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3207 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3210 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3211 (ins KRC:$mask, srcRC:$src),
3212 !strconcat(OpcodeStr,
3213 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3216 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3217 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3220 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3221 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3222 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3223 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3224 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3225 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3226 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3227 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3228 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3229 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3230 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3231 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3232 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3233 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3234 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3235 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3236 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3237 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3238 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3239 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3240 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3241 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3242 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3243 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3244 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3245 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3246 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3247 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3248 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3249 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3251 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3252 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3253 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3254 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3255 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3257 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3258 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3259 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3260 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3261 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3262 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3263 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3264 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3267 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3268 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3269 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3271 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3273 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3274 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3275 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3276 (ins x86memop:$src),
3277 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3279 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3283 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3284 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3286 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3287 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3289 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3290 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3291 EVEX_CD8<16, CD8VH>;
3292 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3293 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3294 EVEX_CD8<16, CD8VQ>;
3295 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3296 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3297 EVEX_CD8<32, CD8VH>;
3299 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3300 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3302 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3303 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3305 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3306 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3307 EVEX_CD8<16, CD8VH>;
3308 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3309 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3310 EVEX_CD8<16, CD8VQ>;
3311 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3312 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3313 EVEX_CD8<32, CD8VH>;
3315 //===----------------------------------------------------------------------===//
3316 // GATHER - SCATTER Operations
3318 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3319 RegisterClass RC, X86MemOperand memop> {
3321 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3322 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3323 (ins RC:$src1, KRC:$mask, memop:$src2),
3324 !strconcat(OpcodeStr,
3325 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3328 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3329 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3330 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3331 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3333 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3334 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3335 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3336 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3338 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3339 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3340 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3341 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3343 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3344 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3345 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3346 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3348 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3349 RegisterClass RC, X86MemOperand memop> {
3350 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3351 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3352 (ins memop:$dst, KRC:$mask, RC:$src2),
3353 !strconcat(OpcodeStr,
3354 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3358 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3359 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3360 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3361 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3363 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3364 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3365 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3366 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3368 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3369 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3370 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3371 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3373 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3374 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3375 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3376 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3378 //===----------------------------------------------------------------------===//
3379 // VSHUFPS - VSHUFPD Operations
3381 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3382 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3384 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3385 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3386 !strconcat(OpcodeStr,
3387 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3388 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3389 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3390 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3391 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3392 (ins RC:$src1, RC:$src2, i8imm:$src3),
3393 !strconcat(OpcodeStr,
3394 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3395 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3396 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3397 EVEX_4V, Sched<[WriteShuffle]>;
3400 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3401 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3402 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3403 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3405 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3406 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3407 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3408 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3409 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3411 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3412 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3413 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3414 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3415 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3417 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3418 X86MemOperand x86memop> {
3419 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3420 (ins RC:$src1, RC:$src2, i8imm:$src3),
3421 !strconcat(OpcodeStr,
3422 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3425 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3426 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3427 !strconcat(OpcodeStr,
3428 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3431 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3432 EVEX_V512, EVEX_CD8<32, CD8VF>;
3433 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3434 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3436 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3437 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3438 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3439 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3440 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3441 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3442 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3443 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3445 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3446 X86MemOperand x86memop> {
3447 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3448 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3450 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3451 (ins x86memop:$src),
3452 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3456 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3457 EVEX_CD8<32, CD8VF>;
3458 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3459 EVEX_CD8<64, CD8VF>;
3461 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3462 RegisterClass RC, RegisterClass KRC, PatFrag memop_frag,
3463 X86MemOperand x86memop, PatFrag scalar_mfrag,
3464 X86MemOperand x86scalar_mop, string BrdcstStr,
3465 Intrinsic Int, Intrinsic maskInt, Intrinsic maskzInt> {
3466 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3468 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
3469 [(set RC:$dst, (Int RC:$src))]>, EVEX;
3470 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3471 (ins x86memop:$src),
3472 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
3473 [(set RC:$dst, (Int (memop_frag addr:$src)))]>, EVEX;
3474 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3475 (ins x86scalar_mop:$src),
3476 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3477 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3479 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3480 (ins KRC:$mask, RC:$src),
3481 !strconcat(OpcodeStr,
3482 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3483 [(set RC:$dst, (maskzInt KRC:$mask, RC:$src))]>, EVEX, EVEX_KZ;
3484 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3485 (ins KRC:$mask, x86memop:$src),
3486 !strconcat(OpcodeStr,
3487 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3488 [(set RC:$dst, (maskzInt KRC:$mask, (memop_frag addr:$src)))]>,
3490 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3491 (ins KRC:$mask, x86scalar_mop:$src),
3492 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3493 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3495 []>, EVEX, EVEX_KZ, EVEX_B;
3497 let Constraints = "$src1 = $dst" in {
3498 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3499 (ins RC:$src1, KRC:$mask, RC:$src2),
3500 !strconcat(OpcodeStr,
3501 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3502 [(set RC:$dst, (maskInt RC:$src1, KRC:$mask, RC:$src2))]>, EVEX, EVEX_K;
3503 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3504 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3505 !strconcat(OpcodeStr,
3506 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3507 [(set RC:$dst, (maskInt RC:$src1, KRC:$mask, (memop_frag addr:$src2)))]>, EVEX, EVEX_K;
3508 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3509 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3510 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3511 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
3512 []>, EVEX, EVEX_K, EVEX_B;
3516 let Predicates = [HasCDI] in {
3517 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
3518 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
3519 int_x86_avx512_conflict_d_512,
3520 int_x86_avx512_conflict_d_mask_512,
3521 int_x86_avx512_conflict_d_maskz_512>,
3522 EVEX_V512, EVEX_CD8<32, CD8VF>;
3524 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
3525 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
3526 int_x86_avx512_conflict_q_512,
3527 int_x86_avx512_conflict_q_mask_512,
3528 int_x86_avx512_conflict_q_maskz_512>,
3529 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;