1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def i32x_info : X86VectorVTInfo<1, i32, GR32, "si">;
149 def i64x_info : X86VectorVTInfo<1, i64, GR64, "sq">;
150 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
151 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
153 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
154 X86VectorVTInfo i128> {
155 X86VectorVTInfo info512 = i512;
156 X86VectorVTInfo info256 = i256;
157 X86VectorVTInfo info128 = i128;
160 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
162 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
164 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
166 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
168 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
170 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
173 // This multiclass generates the masking variants from the non-masking
174 // variant. It only provides the assembly pieces for the masking variants.
175 // It assumes custom ISel patterns for masking which can be provided as
176 // template arguments.
177 multiclass AVX512_maskable_custom<bits<8> O, Format F,
179 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
181 string AttSrcAsm, string IntelSrcAsm,
183 list<dag> MaskingPattern,
184 list<dag> ZeroMaskingPattern,
185 string MaskingConstraint = "",
186 InstrItinClass itin = NoItinerary,
187 bit IsCommutable = 0> {
188 let isCommutable = IsCommutable in
189 def NAME: AVX512<O, F, Outs, Ins,
190 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
191 "$dst , "#IntelSrcAsm#"}",
194 // Prefer over VMOV*rrk Pat<>
195 let AddedComplexity = 20 in
196 def NAME#k: AVX512<O, F, Outs, MaskingIns,
197 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
198 "$dst {${mask}}, "#IntelSrcAsm#"}",
199 MaskingPattern, itin>,
201 // In case of the 3src subclass this is overridden with a let.
202 string Constraints = MaskingConstraint;
204 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
205 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
206 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
207 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
214 // Common base class of AVX512_maskable and AVX512_maskable_3src.
215 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
217 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
219 string AttSrcAsm, string IntelSrcAsm,
220 dag RHS, dag MaskingRHS,
221 SDNode Select = vselect,
222 string MaskingConstraint = "",
223 InstrItinClass itin = NoItinerary,
224 bit IsCommutable = 0> :
225 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
226 AttSrcAsm, IntelSrcAsm,
227 [(set _.RC:$dst, RHS)],
228 [(set _.RC:$dst, MaskingRHS)],
230 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
231 MaskingConstraint, NoItinerary, IsCommutable>;
233 // This multiclass generates the unconditional/non-masking, the masking and
234 // the zero-masking variant of the vector instruction. In the masking case, the
235 // perserved vector elements come from a new dummy input operand tied to $dst.
236 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
237 dag Outs, dag Ins, string OpcodeStr,
238 string AttSrcAsm, string IntelSrcAsm,
240 InstrItinClass itin = NoItinerary,
241 bit IsCommutable = 0> :
242 AVX512_maskable_common<O, F, _, Outs, Ins,
243 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
244 !con((ins _.KRCWM:$mask), Ins),
245 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
246 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
247 "$src0 = $dst", itin, IsCommutable>;
249 // This multiclass generates the unconditional/non-masking, the masking and
250 // the zero-masking variant of the scalar instruction.
251 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
252 dag Outs, dag Ins, string OpcodeStr,
253 string AttSrcAsm, string IntelSrcAsm,
255 InstrItinClass itin = NoItinerary,
256 bit IsCommutable = 0> :
257 AVX512_maskable_common<O, F, _, Outs, Ins,
258 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
259 !con((ins _.KRCWM:$mask), Ins),
260 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
261 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
262 "$src0 = $dst", itin, IsCommutable>;
264 // Similar to AVX512_maskable but in this case one of the source operands
265 // ($src1) is already tied to $dst so we just use that for the preserved
266 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
268 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
269 dag Outs, dag NonTiedIns, string OpcodeStr,
270 string AttSrcAsm, string IntelSrcAsm,
272 AVX512_maskable_common<O, F, _, Outs,
273 !con((ins _.RC:$src1), NonTiedIns),
274 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
275 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
276 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
277 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
279 // Similar to AVX512_maskable_3rc but in this case the input VT for the tied
280 // operand differs from the output VT. This requires a bitconvert on
281 // the preserved vector going into the vselect.
282 multiclass AVX512_maskable_3src_cast<bits<8> O, Format F, X86VectorVTInfo OutVT,
283 X86VectorVTInfo InVT,
284 dag Outs, dag NonTiedIns, string OpcodeStr,
285 string AttSrcAsm, string IntelSrcAsm,
287 AVX512_maskable_common<O, F, OutVT, Outs,
288 !con((ins InVT.RC:$src1), NonTiedIns),
289 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
290 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
291 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
292 (vselect InVT.KRCWM:$mask, RHS,
293 (bitconvert InVT.RC:$src1))>;
295 multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
296 dag Outs, dag NonTiedIns, string OpcodeStr,
297 string AttSrcAsm, string IntelSrcAsm,
299 AVX512_maskable_common<O, F, _, Outs,
300 !con((ins _.RC:$src1), NonTiedIns),
301 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
302 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
303 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
304 (X86select _.KRCWM:$mask, RHS, _.RC:$src1)>;
306 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
309 string AttSrcAsm, string IntelSrcAsm,
311 AVX512_maskable_custom<O, F, Outs, Ins,
312 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
313 !con((ins _.KRCWM:$mask), Ins),
314 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
318 // Instruction with mask that puts result in mask register,
319 // like "compare" and "vptest"
320 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
322 dag Ins, dag MaskingIns,
324 string AttSrcAsm, string IntelSrcAsm,
326 list<dag> MaskingPattern,
328 InstrItinClass itin = NoItinerary> {
329 def NAME: AVX512<O, F, Outs, Ins,
330 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
331 "$dst "#Round#", "#IntelSrcAsm#"}",
334 def NAME#k: AVX512<O, F, Outs, MaskingIns,
335 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
336 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
337 MaskingPattern, itin>, EVEX_K;
340 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
342 dag Ins, dag MaskingIns,
344 string AttSrcAsm, string IntelSrcAsm,
345 dag RHS, dag MaskingRHS,
347 InstrItinClass itin = NoItinerary> :
348 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
349 AttSrcAsm, IntelSrcAsm,
350 [(set _.KRC:$dst, RHS)],
351 [(set _.KRC:$dst, MaskingRHS)],
354 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
355 dag Outs, dag Ins, string OpcodeStr,
356 string AttSrcAsm, string IntelSrcAsm,
357 dag RHS, string Round = "",
358 InstrItinClass itin = NoItinerary> :
359 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
360 !con((ins _.KRCWM:$mask), Ins),
361 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
362 (and _.KRCWM:$mask, RHS),
365 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
366 dag Outs, dag Ins, string OpcodeStr,
367 string AttSrcAsm, string IntelSrcAsm> :
368 AVX512_maskable_custom_cmp<O, F, Outs,
369 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
370 AttSrcAsm, IntelSrcAsm,
371 [],[],"", NoItinerary>;
373 // Bitcasts between 512-bit vector types. Return the original type since
374 // no instruction is needed for the conversion
375 let Predicates = [HasAVX512] in {
376 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
377 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
378 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
379 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
380 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
381 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
382 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
383 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
384 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
385 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
386 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
387 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
388 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
389 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
390 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
391 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
392 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
393 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
394 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
395 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
396 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
397 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
398 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
399 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
400 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
401 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
402 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
403 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
404 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
405 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
406 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
408 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
409 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
410 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
411 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
412 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
413 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
414 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
415 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
416 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
417 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
418 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
419 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
420 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
421 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
422 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
423 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
424 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
425 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
426 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
427 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
428 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
429 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
430 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
431 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
432 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
433 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
434 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
435 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
436 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
437 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
439 // Bitcasts between 256-bit vector types. Return the original type since
440 // no instruction is needed for the conversion
441 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
442 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
443 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
444 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
445 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
446 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
447 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
448 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
449 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
450 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
451 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
452 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
453 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
454 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
455 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
456 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
457 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
458 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
459 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
460 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
461 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
462 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
463 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
464 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
465 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
466 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
467 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
468 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
469 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
470 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
474 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
477 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
478 isPseudo = 1, Predicates = [HasAVX512] in {
479 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
480 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
483 let Predicates = [HasAVX512] in {
484 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
485 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
486 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
489 //===----------------------------------------------------------------------===//
490 // AVX-512 - VECTOR INSERT
492 multiclass vinsert_for_size<int Opcode, X86VectorVTInfo From, X86VectorVTInfo To,
493 PatFrag vinsert_insert> {
494 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
495 defm rr : AVX512_maskable<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
496 (ins To.RC:$src1, From.RC:$src2, i32u8imm:$src3),
497 "vinsert" # From.EltTypeName # "x" # From.NumElts,
498 "$src3, $src2, $src1", "$src1, $src2, $src3",
499 (vinsert_insert:$src3 (To.VT To.RC:$src1),
500 (From.VT From.RC:$src2),
501 (iPTR imm))>, AVX512AIi8Base, EVEX_4V;
504 defm rm : AVX512_maskable<Opcode, MRMSrcMem, To, (outs To.RC:$dst),
505 (ins To.RC:$src1, From.MemOp:$src2, i32u8imm:$src3),
506 "vinsert" # From.EltTypeName # "x" # From.NumElts,
507 "$src3, $src2, $src1", "$src1, $src2, $src3",
508 (vinsert_insert:$src3 (To.VT To.RC:$src1),
509 (From.VT (bitconvert (From.LdFrag addr:$src2))),
510 (iPTR imm))>, AVX512AIi8Base, EVEX_4V,
511 EVEX_CD8<From.EltSize, From.CD8TupleForm>;
515 multiclass vinsert_for_size_lowering<string InstrStr, X86VectorVTInfo From,
516 X86VectorVTInfo To, PatFrag vinsert_insert,
517 SDNodeXForm INSERT_get_vinsert_imm , list<Predicate> p> {
518 let Predicates = p in {
519 def : Pat<(vinsert_insert:$ins
520 (To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
521 (To.VT (!cast<Instruction>(InstrStr#"rr")
522 To.RC:$src1, From.RC:$src2,
523 (INSERT_get_vinsert_imm To.RC:$ins)))>;
525 def : Pat<(vinsert_insert:$ins
527 (From.VT (bitconvert (From.LdFrag addr:$src2))),
529 (To.VT (!cast<Instruction>(InstrStr#"rm")
530 To.RC:$src1, addr:$src2,
531 (INSERT_get_vinsert_imm To.RC:$ins)))>;
535 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
536 ValueType EltVT64, int Opcode256> {
538 let Predicates = [HasVLX] in
539 defm NAME # "32x4Z256" : vinsert_for_size<Opcode128,
540 X86VectorVTInfo< 4, EltVT32, VR128X>,
541 X86VectorVTInfo< 8, EltVT32, VR256X>,
542 vinsert128_insert>, EVEX_V256;
544 defm NAME # "32x4Z" : vinsert_for_size<Opcode128,
545 X86VectorVTInfo< 4, EltVT32, VR128X>,
546 X86VectorVTInfo<16, EltVT32, VR512>,
547 vinsert128_insert>, EVEX_V512;
549 defm NAME # "64x4Z" : vinsert_for_size<Opcode256,
550 X86VectorVTInfo< 4, EltVT64, VR256X>,
551 X86VectorVTInfo< 8, EltVT64, VR512>,
552 vinsert256_insert>, VEX_W, EVEX_V512;
554 let Predicates = [HasVLX, HasDQI] in
555 defm NAME # "64x2Z256" : vinsert_for_size<Opcode128,
556 X86VectorVTInfo< 2, EltVT64, VR128X>,
557 X86VectorVTInfo< 4, EltVT64, VR256X>,
558 vinsert128_insert>, VEX_W, EVEX_V256;
560 let Predicates = [HasDQI] in {
561 defm NAME # "64x2Z" : vinsert_for_size<Opcode128,
562 X86VectorVTInfo< 2, EltVT64, VR128X>,
563 X86VectorVTInfo< 8, EltVT64, VR512>,
564 vinsert128_insert>, VEX_W, EVEX_V512;
566 defm NAME # "32x8Z" : vinsert_for_size<Opcode256,
567 X86VectorVTInfo< 8, EltVT32, VR256X>,
568 X86VectorVTInfo<16, EltVT32, VR512>,
569 vinsert256_insert>, EVEX_V512;
573 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
574 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
576 // Codegen pattern with the alternative types,
577 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
578 defm : vinsert_for_size_lowering<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info,
579 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
580 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info,
581 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
583 defm : vinsert_for_size_lowering<"VINSERTF32x4Z", v2f64x_info, v8f64_info,
584 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
585 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v2i64x_info, v8i64_info,
586 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
588 defm : vinsert_for_size_lowering<"VINSERTF64x4Z", v8f32x_info, v16f32_info,
589 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
590 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v8i32x_info, v16i32_info,
591 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
593 // Codegen pattern with the alternative types insert VEC128 into VEC256
594 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info,
595 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
596 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info,
597 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
598 // Codegen pattern with the alternative types insert VEC128 into VEC512
599 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v8i16x_info, v32i16_info,
600 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
601 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v16i8x_info, v64i8_info,
602 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
603 // Codegen pattern with the alternative types insert VEC256 into VEC512
604 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v16i16x_info, v32i16_info,
605 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
606 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v32i8x_info, v64i8_info,
607 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
609 // vinsertps - insert f32 to XMM
610 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
611 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
612 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
613 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
615 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
616 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
617 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
618 [(set VR128X:$dst, (X86insertps VR128X:$src1,
619 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
620 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
622 //===----------------------------------------------------------------------===//
623 // AVX-512 VECTOR EXTRACT
626 multiclass vextract_for_size_first_position_lowering<X86VectorVTInfo From,
627 X86VectorVTInfo To> {
628 // A subvector extract from the first vector position is
629 // a subregister copy that needs no instruction.
630 def NAME # To.NumElts:
631 Pat<(To.VT (extract_subvector (From.VT From.RC:$src),(iPTR 0))),
632 (To.VT (EXTRACT_SUBREG (From.VT From.RC:$src), To.SubRegIdx))>;
635 multiclass vextract_for_size<int Opcode,
636 X86VectorVTInfo From, X86VectorVTInfo To,
637 PatFrag vextract_extract> :
638 vextract_for_size_first_position_lowering<From, To> {
640 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
641 // use AVX512_maskable_in_asm (AVX512_maskable can't be used due to
642 // vextract_extract), we interesting only in patterns without mask,
643 // intrinsics pattern match generated bellow.
644 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
645 (ins From.RC:$src1, i32u8imm:$idx),
646 "vextract" # To.EltTypeName # "x" # To.NumElts,
647 "$idx, $src1", "$src1, $idx",
648 [(set To.RC:$dst, (vextract_extract:$idx (From.VT From.RC:$src1),
650 AVX512AIi8Base, EVEX;
651 let mayStore = 1 in {
652 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
653 (ins To.MemOp:$dst, From.RC:$src1, i32u8imm:$src2),
654 "vextract" # To.EltTypeName # "x" # To.NumElts #
655 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
658 def rmk : AVX512AIi8<Opcode, MRMDestMem, (outs),
659 (ins To.MemOp:$dst, To.KRCWM:$mask,
660 From.RC:$src1, i32u8imm:$src2),
661 "vextract" # To.EltTypeName # "x" # To.NumElts #
662 "\t{$src2, $src1, $dst {${mask}}|"
663 "$dst {${mask}}, $src1, $src2}",
668 // Intrinsic call with masking.
669 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
670 "x" # To.NumElts # "_" # From.Size)
671 From.RC:$src1, (iPTR imm:$idx), To.RC:$src0, To.MRC:$mask),
672 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
673 From.ZSuffix # "rrk")
675 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
676 From.RC:$src1, imm:$idx)>;
678 // Intrinsic call with zero-masking.
679 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
680 "x" # To.NumElts # "_" # From.Size)
681 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, To.MRC:$mask),
682 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
683 From.ZSuffix # "rrkz")
684 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
685 From.RC:$src1, imm:$idx)>;
687 // Intrinsic call without masking.
688 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
689 "x" # To.NumElts # "_" # From.Size)
690 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
691 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
693 From.RC:$src1, imm:$idx)>;
696 // Codegen pattern for the alternative types
697 multiclass vextract_for_size_lowering<string InstrStr, X86VectorVTInfo From,
698 X86VectorVTInfo To, PatFrag vextract_extract,
699 SDNodeXForm EXTRACT_get_vextract_imm, list<Predicate> p> :
700 vextract_for_size_first_position_lowering<From, To> {
702 let Predicates = p in
703 def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)),
704 (To.VT (!cast<Instruction>(InstrStr#"rr")
706 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
709 multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
710 ValueType EltVT64, int Opcode256> {
711 defm NAME # "32x4Z" : vextract_for_size<Opcode128,
712 X86VectorVTInfo<16, EltVT32, VR512>,
713 X86VectorVTInfo< 4, EltVT32, VR128X>,
714 vextract128_extract>,
715 EVEX_V512, EVEX_CD8<32, CD8VT4>;
716 defm NAME # "64x4Z" : vextract_for_size<Opcode256,
717 X86VectorVTInfo< 8, EltVT64, VR512>,
718 X86VectorVTInfo< 4, EltVT64, VR256X>,
719 vextract256_extract>,
720 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>;
721 let Predicates = [HasVLX] in
722 defm NAME # "32x4Z256" : vextract_for_size<Opcode128,
723 X86VectorVTInfo< 8, EltVT32, VR256X>,
724 X86VectorVTInfo< 4, EltVT32, VR128X>,
725 vextract128_extract>,
726 EVEX_V256, EVEX_CD8<32, CD8VT4>;
727 let Predicates = [HasVLX, HasDQI] in
728 defm NAME # "64x2Z256" : vextract_for_size<Opcode128,
729 X86VectorVTInfo< 4, EltVT64, VR256X>,
730 X86VectorVTInfo< 2, EltVT64, VR128X>,
731 vextract128_extract>,
732 VEX_W, EVEX_V256, EVEX_CD8<64, CD8VT2>;
733 let Predicates = [HasDQI] in {
734 defm NAME # "64x2Z" : vextract_for_size<Opcode128,
735 X86VectorVTInfo< 8, EltVT64, VR512>,
736 X86VectorVTInfo< 2, EltVT64, VR128X>,
737 vextract128_extract>,
738 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>;
739 defm NAME # "32x8Z" : vextract_for_size<Opcode256,
740 X86VectorVTInfo<16, EltVT32, VR512>,
741 X86VectorVTInfo< 8, EltVT32, VR256X>,
742 vextract256_extract>,
743 EVEX_V512, EVEX_CD8<32, CD8VT8>;
747 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
748 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
750 // extract_subvector codegen patterns with the alternative types.
751 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
752 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z", v8f64_info, v2f64x_info,
753 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
754 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v8i64_info, v2i64x_info,
755 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
757 defm : vextract_for_size_lowering<"VEXTRACTF64x4Z", v16f32_info, v8f32x_info,
758 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
759 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v16i32_info, v8i32x_info,
760 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
762 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z256", v4f64x_info, v2f64x_info,
763 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
764 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v4i64x_info, v2i64x_info,
765 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
767 // Codegen pattern with the alternative types extract VEC128 from VEC512
768 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v32i16_info, v8i16x_info,
769 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
770 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v64i8_info, v16i8x_info,
771 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
772 // Codegen pattern with the alternative types extract VEC256 from VEC512
773 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v32i16_info, v16i16x_info,
774 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
775 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v64i8_info, v32i8x_info,
776 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
778 // A 128-bit subvector insert to the first 512-bit vector position
779 // is a subregister copy that needs no instruction.
780 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
781 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
782 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
784 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
785 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
786 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
788 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
789 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
790 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
792 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
793 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
794 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
797 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
798 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
799 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
800 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
801 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
802 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
803 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
804 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
805 def : Pat<(insert_subvector undef, (v16i16 VR256X:$src), (iPTR 0)),
806 (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
807 def : Pat<(insert_subvector undef, (v32i8 VR256X:$src), (iPTR 0)),
808 (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
810 // vextractps - extract 32 bits from XMM
811 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
812 (ins VR128X:$src1, u8imm:$src2),
813 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
814 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
817 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
818 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
819 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
820 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
821 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
823 //===---------------------------------------------------------------------===//
827 multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr,
828 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo> {
830 defm r : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
831 (ins SrcInfo.RC:$src), OpcodeStr, "$src", "$src",
832 (DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src)))>,
835 defm m : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
836 (ins SrcInfo.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
837 (DestInfo.VT (X86VBroadcast
838 (SrcInfo.ScalarLdFrag addr:$src)))>,
839 T8PD, EVEX, EVEX_CD8<SrcInfo.EltSize, CD8VT1>;
842 multiclass avx512_fp_broadcast_vl<bits<8> opc, string OpcodeStr,
843 AVX512VLVectorVTInfo _> {
844 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
847 let Predicates = [HasVLX] in {
848 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
853 let ExeDomain = SSEPackedSingle in {
854 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, "vbroadcastss",
856 let Predicates = [HasVLX] in {
857 defm VBROADCASTSSZ128 : avx512_broadcast_rm<0x18, "vbroadcastss",
858 v4f32x_info, v4f32x_info>, EVEX_V128;
862 let ExeDomain = SSEPackedDouble in {
863 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, "vbroadcastsd",
864 avx512vl_f64_info>, VEX_W;
867 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
868 // Later, we can canonize broadcast instructions before ISel phase and
869 // eliminate additional patterns on ISel.
870 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
871 // representations of source
872 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
873 X86VectorVTInfo _, RegisterClass SrcRC_v,
874 RegisterClass SrcRC_s> {
875 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
876 (!cast<Instruction>(InstName##"r")
877 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
879 let AddedComplexity = 30 in {
880 def : Pat<(_.VT (vselect _.KRCWM:$mask,
881 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
882 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
883 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
885 def : Pat<(_.VT(vselect _.KRCWM:$mask,
886 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
887 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
888 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
892 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
894 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
897 let Predicates = [HasVLX] in {
898 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
899 v8f32x_info, VR128X, FR32X>;
900 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
901 v4f32x_info, VR128X, FR32X>;
902 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
903 v4f64x_info, VR128X, FR64X>;
906 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
907 (VBROADCASTSSZm addr:$src)>;
908 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
909 (VBROADCASTSDZm addr:$src)>;
911 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
912 (VBROADCASTSSZm addr:$src)>;
913 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
914 (VBROADCASTSDZm addr:$src)>;
916 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
917 RegisterClass SrcRC> {
918 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
919 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
920 "$src", "$src", []>, T8PD, EVEX;
923 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
924 RegisterClass SrcRC, Predicate prd> {
925 let Predicates = [prd] in
926 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
927 let Predicates = [prd, HasVLX] in {
928 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
929 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
933 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
935 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
937 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
939 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
942 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
943 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
945 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
946 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
948 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
949 (VPBROADCASTDrZr GR32:$src)>;
950 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
951 (VPBROADCASTQrZr GR64:$src)>;
953 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
954 (VPBROADCASTDrZr GR32:$src)>;
955 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
956 (VPBROADCASTQrZr GR64:$src)>;
958 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
959 (v16i32 immAllZerosV), (i16 GR16:$mask))),
960 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
961 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
962 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
963 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
965 // Provide aliases for broadcast from the same register class that
966 // automatically does the extract.
967 multiclass avx512_int_broadcast_rm_lowering<X86VectorVTInfo DestInfo,
968 X86VectorVTInfo SrcInfo> {
969 def : Pat<(DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src))),
970 (!cast<Instruction>(NAME#DestInfo.ZSuffix#"r")
971 (EXTRACT_SUBREG (SrcInfo.VT SrcInfo.RC:$src), sub_xmm))>;
974 multiclass avx512_int_broadcast_rm_vl<bits<8> opc, string OpcodeStr,
975 AVX512VLVectorVTInfo _, Predicate prd> {
976 let Predicates = [prd] in {
977 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
978 avx512_int_broadcast_rm_lowering<_.info512, _.info256>,
980 // Defined separately to avoid redefinition.
981 defm Z_Alt : avx512_int_broadcast_rm_lowering<_.info512, _.info512>;
983 let Predicates = [prd, HasVLX] in {
984 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
985 avx512_int_broadcast_rm_lowering<_.info256, _.info256>,
987 defm Z128 : avx512_broadcast_rm<opc, OpcodeStr, _.info128, _.info128>,
992 defm VPBROADCASTB : avx512_int_broadcast_rm_vl<0x78, "vpbroadcastb",
993 avx512vl_i8_info, HasBWI>;
994 defm VPBROADCASTW : avx512_int_broadcast_rm_vl<0x79, "vpbroadcastw",
995 avx512vl_i16_info, HasBWI>;
996 defm VPBROADCASTD : avx512_int_broadcast_rm_vl<0x58, "vpbroadcastd",
997 avx512vl_i32_info, HasAVX512>;
998 defm VPBROADCASTQ : avx512_int_broadcast_rm_vl<0x59, "vpbroadcastq",
999 avx512vl_i64_info, HasAVX512>, VEX_W;
1001 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
1002 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
1004 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
1005 (ins _Src.MemOp:$src), OpcodeStr, "$src", "$src",
1006 (_Dst.VT (X86SubVBroadcast
1007 (_Src.VT (bitconvert (_Src.LdFrag addr:$src)))))>,
1011 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1012 v16i32_info, v4i32x_info>,
1013 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1014 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1015 v16f32_info, v4f32x_info>,
1016 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1017 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
1018 v8i64_info, v4i64x_info>, VEX_W,
1019 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1020 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
1021 v8f64_info, v4f64x_info>, VEX_W,
1022 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1024 let Predicates = [HasVLX] in {
1025 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1026 v8i32x_info, v4i32x_info>,
1027 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1028 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1029 v8f32x_info, v4f32x_info>,
1030 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1032 let Predicates = [HasVLX, HasDQI] in {
1033 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1034 v4i64x_info, v2i64x_info>, VEX_W,
1035 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1036 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1037 v4f64x_info, v2f64x_info>, VEX_W,
1038 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1040 let Predicates = [HasDQI] in {
1041 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1042 v8i64_info, v2i64x_info>, VEX_W,
1043 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1044 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
1045 v16i32_info, v8i32x_info>,
1046 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1047 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1048 v8f64_info, v2f64x_info>, VEX_W,
1049 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1050 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
1051 v16f32_info, v8f32x_info>,
1052 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1055 multiclass avx512_broadcast_32x2<bits<8> opc, string OpcodeStr,
1056 X86VectorVTInfo _Dst, X86VectorVTInfo _Src,
1057 SDNode OpNode = X86SubVBroadcast> {
1059 defm r : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
1060 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
1061 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src)))>,
1064 defm m : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
1065 (ins _Src.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
1067 (_Src.VT (scalar_to_vector(loadi64 addr:$src)))))>,
1068 T8PD, EVEX, EVEX_CD8<_Src.EltSize, CD8VT2>;
1071 multiclass avx512_common_broadcast_32x2<bits<8> opc, string OpcodeStr,
1072 AVX512VLVectorVTInfo _> {
1073 let Predicates = [HasDQI] in
1074 defm Z : avx512_broadcast_32x2<opc, OpcodeStr, _.info512, _.info128>,
1076 let Predicates = [HasDQI, HasVLX] in
1077 defm Z256 : avx512_broadcast_32x2<opc, OpcodeStr, _.info256, _.info128>,
1081 multiclass avx512_common_broadcast_i32x2<bits<8> opc, string OpcodeStr,
1082 AVX512VLVectorVTInfo _> :
1083 avx512_common_broadcast_32x2<opc, OpcodeStr, _> {
1085 let Predicates = [HasDQI, HasVLX] in
1086 defm Z128 : avx512_broadcast_32x2<opc, OpcodeStr, _.info128, _.info128,
1087 X86SubV32x2Broadcast>, EVEX_V128;
1090 defm VPBROADCASTI32X2 : avx512_common_broadcast_i32x2<0x59, "vbroadcasti32x2",
1092 defm VPBROADCASTF32X2 : avx512_common_broadcast_32x2<0x19, "vbroadcastf32x2",
1095 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
1096 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
1097 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
1098 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
1100 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
1101 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
1102 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
1103 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
1105 // Provide fallback in case the load node that is used in the patterns above
1106 // is used by additional users, which prevents the pattern selection.
1107 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
1108 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
1109 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
1110 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
1113 //===----------------------------------------------------------------------===//
1114 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
1116 multiclass avx512_mask_broadcastm<bits<8> opc, string OpcodeStr,
1117 X86VectorVTInfo _, RegisterClass KRC> {
1118 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.RC:$dst), (ins KRC:$src),
1119 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1120 [(set _.RC:$dst, (_.VT (X86VBroadcastm KRC:$src)))]>, EVEX;
1123 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
1124 AVX512VLVectorVTInfo VTInfo, RegisterClass KRC> {
1125 let Predicates = [HasCDI] in
1126 defm Z : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info512, KRC>, EVEX_V512;
1127 let Predicates = [HasCDI, HasVLX] in {
1128 defm Z256 : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info256, KRC>, EVEX_V256;
1129 defm Z128 : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info128, KRC>, EVEX_V128;
1133 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
1134 avx512vl_i32_info, VK16>;
1135 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1136 avx512vl_i64_info, VK8>, VEX_W;
1138 //===----------------------------------------------------------------------===//
1139 // -- VPERMI2 - 3 source operands form --
1140 multiclass avx512_perm_i<bits<8> opc, string OpcodeStr,
1141 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1142 let Constraints = "$src1 = $dst" in {
1143 defm rr: AVX512_maskable_3src_cast<opc, MRMSrcReg, _, IdxVT, (outs _.RC:$dst),
1144 (ins _.RC:$src2, _.RC:$src3),
1145 OpcodeStr, "$src3, $src2", "$src2, $src3",
1146 (_.VT (X86VPermi2X IdxVT.RC:$src1, _.RC:$src2, _.RC:$src3))>, EVEX_4V,
1150 defm rm: AVX512_maskable_3src_cast<opc, MRMSrcMem, _, IdxVT, (outs _.RC:$dst),
1151 (ins _.RC:$src2, _.MemOp:$src3),
1152 OpcodeStr, "$src3, $src2", "$src2, $src3",
1153 (_.VT (X86VPermi2X IdxVT.RC:$src1, _.RC:$src2,
1154 (_.VT (bitconvert (_.LdFrag addr:$src3)))))>,
1155 EVEX_4V, AVX5128IBase;
1158 multiclass avx512_perm_i_mb<bits<8> opc, string OpcodeStr,
1159 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1160 let mayLoad = 1, Constraints = "$src1 = $dst" in
1161 defm rmb: AVX512_maskable_3src_cast<opc, MRMSrcMem, _, IdxVT, (outs _.RC:$dst),
1162 (ins _.RC:$src2, _.ScalarMemOp:$src3),
1163 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1164 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1165 (_.VT (X86VPermi2X IdxVT.RC:$src1,
1166 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1167 AVX5128IBase, EVEX_4V, EVEX_B;
1170 multiclass avx512_perm_i_sizes<bits<8> opc, string OpcodeStr,
1171 AVX512VLVectorVTInfo VTInfo,
1172 AVX512VLVectorVTInfo ShuffleMask> {
1173 defm NAME: avx512_perm_i<opc, OpcodeStr, VTInfo.info512,
1174 ShuffleMask.info512>,
1175 avx512_perm_i_mb<opc, OpcodeStr, VTInfo.info512,
1176 ShuffleMask.info512>, EVEX_V512;
1177 let Predicates = [HasVLX] in {
1178 defm NAME#128: avx512_perm_i<opc, OpcodeStr, VTInfo.info128,
1179 ShuffleMask.info128>,
1180 avx512_perm_i_mb<opc, OpcodeStr, VTInfo.info128,
1181 ShuffleMask.info128>, EVEX_V128;
1182 defm NAME#256: avx512_perm_i<opc, OpcodeStr, VTInfo.info256,
1183 ShuffleMask.info256>,
1184 avx512_perm_i_mb<opc, OpcodeStr, VTInfo.info256,
1185 ShuffleMask.info256>, EVEX_V256;
1189 multiclass avx512_perm_i_sizes_w<bits<8> opc, string OpcodeStr,
1190 AVX512VLVectorVTInfo VTInfo,
1191 AVX512VLVectorVTInfo Idx> {
1192 let Predicates = [HasBWI] in
1193 defm NAME: avx512_perm_i<opc, OpcodeStr, VTInfo.info512,
1194 Idx.info512>, EVEX_V512;
1195 let Predicates = [HasBWI, HasVLX] in {
1196 defm NAME#128: avx512_perm_i<opc, OpcodeStr, VTInfo.info128,
1197 Idx.info128>, EVEX_V128;
1198 defm NAME#256: avx512_perm_i<opc, OpcodeStr, VTInfo.info256,
1199 Idx.info256>, EVEX_V256;
1203 defm VPERMI2D : avx512_perm_i_sizes<0x76, "vpermi2d",
1204 avx512vl_i32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1205 defm VPERMI2Q : avx512_perm_i_sizes<0x76, "vpermi2q",
1206 avx512vl_i64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1207 defm VPERMI2W : avx512_perm_i_sizes_w<0x75, "vpermi2w",
1208 avx512vl_i16_info, avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1209 defm VPERMI2PS : avx512_perm_i_sizes<0x77, "vpermi2ps",
1210 avx512vl_f32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1211 defm VPERMI2PD : avx512_perm_i_sizes<0x77, "vpermi2pd",
1212 avx512vl_f64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1215 multiclass avx512_perm_t<bits<8> opc, string OpcodeStr,
1216 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1217 let Constraints = "$src1 = $dst" in {
1218 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1219 (ins IdxVT.RC:$src2, _.RC:$src3),
1220 OpcodeStr, "$src3, $src2", "$src2, $src3",
1221 (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2, _.RC:$src3))>, EVEX_4V,
1225 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1226 (ins IdxVT.RC:$src2, _.MemOp:$src3),
1227 OpcodeStr, "$src3, $src2", "$src2, $src3",
1228 (_.VT (X86VPermt2 _.RC:$src1, IdxVT.RC:$src2,
1229 (bitconvert (_.LdFrag addr:$src3))))>,
1230 EVEX_4V, AVX5128IBase;
1233 multiclass avx512_perm_t_mb<bits<8> opc, string OpcodeStr,
1234 X86VectorVTInfo _, X86VectorVTInfo IdxVT> {
1235 let mayLoad = 1, Constraints = "$src1 = $dst" in
1236 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1237 (ins IdxVT.RC:$src2, _.ScalarMemOp:$src3),
1238 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1239 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1240 (_.VT (X86VPermt2 _.RC:$src1,
1241 IdxVT.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1242 AVX5128IBase, EVEX_4V, EVEX_B;
1245 multiclass avx512_perm_t_sizes<bits<8> opc, string OpcodeStr,
1246 AVX512VLVectorVTInfo VTInfo,
1247 AVX512VLVectorVTInfo ShuffleMask> {
1248 defm NAME: avx512_perm_t<opc, OpcodeStr, VTInfo.info512,
1249 ShuffleMask.info512>,
1250 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info512,
1251 ShuffleMask.info512>, EVEX_V512;
1252 let Predicates = [HasVLX] in {
1253 defm NAME#128: avx512_perm_t<opc, OpcodeStr, VTInfo.info128,
1254 ShuffleMask.info128>,
1255 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info128,
1256 ShuffleMask.info128>, EVEX_V128;
1257 defm NAME#256: avx512_perm_t<opc, OpcodeStr, VTInfo.info256,
1258 ShuffleMask.info256>,
1259 avx512_perm_t_mb<opc, OpcodeStr, VTInfo.info256,
1260 ShuffleMask.info256>, EVEX_V256;
1264 multiclass avx512_perm_t_sizes_w<bits<8> opc, string OpcodeStr,
1265 AVX512VLVectorVTInfo VTInfo,
1266 AVX512VLVectorVTInfo Idx> {
1267 let Predicates = [HasBWI] in
1268 defm NAME: avx512_perm_t<opc, OpcodeStr, VTInfo.info512,
1269 Idx.info512>, EVEX_V512;
1270 let Predicates = [HasBWI, HasVLX] in {
1271 defm NAME#128: avx512_perm_t<opc, OpcodeStr, VTInfo.info128,
1272 Idx.info128>, EVEX_V128;
1273 defm NAME#256: avx512_perm_t<opc, OpcodeStr, VTInfo.info256,
1274 Idx.info256>, EVEX_V256;
1278 defm VPERMT2D : avx512_perm_t_sizes<0x7E, "vpermt2d",
1279 avx512vl_i32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1280 defm VPERMT2Q : avx512_perm_t_sizes<0x7E, "vpermt2q",
1281 avx512vl_i64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1282 defm VPERMT2W : avx512_perm_t_sizes_w<0x7D, "vpermt2w",
1283 avx512vl_i16_info, avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1284 defm VPERMT2PS : avx512_perm_t_sizes<0x7F, "vpermt2ps",
1285 avx512vl_f32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1286 defm VPERMT2PD : avx512_perm_t_sizes<0x7F, "vpermt2pd",
1287 avx512vl_f64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1289 //===----------------------------------------------------------------------===//
1290 // AVX-512 - BLEND using mask
1292 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1293 let ExeDomain = _.ExeDomain in {
1294 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1295 (ins _.RC:$src1, _.RC:$src2),
1296 !strconcat(OpcodeStr,
1297 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1299 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1300 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1301 !strconcat(OpcodeStr,
1302 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1303 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1304 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1305 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1306 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1307 !strconcat(OpcodeStr,
1308 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1309 []>, EVEX_4V, EVEX_KZ;
1310 let mayLoad = 1 in {
1311 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1312 (ins _.RC:$src1, _.MemOp:$src2),
1313 !strconcat(OpcodeStr,
1314 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1315 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1316 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1317 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1318 !strconcat(OpcodeStr,
1319 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1320 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1321 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1322 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1323 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1324 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1325 !strconcat(OpcodeStr,
1326 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1327 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1331 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1333 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1334 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1335 !strconcat(OpcodeStr,
1336 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1337 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1338 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1339 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1340 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1342 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1343 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1344 !strconcat(OpcodeStr,
1345 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1346 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1347 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1351 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1352 AVX512VLVectorVTInfo VTInfo> {
1353 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1354 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1356 let Predicates = [HasVLX] in {
1357 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1358 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1359 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1360 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1364 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1365 AVX512VLVectorVTInfo VTInfo> {
1366 let Predicates = [HasBWI] in
1367 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1369 let Predicates = [HasBWI, HasVLX] in {
1370 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1371 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1376 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1377 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1378 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1379 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1380 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1381 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1384 let Predicates = [HasAVX512] in {
1385 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1386 (v8f32 VR256X:$src2))),
1388 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1389 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1390 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1392 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1393 (v8i32 VR256X:$src2))),
1395 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1396 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1397 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1399 //===----------------------------------------------------------------------===//
1400 // Compare Instructions
1401 //===----------------------------------------------------------------------===//
1403 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1405 multiclass avx512_cmp_scalar<X86VectorVTInfo _, SDNode OpNode, SDNode OpNodeRnd>{
1407 defm rr_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1409 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1410 "vcmp${cc}"#_.Suffix,
1411 "$src2, $src1", "$src1, $src2",
1412 (OpNode (_.VT _.RC:$src1),
1416 defm rm_Int : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1418 (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1419 "vcmp${cc}"#_.Suffix,
1420 "$src2, $src1", "$src1, $src2",
1421 (OpNode (_.VT _.RC:$src1),
1422 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
1423 imm:$cc)>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1425 defm rrb_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1427 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1428 "vcmp${cc}"#_.Suffix,
1429 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1430 (OpNodeRnd (_.VT _.RC:$src1),
1433 (i32 FROUND_NO_EXC))>, EVEX_4V, EVEX_B;
1434 // Accept explicit immediate argument form instead of comparison code.
1435 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1436 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1438 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1440 "$cc, $src2, $src1", "$src1, $src2, $cc">, EVEX_4V;
1441 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1443 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1445 "$cc, $src2, $src1", "$src1, $src2, $cc">,
1446 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1448 defm rrb_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1450 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1452 "$cc,{sae}, $src2, $src1","$src1, $src2,{sae}, $cc">,
1454 }// let isAsmParserOnly = 1, hasSideEffects = 0
1456 let isCodeGenOnly = 1 in {
1457 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1458 (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, AVXCC:$cc),
1459 !strconcat("vcmp${cc}", _.Suffix,
1460 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1461 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1464 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1466 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1468 (ins _.FRC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1469 !strconcat("vcmp${cc}", _.Suffix,
1470 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1471 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1472 (_.ScalarLdFrag addr:$src2),
1474 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1478 let Predicates = [HasAVX512] in {
1479 defm VCMPSSZ : avx512_cmp_scalar<f32x_info, X86cmpms, X86cmpmsRnd>,
1481 defm VCMPSDZ : avx512_cmp_scalar<f64x_info, X86cmpms, X86cmpmsRnd>,
1482 AVX512XDIi8Base, VEX_W;
1485 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1486 X86VectorVTInfo _> {
1487 def rr : AVX512BI<opc, MRMSrcReg,
1488 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1489 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1490 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1491 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1493 def rm : AVX512BI<opc, MRMSrcMem,
1494 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1495 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1496 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1497 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1498 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1499 def rrk : AVX512BI<opc, MRMSrcReg,
1500 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1501 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1502 "$dst {${mask}}, $src1, $src2}"),
1503 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1504 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1505 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1507 def rmk : AVX512BI<opc, MRMSrcMem,
1508 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1509 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1510 "$dst {${mask}}, $src1, $src2}"),
1511 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1512 (OpNode (_.VT _.RC:$src1),
1514 (_.LdFrag addr:$src2))))))],
1515 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1518 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1519 X86VectorVTInfo _> :
1520 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1521 let mayLoad = 1 in {
1522 def rmb : AVX512BI<opc, MRMSrcMem,
1523 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1524 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1525 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1526 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1527 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1528 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1529 def rmbk : AVX512BI<opc, MRMSrcMem,
1530 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1531 _.ScalarMemOp:$src2),
1532 !strconcat(OpcodeStr,
1533 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1534 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1535 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1536 (OpNode (_.VT _.RC:$src1),
1538 (_.ScalarLdFrag addr:$src2)))))],
1539 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1543 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1544 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1545 let Predicates = [prd] in
1546 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1549 let Predicates = [prd, HasVLX] in {
1550 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1552 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1557 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1558 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1560 let Predicates = [prd] in
1561 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1564 let Predicates = [prd, HasVLX] in {
1565 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1567 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1572 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1573 avx512vl_i8_info, HasBWI>,
1576 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1577 avx512vl_i16_info, HasBWI>,
1578 EVEX_CD8<16, CD8VF>;
1580 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1581 avx512vl_i32_info, HasAVX512>,
1582 EVEX_CD8<32, CD8VF>;
1584 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1585 avx512vl_i64_info, HasAVX512>,
1586 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1588 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1589 avx512vl_i8_info, HasBWI>,
1592 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1593 avx512vl_i16_info, HasBWI>,
1594 EVEX_CD8<16, CD8VF>;
1596 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1597 avx512vl_i32_info, HasAVX512>,
1598 EVEX_CD8<32, CD8VF>;
1600 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1601 avx512vl_i64_info, HasAVX512>,
1602 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1604 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1605 (COPY_TO_REGCLASS (VPCMPGTDZrr
1606 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1607 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1609 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1610 (COPY_TO_REGCLASS (VPCMPEQDZrr
1611 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1612 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1614 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1615 X86VectorVTInfo _> {
1616 def rri : AVX512AIi8<opc, MRMSrcReg,
1617 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1618 !strconcat("vpcmp${cc}", Suffix,
1619 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1620 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1622 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1624 def rmi : AVX512AIi8<opc, MRMSrcMem,
1625 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1626 !strconcat("vpcmp${cc}", Suffix,
1627 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1628 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1629 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1631 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1632 def rrik : AVX512AIi8<opc, MRMSrcReg,
1633 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1635 !strconcat("vpcmp${cc}", Suffix,
1636 "\t{$src2, $src1, $dst {${mask}}|",
1637 "$dst {${mask}}, $src1, $src2}"),
1638 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1639 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1641 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1643 def rmik : AVX512AIi8<opc, MRMSrcMem,
1644 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1646 !strconcat("vpcmp${cc}", Suffix,
1647 "\t{$src2, $src1, $dst {${mask}}|",
1648 "$dst {${mask}}, $src1, $src2}"),
1649 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1650 (OpNode (_.VT _.RC:$src1),
1651 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1653 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1655 // Accept explicit immediate argument form instead of comparison code.
1656 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1657 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1658 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1659 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1660 "$dst, $src1, $src2, $cc}"),
1661 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1663 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1664 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1665 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1666 "$dst, $src1, $src2, $cc}"),
1667 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1668 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1669 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1671 !strconcat("vpcmp", Suffix,
1672 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1673 "$dst {${mask}}, $src1, $src2, $cc}"),
1674 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1676 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1677 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1679 !strconcat("vpcmp", Suffix,
1680 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1681 "$dst {${mask}}, $src1, $src2, $cc}"),
1682 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1686 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1687 X86VectorVTInfo _> :
1688 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1689 def rmib : AVX512AIi8<opc, MRMSrcMem,
1690 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1692 !strconcat("vpcmp${cc}", Suffix,
1693 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1694 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1695 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1696 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1698 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1699 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1700 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1701 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1702 !strconcat("vpcmp${cc}", Suffix,
1703 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1704 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1705 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1706 (OpNode (_.VT _.RC:$src1),
1707 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1709 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1711 // Accept explicit immediate argument form instead of comparison code.
1712 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1713 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1714 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1716 !strconcat("vpcmp", Suffix,
1717 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1718 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1719 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1720 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1721 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1722 _.ScalarMemOp:$src2, u8imm:$cc),
1723 !strconcat("vpcmp", Suffix,
1724 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1725 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1726 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1730 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1731 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1732 let Predicates = [prd] in
1733 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1735 let Predicates = [prd, HasVLX] in {
1736 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1737 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1741 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1742 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1743 let Predicates = [prd] in
1744 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1747 let Predicates = [prd, HasVLX] in {
1748 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1750 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1755 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1756 HasBWI>, EVEX_CD8<8, CD8VF>;
1757 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1758 HasBWI>, EVEX_CD8<8, CD8VF>;
1760 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1761 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1762 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1763 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1765 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1766 HasAVX512>, EVEX_CD8<32, CD8VF>;
1767 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1768 HasAVX512>, EVEX_CD8<32, CD8VF>;
1770 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1771 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1772 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1773 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1775 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1777 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1778 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1779 "vcmp${cc}"#_.Suffix,
1780 "$src2, $src1", "$src1, $src2",
1781 (X86cmpm (_.VT _.RC:$src1),
1785 let mayLoad = 1 in {
1786 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1787 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1788 "vcmp${cc}"#_.Suffix,
1789 "$src2, $src1", "$src1, $src2",
1790 (X86cmpm (_.VT _.RC:$src1),
1791 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1794 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1796 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1797 "vcmp${cc}"#_.Suffix,
1798 "${src2}"##_.BroadcastStr##", $src1",
1799 "$src1, ${src2}"##_.BroadcastStr,
1800 (X86cmpm (_.VT _.RC:$src1),
1801 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1804 // Accept explicit immediate argument form instead of comparison code.
1805 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1806 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1808 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1810 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1812 let mayLoad = 1 in {
1813 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1815 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1817 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1819 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1821 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1823 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1824 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1829 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1830 // comparison code form (VCMP[EQ/LT/LE/...]
1831 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1832 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1833 "vcmp${cc}"#_.Suffix,
1834 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1835 (X86cmpmRnd (_.VT _.RC:$src1),
1838 (i32 FROUND_NO_EXC))>, EVEX_B;
1840 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1841 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1843 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1845 "$cc,{sae}, $src2, $src1",
1846 "$src1, $src2,{sae}, $cc">, EVEX_B;
1850 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1851 let Predicates = [HasAVX512] in {
1852 defm Z : avx512_vcmp_common<_.info512>,
1853 avx512_vcmp_sae<_.info512>, EVEX_V512;
1856 let Predicates = [HasAVX512,HasVLX] in {
1857 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1858 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1862 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1863 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1864 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1865 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1867 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1868 (COPY_TO_REGCLASS (VCMPPSZrri
1869 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1870 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1872 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1873 (COPY_TO_REGCLASS (VPCMPDZrri
1874 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1875 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1877 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1878 (COPY_TO_REGCLASS (VPCMPUDZrri
1879 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1880 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1883 // ----------------------------------------------------------------
1885 //handle fpclass instruction mask = op(reg_scalar,imm)
1886 // op(mem_scalar,imm)
1887 multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1888 X86VectorVTInfo _, Predicate prd> {
1889 let Predicates = [prd] in {
1890 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),//_.KRC:$dst),
1891 (ins _.RC:$src1, i32u8imm:$src2),
1892 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1893 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1894 (i32 imm:$src2)))], NoItinerary>;
1895 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1896 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1897 OpcodeStr##_.Suffix#
1898 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1899 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1900 (OpNode (_.VT _.RC:$src1),
1901 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1902 let mayLoad = 1, AddedComplexity = 20 in {
1903 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1904 (ins _.MemOp:$src1, i32u8imm:$src2),
1905 OpcodeStr##_.Suffix##
1906 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1908 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1909 (i32 imm:$src2)))], NoItinerary>;
1910 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1911 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1912 OpcodeStr##_.Suffix##
1913 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1914 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1915 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1916 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1921 //handle fpclass instruction mask = fpclass(reg_vec, reg_vec, imm)
1922 // fpclass(reg_vec, mem_vec, imm)
1923 // fpclass(reg_vec, broadcast(eltVt), imm)
1924 multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1925 X86VectorVTInfo _, string mem, string broadcast>{
1926 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1927 (ins _.RC:$src1, i32u8imm:$src2),
1928 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1929 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1930 (i32 imm:$src2)))], NoItinerary>;
1931 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1932 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1933 OpcodeStr##_.Suffix#
1934 "\t{$src2, $src1, $dst {${mask}}| $dst {${mask}}, $src1, $src2}",
1935 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1936 (OpNode (_.VT _.RC:$src1),
1937 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1938 let mayLoad = 1 in {
1939 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1940 (ins _.MemOp:$src1, i32u8imm:$src2),
1941 OpcodeStr##_.Suffix##mem#
1942 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1943 [(set _.KRC:$dst,(OpNode
1944 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1945 (i32 imm:$src2)))], NoItinerary>;
1946 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1947 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1948 OpcodeStr##_.Suffix##mem#
1949 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1950 [(set _.KRC:$dst, (or _.KRCWM:$mask, (OpNode
1951 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1952 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1953 def rmb : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1954 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
1955 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1956 _.BroadcastStr##", $dst | $dst, ${src1}"
1957 ##_.BroadcastStr##", $src2}",
1958 [(set _.KRC:$dst,(OpNode
1959 (_.VT (X86VBroadcast
1960 (_.ScalarLdFrag addr:$src1))),
1961 (i32 imm:$src2)))], NoItinerary>,EVEX_B;
1962 def rmbk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1963 (ins _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2),
1964 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1965 _.BroadcastStr##", $dst {${mask}} | $dst {${mask}}, ${src1}"##
1966 _.BroadcastStr##", $src2}",
1967 [(set _.KRC:$dst,(or _.KRCWM:$mask, (OpNode
1968 (_.VT (X86VBroadcast
1969 (_.ScalarLdFrag addr:$src1))),
1970 (i32 imm:$src2))))], NoItinerary>,
1975 multiclass avx512_vector_fpclass_all<string OpcodeStr,
1976 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd,
1978 let Predicates = [prd] in {
1979 defm Z : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info512, "{z}",
1980 broadcast>, EVEX_V512;
1982 let Predicates = [prd, HasVLX] in {
1983 defm Z128 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info128, "{x}",
1984 broadcast>, EVEX_V128;
1985 defm Z256 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info256, "{y}",
1986 broadcast>, EVEX_V256;
1990 multiclass avx512_fp_fpclass_all<string OpcodeStr, bits<8> opcVec,
1991 bits<8> opcScalar, SDNode VecOpNode, SDNode ScalarOpNode, Predicate prd>{
1992 defm PS : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f32_info, opcVec,
1993 VecOpNode, prd, "{l}">, EVEX_CD8<32, CD8VF>;
1994 defm PD : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f64_info, opcVec,
1995 VecOpNode, prd, "{q}">,EVEX_CD8<64, CD8VF> , VEX_W;
1996 defm SS : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
1997 f32x_info, prd>, EVEX_CD8<32, CD8VT1>;
1998 defm SD : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
1999 f64x_info, prd>, EVEX_CD8<64, CD8VT1>, VEX_W;
2002 defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass,
2003 X86Vfpclasss, HasDQI>, AVX512AIi8Base,EVEX;
2005 //-----------------------------------------------------------------
2006 // Mask register copy, including
2007 // - copy between mask registers
2008 // - load/store mask registers
2009 // - copy from GPR to mask register and vice versa
2011 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
2012 string OpcodeStr, RegisterClass KRC,
2013 ValueType vvt, X86MemOperand x86memop> {
2014 let hasSideEffects = 0 in {
2015 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2016 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
2018 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
2019 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2020 [(set KRC:$dst, (vvt (load addr:$src)))]>;
2022 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
2023 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2024 [(store KRC:$src, addr:$dst)]>;
2028 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
2030 RegisterClass KRC, RegisterClass GRC> {
2031 let hasSideEffects = 0 in {
2032 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
2033 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
2034 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
2035 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
2039 let Predicates = [HasDQI] in
2040 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
2041 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
2044 let Predicates = [HasAVX512] in
2045 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
2046 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
2049 let Predicates = [HasBWI] in {
2050 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
2052 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
2056 let Predicates = [HasBWI] in {
2057 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
2059 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
2063 // GR from/to mask register
2064 let Predicates = [HasDQI] in {
2065 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2066 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
2067 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2068 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
2070 let Predicates = [HasAVX512] in {
2071 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
2072 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
2073 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
2074 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
2076 let Predicates = [HasBWI] in {
2077 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
2078 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
2080 let Predicates = [HasBWI] in {
2081 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
2082 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
2086 let Predicates = [HasDQI] in {
2087 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2088 (KMOVBmk addr:$dst, VK8:$src)>;
2089 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2090 (KMOVBkm addr:$src)>;
2092 def : Pat<(store VK4:$src, addr:$dst),
2093 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK4:$src, VK8))>;
2094 def : Pat<(store VK2:$src, addr:$dst),
2095 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK2:$src, VK8))>;
2097 let Predicates = [HasAVX512, NoDQI] in {
2098 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2099 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
2100 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2101 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
2103 let Predicates = [HasAVX512] in {
2104 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
2105 (KMOVWmk addr:$dst, VK16:$src)>;
2106 def : Pat<(i1 (load addr:$src)),
2107 (COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
2108 (MOV8rm addr:$src), sub_8bit)),
2110 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
2111 (KMOVWkm addr:$src)>;
2113 let Predicates = [HasBWI] in {
2114 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
2115 (KMOVDmk addr:$dst, VK32:$src)>;
2116 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
2117 (KMOVDkm addr:$src)>;
2119 let Predicates = [HasBWI] in {
2120 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
2121 (KMOVQmk addr:$dst, VK64:$src)>;
2122 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
2123 (KMOVQkm addr:$src)>;
2126 let Predicates = [HasAVX512] in {
2127 def : Pat<(i1 (trunc (i64 GR64:$src))),
2128 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
2131 def : Pat<(i1 (trunc (i32 GR32:$src))),
2132 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
2134 def : Pat<(i1 (trunc (i8 GR8:$src))),
2136 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
2138 def : Pat<(i1 (trunc (i16 GR16:$src))),
2140 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
2143 def : Pat<(i32 (zext VK1:$src)),
2144 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
2145 def : Pat<(i32 (anyext VK1:$src)),
2146 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
2148 def : Pat<(i8 (zext VK1:$src)),
2151 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
2152 def : Pat<(i8 (anyext VK1:$src)),
2154 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
2156 def : Pat<(i64 (zext VK1:$src)),
2157 (AND64ri8 (SUBREG_TO_REG (i64 0),
2158 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
2159 def : Pat<(i16 (zext VK1:$src)),
2161 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
2164 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
2165 (COPY_TO_REGCLASS VK1:$src, VK16)>;
2166 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
2167 (COPY_TO_REGCLASS VK1:$src, VK8)>;
2168 def : Pat<(v4i1 (scalar_to_vector VK1:$src)),
2169 (COPY_TO_REGCLASS VK1:$src, VK4)>;
2170 def : Pat<(v2i1 (scalar_to_vector VK1:$src)),
2171 (COPY_TO_REGCLASS VK1:$src, VK2)>;
2172 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
2173 (COPY_TO_REGCLASS VK1:$src, VK32)>;
2174 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
2175 (COPY_TO_REGCLASS VK1:$src, VK64)>;
2178 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2179 let Predicates = [HasAVX512, NoDQI] in {
2180 // GR from/to 8-bit mask without native support
2181 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2183 (KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
2184 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2186 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
2190 let Predicates = [HasAVX512] in {
2191 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
2192 (COPY_TO_REGCLASS VK16:$src, VK1)>;
2193 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
2194 (COPY_TO_REGCLASS VK8:$src, VK1)>;
2196 let Predicates = [HasBWI] in {
2197 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
2198 (COPY_TO_REGCLASS VK32:$src, VK1)>;
2199 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
2200 (COPY_TO_REGCLASS VK64:$src, VK1)>;
2203 // Mask unary operation
2205 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
2206 RegisterClass KRC, SDPatternOperator OpNode,
2208 let Predicates = [prd] in
2209 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2210 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2211 [(set KRC:$dst, (OpNode KRC:$src))]>;
2214 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
2215 SDPatternOperator OpNode> {
2216 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2218 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2219 HasAVX512>, VEX, PS;
2220 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2221 HasBWI>, VEX, PD, VEX_W;
2222 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2223 HasBWI>, VEX, PS, VEX_W;
2226 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
2228 multiclass avx512_mask_unop_int<string IntName, string InstName> {
2229 let Predicates = [HasAVX512] in
2230 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2232 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2233 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
2235 defm : avx512_mask_unop_int<"knot", "KNOT">;
2237 let Predicates = [HasDQI] in
2238 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
2239 let Predicates = [HasAVX512] in
2240 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
2241 let Predicates = [HasBWI] in
2242 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
2243 let Predicates = [HasBWI] in
2244 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
2246 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
2247 let Predicates = [HasAVX512, NoDQI] in {
2248 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
2249 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
2250 def : Pat<(not VK8:$src),
2252 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
2254 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
2255 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
2256 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
2257 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
2259 // Mask binary operation
2260 // - KAND, KANDN, KOR, KXNOR, KXOR
2261 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
2262 RegisterClass KRC, SDPatternOperator OpNode,
2263 Predicate prd, bit IsCommutable> {
2264 let Predicates = [prd], isCommutable = IsCommutable in
2265 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2266 !strconcat(OpcodeStr,
2267 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2268 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
2271 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
2272 SDPatternOperator OpNode, bit IsCommutable,
2273 Predicate prdW = HasAVX512> {
2274 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2275 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
2276 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2277 prdW, IsCommutable>, VEX_4V, VEX_L, PS;
2278 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2279 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
2280 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2281 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
2284 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
2285 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
2287 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
2288 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
2289 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
2290 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
2291 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
2292 defm KADD : avx512_mask_binop_all<0x4A, "kadd", add, 1, HasDQI>;
2294 multiclass avx512_mask_binop_int<string IntName, string InstName> {
2295 let Predicates = [HasAVX512] in
2296 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2297 (i16 GR16:$src1), (i16 GR16:$src2)),
2298 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2299 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2300 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2303 defm : avx512_mask_binop_int<"kand", "KAND">;
2304 defm : avx512_mask_binop_int<"kandn", "KANDN">;
2305 defm : avx512_mask_binop_int<"kor", "KOR">;
2306 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
2307 defm : avx512_mask_binop_int<"kxor", "KXOR">;
2309 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
2310 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
2311 // for the DQI set, this type is legal and KxxxB instruction is used
2312 let Predicates = [NoDQI] in
2313 def : Pat<(OpNode VK8:$src1, VK8:$src2),
2315 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2316 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2318 // All types smaller than 8 bits require conversion anyway
2319 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2320 (COPY_TO_REGCLASS (Inst
2321 (COPY_TO_REGCLASS VK1:$src1, VK16),
2322 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2323 def : Pat<(OpNode VK2:$src1, VK2:$src2),
2324 (COPY_TO_REGCLASS (Inst
2325 (COPY_TO_REGCLASS VK2:$src1, VK16),
2326 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2327 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2328 (COPY_TO_REGCLASS (Inst
2329 (COPY_TO_REGCLASS VK4:$src1, VK16),
2330 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2333 defm : avx512_binop_pat<and, KANDWrr>;
2334 defm : avx512_binop_pat<andn, KANDNWrr>;
2335 defm : avx512_binop_pat<or, KORWrr>;
2336 defm : avx512_binop_pat<xnor, KXNORWrr>;
2337 defm : avx512_binop_pat<xor, KXORWrr>;
2339 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2340 (KXNORWrr VK16:$src1, VK16:$src2)>;
2341 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2342 (KXNORBrr VK8:$src1, VK8:$src2)>, Requires<[HasDQI]>;
2343 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2344 (KXNORDrr VK32:$src1, VK32:$src2)>, Requires<[HasBWI]>;
2345 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2346 (KXNORQrr VK64:$src1, VK64:$src2)>, Requires<[HasBWI]>;
2348 let Predicates = [NoDQI] in
2349 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2350 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2351 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2353 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2354 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2355 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2357 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2358 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2359 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2361 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2362 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2363 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2366 multiclass avx512_mask_unpck<string Suffix,RegisterClass KRC, ValueType VT,
2367 RegisterClass KRCSrc, Predicate prd> {
2368 let Predicates = [prd] in {
2369 def rr : I<0x4b, MRMSrcReg, (outs KRC:$dst),
2370 (ins KRC:$src1, KRC:$src2),
2371 "kunpck"#Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2374 def : Pat<(VT (concat_vectors KRCSrc:$src1, KRCSrc:$src2)),
2375 (!cast<Instruction>(NAME##rr)
2376 (COPY_TO_REGCLASS KRCSrc:$src2, KRC),
2377 (COPY_TO_REGCLASS KRCSrc:$src1, KRC))>;
2381 defm KUNPCKBW : avx512_mask_unpck<"bw", VK16, v16i1, VK8, HasAVX512>, PD;
2382 defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, HasBWI>, PS;
2383 defm KUNPCKDQ : avx512_mask_unpck<"dq", VK64, v64i1, VK32, HasBWI>, PS, VEX_W;
2386 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2387 SDNode OpNode, Predicate prd> {
2388 let Predicates = [prd], Defs = [EFLAGS] in
2389 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2390 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2391 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2394 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2395 Predicate prdW = HasAVX512> {
2396 defm B : avx512_mask_testop<opc, OpcodeStr#"b", VK8, OpNode, HasDQI>,
2398 defm W : avx512_mask_testop<opc, OpcodeStr#"w", VK16, OpNode, prdW>,
2400 defm Q : avx512_mask_testop<opc, OpcodeStr#"q", VK64, OpNode, HasBWI>,
2402 defm D : avx512_mask_testop<opc, OpcodeStr#"d", VK32, OpNode, HasBWI>,
2406 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2407 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest, HasDQI>;
2410 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2412 let Predicates = [HasAVX512] in
2413 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2414 !strconcat(OpcodeStr,
2415 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2416 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2419 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2421 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2423 let Predicates = [HasDQI] in
2424 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2426 let Predicates = [HasBWI] in {
2427 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2429 let Predicates = [HasDQI] in
2430 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2435 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2436 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2438 // Mask setting all 0s or 1s
2439 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2440 let Predicates = [HasAVX512] in
2441 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2442 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2443 [(set KRC:$dst, (VT Val))]>;
2446 multiclass avx512_mask_setop_w<PatFrag Val> {
2447 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2448 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2449 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2450 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2453 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2454 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2456 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2457 let Predicates = [HasAVX512] in {
2458 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2459 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2460 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2461 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2462 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2463 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2464 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2466 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2467 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2469 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2470 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2472 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2473 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2475 def : Pat<(v16i1 (extract_subvector (v32i1 VK32:$src), (iPTR 0))),
2476 (v16i1 (COPY_TO_REGCLASS VK32:$src, VK16))>;
2478 def : Pat<(v16i1 (extract_subvector (v32i1 VK32:$src), (iPTR 16))),
2479 (v16i1 (COPY_TO_REGCLASS (KSHIFTRDri VK32:$src, (i8 16)), VK16))>;
2481 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
2482 (v32i1 (COPY_TO_REGCLASS VK64:$src, VK32))>;
2484 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2485 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2487 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2488 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2490 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2491 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2493 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2494 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2496 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2497 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2498 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2499 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2501 def : Pat<(v32i1 (insert_subvector undef, VK2:$src, (iPTR 0))),
2502 (v32i1 (COPY_TO_REGCLASS VK2:$src, VK32))>;
2503 def : Pat<(v32i1 (insert_subvector undef, VK4:$src, (iPTR 0))),
2504 (v32i1 (COPY_TO_REGCLASS VK4:$src, VK32))>;
2505 def : Pat<(v32i1 (insert_subvector undef, VK8:$src, (iPTR 0))),
2506 (v32i1 (COPY_TO_REGCLASS VK8:$src, VK32))>;
2507 def : Pat<(v32i1 (insert_subvector undef, VK16:$src, (iPTR 0))),
2508 (v32i1 (COPY_TO_REGCLASS VK16:$src, VK32))>;
2510 def : Pat<(v64i1 (insert_subvector undef, VK2:$src, (iPTR 0))),
2511 (v64i1 (COPY_TO_REGCLASS VK2:$src, VK64))>;
2512 def : Pat<(v64i1 (insert_subvector undef, VK4:$src, (iPTR 0))),
2513 (v64i1 (COPY_TO_REGCLASS VK4:$src, VK64))>;
2514 def : Pat<(v64i1 (insert_subvector undef, VK8:$src, (iPTR 0))),
2515 (v64i1 (COPY_TO_REGCLASS VK8:$src, VK64))>;
2516 def : Pat<(v64i1 (insert_subvector undef, VK16:$src, (iPTR 0))),
2517 (v64i1 (COPY_TO_REGCLASS VK16:$src, VK64))>;
2518 def : Pat<(v64i1 (insert_subvector undef, VK32:$src, (iPTR 0))),
2519 (v64i1 (COPY_TO_REGCLASS VK32:$src, VK64))>;
2522 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2523 (v8i1 (COPY_TO_REGCLASS
2524 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2525 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2527 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2528 (v8i1 (COPY_TO_REGCLASS
2529 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2530 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2532 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2533 (v4i1 (COPY_TO_REGCLASS
2534 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2535 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2537 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2538 (v4i1 (COPY_TO_REGCLASS
2539 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2540 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2542 //===----------------------------------------------------------------------===//
2543 // AVX-512 - Aligned and unaligned load and store
2547 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2548 PatFrag ld_frag, PatFrag mload,
2549 bit IsReMaterializable = 1> {
2550 let hasSideEffects = 0 in {
2551 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2552 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2554 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2555 (ins _.KRCWM:$mask, _.RC:$src),
2556 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2557 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2560 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2561 SchedRW = [WriteLoad] in
2562 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2563 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2564 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2567 let Constraints = "$src0 = $dst" in {
2568 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2569 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2570 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2571 "${dst} {${mask}}, $src1}"),
2572 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2574 (_.VT _.RC:$src0))))], _.ExeDomain>,
2576 let mayLoad = 1, SchedRW = [WriteLoad] in
2577 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2578 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2579 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2580 "${dst} {${mask}}, $src1}"),
2581 [(set _.RC:$dst, (_.VT
2582 (vselect _.KRCWM:$mask,
2583 (_.VT (bitconvert (ld_frag addr:$src1))),
2584 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2586 let mayLoad = 1, SchedRW = [WriteLoad] in
2587 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2588 (ins _.KRCWM:$mask, _.MemOp:$src),
2589 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2590 "${dst} {${mask}} {z}, $src}",
2591 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2592 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2593 _.ExeDomain>, EVEX, EVEX_KZ;
2595 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2596 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2598 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2599 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2601 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2602 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2603 _.KRCWM:$mask, addr:$ptr)>;
2606 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2607 AVX512VLVectorVTInfo _,
2609 bit IsReMaterializable = 1> {
2610 let Predicates = [prd] in
2611 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2612 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2614 let Predicates = [prd, HasVLX] in {
2615 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2616 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2617 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2618 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2622 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2623 AVX512VLVectorVTInfo _,
2625 bit IsReMaterializable = 1> {
2626 let Predicates = [prd] in
2627 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2628 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2630 let Predicates = [prd, HasVLX] in {
2631 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2632 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2633 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2634 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2638 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2639 PatFrag st_frag, PatFrag mstore> {
2641 def rr_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2642 OpcodeStr # ".s\t{$src, $dst|$dst, $src}",
2643 [], _.ExeDomain>, EVEX;
2644 def rrk_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2645 (ins _.KRCWM:$mask, _.RC:$src),
2646 OpcodeStr # ".s\t{$src, ${dst} {${mask}}|"#
2647 "${dst} {${mask}}, $src}",
2648 [], _.ExeDomain>, EVEX, EVEX_K;
2649 def rrkz_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2650 (ins _.KRCWM:$mask, _.RC:$src),
2651 OpcodeStr # ".s\t{$src, ${dst} {${mask}} {z}|" #
2652 "${dst} {${mask}} {z}, $src}",
2653 [], _.ExeDomain>, EVEX, EVEX_KZ;
2655 let mayStore = 1 in {
2656 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2657 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2658 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2659 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2660 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2661 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2662 [], _.ExeDomain>, EVEX, EVEX_K;
2665 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2666 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2667 _.KRCWM:$mask, _.RC:$src)>;
2671 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2672 AVX512VLVectorVTInfo _, Predicate prd> {
2673 let Predicates = [prd] in
2674 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2675 masked_store_unaligned>, EVEX_V512;
2677 let Predicates = [prd, HasVLX] in {
2678 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2679 masked_store_unaligned>, EVEX_V256;
2680 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2681 masked_store_unaligned>, EVEX_V128;
2685 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2686 AVX512VLVectorVTInfo _, Predicate prd> {
2687 let Predicates = [prd] in
2688 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2689 masked_store_aligned512>, EVEX_V512;
2691 let Predicates = [prd, HasVLX] in {
2692 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2693 masked_store_aligned256>, EVEX_V256;
2694 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2695 masked_store_aligned128>, EVEX_V128;
2699 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2701 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2702 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2704 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2706 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2707 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2709 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2710 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2711 PS, EVEX_CD8<32, CD8VF>;
2713 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2714 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2715 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2717 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2718 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2719 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2721 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2722 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2723 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2725 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2726 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2727 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2729 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2730 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2731 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2733 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2734 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2735 (VMOVAPDZrm addr:$ptr)>;
2737 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2738 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2739 (VMOVAPSZrm addr:$ptr)>;
2741 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2743 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2745 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2747 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2750 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2752 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2754 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2756 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2759 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2761 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2762 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2764 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2766 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2767 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2769 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2770 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2771 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2773 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2774 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2775 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2777 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2778 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2779 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2781 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2782 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2783 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2785 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2786 (v16i32 immAllZerosV), GR16:$mask)),
2787 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2789 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2790 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2791 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2793 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2795 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2797 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2799 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2802 let AddedComplexity = 20 in {
2803 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2804 (bc_v8i64 (v16i32 immAllZerosV)))),
2805 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2807 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2808 (v8i64 VR512:$src))),
2809 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2812 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2813 (v16i32 immAllZerosV))),
2814 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2816 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2817 (v16i32 VR512:$src))),
2818 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2821 // Move Int Doubleword to Packed Double Int
2823 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2824 "vmovd\t{$src, $dst|$dst, $src}",
2826 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2828 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2829 "vmovd\t{$src, $dst|$dst, $src}",
2831 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2832 IIC_SSE_MOVDQ>, EVEX, EVEX_CD8<32, CD8VT1>;
2833 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2834 "vmovq\t{$src, $dst|$dst, $src}",
2836 (v2i64 (scalar_to_vector GR64:$src)))],
2837 IIC_SSE_MOVDQ>, EVEX, VEX_W;
2838 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
2839 def VMOV64toPQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2841 "vmovq\t{$src, $dst|$dst, $src}", []>,
2842 EVEX, VEX_W, EVEX_CD8<64, CD8VT1>;
2843 let isCodeGenOnly = 1 in {
2844 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64X:$dst), (ins GR64:$src),
2845 "vmovq\t{$src, $dst|$dst, $src}",
2846 [(set FR64X:$dst, (bitconvert GR64:$src))],
2847 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2848 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64X:$src),
2849 "vmovq\t{$src, $dst|$dst, $src}",
2850 [(set GR64:$dst, (bitconvert FR64X:$src))],
2851 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2852 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64X:$src),
2853 "vmovq\t{$src, $dst|$dst, $src}",
2854 [(store (i64 (bitconvert FR64X:$src)), addr:$dst)],
2855 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2856 EVEX_CD8<64, CD8VT1>;
2859 // Move Int Doubleword to Single Scalar
2861 let isCodeGenOnly = 1 in {
2862 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2863 "vmovd\t{$src, $dst|$dst, $src}",
2864 [(set FR32X:$dst, (bitconvert GR32:$src))],
2865 IIC_SSE_MOVDQ>, EVEX;
2867 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2868 "vmovd\t{$src, $dst|$dst, $src}",
2869 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2870 IIC_SSE_MOVDQ>, EVEX, EVEX_CD8<32, CD8VT1>;
2873 // Move doubleword from xmm register to r/m32
2875 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2876 "vmovd\t{$src, $dst|$dst, $src}",
2877 [(set GR32:$dst, (extractelt (v4i32 VR128X:$src),
2878 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2880 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2881 (ins i32mem:$dst, VR128X:$src),
2882 "vmovd\t{$src, $dst|$dst, $src}",
2883 [(store (i32 (extractelt (v4i32 VR128X:$src),
2884 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2885 EVEX, EVEX_CD8<32, CD8VT1>;
2887 // Move quadword from xmm1 register to r/m64
2889 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2890 "vmovq\t{$src, $dst|$dst, $src}",
2891 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2893 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_W,
2894 Requires<[HasAVX512, In64BitMode]>;
2896 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
2897 def VMOVPQIto64Zmr : I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128X:$src),
2898 "vmovq\t{$src, $dst|$dst, $src}",
2899 [], IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_W,
2900 Requires<[HasAVX512, In64BitMode]>;
2902 def VMOVPQI2QIZmr : I<0xD6, MRMDestMem, (outs),
2903 (ins i64mem:$dst, VR128X:$src),
2904 "vmovq\t{$src, $dst|$dst, $src}",
2905 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2906 addr:$dst)], IIC_SSE_MOVDQ>,
2907 EVEX, PD, VEX_W, EVEX_CD8<64, CD8VT1>,
2908 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2910 let hasSideEffects = 0 in
2911 def VMOVPQI2QIZrr : AVX512BI<0xD6, MRMDestReg, (outs VR128X:$dst),
2913 "vmovq.s\t{$src, $dst|$dst, $src}",[]>,
2916 // Move Scalar Single to Double Int
2918 let isCodeGenOnly = 1 in {
2919 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2921 "vmovd\t{$src, $dst|$dst, $src}",
2922 [(set GR32:$dst, (bitconvert FR32X:$src))],
2923 IIC_SSE_MOVD_ToGP>, EVEX;
2924 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2925 (ins i32mem:$dst, FR32X:$src),
2926 "vmovd\t{$src, $dst|$dst, $src}",
2927 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2928 IIC_SSE_MOVDQ>, EVEX, EVEX_CD8<32, CD8VT1>;
2931 // Move Quadword Int to Packed Quadword Int
2933 def VMOVQI2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2935 "vmovq\t{$src, $dst|$dst, $src}",
2937 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2938 EVEX, VEX_W, EVEX_CD8<8, CD8VT8>;
2940 //===----------------------------------------------------------------------===//
2941 // AVX-512 MOVSS, MOVSD
2942 //===----------------------------------------------------------------------===//
2944 multiclass avx512_move_scalar <string asm, SDNode OpNode,
2945 X86VectorVTInfo _> {
2946 defm rr_Int : AVX512_maskable_scalar<0x10, MRMSrcReg, _, (outs _.RC:$dst),
2947 (ins _.RC:$src1, _.RC:$src2),
2948 asm, "$src2, $src1","$src1, $src2",
2949 (_.VT (OpNode (_.VT _.RC:$src1),
2950 (_.VT _.RC:$src2))),
2951 IIC_SSE_MOV_S_RR>, EVEX_4V;
2952 let Constraints = "$src1 = $dst" , mayLoad = 1 in
2953 defm rm_Int : AVX512_maskable_3src_scalar<0x10, MRMSrcMem, _,
2955 (ins _.ScalarMemOp:$src),
2957 (_.VT (OpNode (_.VT _.RC:$src1),
2958 (_.VT (scalar_to_vector
2959 (_.ScalarLdFrag addr:$src)))))>, EVEX;
2960 let isCodeGenOnly = 1 in {
2961 def rr : AVX512PI<0x10, MRMSrcReg, (outs _.RC:$dst),
2962 (ins _.RC:$src1, _.FRC:$src2),
2963 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2964 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1,
2965 (scalar_to_vector _.FRC:$src2))))],
2966 _.ExeDomain,IIC_SSE_MOV_S_RR>, EVEX_4V;
2968 def rm : AVX512PI<0x10, MRMSrcMem, (outs _.FRC:$dst), (ins _.ScalarMemOp:$src),
2969 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2970 [(set _.FRC:$dst, (_.ScalarLdFrag addr:$src))],
2971 _.ExeDomain, IIC_SSE_MOV_S_RM>, EVEX;
2973 let mayStore = 1 in {
2974 def mr: AVX512PI<0x11, MRMDestMem, (outs), (ins _.ScalarMemOp:$dst, _.FRC:$src),
2975 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2976 [(store _.FRC:$src, addr:$dst)], _.ExeDomain, IIC_SSE_MOV_S_MR>,
2978 def mrk: AVX512PI<0x11, MRMDestMem, (outs),
2979 (ins _.ScalarMemOp:$dst, VK1WM:$mask, _.FRC:$src),
2980 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2981 [], _.ExeDomain, IIC_SSE_MOV_S_MR>, EVEX, EVEX_K;
2985 defm VMOVSSZ : avx512_move_scalar<"vmovss", X86Movss, f32x_info>,
2986 VEX_LIG, XS, EVEX_CD8<32, CD8VT1>;
2988 defm VMOVSDZ : avx512_move_scalar<"vmovsd", X86Movsd, f64x_info>,
2989 VEX_LIG, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2991 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2992 (COPY_TO_REGCLASS (VMOVSSZrr_Intk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2993 VK1WM:$mask, (v4f32 (IMPLICIT_DEF)),(COPY_TO_REGCLASS FR32X:$src1, VR128X)), FR32X)>;
2995 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2996 (COPY_TO_REGCLASS (VMOVSDZrr_Intk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2997 VK1WM:$mask, (v2f64 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR64X:$src1, VR128X)), FR64X)>;
2999 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
3000 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
3001 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3003 defm VMOVSSZrr_REV : AVX512_maskable_in_asm<0x11, MRMDestReg, f32x_info,
3004 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2),
3005 "vmovss.s", "$src2, $src1", "$src1, $src2", []>,
3006 XS, EVEX_4V, VEX_LIG;
3008 defm VMOVSSDrr_REV : AVX512_maskable_in_asm<0x11, MRMDestReg, f64x_info,
3009 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2),
3010 "vmovsd.s", "$src2, $src1", "$src1, $src2", []>,
3011 XD, EVEX_4V, VEX_LIG, VEX_W;
3013 let Predicates = [HasAVX512] in {
3014 let AddedComplexity = 15 in {
3015 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
3016 // MOVS{S,D} to the lower bits.
3017 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
3018 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
3019 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
3020 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3021 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
3022 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
3023 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
3024 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
3026 // Move low f32 and clear high bits.
3027 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
3028 (SUBREG_TO_REG (i32 0),
3029 (VMOVSSZrr (v4f32 (V_SET0)),
3030 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
3031 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
3032 (SUBREG_TO_REG (i32 0),
3033 (VMOVSSZrr (v4i32 (V_SET0)),
3034 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
3037 let AddedComplexity = 20 in {
3038 // MOVSSrm zeros the high parts of the register; represent this
3039 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
3040 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
3041 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3042 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
3043 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3044 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
3045 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
3047 // MOVSDrm zeros the high parts of the register; represent this
3048 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
3049 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
3050 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3051 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
3052 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3053 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
3054 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3055 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
3056 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3057 def : Pat<(v2f64 (X86vzload addr:$src)),
3058 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
3060 // Represent the same patterns above but in the form they appear for
3062 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3063 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
3064 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
3065 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
3066 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
3067 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
3068 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
3069 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
3070 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
3072 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
3073 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
3074 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
3075 FR32X:$src)), sub_xmm)>;
3076 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
3077 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
3078 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
3079 FR64X:$src)), sub_xmm)>;
3080 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3081 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
3082 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
3084 // Move low f64 and clear high bits.
3085 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
3086 (SUBREG_TO_REG (i32 0),
3087 (VMOVSDZrr (v2f64 (V_SET0)),
3088 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
3090 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
3091 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
3092 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
3094 // Extract and store.
3095 def : Pat<(store (f32 (extractelt (v4f32 VR128X:$src), (iPTR 0))),
3097 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
3098 def : Pat<(store (f64 (extractelt (v2f64 VR128X:$src), (iPTR 0))),
3100 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
3102 // Shuffle with VMOVSS
3103 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
3104 (VMOVSSZrr (v4i32 VR128X:$src1),
3105 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
3106 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
3107 (VMOVSSZrr (v4f32 VR128X:$src1),
3108 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
3111 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
3112 (SUBREG_TO_REG (i32 0),
3113 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
3114 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
3116 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
3117 (SUBREG_TO_REG (i32 0),
3118 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
3119 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
3122 // Shuffle with VMOVSD
3123 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3124 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3125 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3126 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3127 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3128 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3129 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3130 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3133 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3134 (SUBREG_TO_REG (i32 0),
3135 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
3136 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
3138 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3139 (SUBREG_TO_REG (i32 0),
3140 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
3141 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
3144 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3145 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3146 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3147 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3148 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3149 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3150 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3151 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3154 let AddedComplexity = 15 in
3155 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
3157 "vmovq\t{$src, $dst|$dst, $src}",
3158 [(set VR128X:$dst, (v2i64 (X86vzmovl
3159 (v2i64 VR128X:$src))))],
3160 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
3162 let AddedComplexity = 20 , isCodeGenOnly = 1 in
3163 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
3165 "vmovq\t{$src, $dst|$dst, $src}",
3166 [(set VR128X:$dst, (v2i64 (X86vzmovl
3167 (loadv2i64 addr:$src))))],
3168 IIC_SSE_MOVDQ>, EVEX, VEX_W,
3169 EVEX_CD8<8, CD8VT8>;
3171 let Predicates = [HasAVX512] in {
3172 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3173 let AddedComplexity = 20 in {
3174 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
3175 (VMOVDI2PDIZrm addr:$src)>;
3176 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
3177 (VMOV64toPQIZrr GR64:$src)>;
3178 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
3179 (VMOVDI2PDIZrr GR32:$src)>;
3181 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3182 (VMOVDI2PDIZrm addr:$src)>;
3183 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3184 (VMOVDI2PDIZrm addr:$src)>;
3185 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3186 (VMOVZPQILo2PQIZrm addr:$src)>;
3187 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
3188 (VMOVZPQILo2PQIZrr VR128X:$src)>;
3189 def : Pat<(v2i64 (X86vzload addr:$src)),
3190 (VMOVZPQILo2PQIZrm addr:$src)>;
3193 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3194 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3195 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
3196 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
3197 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3198 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
3199 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
3202 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
3203 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3205 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
3206 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3208 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
3209 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3211 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
3212 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3214 //===----------------------------------------------------------------------===//
3215 // AVX-512 - Non-temporals
3216 //===----------------------------------------------------------------------===//
3217 let SchedRW = [WriteLoad] in {
3218 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
3219 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
3220 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
3221 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
3222 EVEX_CD8<64, CD8VF>;
3224 let Predicates = [HasAVX512, HasVLX] in {
3225 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
3227 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3228 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
3229 EVEX_CD8<64, CD8VF>;
3231 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
3233 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3234 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
3235 EVEX_CD8<64, CD8VF>;
3239 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3240 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
3241 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
3242 let SchedRW = [WriteStore], mayStore = 1,
3243 AddedComplexity = 400 in
3244 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
3245 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3246 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
3249 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3250 string elty, string elsz, string vsz512,
3251 string vsz256, string vsz128, Domain d,
3252 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
3253 let Predicates = [prd] in
3254 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
3255 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
3256 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
3259 let Predicates = [prd, HasVLX] in {
3260 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
3261 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
3262 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
3265 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
3266 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
3267 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
3272 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
3273 "i", "64", "8", "4", "2", SSEPackedInt,
3274 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
3276 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
3277 "f", "64", "8", "4", "2", SSEPackedDouble,
3278 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3280 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
3281 "f", "32", "16", "8", "4", SSEPackedSingle,
3282 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
3284 //===----------------------------------------------------------------------===//
3285 // AVX-512 - Integer arithmetic
3287 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3288 X86VectorVTInfo _, OpndItins itins,
3289 bit IsCommutable = 0> {
3290 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3291 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3292 "$src2, $src1", "$src1, $src2",
3293 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3294 itins.rr, IsCommutable>,
3295 AVX512BIBase, EVEX_4V;
3298 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3299 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3300 "$src2, $src1", "$src1, $src2",
3301 (_.VT (OpNode _.RC:$src1,
3302 (bitconvert (_.LdFrag addr:$src2)))),
3304 AVX512BIBase, EVEX_4V;
3307 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3308 X86VectorVTInfo _, OpndItins itins,
3309 bit IsCommutable = 0> :
3310 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
3312 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3313 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3314 "${src2}"##_.BroadcastStr##", $src1",
3315 "$src1, ${src2}"##_.BroadcastStr,
3316 (_.VT (OpNode _.RC:$src1,
3318 (_.ScalarLdFrag addr:$src2)))),
3320 AVX512BIBase, EVEX_4V, EVEX_B;
3323 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3324 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3325 Predicate prd, bit IsCommutable = 0> {
3326 let Predicates = [prd] in
3327 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3328 IsCommutable>, EVEX_V512;
3330 let Predicates = [prd, HasVLX] in {
3331 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3332 IsCommutable>, EVEX_V256;
3333 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3334 IsCommutable>, EVEX_V128;
3338 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3339 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3340 Predicate prd, bit IsCommutable = 0> {
3341 let Predicates = [prd] in
3342 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3343 IsCommutable>, EVEX_V512;
3345 let Predicates = [prd, HasVLX] in {
3346 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3347 IsCommutable>, EVEX_V256;
3348 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3349 IsCommutable>, EVEX_V128;
3353 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3354 OpndItins itins, Predicate prd,
3355 bit IsCommutable = 0> {
3356 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3357 itins, prd, IsCommutable>,
3358 VEX_W, EVEX_CD8<64, CD8VF>;
3361 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3362 OpndItins itins, Predicate prd,
3363 bit IsCommutable = 0> {
3364 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3365 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3368 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3369 OpndItins itins, Predicate prd,
3370 bit IsCommutable = 0> {
3371 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3372 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3375 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3376 OpndItins itins, Predicate prd,
3377 bit IsCommutable = 0> {
3378 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3379 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3382 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3383 SDNode OpNode, OpndItins itins, Predicate prd,
3384 bit IsCommutable = 0> {
3385 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr#"q", OpNode, itins, prd,
3388 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr#"d", OpNode, itins, prd,
3392 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3393 SDNode OpNode, OpndItins itins, Predicate prd,
3394 bit IsCommutable = 0> {
3395 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr#"w", OpNode, itins, prd,
3398 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr#"b", OpNode, itins, prd,
3402 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3403 bits<8> opc_d, bits<8> opc_q,
3404 string OpcodeStr, SDNode OpNode,
3405 OpndItins itins, bit IsCommutable = 0> {
3406 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3407 itins, HasAVX512, IsCommutable>,
3408 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3409 itins, HasBWI, IsCommutable>;
3412 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3413 SDNode OpNode,X86VectorVTInfo _Src,
3414 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3415 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3416 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3417 "$src2, $src1","$src1, $src2",
3419 (_Src.VT _Src.RC:$src1),
3420 (_Src.VT _Src.RC:$src2))),
3421 itins.rr, IsCommutable>,
3422 AVX512BIBase, EVEX_4V;
3423 let mayLoad = 1 in {
3424 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3425 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3426 "$src2, $src1", "$src1, $src2",
3427 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3428 (bitconvert (_Src.LdFrag addr:$src2)))),
3430 AVX512BIBase, EVEX_4V;
3432 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3433 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3435 "${src2}"##_Dst.BroadcastStr##", $src1",
3436 "$src1, ${src2}"##_Dst.BroadcastStr,
3437 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3438 (_Dst.VT (X86VBroadcast
3439 (_Dst.ScalarLdFrag addr:$src2)))))),
3441 AVX512BIBase, EVEX_4V, EVEX_B;
3445 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3446 SSE_INTALU_ITINS_P, 1>;
3447 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3448 SSE_INTALU_ITINS_P, 0>;
3449 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3450 SSE_INTALU_ITINS_P, HasBWI, 1>;
3451 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3452 SSE_INTALU_ITINS_P, HasBWI, 0>;
3453 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3454 SSE_INTALU_ITINS_P, HasBWI, 1>;
3455 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3456 SSE_INTALU_ITINS_P, HasBWI, 0>;
3457 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmulld", mul,
3458 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3459 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmullw", mul,
3460 SSE_INTALU_ITINS_P, HasBWI, 1>;
3461 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmullq", mul,
3462 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3463 defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SSE_INTALU_ITINS_P,
3465 defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SSE_INTMUL_ITINS_P,
3467 defm VPMULHRSW : avx512_binop_rm_vl_w<0x0B, "vpmulhrsw", X86mulhrs, SSE_INTMUL_ITINS_P,
3469 defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg,
3470 SSE_INTALU_ITINS_P, HasBWI, 1>;
3472 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3473 SDNode OpNode, bit IsCommutable = 0> {
3475 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3476 v16i32_info, v8i64_info, IsCommutable>,
3477 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3478 let Predicates = [HasVLX] in {
3479 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3480 v8i32x_info, v4i64x_info, IsCommutable>,
3481 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3482 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3483 v4i32x_info, v2i64x_info, IsCommutable>,
3484 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3488 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3490 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3493 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3494 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3495 let mayLoad = 1 in {
3496 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3497 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3499 "${src2}"##_Src.BroadcastStr##", $src1",
3500 "$src1, ${src2}"##_Src.BroadcastStr,
3501 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3502 (_Src.VT (X86VBroadcast
3503 (_Src.ScalarLdFrag addr:$src2))))))>,
3504 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3508 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3509 SDNode OpNode,X86VectorVTInfo _Src,
3510 X86VectorVTInfo _Dst> {
3511 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3512 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3513 "$src2, $src1","$src1, $src2",
3515 (_Src.VT _Src.RC:$src1),
3516 (_Src.VT _Src.RC:$src2)))>,
3517 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3518 let mayLoad = 1 in {
3519 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3520 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3521 "$src2, $src1", "$src1, $src2",
3522 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3523 (bitconvert (_Src.LdFrag addr:$src2))))>,
3524 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3528 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3530 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3532 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3533 v32i16_info>, EVEX_V512;
3534 let Predicates = [HasVLX] in {
3535 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3537 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3538 v16i16x_info>, EVEX_V256;
3539 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3541 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3542 v8i16x_info>, EVEX_V128;
3545 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3547 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3548 v64i8_info>, EVEX_V512;
3549 let Predicates = [HasVLX] in {
3550 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3551 v32i8x_info>, EVEX_V256;
3552 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3553 v16i8x_info>, EVEX_V128;
3557 multiclass avx512_vpmadd<bits<8> opc, string OpcodeStr,
3558 SDNode OpNode, AVX512VLVectorVTInfo _Src,
3559 AVX512VLVectorVTInfo _Dst> {
3560 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info512,
3561 _Dst.info512>, EVEX_V512;
3562 let Predicates = [HasVLX] in {
3563 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info256,
3564 _Dst.info256>, EVEX_V256;
3565 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info128,
3566 _Dst.info128>, EVEX_V128;
3570 let Predicates = [HasBWI] in {
3571 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3572 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3573 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3574 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3576 defm VPMADDUBSW : avx512_vpmadd<0x04, "vpmaddubsw", X86vpmaddubsw,
3577 avx512vl_i8_info, avx512vl_i16_info>, AVX512BIBase, T8PD;
3578 defm VPMADDWD : avx512_vpmadd<0xF5, "vpmaddwd", X86vpmaddwd,
3579 avx512vl_i16_info, avx512vl_i32_info>, AVX512BIBase;
3582 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxsb", smax,
3583 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3584 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxsw", smax,
3585 SSE_INTALU_ITINS_P, HasBWI, 1>;
3586 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", smax,
3587 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3589 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxub", umax,
3590 SSE_INTALU_ITINS_P, HasBWI, 1>;
3591 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxuw", umax,
3592 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3593 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", umax,
3594 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3596 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpminsb", smin,
3597 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3598 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpminsw", smin,
3599 SSE_INTALU_ITINS_P, HasBWI, 1>;
3600 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", smin,
3601 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3603 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminub", umin,
3604 SSE_INTALU_ITINS_P, HasBWI, 1>;
3605 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin,
3606 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3607 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", umin,
3608 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3609 //===----------------------------------------------------------------------===//
3610 // AVX-512 Logical Instructions
3611 //===----------------------------------------------------------------------===//
3613 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3614 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3615 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3616 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3617 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3618 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3619 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3620 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3622 //===----------------------------------------------------------------------===//
3623 // AVX-512 FP arithmetic
3624 //===----------------------------------------------------------------------===//
3625 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3626 SDNode OpNode, SDNode VecNode, OpndItins itins,
3629 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3630 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3631 "$src2, $src1", "$src1, $src2",
3632 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3633 (i32 FROUND_CURRENT)),
3634 itins.rr, IsCommutable>;
3636 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3637 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3638 "$src2, $src1", "$src1, $src2",
3639 (VecNode (_.VT _.RC:$src1),
3640 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3641 (i32 FROUND_CURRENT)),
3642 itins.rm, IsCommutable>;
3643 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3644 Predicates = [HasAVX512] in {
3645 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3646 (ins _.FRC:$src1, _.FRC:$src2),
3647 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3648 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3650 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3651 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3652 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3653 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3654 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3658 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3659 SDNode VecNode, OpndItins itins, bit IsCommutable = 0> {
3661 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3662 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3663 "$rc, $src2, $src1", "$src1, $src2, $rc",
3664 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3665 (i32 imm:$rc)), itins.rr, IsCommutable>,
3668 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3669 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3671 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3672 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3673 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3674 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3675 (i32 FROUND_NO_EXC))>, EVEX_B;
3678 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3680 SizeItins itins, bit IsCommutable> {
3681 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3682 itins.s, IsCommutable>,
3683 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3684 itins.s, IsCommutable>,
3685 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3686 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3687 itins.d, IsCommutable>,
3688 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3689 itins.d, IsCommutable>,
3690 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3693 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3695 SizeItins itins, bit IsCommutable> {
3696 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3697 itins.s, IsCommutable>,
3698 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3699 itins.s, IsCommutable>,
3700 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3701 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3702 itins.d, IsCommutable>,
3703 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3704 itins.d, IsCommutable>,
3705 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3707 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3708 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3709 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3710 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3711 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3712 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3714 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3715 X86VectorVTInfo _, bit IsCommutable> {
3716 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3717 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3718 "$src2, $src1", "$src1, $src2",
3719 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3720 let mayLoad = 1 in {
3721 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3722 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3723 "$src2, $src1", "$src1, $src2",
3724 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3725 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3726 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3727 "${src2}"##_.BroadcastStr##", $src1",
3728 "$src1, ${src2}"##_.BroadcastStr,
3729 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3730 (_.ScalarLdFrag addr:$src2))))>,
3735 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3736 X86VectorVTInfo _> {
3737 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3738 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3739 "$rc, $src2, $src1", "$src1, $src2, $rc",
3740 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3741 EVEX_4V, EVEX_B, EVEX_RC;
3745 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3746 X86VectorVTInfo _> {
3747 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3748 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3749 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3750 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3754 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3755 bit IsCommutable = 0> {
3756 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3757 IsCommutable>, EVEX_V512, PS,
3758 EVEX_CD8<32, CD8VF>;
3759 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3760 IsCommutable>, EVEX_V512, PD, VEX_W,
3761 EVEX_CD8<64, CD8VF>;
3763 // Define only if AVX512VL feature is present.
3764 let Predicates = [HasVLX] in {
3765 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3766 IsCommutable>, EVEX_V128, PS,
3767 EVEX_CD8<32, CD8VF>;
3768 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3769 IsCommutable>, EVEX_V256, PS,
3770 EVEX_CD8<32, CD8VF>;
3771 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3772 IsCommutable>, EVEX_V128, PD, VEX_W,
3773 EVEX_CD8<64, CD8VF>;
3774 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3775 IsCommutable>, EVEX_V256, PD, VEX_W,
3776 EVEX_CD8<64, CD8VF>;
3780 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3781 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3782 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3783 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3784 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3787 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3788 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3789 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3790 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3791 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3794 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3795 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3796 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3797 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3798 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3799 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3800 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3801 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3802 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3803 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3804 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3805 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3806 let Predicates = [HasDQI] in {
3807 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3808 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3809 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3810 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3813 multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3814 X86VectorVTInfo _> {
3815 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3816 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3817 "$src2, $src1", "$src1, $src2",
3818 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>, EVEX_4V;
3819 let mayLoad = 1 in {
3820 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3821 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3822 "$src2, $src1", "$src1, $src2",
3823 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>, EVEX_4V;
3824 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3825 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3826 "${src2}"##_.BroadcastStr##", $src1",
3827 "$src1, ${src2}"##_.BroadcastStr,
3828 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3829 (_.ScalarLdFrag addr:$src2))), (i32 FROUND_CURRENT))>,
3834 multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
3835 X86VectorVTInfo _> {
3836 defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3837 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3838 "$src2, $src1", "$src1, $src2",
3839 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>;
3840 let mayLoad = 1 in {
3841 defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3842 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3843 "$src2, $src1", "$src1, $src2",
3844 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>;
3848 multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode> {
3849 defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v16f32_info>,
3850 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
3851 EVEX_V512, EVEX_CD8<32, CD8VF>;
3852 defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f64_info>,
3853 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v8f64_info>,
3854 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3855 defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f32x_info>,
3856 avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNode, SSE_ALU_ITINS_S.s>,
3857 EVEX_4V,EVEX_CD8<32, CD8VT1>;
3858 defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f64x_info>,
3859 avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNode, SSE_ALU_ITINS_S.d>,
3860 EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
3862 // Define only if AVX512VL feature is present.
3863 let Predicates = [HasVLX] in {
3864 defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f32x_info>,
3865 EVEX_V128, EVEX_CD8<32, CD8VF>;
3866 defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f32x_info>,
3867 EVEX_V256, EVEX_CD8<32, CD8VF>;
3868 defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v2f64x_info>,
3869 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
3870 defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f64x_info>,
3871 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
3874 defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef>, T8PD;
3876 //===----------------------------------------------------------------------===//
3877 // AVX-512 VPTESTM instructions
3878 //===----------------------------------------------------------------------===//
3880 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3881 X86VectorVTInfo _> {
3882 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3883 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3884 "$src2, $src1", "$src1, $src2",
3885 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3888 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3889 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3890 "$src2, $src1", "$src1, $src2",
3891 (OpNode (_.VT _.RC:$src1),
3892 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3894 EVEX_CD8<_.EltSize, CD8VF>;
3897 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3898 X86VectorVTInfo _> {
3900 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3901 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3902 "${src2}"##_.BroadcastStr##", $src1",
3903 "$src1, ${src2}"##_.BroadcastStr,
3904 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3905 (_.ScalarLdFrag addr:$src2))))>,
3906 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3908 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3909 AVX512VLVectorVTInfo _> {
3910 let Predicates = [HasAVX512] in
3911 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3912 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3914 let Predicates = [HasAVX512, HasVLX] in {
3915 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3916 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3917 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3918 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3922 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3923 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3925 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3926 avx512vl_i64_info>, VEX_W;
3929 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3931 let Predicates = [HasBWI] in {
3932 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3934 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3937 let Predicates = [HasVLX, HasBWI] in {
3939 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3941 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3943 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3945 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3950 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3952 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3953 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3955 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3956 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3958 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3959 (v16i32 VR512:$src2), (i16 -1))),
3960 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3962 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3963 (v8i64 VR512:$src2), (i8 -1))),
3964 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3966 //===----------------------------------------------------------------------===//
3967 // AVX-512 Shift instructions
3968 //===----------------------------------------------------------------------===//
3969 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3970 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3971 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3972 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3973 "$src2, $src1", "$src1, $src2",
3974 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3975 SSE_INTSHIFT_ITINS_P.rr>;
3977 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3978 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3979 "$src2, $src1", "$src1, $src2",
3980 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3982 SSE_INTSHIFT_ITINS_P.rm>;
3985 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3986 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3988 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3989 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3990 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3991 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3992 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
3995 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3996 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3997 // src2 is always 128-bit
3998 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3999 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
4000 "$src2, $src1", "$src1, $src2",
4001 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
4002 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
4003 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4004 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
4005 "$src2, $src1", "$src1, $src2",
4006 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
4007 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
4011 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4012 ValueType SrcVT, PatFrag bc_frag,
4013 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
4014 let Predicates = [prd] in
4015 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4016 VTInfo.info512>, EVEX_V512,
4017 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
4018 let Predicates = [prd, HasVLX] in {
4019 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4020 VTInfo.info256>, EVEX_V256,
4021 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
4022 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
4023 VTInfo.info128>, EVEX_V128,
4024 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
4028 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
4029 string OpcodeStr, SDNode OpNode> {
4030 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
4031 avx512vl_i32_info, HasAVX512>;
4032 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
4033 avx512vl_i64_info, HasAVX512>, VEX_W;
4034 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
4035 avx512vl_i16_info, HasBWI>;
4038 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4039 string OpcodeStr, SDNode OpNode,
4040 AVX512VLVectorVTInfo VTInfo> {
4041 let Predicates = [HasAVX512] in
4042 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4044 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4045 VTInfo.info512>, EVEX_V512;
4046 let Predicates = [HasAVX512, HasVLX] in {
4047 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4049 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4050 VTInfo.info256>, EVEX_V256;
4051 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4053 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4054 VTInfo.info128>, EVEX_V128;
4058 multiclass avx512_shift_rmi_w<bits<8> opcw,
4059 Format ImmFormR, Format ImmFormM,
4060 string OpcodeStr, SDNode OpNode> {
4061 let Predicates = [HasBWI] in
4062 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4063 v32i16_info>, EVEX_V512;
4064 let Predicates = [HasVLX, HasBWI] in {
4065 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4066 v16i16x_info>, EVEX_V256;
4067 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4068 v8i16x_info>, EVEX_V128;
4072 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
4073 Format ImmFormR, Format ImmFormM,
4074 string OpcodeStr, SDNode OpNode> {
4075 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
4076 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
4077 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
4078 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
4081 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
4082 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
4084 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
4085 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
4087 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
4088 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
4090 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>, AVX512BIi8Base, EVEX_4V;
4091 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
4093 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
4094 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
4095 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
4097 //===-------------------------------------------------------------------===//
4098 // Variable Bit Shifts
4099 //===-------------------------------------------------------------------===//
4100 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
4101 X86VectorVTInfo _> {
4102 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4103 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4104 "$src2, $src1", "$src1, $src2",
4105 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
4106 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
4108 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4109 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4110 "$src2, $src1", "$src1, $src2",
4111 (_.VT (OpNode _.RC:$src1,
4112 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
4113 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
4114 EVEX_CD8<_.EltSize, CD8VF>;
4117 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
4118 X86VectorVTInfo _> {
4120 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4121 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4122 "${src2}"##_.BroadcastStr##", $src1",
4123 "$src1, ${src2}"##_.BroadcastStr,
4124 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4125 (_.ScalarLdFrag addr:$src2))))),
4126 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
4127 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4129 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4130 AVX512VLVectorVTInfo _> {
4131 let Predicates = [HasAVX512] in
4132 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4133 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4135 let Predicates = [HasAVX512, HasVLX] in {
4136 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4137 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4138 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
4139 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
4143 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
4145 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
4147 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
4148 avx512vl_i64_info>, VEX_W;
4151 // Use 512bit version to implement 128/256 bit in case NoVLX.
4152 multiclass avx512_var_shift_w_lowering<AVX512VLVectorVTInfo _, SDNode OpNode> {
4153 let Predicates = [HasBWI, NoVLX] in {
4154 def : Pat<(_.info256.VT (OpNode (_.info256.VT _.info256.RC:$src1),
4155 (_.info256.VT _.info256.RC:$src2))),
4157 (!cast<Instruction>(NAME#"WZrr")
4158 (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR256X:$src1, sub_ymm),
4159 (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR256X:$src2, sub_ymm)),
4162 def : Pat<(_.info128.VT (OpNode (_.info128.VT _.info128.RC:$src1),
4163 (_.info128.VT _.info128.RC:$src2))),
4165 (!cast<Instruction>(NAME#"WZrr")
4166 (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR128X:$src1, sub_xmm),
4167 (INSERT_SUBREG (_.info512.VT (IMPLICIT_DEF)), VR128X:$src2, sub_xmm)),
4172 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
4174 let Predicates = [HasBWI] in
4175 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
4177 let Predicates = [HasVLX, HasBWI] in {
4179 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
4181 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
4186 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
4187 avx512_var_shift_w<0x12, "vpsllvw", shl>,
4188 avx512_var_shift_w_lowering<avx512vl_i16_info, shl>;
4189 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
4190 avx512_var_shift_w<0x11, "vpsravw", sra>,
4191 avx512_var_shift_w_lowering<avx512vl_i16_info, sra>;
4192 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
4193 avx512_var_shift_w<0x10, "vpsrlvw", srl>,
4194 avx512_var_shift_w_lowering<avx512vl_i16_info, srl>;
4195 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
4196 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
4198 //===-------------------------------------------------------------------===//
4199 // 1-src variable permutation VPERMW/D/Q
4200 //===-------------------------------------------------------------------===//
4201 multiclass avx512_vperm_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4202 AVX512VLVectorVTInfo _> {
4203 let Predicates = [HasAVX512] in
4204 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4205 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4207 let Predicates = [HasAVX512, HasVLX] in
4208 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4209 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4212 multiclass avx512_vpermi_dq_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4213 string OpcodeStr, SDNode OpNode,
4214 AVX512VLVectorVTInfo VTInfo> {
4215 let Predicates = [HasAVX512] in
4216 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4218 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4219 VTInfo.info512>, EVEX_V512;
4220 let Predicates = [HasAVX512, HasVLX] in
4221 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4223 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4224 VTInfo.info256>, EVEX_V256;
4228 defm VPERM : avx512_var_shift_w<0x8D, "vpermw", X86VPermv>;
4230 defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv,
4232 defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv,
4233 avx512vl_i64_info>, VEX_W;
4234 defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv,
4236 defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv,
4237 avx512vl_f64_info>, VEX_W;
4239 defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq",
4240 X86VPermi, avx512vl_i64_info>,
4241 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4242 defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
4243 X86VPermi, avx512vl_f64_info>,
4244 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4245 //===----------------------------------------------------------------------===//
4246 // AVX-512 - VPERMIL
4247 //===----------------------------------------------------------------------===//
4249 multiclass avx512_permil_vec<bits<8> OpcVar, string OpcodeStr, SDNode OpNode,
4250 X86VectorVTInfo _, X86VectorVTInfo Ctrl> {
4251 defm rr: AVX512_maskable<OpcVar, MRMSrcReg, _, (outs _.RC:$dst),
4252 (ins _.RC:$src1, Ctrl.RC:$src2), OpcodeStr,
4253 "$src2, $src1", "$src1, $src2",
4254 (_.VT (OpNode _.RC:$src1,
4255 (Ctrl.VT Ctrl.RC:$src2)))>,
4257 let mayLoad = 1 in {
4258 defm rm: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4259 (ins _.RC:$src1, Ctrl.MemOp:$src2), OpcodeStr,
4260 "$src2, $src1", "$src1, $src2",
4263 (Ctrl.VT (bitconvert(Ctrl.LdFrag addr:$src2)))))>,
4264 T8PD, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4265 defm rmb: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4266 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4267 "${src2}"##_.BroadcastStr##", $src1",
4268 "$src1, ${src2}"##_.BroadcastStr,
4271 (Ctrl.VT (X86VBroadcast
4272 (Ctrl.ScalarLdFrag addr:$src2)))))>,
4273 T8PD, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
4277 multiclass avx512_permil_vec_common<string OpcodeStr, bits<8> OpcVar,
4278 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4279 let Predicates = [HasAVX512] in {
4280 defm Z : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info512,
4281 Ctrl.info512>, EVEX_V512;
4283 let Predicates = [HasAVX512, HasVLX] in {
4284 defm Z128 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info128,
4285 Ctrl.info128>, EVEX_V128;
4286 defm Z256 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info256,
4287 Ctrl.info256>, EVEX_V256;
4291 multiclass avx512_permil<string OpcodeStr, bits<8> OpcImm, bits<8> OpcVar,
4292 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4294 defm NAME: avx512_permil_vec_common<OpcodeStr, OpcVar, _, Ctrl>;
4295 defm NAME: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem, OpcodeStr,
4297 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4300 defm VPERMILPS : avx512_permil<"vpermilps", 0x04, 0x0C, avx512vl_f32_info,
4302 defm VPERMILPD : avx512_permil<"vpermilpd", 0x05, 0x0D, avx512vl_f64_info,
4303 avx512vl_i64_info>, VEX_W;
4304 //===----------------------------------------------------------------------===//
4305 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
4306 //===----------------------------------------------------------------------===//
4308 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
4309 X86PShufd, avx512vl_i32_info>,
4310 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
4311 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
4312 X86PShufhw>, EVEX, AVX512XSIi8Base;
4313 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
4314 X86PShuflw>, EVEX, AVX512XDIi8Base;
4316 multiclass avx512_pshufb_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4317 let Predicates = [HasBWI] in
4318 defm Z: avx512_var_shift<opc, OpcodeStr, OpNode, v64i8_info>, EVEX_V512;
4320 let Predicates = [HasVLX, HasBWI] in {
4321 defm Z256: avx512_var_shift<opc, OpcodeStr, OpNode, v32i8x_info>, EVEX_V256;
4322 defm Z128: avx512_var_shift<opc, OpcodeStr, OpNode, v16i8x_info>, EVEX_V128;
4326 defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb>;
4328 //===----------------------------------------------------------------------===//
4329 // Move Low to High and High to Low packed FP Instructions
4330 //===----------------------------------------------------------------------===//
4331 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
4332 (ins VR128X:$src1, VR128X:$src2),
4333 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4334 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
4335 IIC_SSE_MOV_LH>, EVEX_4V;
4336 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
4337 (ins VR128X:$src1, VR128X:$src2),
4338 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4339 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
4340 IIC_SSE_MOV_LH>, EVEX_4V;
4342 let Predicates = [HasAVX512] in {
4344 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4345 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
4346 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4347 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
4350 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
4351 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
4354 //===----------------------------------------------------------------------===//
4355 // VMOVHPS/PD VMOVLPS Instructions
4356 // All patterns was taken from SSS implementation.
4357 //===----------------------------------------------------------------------===//
4358 multiclass avx512_mov_hilo_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
4359 X86VectorVTInfo _> {
4361 def rm : AVX512<opc, MRMSrcMem, (outs _.RC:$dst),
4362 (ins _.RC:$src1, f64mem:$src2),
4363 !strconcat(OpcodeStr,
4364 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4368 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))))))],
4369 IIC_SSE_MOV_LH>, EVEX_4V;
4372 defm VMOVHPSZ128 : avx512_mov_hilo_packed<0x16, "vmovhps", X86Movlhps,
4373 v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS;
4374 defm VMOVHPDZ128 : avx512_mov_hilo_packed<0x16, "vmovhpd", X86Movlhpd,
4375 v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W;
4376 defm VMOVLPSZ128 : avx512_mov_hilo_packed<0x12, "vmovlps", X86Movlps,
4377 v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS;
4378 defm VMOVLPDZ128 : avx512_mov_hilo_packed<0x12, "vmovlpd", X86Movlpd,
4379 v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W;
4381 let Predicates = [HasAVX512] in {
4383 def : Pat<(X86Movlhps VR128X:$src1,
4384 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
4385 (VMOVHPSZ128rm VR128X:$src1, addr:$src2)>;
4386 def : Pat<(X86Movlhps VR128X:$src1,
4387 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
4388 (VMOVHPSZ128rm VR128X:$src1, addr:$src2)>;
4390 def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
4391 (scalar_to_vector (loadf64 addr:$src2)))),
4392 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
4393 def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
4394 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
4395 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
4397 def : Pat<(v4f32 (X86Movlps VR128X:$src1, (load addr:$src2))),
4398 (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
4399 def : Pat<(v4i32 (X86Movlps VR128X:$src1, (load addr:$src2))),
4400 (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
4402 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, (load addr:$src2))),
4403 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4404 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, (load addr:$src2))),
4405 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4406 def : Pat<(v2f64 (X86Movsd VR128X:$src1,
4407 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
4408 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4411 let mayStore = 1 in {
4412 def VMOVHPSZ128mr : AVX512PSI<0x17, MRMDestMem, (outs),
4413 (ins f64mem:$dst, VR128X:$src),
4414 "vmovhps\t{$src, $dst|$dst, $src}",
4415 [(store (f64 (vector_extract
4416 (X86Unpckh (bc_v2f64 (v4f32 VR128X:$src)),
4417 (bc_v2f64 (v4f32 VR128X:$src))),
4418 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>,
4419 EVEX, EVEX_CD8<32, CD8VT2>;
4420 def VMOVHPDZ128mr : AVX512PDI<0x17, MRMDestMem, (outs),
4421 (ins f64mem:$dst, VR128X:$src),
4422 "vmovhpd\t{$src, $dst|$dst, $src}",
4423 [(store (f64 (vector_extract
4424 (v2f64 (X86Unpckh VR128X:$src, VR128X:$src)),
4425 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>,
4426 EVEX, EVEX_CD8<64, CD8VT1>, VEX_W;
4427 def VMOVLPSZ128mr : AVX512PSI<0x13, MRMDestMem, (outs),
4428 (ins f64mem:$dst, VR128X:$src),
4429 "vmovlps\t{$src, $dst|$dst, $src}",
4430 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128X:$src)),
4431 (iPTR 0))), addr:$dst)],
4433 EVEX, EVEX_CD8<32, CD8VT2>;
4434 def VMOVLPDZ128mr : AVX512PDI<0x13, MRMDestMem, (outs),
4435 (ins f64mem:$dst, VR128X:$src),
4436 "vmovlpd\t{$src, $dst|$dst, $src}",
4437 [(store (f64 (vector_extract (v2f64 VR128X:$src),
4438 (iPTR 0))), addr:$dst)],
4440 EVEX, EVEX_CD8<64, CD8VT1>, VEX_W;
4442 let Predicates = [HasAVX512] in {
4444 def : Pat<(store (f64 (vector_extract
4445 (v2f64 (X86VPermilpi VR128X:$src, (i8 1))),
4446 (iPTR 0))), addr:$dst),
4447 (VMOVHPDZ128mr addr:$dst, VR128X:$src)>;
4449 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128X:$src2)),
4451 (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
4452 def : Pat<(store (v4i32 (X86Movlps
4453 (bc_v4i32 (loadv2i64 addr:$src1)), VR128X:$src2)), addr:$src1),
4454 (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
4456 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128X:$src2)),
4458 (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
4459 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128X:$src2)),
4461 (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
4463 //===----------------------------------------------------------------------===//
4464 // FMA - Fused Multiply Operations
4467 let Constraints = "$src1 = $dst" in {
4468 multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4469 X86VectorVTInfo _> {
4470 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4471 (ins _.RC:$src2, _.RC:$src3),
4472 OpcodeStr, "$src3, $src2", "$src2, $src3",
4473 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4476 let mayLoad = 1 in {
4477 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4478 (ins _.RC:$src2, _.MemOp:$src3),
4479 OpcodeStr, "$src3, $src2", "$src2, $src3",
4480 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
4483 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4484 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4485 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
4486 !strconcat("$src2, ${src3}", _.BroadcastStr ),
4488 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
4489 AVX512FMA3Base, EVEX_B;
4493 multiclass avx512_fma3_213_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4494 X86VectorVTInfo _> {
4495 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4496 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4497 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4498 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4499 AVX512FMA3Base, EVEX_B, EVEX_RC;
4501 } // Constraints = "$src1 = $dst"
4503 multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4504 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4505 let Predicates = [HasAVX512] in {
4506 defm Z : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info512>,
4507 avx512_fma3_213_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4508 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4510 let Predicates = [HasVLX, HasAVX512] in {
4511 defm Z256 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info256>,
4512 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4513 defm Z128 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info128>,
4514 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4518 multiclass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4519 SDNode OpNodeRnd > {
4520 defm PS : avx512_fma3p_213_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4522 defm PD : avx512_fma3p_213_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4523 avx512vl_f64_info>, VEX_W;
4526 defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86Fmadd, X86FmaddRnd>;
4527 defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86Fmsub, X86FmsubRnd>;
4528 defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub, X86FmaddsubRnd>;
4529 defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd, X86FmsubaddRnd>;
4530 defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86Fnmadd, X86FnmaddRnd>;
4531 defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86Fnmsub, X86FnmsubRnd>;
4534 let Constraints = "$src1 = $dst" in {
4535 multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4536 X86VectorVTInfo _> {
4537 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4538 (ins _.RC:$src2, _.RC:$src3),
4539 OpcodeStr, "$src3, $src2", "$src2, $src3",
4540 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1))>,
4543 let mayLoad = 1 in {
4544 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4545 (ins _.RC:$src2, _.MemOp:$src3),
4546 OpcodeStr, "$src3, $src2", "$src2, $src3",
4547 (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1))>,
4550 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4551 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4552 OpcodeStr, "${src3}"##_.BroadcastStr##", $src2",
4553 "$src2, ${src3}"##_.BroadcastStr,
4554 (_.VT (OpNode _.RC:$src2,
4555 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
4556 _.RC:$src1))>, AVX512FMA3Base, EVEX_B;
4560 multiclass avx512_fma3_231_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4561 X86VectorVTInfo _> {
4562 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4563 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4564 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4565 (_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc)))>,
4566 AVX512FMA3Base, EVEX_B, EVEX_RC;
4568 } // Constraints = "$src1 = $dst"
4570 multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4571 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4572 let Predicates = [HasAVX512] in {
4573 defm Z : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info512>,
4574 avx512_fma3_231_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4575 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4577 let Predicates = [HasVLX, HasAVX512] in {
4578 defm Z256 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info256>,
4579 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4580 defm Z128 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info128>,
4581 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4585 multiclass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4586 SDNode OpNodeRnd > {
4587 defm PS : avx512_fma3p_231_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4589 defm PD : avx512_fma3p_231_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4590 avx512vl_f64_info>, VEX_W;
4593 defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86Fmadd, X86FmaddRnd>;
4594 defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86Fmsub, X86FmsubRnd>;
4595 defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub, X86FmaddsubRnd>;
4596 defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd, X86FmsubaddRnd>;
4597 defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86Fnmadd, X86FnmaddRnd>;
4598 defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86Fnmsub, X86FnmsubRnd>;
4600 let Constraints = "$src1 = $dst" in {
4601 multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4602 X86VectorVTInfo _> {
4603 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4604 (ins _.RC:$src3, _.RC:$src2),
4605 OpcodeStr, "$src2, $src3", "$src3, $src2",
4606 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4609 let mayLoad = 1 in {
4610 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4611 (ins _.RC:$src3, _.MemOp:$src2),
4612 OpcodeStr, "$src2, $src3", "$src3, $src2",
4613 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2), _.RC:$src3))>,
4616 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4617 (ins _.RC:$src3, _.ScalarMemOp:$src2),
4618 OpcodeStr, "${src2}"##_.BroadcastStr##", $src3",
4619 "$src3, ${src2}"##_.BroadcastStr,
4620 (_.VT (OpNode _.RC:$src1,
4621 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
4622 _.RC:$src3))>, AVX512FMA3Base, EVEX_B;
4626 multiclass avx512_fma3_132_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4627 X86VectorVTInfo _> {
4628 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4629 (ins _.RC:$src3, _.RC:$src2, AVX512RC:$rc),
4630 OpcodeStr, "$rc, $src2, $src3", "$src3, $src2, $rc",
4631 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4632 AVX512FMA3Base, EVEX_B, EVEX_RC;
4634 } // Constraints = "$src1 = $dst"
4636 multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4637 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4638 let Predicates = [HasAVX512] in {
4639 defm Z : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info512>,
4640 avx512_fma3_132_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4641 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4643 let Predicates = [HasVLX, HasAVX512] in {
4644 defm Z256 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info256>,
4645 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4646 defm Z128 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info128>,
4647 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4651 multiclass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4652 SDNode OpNodeRnd > {
4653 defm PS : avx512_fma3p_132_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4655 defm PD : avx512_fma3p_132_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4656 avx512vl_f64_info>, VEX_W;
4659 defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86Fmadd, X86FmaddRnd>;
4660 defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86Fmsub, X86FmsubRnd>;
4661 defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub, X86FmaddsubRnd>;
4662 defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd, X86FmsubaddRnd>;
4663 defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86Fnmadd, X86FnmaddRnd>;
4664 defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubRnd>;
4667 let Constraints = "$src1 = $dst" in {
4668 multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4669 dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
4670 dag RHS_r, dag RHS_m > {
4671 defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4672 (ins _.RC:$src2, _.RC:$src3), OpcodeStr,
4673 "$src3, $src2", "$src2, $src3", RHS_VEC_r>, AVX512FMA3Base;
4676 defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4677 (ins _.RC:$src2, _.MemOp:$src3), OpcodeStr,
4678 "$src3, $src2", "$src2, $src3", RHS_VEC_m>, AVX512FMA3Base;
4680 defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4681 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4682 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb>,
4683 AVX512FMA3Base, EVEX_B, EVEX_RC;
4685 let isCodeGenOnly = 1 in {
4686 def r : AVX512FMA3<opc, MRMSrcReg, (outs _.FRC:$dst),
4687 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
4688 !strconcat(OpcodeStr,
4689 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4692 def m : AVX512FMA3<opc, MRMSrcMem, (outs _.FRC:$dst),
4693 (ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
4694 !strconcat(OpcodeStr,
4695 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4697 }// isCodeGenOnly = 1
4699 }// Constraints = "$src1 = $dst"
4701 multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4702 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd, X86VectorVTInfo _ ,
4705 defm NAME#213#SUFF: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix , _ ,
4706 (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)),
4707 (_.VT (OpNode _.RC:$src2, _.RC:$src1,
4708 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))))),
4709 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src1, _.RC:$src3,
4711 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4713 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4714 (_.ScalarLdFrag addr:$src3))))>;
4716 defm NAME#231#SUFF: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix , _ ,
4717 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)),
4718 (_.VT (OpNode _.RC:$src2,
4719 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4721 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src3, _.RC:$src1,
4723 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
4725 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
4726 (_.ScalarLdFrag addr:$src3), _.FRC:$src1)))>;
4728 defm NAME#132#SUFF: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix , _ ,
4729 (_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)),
4730 (_.VT (OpNode _.RC:$src1,
4731 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4733 (_.VT ( OpNodeRnd _.RC:$src1, _.RC:$src3, _.RC:$src2,
4735 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
4737 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1,
4738 (_.ScalarLdFrag addr:$src3), _.FRC:$src2)))>;
4741 multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4742 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd>{
4743 let Predicates = [HasAVX512] in {
4744 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4745 OpNodeRnd, f32x_info, "SS">,
4746 EVEX_CD8<32, CD8VT1>, VEX_LIG;
4747 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4748 OpNodeRnd, f64x_info, "SD">,
4749 EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
4753 defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>;
4754 defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>;
4755 defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4756 defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4758 //===----------------------------------------------------------------------===//
4759 // AVX-512 Scalar convert from sign integer to float/double
4760 //===----------------------------------------------------------------------===//
4762 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4763 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4764 PatFrag ld_frag, string asm> {
4765 let hasSideEffects = 0 in {
4766 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
4767 (ins DstVT.FRC:$src1, SrcRC:$src),
4768 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4771 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
4772 (ins DstVT.FRC:$src1, x86memop:$src),
4773 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4775 } // hasSideEffects = 0
4776 let isCodeGenOnly = 1 in {
4777 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4778 (ins DstVT.RC:$src1, SrcRC:$src2),
4779 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4780 [(set DstVT.RC:$dst,
4781 (OpNode (DstVT.VT DstVT.RC:$src1),
4783 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4785 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
4786 (ins DstVT.RC:$src1, x86memop:$src2),
4787 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4788 [(set DstVT.RC:$dst,
4789 (OpNode (DstVT.VT DstVT.RC:$src1),
4790 (ld_frag addr:$src2),
4791 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4792 }//isCodeGenOnly = 1
4795 multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4796 X86VectorVTInfo DstVT, string asm> {
4797 def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4798 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
4800 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
4801 [(set DstVT.RC:$dst,
4802 (OpNode (DstVT.VT DstVT.RC:$src1),
4804 (i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
4807 multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4808 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4809 PatFrag ld_frag, string asm> {
4810 defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
4811 avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
4815 let Predicates = [HasAVX512] in {
4816 defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4817 v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
4818 XS, EVEX_CD8<32, CD8VT1>;
4819 defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4820 v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
4821 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4822 defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4823 v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
4824 XD, EVEX_CD8<32, CD8VT1>;
4825 defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4826 v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
4827 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4829 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4830 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4831 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4832 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4833 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4834 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4835 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4836 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4838 def : Pat<(f32 (sint_to_fp GR32:$src)),
4839 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4840 def : Pat<(f32 (sint_to_fp GR64:$src)),
4841 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4842 def : Pat<(f64 (sint_to_fp GR32:$src)),
4843 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4844 def : Pat<(f64 (sint_to_fp GR64:$src)),
4845 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4847 defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR32,
4848 v4f32x_info, i32mem, loadi32,
4849 "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
4850 defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4851 v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
4852 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4853 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86UintToFpRnd, GR32, v2f64x_info,
4854 i32mem, loadi32, "cvtusi2sd{l}">,
4855 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4856 defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4857 v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
4858 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4860 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4861 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4862 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4863 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4864 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4865 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4866 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4867 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4869 def : Pat<(f32 (uint_to_fp GR32:$src)),
4870 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4871 def : Pat<(f32 (uint_to_fp GR64:$src)),
4872 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4873 def : Pat<(f64 (uint_to_fp GR32:$src)),
4874 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4875 def : Pat<(f64 (uint_to_fp GR64:$src)),
4876 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4879 //===----------------------------------------------------------------------===//
4880 // AVX-512 Scalar convert from float/double to integer
4881 //===----------------------------------------------------------------------===//
4882 multiclass avx512_cvt_s_int_round<bits<8> opc, RegisterClass SrcRC,
4883 RegisterClass DstRC, Intrinsic Int,
4884 Operand memop, ComplexPattern mem_cpat, string asm> {
4885 let hasSideEffects = 0, Predicates = [HasAVX512] in {
4886 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4887 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4888 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
4889 def rb : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4890 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"), []>,
4891 EVEX, VEX_LIG, EVEX_B, EVEX_RC;
4893 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4894 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
4895 } // hasSideEffects = 0, Predicates = [HasAVX512]
4898 // Convert float/double to signed/unsigned int 32/64
4899 defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4900 ssmem, sse_load_f32, "cvtss2si">,
4901 XS, EVEX_CD8<32, CD8VT1>;
4902 defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4903 int_x86_sse_cvtss2si64,
4904 ssmem, sse_load_f32, "cvtss2si">,
4905 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4906 defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4907 int_x86_avx512_cvtss2usi,
4908 ssmem, sse_load_f32, "cvtss2usi">,
4909 XS, EVEX_CD8<32, CD8VT1>;
4910 defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4911 int_x86_avx512_cvtss2usi64, ssmem,
4912 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4913 EVEX_CD8<32, CD8VT1>;
4914 defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4915 sdmem, sse_load_f64, "cvtsd2si">,
4916 XD, EVEX_CD8<64, CD8VT1>;
4917 defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4918 int_x86_sse2_cvtsd2si64,
4919 sdmem, sse_load_f64, "cvtsd2si">,
4920 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4921 defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4922 int_x86_avx512_cvtsd2usi,
4923 sdmem, sse_load_f64, "cvtsd2usi">,
4924 XD, EVEX_CD8<64, CD8VT1>;
4925 defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4926 int_x86_avx512_cvtsd2usi64, sdmem,
4927 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4928 EVEX_CD8<64, CD8VT1>;
4930 let isCodeGenOnly = 1 , Predicates = [HasAVX512] in {
4931 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4932 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4933 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4934 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4935 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4936 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4937 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4938 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4939 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4940 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4941 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4942 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4944 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4945 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4946 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4947 } // isCodeGenOnly = 1, Predicates = [HasAVX512]
4949 // Convert float/double to signed/unsigned int 32/64 with truncation
4950 multiclass avx512_cvt_s_all<bits<8> opc, string asm, X86VectorVTInfo _SrcRC,
4951 X86VectorVTInfo _DstRC, SDNode OpNode,
4953 let Predicates = [HasAVX512] in {
4954 def rr : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4955 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4956 [(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))]>, EVEX;
4957 def rb : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4958 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4960 def rm : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.MemOp:$src),
4961 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4962 [(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src)))]>,
4965 let isCodeGenOnly = 1,hasSideEffects = 0 in {
4966 def rr_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4967 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4968 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4969 (i32 FROUND_CURRENT)))]>, EVEX, VEX_LIG;
4970 def rb_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4971 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4972 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4973 (i32 FROUND_NO_EXC)))]>,
4974 EVEX,VEX_LIG , EVEX_B;
4976 def rm_Int : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst),
4977 (ins _SrcRC.MemOp:$src),
4978 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4981 } // isCodeGenOnly = 1, hasSideEffects = 0
4986 defm VCVTTSS2SIZ: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i32x_info,
4987 fp_to_sint,X86cvttss2IntRnd>,
4988 XS, EVEX_CD8<32, CD8VT1>;
4989 defm VCVTTSS2SI64Z: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i64x_info,
4990 fp_to_sint,X86cvttss2IntRnd>,
4991 VEX_W, XS, EVEX_CD8<32, CD8VT1>;
4992 defm VCVTTSD2SIZ: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i32x_info,
4993 fp_to_sint,X86cvttsd2IntRnd>,
4994 XD, EVEX_CD8<64, CD8VT1>;
4995 defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i64x_info,
4996 fp_to_sint,X86cvttsd2IntRnd>,
4997 VEX_W, XD, EVEX_CD8<64, CD8VT1>;
4999 defm VCVTTSS2USIZ: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i32x_info,
5000 fp_to_uint,X86cvttss2UIntRnd>,
5001 XS, EVEX_CD8<32, CD8VT1>;
5002 defm VCVTTSS2USI64Z: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i64x_info,
5003 fp_to_uint,X86cvttss2UIntRnd>,
5004 XS,VEX_W, EVEX_CD8<32, CD8VT1>;
5005 defm VCVTTSD2USIZ: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i32x_info,
5006 fp_to_uint,X86cvttsd2UIntRnd>,
5007 XD, EVEX_CD8<64, CD8VT1>;
5008 defm VCVTTSD2USI64Z: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i64x_info,
5009 fp_to_uint,X86cvttsd2UIntRnd>,
5010 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
5011 let Predicates = [HasAVX512] in {
5012 def : Pat<(i32 (int_x86_sse_cvttss2si (v4f32 VR128X:$src))),
5013 (VCVTTSS2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
5014 def : Pat<(i64 (int_x86_sse_cvttss2si64 (v4f32 VR128X:$src))),
5015 (VCVTTSS2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
5016 def : Pat<(i32 (int_x86_sse2_cvttsd2si (v2f64 VR128X:$src))),
5017 (VCVTTSD2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
5018 def : Pat<(i64 (int_x86_sse2_cvttsd2si64 (v2f64 VR128X:$src))),
5019 (VCVTTSD2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
5022 //===----------------------------------------------------------------------===//
5023 // AVX-512 Convert form float to double and back
5024 //===----------------------------------------------------------------------===//
5025 multiclass avx512_cvt_fp_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5026 X86VectorVTInfo _Src, SDNode OpNode> {
5027 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5028 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
5029 "$src2, $src1", "$src1, $src2",
5030 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
5031 (_Src.VT _Src.RC:$src2)))>,
5032 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
5033 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5034 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
5035 "$src2, $src1", "$src1, $src2",
5036 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
5037 (_Src.VT (scalar_to_vector
5038 (_Src.ScalarLdFrag addr:$src2)))))>,
5039 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>;
5042 // Scalar Coversion with SAE - suppress all exceptions
5043 multiclass avx512_cvt_fp_sae_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5044 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5045 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5046 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
5047 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5048 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
5049 (_Src.VT _Src.RC:$src2),
5050 (i32 FROUND_NO_EXC)))>,
5051 EVEX_4V, VEX_LIG, EVEX_B;
5054 // Scalar Conversion with rounding control (RC)
5055 multiclass avx512_cvt_fp_rc_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5056 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5057 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5058 (ins _Src.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr,
5059 "$rc, $src2, $src1", "$src1, $src2, $rc",
5060 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
5061 (_Src.VT _Src.RC:$src2), (i32 imm:$rc)))>,
5062 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
5065 multiclass avx512_cvt_fp_scalar_sd2ss<bits<8> opc, string OpcodeStr, SDNode OpNode,
5066 SDNode OpNodeRnd, X86VectorVTInfo _src,
5067 X86VectorVTInfo _dst> {
5068 let Predicates = [HasAVX512] in {
5069 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
5070 avx512_cvt_fp_rc_scalar<opc, OpcodeStr, _dst, _src,
5071 OpNodeRnd>, VEX_W, EVEX_CD8<64, CD8VT1>,
5076 multiclass avx512_cvt_fp_scalar_ss2sd<bits<8> opc, string OpcodeStr, SDNode OpNode,
5077 SDNode OpNodeRnd, X86VectorVTInfo _src,
5078 X86VectorVTInfo _dst> {
5079 let Predicates = [HasAVX512] in {
5080 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
5081 avx512_cvt_fp_sae_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>,
5082 EVEX_CD8<32, CD8VT1>, XS, EVEX_V512;
5085 defm VCVTSD2SS : avx512_cvt_fp_scalar_sd2ss<0x5A, "vcvtsd2ss", X86fround,
5086 X86froundRnd, f64x_info, f32x_info>;
5087 defm VCVTSS2SD : avx512_cvt_fp_scalar_ss2sd<0x5A, "vcvtss2sd", X86fpext,
5088 X86fpextRnd,f32x_info, f64x_info >;
5090 def : Pat<(f64 (fextend FR32X:$src)),
5091 (COPY_TO_REGCLASS (VCVTSS2SDZrr (COPY_TO_REGCLASS FR32X:$src, VR128X),
5092 (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>,
5093 Requires<[HasAVX512]>;
5094 def : Pat<(f64 (fextend (loadf32 addr:$src))),
5095 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5096 Requires<[HasAVX512]>;
5098 def : Pat<(f64 (extloadf32 addr:$src)),
5099 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5100 Requires<[HasAVX512, OptForSize]>;
5102 def : Pat<(f64 (extloadf32 addr:$src)),
5103 (COPY_TO_REGCLASS (VCVTSS2SDZrr (v4f32 (IMPLICIT_DEF)),
5104 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)), VR128X)>,
5105 Requires<[HasAVX512, OptForSpeed]>;
5107 def : Pat<(f32 (fround FR64X:$src)),
5108 (COPY_TO_REGCLASS (VCVTSD2SSZrr (COPY_TO_REGCLASS FR64X:$src, VR128X),
5109 (COPY_TO_REGCLASS FR64X:$src, VR128X)), VR128X)>,
5110 Requires<[HasAVX512]>;
5111 //===----------------------------------------------------------------------===//
5112 // AVX-512 Vector convert from signed/unsigned integer to float/double
5113 // and from float/double to signed/unsigned integer
5114 //===----------------------------------------------------------------------===//
5116 multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5117 X86VectorVTInfo _Src, SDNode OpNode,
5118 string Broadcast = _.BroadcastStr,
5119 string Alias = ""> {
5121 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5122 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
5123 (_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
5125 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5126 (ins _Src.MemOp:$src), OpcodeStr#Alias, "$src", "$src",
5127 (_.VT (OpNode (_Src.VT
5128 (bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
5130 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5131 (ins _Src.MemOp:$src), OpcodeStr,
5132 "${src}"##Broadcast, "${src}"##Broadcast,
5133 (_.VT (OpNode (_Src.VT
5134 (X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
5137 // Coversion with SAE - suppress all exceptions
5138 multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5139 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5140 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5141 (ins _Src.RC:$src), OpcodeStr,
5142 "{sae}, $src", "$src, {sae}",
5143 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src),
5144 (i32 FROUND_NO_EXC)))>,
5148 // Conversion with rounding control (RC)
5149 multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5150 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5151 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5152 (ins _Src.RC:$src, AVX512RC:$rc), OpcodeStr,
5153 "$rc, $src", "$src, $rc",
5154 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc)))>,
5155 EVEX, EVEX_B, EVEX_RC;
5158 // Extend Float to Double
5159 multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
5160 let Predicates = [HasAVX512] in {
5161 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fextend>,
5162 avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
5163 X86vfpextRnd>, EVEX_V512;
5165 let Predicates = [HasVLX] in {
5166 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
5167 X86vfpext, "{1to2}">, EVEX_V128;
5168 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fextend>,
5173 // Truncate Double to Float
5174 multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
5175 let Predicates = [HasAVX512] in {
5176 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fround>,
5177 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
5178 X86vfproundRnd>, EVEX_V512;
5180 let Predicates = [HasVLX] in {
5181 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
5182 X86vfpround, "{1to2}", "{x}">, EVEX_V128;
5183 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fround,
5184 "{1to4}", "{y}">, EVEX_V256;
5188 defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps">,
5189 VEX_W, PD, EVEX_CD8<64, CD8VF>;
5190 defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd">,
5191 PS, EVEX_CD8<32, CD8VH>;
5193 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5194 (VCVTPS2PDZrm addr:$src)>;
5196 let Predicates = [HasVLX] in {
5197 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
5198 (VCVTPS2PDZ256rm addr:$src)>;
5201 // Convert Signed/Unsigned Doubleword to Double
5202 multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
5204 // No rounding in this op
5205 let Predicates = [HasAVX512] in
5206 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode>,
5209 let Predicates = [HasVLX] in {
5210 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
5211 OpNode128, "{1to2}">, EVEX_V128;
5212 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
5217 // Convert Signed/Unsigned Doubleword to Float
5218 multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
5220 let Predicates = [HasAVX512] in
5221 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode>,
5222 avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
5223 OpNodeRnd>, EVEX_V512;
5225 let Predicates = [HasVLX] in {
5226 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode>,
5228 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode>,
5233 // Convert Float to Signed/Unsigned Doubleword with truncation
5234 multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr,
5235 SDNode OpNode, SDNode OpNodeRnd> {
5236 let Predicates = [HasAVX512] in {
5237 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5238 avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
5239 OpNodeRnd>, EVEX_V512;
5241 let Predicates = [HasVLX] in {
5242 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5244 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5249 // Convert Float to Signed/Unsigned Doubleword
5250 multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr,
5251 SDNode OpNode, SDNode OpNodeRnd> {
5252 let Predicates = [HasAVX512] in {
5253 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5254 avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
5255 OpNodeRnd>, EVEX_V512;
5257 let Predicates = [HasVLX] in {
5258 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5260 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5265 // Convert Double to Signed/Unsigned Doubleword with truncation
5266 multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr,
5267 SDNode OpNode, SDNode OpNodeRnd> {
5268 let Predicates = [HasAVX512] in {
5269 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5270 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
5271 OpNodeRnd>, EVEX_V512;
5273 let Predicates = [HasVLX] in {
5274 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5275 // memory forms of these instructions in Asm Parcer. They have the same
5276 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5277 // due to the same reason.
5278 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5279 "{1to2}", "{x}">, EVEX_V128;
5280 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5281 "{1to4}", "{y}">, EVEX_V256;
5285 // Convert Double to Signed/Unsigned Doubleword
5286 multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr,
5287 SDNode OpNode, SDNode OpNodeRnd> {
5288 let Predicates = [HasAVX512] in {
5289 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5290 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
5291 OpNodeRnd>, EVEX_V512;
5293 let Predicates = [HasVLX] in {
5294 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5295 // memory forms of these instructions in Asm Parcer. They have the same
5296 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5297 // due to the same reason.
5298 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5299 "{1to2}", "{x}">, EVEX_V128;
5300 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5301 "{1to4}", "{y}">, EVEX_V256;
5305 // Convert Double to Signed/Unsigned Quardword
5306 multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr,
5307 SDNode OpNode, SDNode OpNodeRnd> {
5308 let Predicates = [HasDQI] in {
5309 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5310 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
5311 OpNodeRnd>, EVEX_V512;
5313 let Predicates = [HasDQI, HasVLX] in {
5314 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5316 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5321 // Convert Double to Signed/Unsigned Quardword with truncation
5322 multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr,
5323 SDNode OpNode, SDNode OpNodeRnd> {
5324 let Predicates = [HasDQI] in {
5325 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5326 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
5327 OpNodeRnd>, EVEX_V512;
5329 let Predicates = [HasDQI, HasVLX] in {
5330 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5332 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5337 // Convert Signed/Unsigned Quardword to Double
5338 multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr,
5339 SDNode OpNode, SDNode OpNodeRnd> {
5340 let Predicates = [HasDQI] in {
5341 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode>,
5342 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
5343 OpNodeRnd>, EVEX_V512;
5345 let Predicates = [HasDQI, HasVLX] in {
5346 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode>,
5348 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode>,
5353 // Convert Float to Signed/Unsigned Quardword
5354 multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr,
5355 SDNode OpNode, SDNode OpNodeRnd> {
5356 let Predicates = [HasDQI] in {
5357 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5358 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
5359 OpNodeRnd>, EVEX_V512;
5361 let Predicates = [HasDQI, HasVLX] in {
5362 // Explicitly specified broadcast string, since we take only 2 elements
5363 // from v4f32x_info source
5364 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5365 "{1to2}">, EVEX_V128;
5366 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5371 // Convert Float to Signed/Unsigned Quardword with truncation
5372 multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr,
5373 SDNode OpNode, SDNode OpNodeRnd> {
5374 let Predicates = [HasDQI] in {
5375 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5376 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
5377 OpNodeRnd>, EVEX_V512;
5379 let Predicates = [HasDQI, HasVLX] in {
5380 // Explicitly specified broadcast string, since we take only 2 elements
5381 // from v4f32x_info source
5382 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5383 "{1to2}">, EVEX_V128;
5384 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5389 // Convert Signed/Unsigned Quardword to Float
5390 multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
5391 SDNode OpNode, SDNode OpNodeRnd> {
5392 let Predicates = [HasDQI] in {
5393 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
5394 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
5395 OpNodeRnd>, EVEX_V512;
5397 let Predicates = [HasDQI, HasVLX] in {
5398 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5399 // memory forms of these instructions in Asm Parcer. They have the same
5400 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5401 // due to the same reason.
5402 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode,
5403 "{1to2}", "{x}">, EVEX_V128;
5404 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
5405 "{1to4}", "{y}">, EVEX_V256;
5409 defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>, XS,
5410 EVEX_CD8<32, CD8VH>;
5412 defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
5414 PS, EVEX_CD8<32, CD8VF>;
5416 defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
5418 XS, EVEX_CD8<32, CD8VF>;
5420 defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint,
5422 PD, VEX_W, EVEX_CD8<64, CD8VF>;
5424 defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint,
5425 X86VFpToUintRnd>, PS,
5426 EVEX_CD8<32, CD8VF>;
5428 defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
5429 X86VFpToUintRnd>, PS, VEX_W,
5430 EVEX_CD8<64, CD8VF>;
5432 defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86cvtudq2pd>,
5433 XS, EVEX_CD8<32, CD8VH>;
5435 defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
5436 X86VUintToFpRnd>, XD,
5437 EVEX_CD8<32, CD8VF>;
5439 defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtps2Int,
5440 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
5442 defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtpd2Int,
5443 X86cvtpd2IntRnd>, XD, VEX_W,
5444 EVEX_CD8<64, CD8VF>;
5446 defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtps2UInt,
5448 PS, EVEX_CD8<32, CD8VF>;
5449 defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtpd2UInt,
5450 X86cvtpd2UIntRnd>, VEX_W,
5451 PS, EVEX_CD8<64, CD8VF>;
5453 defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtpd2Int,
5454 X86cvtpd2IntRnd>, VEX_W,
5455 PD, EVEX_CD8<64, CD8VF>;
5457 defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtps2Int,
5458 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
5460 defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtpd2UInt,
5461 X86cvtpd2UIntRnd>, VEX_W,
5462 PD, EVEX_CD8<64, CD8VF>;
5464 defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtps2UInt,
5465 X86cvtps2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
5467 defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint,
5468 X86VFpToSlongRnd>, VEX_W,
5469 PD, EVEX_CD8<64, CD8VF>;
5471 defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint,
5472 X86VFpToSlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5474 defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint,
5475 X86VFpToUlongRnd>, VEX_W,
5476 PD, EVEX_CD8<64, CD8VF>;
5478 defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint,
5479 X86VFpToUlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5481 defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
5482 X86VSlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5484 defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
5485 X86VUlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5487 defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp,
5488 X86VSlongToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
5490 defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
5491 X86VUlongToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
5493 let Predicates = [HasAVX512, NoVLX] in {
5494 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
5495 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5496 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5498 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
5499 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5500 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5502 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
5503 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5504 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5506 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
5507 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5508 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5510 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
5511 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
5512 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
5515 let Predicates = [HasAVX512] in {
5516 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
5517 (VCVTPD2PSZrm addr:$src)>;
5518 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5519 (VCVTPS2PDZrm addr:$src)>;
5522 //===----------------------------------------------------------------------===//
5523 // Half precision conversion instructions
5524 //===----------------------------------------------------------------------===//
5525 multiclass avx512_cvtph2ps<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5526 X86MemOperand x86memop, PatFrag ld_frag> {
5527 defm rr : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5528 "vcvtph2ps", "$src", "$src",
5529 (X86cvtph2ps (_src.VT _src.RC:$src),
5530 (i32 FROUND_CURRENT))>, T8PD;
5531 let hasSideEffects = 0, mayLoad = 1 in {
5532 defm rm : AVX512_maskable<0x13, MRMSrcMem, _dest, (outs _dest.RC:$dst), (ins x86memop:$src),
5533 "vcvtph2ps", "$src", "$src",
5534 (X86cvtph2ps (_src.VT (bitconvert (ld_frag addr:$src))),
5535 (i32 FROUND_CURRENT))>, T8PD;
5539 multiclass avx512_cvtph2ps_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
5540 defm rb : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5541 "vcvtph2ps", "{sae}, $src", "$src, {sae}",
5542 (X86cvtph2ps (_src.VT _src.RC:$src),
5543 (i32 FROUND_NO_EXC))>, T8PD, EVEX_B;
5547 let Predicates = [HasAVX512] in {
5548 defm VCVTPH2PSZ : avx512_cvtph2ps<v16f32_info, v16i16x_info, f256mem, loadv4i64>,
5549 avx512_cvtph2ps_sae<v16f32_info, v16i16x_info>,
5550 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5551 let Predicates = [HasVLX] in {
5552 defm VCVTPH2PSZ256 : avx512_cvtph2ps<v8f32x_info, v8i16x_info, f128mem,
5553 loadv2i64>,EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5554 defm VCVTPH2PSZ128 : avx512_cvtph2ps<v4f32x_info, v8i16x_info, f64mem,
5555 loadv2i64>, EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5559 multiclass avx512_cvtps2ph<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5560 X86MemOperand x86memop> {
5561 defm rr : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
5562 (ins _src.RC:$src1, i32u8imm:$src2),
5563 "vcvtps2ph", "$src2, $src1", "$src1, $src2",
5564 (X86cvtps2ph (_src.VT _src.RC:$src1),
5566 (i32 FROUND_CURRENT))>, AVX512AIi8Base;
5567 let hasSideEffects = 0, mayStore = 1 in {
5568 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
5569 (ins x86memop:$dst, _src.RC:$src1, i32u8imm:$src2),
5570 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5571 [(store (_dest.VT (X86cvtps2ph (_src.VT _src.RC:$src1),
5572 (i32 imm:$src2), (i32 FROUND_CURRENT) )),
5574 def mrk : AVX512AIi8<0x1D, MRMDestMem, (outs),
5575 (ins x86memop:$dst, _dest.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2),
5576 "vcvtps2ph\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
5580 multiclass avx512_cvtps2ph_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
5581 defm rb : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
5582 (ins _src.RC:$src1, i32u8imm:$src2),
5583 "vcvtps2ph", "$src2, {sae}, $src1", "$src1, $src2, {sae}",
5584 (X86cvtps2ph (_src.VT _src.RC:$src1),
5586 (i32 FROUND_NO_EXC))>, EVEX_B, AVX512AIi8Base;
5588 let Predicates = [HasAVX512] in {
5589 defm VCVTPS2PHZ : avx512_cvtps2ph<v16i16x_info, v16f32_info, f256mem>,
5590 avx512_cvtps2ph_sae<v16i16x_info, v16f32_info>,
5591 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5592 let Predicates = [HasVLX] in {
5593 defm VCVTPS2PHZ256 : avx512_cvtps2ph<v8i16x_info, v8f32x_info, f128mem>,
5594 EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5595 defm VCVTPS2PHZ128 : avx512_cvtps2ph<v8i16x_info, v4f32x_info, f128mem>,
5596 EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5600 // Unordered/Ordered scalar fp compare with Sea and set EFLAGS
5601 multiclass avx512_ord_cmp_sae<bits<8> opc, X86VectorVTInfo _, SDNode OpNode,
5603 def rb: AVX512<opc, MRMSrcReg, (outs), (ins _.RC:$src1, _.RC:$src2),
5604 !strconcat(OpcodeStr, "\t{{sae}, $src2, $src1|$src1, $src2, {sae}}"),
5605 [(set EFLAGS, (OpNode (_.VT _.RC:$src1), _.RC:$src2,
5606 (i32 FROUND_NO_EXC)))],
5607 IIC_SSE_COMIS_RR>, EVEX, EVEX_B, VEX_LIG, EVEX_V128,
5611 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5612 defm VUCOMISSZ : avx512_ord_cmp_sae<0x2E, v4f32x_info, X86ucomiSae, "vucomiss">,
5613 AVX512PSIi8Base, EVEX_CD8<32, CD8VT1>;
5614 defm VUCOMISDZ : avx512_ord_cmp_sae<0x2E, v2f64x_info, X86ucomiSae, "vucomisd">,
5615 AVX512PDIi8Base, VEX_W, EVEX_CD8<64, CD8VT1>;
5616 defm VCOMISSZ : avx512_ord_cmp_sae<0x2F, v4f32x_info, X86comiSae, "vcomiss">,
5617 AVX512PSIi8Base, EVEX_CD8<32, CD8VT1>;
5618 defm VCOMISDZ : avx512_ord_cmp_sae<0x2F, v2f64x_info, X86comiSae, "vcomisd">,
5619 AVX512PDIi8Base, VEX_W, EVEX_CD8<64, CD8VT1>;
5622 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5623 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
5624 "ucomiss">, PS, EVEX, VEX_LIG,
5625 EVEX_CD8<32, CD8VT1>;
5626 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
5627 "ucomisd">, PD, EVEX,
5628 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5629 let Pattern = []<dag> in {
5630 defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32,
5631 "comiss">, PS, EVEX, VEX_LIG,
5632 EVEX_CD8<32, CD8VT1>;
5633 defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64,
5634 "comisd">, PD, EVEX,
5635 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5637 let isCodeGenOnly = 1 in {
5638 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
5639 load, "ucomiss">, PS, EVEX, VEX_LIG,
5640 EVEX_CD8<32, CD8VT1>;
5641 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
5642 load, "ucomisd">, PD, EVEX,
5643 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5645 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
5646 load, "comiss">, PS, EVEX, VEX_LIG,
5647 EVEX_CD8<32, CD8VT1>;
5648 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
5649 load, "comisd">, PD, EVEX,
5650 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5654 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
5655 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
5656 X86VectorVTInfo _> {
5657 let hasSideEffects = 0, AddedComplexity = 20 , Predicates = [HasAVX512] in {
5658 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5659 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5660 "$src2, $src1", "$src1, $src2",
5661 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>, EVEX_4V;
5662 let mayLoad = 1 in {
5663 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5664 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5665 "$src2, $src1", "$src1, $src2",
5666 (OpNode (_.VT _.RC:$src1),
5667 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))))>, EVEX_4V;
5672 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", X86frcp14s, f32x_info>,
5673 EVEX_CD8<32, CD8VT1>, T8PD;
5674 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", X86frcp14s, f64x_info>,
5675 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5676 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", X86frsqrt14s, f32x_info>,
5677 EVEX_CD8<32, CD8VT1>, T8PD;
5678 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", X86frsqrt14s, f64x_info>,
5679 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5681 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
5682 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
5683 X86VectorVTInfo _> {
5684 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5685 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5686 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
5687 let mayLoad = 1 in {
5688 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5689 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5691 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
5692 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5693 (ins _.ScalarMemOp:$src), OpcodeStr,
5694 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5696 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5701 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5702 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
5703 EVEX_V512, EVEX_CD8<32, CD8VF>;
5704 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
5705 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5707 // Define only if AVX512VL feature is present.
5708 let Predicates = [HasVLX] in {
5709 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5710 OpNode, v4f32x_info>,
5711 EVEX_V128, EVEX_CD8<32, CD8VF>;
5712 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5713 OpNode, v8f32x_info>,
5714 EVEX_V256, EVEX_CD8<32, CD8VF>;
5715 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5716 OpNode, v2f64x_info>,
5717 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
5718 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5719 OpNode, v4f64x_info>,
5720 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
5724 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
5725 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
5727 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
5728 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5731 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5732 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5733 "$src2, $src1", "$src1, $src2",
5734 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5735 (i32 FROUND_CURRENT))>;
5737 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5738 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5739 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5740 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5741 (i32 FROUND_NO_EXC))>, EVEX_B;
5743 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5744 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5745 "$src2, $src1", "$src1, $src2",
5746 (OpNode (_.VT _.RC:$src1),
5747 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5748 (i32 FROUND_CURRENT))>;
5751 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5752 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
5753 EVEX_CD8<32, CD8VT1>;
5754 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
5755 EVEX_CD8<64, CD8VT1>, VEX_W;
5758 let hasSideEffects = 0, Predicates = [HasERI] in {
5759 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
5760 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
5763 defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds>, T8PD, EVEX_4V;
5764 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
5766 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5769 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5770 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5771 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
5773 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5774 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5776 (bitconvert (_.LdFrag addr:$src))),
5777 (i32 FROUND_CURRENT))>;
5779 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5780 (ins _.MemOp:$src), OpcodeStr,
5781 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5783 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
5784 (i32 FROUND_CURRENT))>, EVEX_B;
5786 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5788 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5789 (ins _.RC:$src), OpcodeStr,
5790 "{sae}, $src", "$src, {sae}",
5791 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
5794 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5795 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5796 avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5797 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
5798 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5799 avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5800 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5803 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
5805 // Define only if AVX512VL feature is present.
5806 let Predicates = [HasVLX] in {
5807 defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
5808 EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;
5809 defm PSZ256 : avx512_fp28_p<opc, OpcodeStr#"ps", v8f32x_info, OpNode>,
5810 EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>;
5811 defm PDZ128 : avx512_fp28_p<opc, OpcodeStr#"pd", v2f64x_info, OpNode>,
5812 EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5813 defm PDZ256 : avx512_fp28_p<opc, OpcodeStr#"pd", v4f64x_info, OpNode>,
5814 EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5817 let Predicates = [HasERI], hasSideEffects = 0 in {
5819 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX;
5820 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX;
5821 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX;
5823 defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
5824 avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
5826 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
5827 SDNode OpNodeRnd, X86VectorVTInfo _>{
5828 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5829 (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
5830 (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
5831 EVEX, EVEX_B, EVEX_RC;
5834 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
5835 SDNode OpNode, X86VectorVTInfo _>{
5836 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5837 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5838 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
5839 let mayLoad = 1 in {
5840 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5841 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5843 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
5845 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5846 (ins _.ScalarMemOp:$src), OpcodeStr,
5847 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5849 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5854 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
5856 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
5858 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5859 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
5861 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5862 // Define only if AVX512VL feature is present.
5863 let Predicates = [HasVLX] in {
5864 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5865 OpNode, v4f32x_info>,
5866 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
5867 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5868 OpNode, v8f32x_info>,
5869 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
5870 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5871 OpNode, v2f64x_info>,
5872 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5873 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5874 OpNode, v4f64x_info>,
5875 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5879 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
5881 defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
5882 v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5883 defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
5884 v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5887 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5888 string SUFF, SDNode OpNode, SDNode OpNodeRnd> {
5890 defm r_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5891 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5892 "$src2, $src1", "$src1, $src2",
5893 (OpNodeRnd (_.VT _.RC:$src1),
5895 (i32 FROUND_CURRENT))>;
5897 defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5898 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5899 "$src2, $src1", "$src1, $src2",
5900 (OpNodeRnd (_.VT _.RC:$src1),
5901 (_.VT (scalar_to_vector
5902 (_.ScalarLdFrag addr:$src2))),
5903 (i32 FROUND_CURRENT))>;
5905 defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5906 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
5907 "$rc, $src2, $src1", "$src1, $src2, $rc",
5908 (OpNodeRnd (_.VT _.RC:$src1),
5913 let isCodeGenOnly = 1 in {
5914 def r : I<opc, MRMSrcReg, (outs _.FRC:$dst),
5915 (ins _.FRC:$src1, _.FRC:$src2),
5916 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5919 def m : I<opc, MRMSrcMem, (outs _.FRC:$dst),
5920 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
5921 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5924 def : Pat<(_.EltVT (OpNode _.FRC:$src)),
5925 (!cast<Instruction>(NAME#SUFF#Zr)
5926 (_.EltVT (IMPLICIT_DEF)), _.FRC:$src)>;
5928 def : Pat<(_.EltVT (OpNode (load addr:$src))),
5929 (!cast<Instruction>(NAME#SUFF#Zm)
5930 (_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[OptForSize]>;
5933 multiclass avx512_sqrt_scalar_all<bits<8> opc, string OpcodeStr> {
5934 defm SSZ : avx512_sqrt_scalar<opc, OpcodeStr#"ss", f32x_info, "SS", fsqrt,
5935 X86fsqrtRnds>, EVEX_CD8<32, CD8VT1>, EVEX_4V, XS;
5936 defm SDZ : avx512_sqrt_scalar<opc, OpcodeStr#"sd", f64x_info, "SD", fsqrt,
5937 X86fsqrtRnds>, EVEX_CD8<64, CD8VT1>, EVEX_4V, XD, VEX_W;
5940 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>,
5941 avx512_sqrt_packed_all_round<0x51, "vsqrt", X86fsqrtRnd>;
5943 defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt">, VEX_LIG;
5945 let Predicates = [HasAVX512] in {
5946 def : Pat<(f32 (X86frsqrt FR32X:$src)),
5947 (COPY_TO_REGCLASS (VRSQRT14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>;
5948 def : Pat<(f32 (X86frsqrt (load addr:$src))),
5949 (COPY_TO_REGCLASS (VRSQRT14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5950 Requires<[OptForSize]>;
5951 def : Pat<(f32 (X86frcp FR32X:$src)),
5952 (COPY_TO_REGCLASS (VRCP14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X )>;
5953 def : Pat<(f32 (X86frcp (load addr:$src))),
5954 (COPY_TO_REGCLASS (VRCP14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5955 Requires<[OptForSize]>;
5959 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5961 let ExeDomain = _.ExeDomain in {
5962 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5963 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5964 "$src3, $src2, $src1", "$src1, $src2, $src3",
5965 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5966 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5968 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5969 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5970 "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
5971 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5972 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5975 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5976 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5977 "$src3, $src2, $src1", "$src1, $src2, $src3",
5978 (_.VT (X86RndScales (_.VT _.RC:$src1),
5979 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5980 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5982 let Predicates = [HasAVX512] in {
5983 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5984 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5985 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5986 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5987 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5988 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5989 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5990 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5991 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5992 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5993 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5994 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5995 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5996 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5997 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
5999 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6000 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6001 addr:$src, (i32 0x1))), _.FRC)>;
6002 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6003 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6004 addr:$src, (i32 0x2))), _.FRC)>;
6005 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6006 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6007 addr:$src, (i32 0x3))), _.FRC)>;
6008 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6009 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6010 addr:$src, (i32 0x4))), _.FRC)>;
6011 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
6012 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
6013 addr:$src, (i32 0xc))), _.FRC)>;
6017 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
6018 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6020 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
6021 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
6023 //-------------------------------------------------
6024 // Integer truncate and extend operations
6025 //-------------------------------------------------
6027 multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
6028 X86VectorVTInfo SrcInfo, X86VectorVTInfo DestInfo,
6029 X86MemOperand x86memop> {
6031 defm rr : AVX512_maskable<opc, MRMDestReg, DestInfo, (outs DestInfo.RC:$dst),
6032 (ins SrcInfo.RC:$src1), OpcodeStr ,"$src1", "$src1",
6033 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1)))>,
6036 // for intrinsic patter match
6037 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
6038 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6040 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
6043 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
6044 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6045 DestInfo.ImmAllZerosV)),
6046 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
6049 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
6050 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
6051 DestInfo.RC:$src0)),
6052 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrk) DestInfo.RC:$src0,
6053 DestInfo.KRCWM:$mask ,
6056 let mayStore = 1 in {
6057 def mr : AVX512XS8I<opc, MRMDestMem, (outs),
6058 (ins x86memop:$dst, SrcInfo.RC:$src),
6059 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6062 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
6063 (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
6064 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6069 multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,
6070 X86VectorVTInfo DestInfo,
6071 PatFrag truncFrag, PatFrag mtruncFrag > {
6073 def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
6074 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr)
6075 addr:$dst, SrcInfo.RC:$src)>;
6077 def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask,
6078 (SrcInfo.VT SrcInfo.RC:$src)),
6079 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk)
6080 addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
6083 multiclass avx512_trunc_sat_mr_lowering<X86VectorVTInfo SrcInfo,
6084 X86VectorVTInfo DestInfo, string sat > {
6086 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
6087 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
6088 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), SrcInfo.MRC:$mask),
6089 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk) addr:$ptr,
6090 (COPY_TO_REGCLASS SrcInfo.MRC:$mask, SrcInfo.KRCWM),
6091 (SrcInfo.VT SrcInfo.RC:$src))>;
6093 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
6094 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
6095 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), -1),
6096 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr) addr:$ptr,
6097 (SrcInfo.VT SrcInfo.RC:$src))>;
6100 multiclass avx512_trunc<bits<8> opc, string OpcodeStr, SDNode OpNode,
6101 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
6102 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
6103 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
6104 X86MemOperand x86memopZ, PatFrag truncFrag, PatFrag mtruncFrag,
6105 Predicate prd = HasAVX512>{
6107 let Predicates = [HasVLX, prd] in {
6108 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
6109 DestInfoZ128, x86memopZ128>,
6110 avx512_trunc_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
6111 truncFrag, mtruncFrag>, EVEX_V128;
6113 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
6114 DestInfoZ256, x86memopZ256>,
6115 avx512_trunc_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
6116 truncFrag, mtruncFrag>, EVEX_V256;
6118 let Predicates = [prd] in
6119 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
6120 DestInfoZ, x86memopZ>,
6121 avx512_trunc_mr_lowering<VTSrcInfo.info512, DestInfoZ,
6122 truncFrag, mtruncFrag>, EVEX_V512;
6125 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr, SDNode OpNode,
6126 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
6127 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
6128 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
6129 X86MemOperand x86memopZ, string sat, Predicate prd = HasAVX512>{
6131 let Predicates = [HasVLX, prd] in {
6132 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
6133 DestInfoZ128, x86memopZ128>,
6134 avx512_trunc_sat_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
6137 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
6138 DestInfoZ256, x86memopZ256>,
6139 avx512_trunc_sat_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
6142 let Predicates = [prd] in
6143 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
6144 DestInfoZ, x86memopZ>,
6145 avx512_trunc_sat_mr_lowering<VTSrcInfo.info512, DestInfoZ,
6149 multiclass avx512_trunc_qb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6150 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6151 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
6152 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VO>;
6154 multiclass avx512_trunc_sat_qb<bits<8> opc, string sat, SDNode OpNode> {
6155 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qb", OpNode, avx512vl_i64_info,
6156 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
6157 sat>, EVEX_CD8<8, CD8VO>;
6160 multiclass avx512_trunc_qw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6161 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6162 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
6163 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VQ>;
6165 multiclass avx512_trunc_sat_qw<bits<8> opc, string sat, SDNode OpNode> {
6166 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qw", OpNode, avx512vl_i64_info,
6167 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
6168 sat>, EVEX_CD8<16, CD8VQ>;
6171 multiclass avx512_trunc_qd<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6172 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6173 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
6174 truncstorevi32, masked_truncstorevi32>, EVEX_CD8<32, CD8VH>;
6176 multiclass avx512_trunc_sat_qd<bits<8> opc, string sat, SDNode OpNode> {
6177 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qd", OpNode, avx512vl_i64_info,
6178 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
6179 sat>, EVEX_CD8<32, CD8VH>;
6182 multiclass avx512_trunc_db<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6183 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
6184 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
6185 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VQ>;
6187 multiclass avx512_trunc_sat_db<bits<8> opc, string sat, SDNode OpNode> {
6188 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"db", OpNode, avx512vl_i32_info,
6189 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
6190 sat>, EVEX_CD8<8, CD8VQ>;
6193 multiclass avx512_trunc_dw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6194 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
6195 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
6196 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VH>;
6198 multiclass avx512_trunc_sat_dw<bits<8> opc, string sat, SDNode OpNode> {
6199 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"dw", OpNode, avx512vl_i32_info,
6200 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
6201 sat>, EVEX_CD8<16, CD8VH>;
6204 multiclass avx512_trunc_wb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6205 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i16_info,
6206 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
6207 truncstorevi8, masked_truncstorevi8,HasBWI>, EVEX_CD8<16, CD8VH>;
6209 multiclass avx512_trunc_sat_wb<bits<8> opc, string sat, SDNode OpNode> {
6210 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"wb", OpNode, avx512vl_i16_info,
6211 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
6212 sat, HasBWI>, EVEX_CD8<16, CD8VH>;
6215 defm VPMOVQB : avx512_trunc_qb<0x32, "vpmovqb", X86vtrunc>;
6216 defm VPMOVSQB : avx512_trunc_sat_qb<0x22, "s", X86vtruncs>;
6217 defm VPMOVUSQB : avx512_trunc_sat_qb<0x12, "us", X86vtruncus>;
6219 defm VPMOVQW : avx512_trunc_qw<0x34, "vpmovqw", X86vtrunc>;
6220 defm VPMOVSQW : avx512_trunc_sat_qw<0x24, "s", X86vtruncs>;
6221 defm VPMOVUSQW : avx512_trunc_sat_qw<0x14, "us", X86vtruncus>;
6223 defm VPMOVQD : avx512_trunc_qd<0x35, "vpmovqd", X86vtrunc>;
6224 defm VPMOVSQD : avx512_trunc_sat_qd<0x25, "s", X86vtruncs>;
6225 defm VPMOVUSQD : avx512_trunc_sat_qd<0x15, "us", X86vtruncus>;
6227 defm VPMOVDB : avx512_trunc_db<0x31, "vpmovdb", X86vtrunc>;
6228 defm VPMOVSDB : avx512_trunc_sat_db<0x21, "s", X86vtruncs>;
6229 defm VPMOVUSDB : avx512_trunc_sat_db<0x11, "us", X86vtruncus>;
6231 defm VPMOVDW : avx512_trunc_dw<0x33, "vpmovdw", X86vtrunc>;
6232 defm VPMOVSDW : avx512_trunc_sat_dw<0x23, "s", X86vtruncs>;
6233 defm VPMOVUSDW : avx512_trunc_sat_dw<0x13, "us", X86vtruncus>;
6235 defm VPMOVWB : avx512_trunc_wb<0x30, "vpmovwb", X86vtrunc>;
6236 defm VPMOVSWB : avx512_trunc_sat_wb<0x20, "s", X86vtruncs>;
6237 defm VPMOVUSWB : avx512_trunc_sat_wb<0x10, "us", X86vtruncus>;
6239 let Predicates = [HasAVX512, NoVLX] in {
6240 def: Pat<(v8i16 (X86vtrunc (v8i32 VR256X:$src))),
6241 (v8i16 (EXTRACT_SUBREG
6242 (v16i16 (VPMOVDWZrr (v16i32 (SUBREG_TO_REG (i32 0),
6243 VR256X:$src, sub_ymm)))), sub_xmm))>;
6244 def: Pat<(v4i32 (X86vtrunc (v4i64 VR256X:$src))),
6245 (v4i32 (EXTRACT_SUBREG
6246 (v8i32 (VPMOVQDZrr (v8i64 (SUBREG_TO_REG (i32 0),
6247 VR256X:$src, sub_ymm)))), sub_xmm))>;
6250 let Predicates = [HasBWI, NoVLX] in {
6251 def: Pat<(v16i8 (X86vtrunc (v16i16 VR256X:$src))),
6252 (v16i8 (EXTRACT_SUBREG (VPMOVWBZrr (v32i16 (SUBREG_TO_REG (i32 0),
6253 VR256X:$src, sub_ymm))), sub_xmm))>;
6256 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
6257 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
6258 X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{
6260 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6261 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
6262 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
6265 let mayLoad = 1 in {
6266 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6267 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
6268 (DestInfo.VT (LdFrag addr:$src))>,
6273 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode,
6274 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6275 let Predicates = [HasVLX, HasBWI] in {
6276 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
6277 v16i8x_info, i64mem, LdFrag, OpNode>,
6278 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
6280 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
6281 v16i8x_info, i128mem, LdFrag, OpNode>,
6282 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
6284 let Predicates = [HasBWI] in {
6285 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
6286 v32i8x_info, i256mem, LdFrag, OpNode>,
6287 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
6291 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6292 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6293 let Predicates = [HasVLX, HasAVX512] in {
6294 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6295 v16i8x_info, i32mem, LdFrag, OpNode>,
6296 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
6298 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6299 v16i8x_info, i64mem, LdFrag, OpNode>,
6300 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
6302 let Predicates = [HasAVX512] in {
6303 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6304 v16i8x_info, i128mem, LdFrag, OpNode>,
6305 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
6309 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6310 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6311 let Predicates = [HasVLX, HasAVX512] in {
6312 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6313 v16i8x_info, i16mem, LdFrag, OpNode>,
6314 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
6316 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6317 v16i8x_info, i32mem, LdFrag, OpNode>,
6318 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
6320 let Predicates = [HasAVX512] in {
6321 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6322 v16i8x_info, i64mem, LdFrag, OpNode>,
6323 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
6327 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6328 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6329 let Predicates = [HasVLX, HasAVX512] in {
6330 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6331 v8i16x_info, i64mem, LdFrag, OpNode>,
6332 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
6334 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6335 v8i16x_info, i128mem, LdFrag, OpNode>,
6336 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
6338 let Predicates = [HasAVX512] in {
6339 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6340 v16i16x_info, i256mem, LdFrag, OpNode>,
6341 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
6345 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6346 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6347 let Predicates = [HasVLX, HasAVX512] in {
6348 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6349 v8i16x_info, i32mem, LdFrag, OpNode>,
6350 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
6352 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6353 v8i16x_info, i64mem, LdFrag, OpNode>,
6354 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
6356 let Predicates = [HasAVX512] in {
6357 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6358 v8i16x_info, i128mem, LdFrag, OpNode>,
6359 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
6363 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6364 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
6366 let Predicates = [HasVLX, HasAVX512] in {
6367 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6368 v4i32x_info, i64mem, LdFrag, OpNode>,
6369 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
6371 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6372 v4i32x_info, i128mem, LdFrag, OpNode>,
6373 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
6375 let Predicates = [HasAVX512] in {
6376 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6377 v8i32x_info, i256mem, LdFrag, OpNode>,
6378 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
6382 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, "z">;
6383 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, "z">;
6384 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, "z">;
6385 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, "z">;
6386 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, "z">;
6387 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, "z">;
6390 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, "s">;
6391 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, "s">;
6392 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, "s">;
6393 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, "s">;
6394 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, "s">;
6395 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, "s">;
6397 //===----------------------------------------------------------------------===//
6398 // GATHER - SCATTER Operations
6400 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6401 X86MemOperand memop, PatFrag GatherNode> {
6402 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb",
6403 ExeDomain = _.ExeDomain in
6404 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
6405 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
6406 !strconcat(OpcodeStr#_.Suffix,
6407 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
6408 [(set _.RC:$dst, _.KRCWM:$mask_wb,
6409 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
6410 vectoraddr:$src2))]>, EVEX, EVEX_K,
6411 EVEX_CD8<_.EltSize, CD8VT1>;
6414 multiclass avx512_gather_q_pd<bits<8> dopc, bits<8> qopc,
6415 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6416 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512,
6417 vy32xmem, mgatherv8i32>, EVEX_V512, VEX_W;
6418 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info512,
6419 vz64mem, mgatherv8i64>, EVEX_V512, VEX_W;
6420 let Predicates = [HasVLX] in {
6421 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6422 vx32xmem, mgatherv4i32>, EVEX_V256, VEX_W;
6423 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info256,
6424 vy64xmem, mgatherv4i64>, EVEX_V256, VEX_W;
6425 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6426 vx32xmem, mgatherv4i32>, EVEX_V128, VEX_W;
6427 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6428 vx64xmem, mgatherv2i64>, EVEX_V128, VEX_W;
6432 multiclass avx512_gather_d_ps<bits<8> dopc, bits<8> qopc,
6433 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6434 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512, vz32mem,
6435 mgatherv16i32>, EVEX_V512;
6436 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info256, vz64mem,
6437 mgatherv8i64>, EVEX_V512;
6438 let Predicates = [HasVLX] in {
6439 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6440 vy32xmem, mgatherv8i32>, EVEX_V256;
6441 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6442 vy64xmem, mgatherv4i64>, EVEX_V256;
6443 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6444 vx32xmem, mgatherv4i32>, EVEX_V128;
6445 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6446 vx64xmem, mgatherv2i64>, EVEX_V128;
6451 defm VGATHER : avx512_gather_q_pd<0x92, 0x93, avx512vl_f64_info, "vgather", "PD">,
6452 avx512_gather_d_ps<0x92, 0x93, avx512vl_f32_info, "vgather", "PS">;
6454 defm VPGATHER : avx512_gather_q_pd<0x90, 0x91, avx512vl_i64_info, "vpgather", "Q">,
6455 avx512_gather_d_ps<0x90, 0x91, avx512vl_i32_info, "vpgather", "D">;
6457 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6458 X86MemOperand memop, PatFrag ScatterNode> {
6460 let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain in
6462 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
6463 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
6464 !strconcat(OpcodeStr#_.Suffix,
6465 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
6466 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
6467 _.KRCWM:$mask, vectoraddr:$dst))]>,
6468 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6471 multiclass avx512_scatter_q_pd<bits<8> dopc, bits<8> qopc,
6472 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6473 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512,
6474 vy32xmem, mscatterv8i32>, EVEX_V512, VEX_W;
6475 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info512,
6476 vz64mem, mscatterv8i64>, EVEX_V512, VEX_W;
6477 let Predicates = [HasVLX] in {
6478 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6479 vx32xmem, mscatterv4i32>, EVEX_V256, VEX_W;
6480 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info256,
6481 vy64xmem, mscatterv4i64>, EVEX_V256, VEX_W;
6482 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6483 vx32xmem, mscatterv4i32>, EVEX_V128, VEX_W;
6484 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6485 vx64xmem, mscatterv2i64>, EVEX_V128, VEX_W;
6489 multiclass avx512_scatter_d_ps<bits<8> dopc, bits<8> qopc,
6490 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6491 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512, vz32mem,
6492 mscatterv16i32>, EVEX_V512;
6493 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info256, vz64mem,
6494 mscatterv8i64>, EVEX_V512;
6495 let Predicates = [HasVLX] in {
6496 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6497 vy32xmem, mscatterv8i32>, EVEX_V256;
6498 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6499 vy64xmem, mscatterv4i64>, EVEX_V256;
6500 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6501 vx32xmem, mscatterv4i32>, EVEX_V128;
6502 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6503 vx64xmem, mscatterv2i64>, EVEX_V128;
6507 defm VSCATTER : avx512_scatter_q_pd<0xA2, 0xA3, avx512vl_f64_info, "vscatter", "PD">,
6508 avx512_scatter_d_ps<0xA2, 0xA3, avx512vl_f32_info, "vscatter", "PS">;
6510 defm VPSCATTER : avx512_scatter_q_pd<0xA0, 0xA1, avx512vl_i64_info, "vpscatter", "Q">,
6511 avx512_scatter_d_ps<0xA0, 0xA1, avx512vl_i32_info, "vpscatter", "D">;
6514 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
6515 RegisterClass KRC, X86MemOperand memop> {
6516 let Predicates = [HasPFI], hasSideEffects = 1 in
6517 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
6518 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
6522 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
6523 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6525 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
6526 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6528 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
6529 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6531 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
6532 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6534 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
6535 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6537 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
6538 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6540 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
6541 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6543 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
6544 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6546 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
6547 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6549 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
6550 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6552 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
6553 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6555 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
6556 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6558 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
6559 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6561 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
6562 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6564 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
6565 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6567 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
6568 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6570 // Helper fragments to match sext vXi1 to vXiY.
6571 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
6572 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
6574 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6575 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6576 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
6578 def : Pat<(store VK1:$src, addr:$dst),
6580 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
6581 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6583 def : Pat<(store VK8:$src, addr:$dst),
6585 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
6586 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6588 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
6589 (truncstore node:$val, node:$ptr), [{
6590 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
6593 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
6594 (MOV8mr addr:$dst, GR8:$src)>;
6596 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
6597 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
6598 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
6599 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
6602 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
6603 string OpcodeStr, Predicate prd> {
6604 let Predicates = [prd] in
6605 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6607 let Predicates = [prd, HasVLX] in {
6608 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6609 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6613 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
6614 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
6616 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
6618 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
6620 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
6624 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
6626 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
6627 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
6628 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6629 [(set _.KRC:$dst, (X86cvt2mask (_.VT _.RC:$src)))]>, EVEX;
6632 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
6633 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6634 let Predicates = [prd] in
6635 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
6638 let Predicates = [prd, HasVLX] in {
6639 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
6641 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
6646 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
6647 avx512vl_i8_info, HasBWI>;
6648 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
6649 avx512vl_i16_info, HasBWI>, VEX_W;
6650 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
6651 avx512vl_i32_info, HasDQI>;
6652 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
6653 avx512vl_i64_info, HasDQI>, VEX_W;
6655 //===----------------------------------------------------------------------===//
6656 // AVX-512 - COMPRESS and EXPAND
6659 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6661 defm rr : AVX512_maskable<opc, MRMDestReg, _, (outs _.RC:$dst),
6662 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6663 (_.VT (X86compress _.RC:$src1))>, AVX5128IBase;
6665 let mayStore = 1 in {
6666 def mr : AVX5128I<opc, MRMDestMem, (outs),
6667 (ins _.MemOp:$dst, _.RC:$src),
6668 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6669 []>, EVEX_CD8<_.EltSize, CD8VT1>;
6671 def mrk : AVX5128I<opc, MRMDestMem, (outs),
6672 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
6673 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6674 [(store (_.VT (vselect _.KRCWM:$mask,
6675 (_.VT (X86compress _.RC:$src)), _.ImmAllZerosV)),
6677 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6681 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
6682 AVX512VLVectorVTInfo VTInfo> {
6683 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6685 let Predicates = [HasVLX] in {
6686 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6687 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6691 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
6693 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
6695 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
6697 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
6701 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6703 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6704 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6705 (_.VT (X86expand _.RC:$src1))>, AVX5128IBase;
6708 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6709 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
6710 (_.VT (X86expand (_.VT (bitconvert
6711 (_.LdFrag addr:$src1)))))>,
6712 AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>;
6715 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
6716 AVX512VLVectorVTInfo VTInfo> {
6717 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6719 let Predicates = [HasVLX] in {
6720 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6721 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6725 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
6727 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
6729 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
6731 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
6734 //handle instruction reg_vec1 = op(reg_vec,imm)
6736 // op(broadcast(eltVt),imm)
6737 //all instruction created with FROUND_CURRENT
6738 multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6740 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6741 (ins _.RC:$src1, i32u8imm:$src2),
6742 OpcodeStr##_.Suffix, "$src2, $src1", "$src2, $src2",
6743 (OpNode (_.VT _.RC:$src1),
6745 (i32 FROUND_CURRENT))>;
6746 let mayLoad = 1 in {
6747 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6748 (ins _.MemOp:$src1, i32u8imm:$src2),
6749 OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
6750 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
6752 (i32 FROUND_CURRENT))>;
6753 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6754 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
6755 OpcodeStr##_.Suffix, "$src2, ${src1}"##_.BroadcastStr,
6756 "${src1}"##_.BroadcastStr##", $src2",
6757 (OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src1))),
6759 (i32 FROUND_CURRENT))>, EVEX_B;
6763 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6764 multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6765 SDNode OpNode, X86VectorVTInfo _>{
6766 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6767 (ins _.RC:$src1, i32u8imm:$src2),
6768 OpcodeStr##_.Suffix, "$src2,{sae}, $src1",
6769 "$src1, {sae}, $src2",
6770 (OpNode (_.VT _.RC:$src1),
6772 (i32 FROUND_NO_EXC))>, EVEX_B;
6775 multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
6776 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6777 let Predicates = [prd] in {
6778 defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6779 avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6782 let Predicates = [prd, HasVLX] in {
6783 defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6785 defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6790 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6791 // op(reg_vec2,mem_vec,imm)
6792 // op(reg_vec2,broadcast(eltVt),imm)
6793 //all instruction created with FROUND_CURRENT
6794 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6796 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6797 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6798 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6799 (OpNode (_.VT _.RC:$src1),
6802 (i32 FROUND_CURRENT))>;
6803 let mayLoad = 1 in {
6804 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6805 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6806 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6807 (OpNode (_.VT _.RC:$src1),
6808 (_.VT (bitconvert (_.LdFrag addr:$src2))),
6810 (i32 FROUND_CURRENT))>;
6811 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6812 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
6813 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6814 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6815 (OpNode (_.VT _.RC:$src1),
6816 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6818 (i32 FROUND_CURRENT))>, EVEX_B;
6822 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6823 // op(reg_vec2,mem_vec,imm)
6824 multiclass avx512_3Op_rm_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6825 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo>{
6827 defm rri : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6828 (ins SrcInfo.RC:$src1, SrcInfo.RC:$src2, u8imm:$src3),
6829 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6830 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6831 (SrcInfo.VT SrcInfo.RC:$src2),
6834 defm rmi : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6835 (ins SrcInfo.RC:$src1, SrcInfo.MemOp:$src2, u8imm:$src3),
6836 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6837 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6838 (SrcInfo.VT (bitconvert
6839 (SrcInfo.LdFrag addr:$src2))),
6843 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6844 // op(reg_vec2,mem_vec,imm)
6845 // op(reg_vec2,broadcast(eltVt),imm)
6846 multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6848 avx512_3Op_rm_imm8<opc, OpcodeStr, OpNode, _, _>{
6851 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6852 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6853 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6854 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6855 (OpNode (_.VT _.RC:$src1),
6856 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6857 (i8 imm:$src3))>, EVEX_B;
6860 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6861 // op(reg_vec2,mem_scalar,imm)
6862 //all instruction created with FROUND_CURRENT
6863 multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6864 X86VectorVTInfo _> {
6866 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6867 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6868 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6869 (OpNode (_.VT _.RC:$src1),
6872 (i32 FROUND_CURRENT))>;
6873 let mayLoad = 1 in {
6874 defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6875 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6876 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6877 (OpNode (_.VT _.RC:$src1),
6878 (_.VT (scalar_to_vector
6879 (_.ScalarLdFrag addr:$src2))),
6881 (i32 FROUND_CURRENT))>;
6883 let isAsmParserOnly = 1 in {
6884 defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
6885 (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6886 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6892 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6893 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6894 SDNode OpNode, X86VectorVTInfo _>{
6895 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6896 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6897 OpcodeStr, "$src3,{sae}, $src2, $src1",
6898 "$src1, $src2,{sae}, $src3",
6899 (OpNode (_.VT _.RC:$src1),
6902 (i32 FROUND_NO_EXC))>, EVEX_B;
6904 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6905 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
6906 SDNode OpNode, X86VectorVTInfo _> {
6907 defm NAME#rrib : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6908 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6909 OpcodeStr, "$src3,{sae}, $src2, $src1",
6910 "$src1, $src2,{sae}, $src3",
6911 (OpNode (_.VT _.RC:$src1),
6914 (i32 FROUND_NO_EXC))>, EVEX_B;
6917 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
6918 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6919 let Predicates = [prd] in {
6920 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6921 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6925 let Predicates = [prd, HasVLX] in {
6926 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6928 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6933 multiclass avx512_common_3Op_rm_imm8<bits<8> opc, SDNode OpNode, string OpStr,
6934 AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo>{
6935 let Predicates = [HasBWI] in {
6936 defm Z : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info512,
6937 SrcInfo.info512>, EVEX_V512, AVX512AIi8Base, EVEX_4V;
6939 let Predicates = [HasBWI, HasVLX] in {
6940 defm Z128 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info128,
6941 SrcInfo.info128>, EVEX_V128, AVX512AIi8Base, EVEX_4V;
6942 defm Z256 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info256,
6943 SrcInfo.info256>, EVEX_V256, AVX512AIi8Base, EVEX_4V;
6947 multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
6948 bits<8> opc, SDNode OpNode>{
6949 let Predicates = [HasAVX512] in {
6950 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6952 let Predicates = [HasAVX512, HasVLX] in {
6953 defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
6954 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6958 multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
6959 X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6960 let Predicates = [prd] in {
6961 defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
6962 avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
6966 multiclass avx512_common_unary_fp_sae_packed_imm_all<string OpcodeStr,
6967 bits<8> opcPs, bits<8> opcPd, SDNode OpNode, Predicate prd>{
6968 defm PS : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f32_info,
6969 opcPs, OpNode, prd>, EVEX_CD8<32, CD8VF>;
6970 defm PD : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f64_info,
6971 opcPd, OpNode, prd>, EVEX_CD8<64, CD8VF>, VEX_W;
6974 defm VFIXUPIMMPD : avx512_common_fp_sae_packed_imm<"vfixupimmpd",
6975 avx512vl_f64_info, 0x54, X86VFixupimm, HasAVX512>,
6976 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6977 defm VFIXUPIMMPS : avx512_common_fp_sae_packed_imm<"vfixupimmps",
6978 avx512vl_f32_info, 0x54, X86VFixupimm, HasAVX512>,
6979 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6981 defm VFIXUPIMMSD: avx512_common_fp_sae_scalar_imm<"vfixupimmsd", f64x_info,
6982 0x55, X86VFixupimm, HasAVX512>,
6983 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6984 defm VFIXUPIMMSS: avx512_common_fp_sae_scalar_imm<"vfixupimmss", f32x_info,
6985 0x55, X86VFixupimm, HasAVX512>,
6986 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6988 defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56,
6989 X86VReduce, HasDQI>, AVX512AIi8Base, EVEX;
6990 defm VRNDSCALE : avx512_common_unary_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09,
6991 X86VRndScale, HasAVX512>, AVX512AIi8Base, EVEX;
6992 defm VGETMANT : avx512_common_unary_fp_sae_packed_imm_all<"vgetmant", 0x26, 0x26,
6993 X86VGetMant, HasAVX512>, AVX512AIi8Base, EVEX;
6996 defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
6997 0x50, X86VRange, HasDQI>,
6998 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6999 defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
7000 0x50, X86VRange, HasDQI>,
7001 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
7003 defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
7004 0x51, X86VRange, HasDQI>,
7005 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
7006 defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
7007 0x51, X86VRange, HasDQI>,
7008 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
7010 defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info,
7011 0x57, X86Reduces, HasDQI>,
7012 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
7013 defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info,
7014 0x57, X86Reduces, HasDQI>,
7015 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
7017 defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info,
7018 0x27, X86GetMants, HasAVX512>,
7019 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
7020 defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info,
7021 0x27, X86GetMants, HasAVX512>,
7022 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
7024 multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
7025 bits<8> opc, SDNode OpNode = X86Shuf128>{
7026 let Predicates = [HasAVX512] in {
7027 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
7030 let Predicates = [HasAVX512, HasVLX] in {
7031 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
7034 let Predicates = [HasAVX512] in {
7035 def : Pat<(v16f32 (ffloor VR512:$src)),
7036 (VRNDSCALEPSZrri VR512:$src, (i32 0x1))>;
7037 def : Pat<(v16f32 (fnearbyint VR512:$src)),
7038 (VRNDSCALEPSZrri VR512:$src, (i32 0xC))>;
7039 def : Pat<(v16f32 (fceil VR512:$src)),
7040 (VRNDSCALEPSZrri VR512:$src, (i32 0x2))>;
7041 def : Pat<(v16f32 (frint VR512:$src)),
7042 (VRNDSCALEPSZrri VR512:$src, (i32 0x4))>;
7043 def : Pat<(v16f32 (ftrunc VR512:$src)),
7044 (VRNDSCALEPSZrri VR512:$src, (i32 0x3))>;
7046 def : Pat<(v8f64 (ffloor VR512:$src)),
7047 (VRNDSCALEPDZrri VR512:$src, (i32 0x1))>;
7048 def : Pat<(v8f64 (fnearbyint VR512:$src)),
7049 (VRNDSCALEPDZrri VR512:$src, (i32 0xC))>;
7050 def : Pat<(v8f64 (fceil VR512:$src)),
7051 (VRNDSCALEPDZrri VR512:$src, (i32 0x2))>;
7052 def : Pat<(v8f64 (frint VR512:$src)),
7053 (VRNDSCALEPDZrri VR512:$src, (i32 0x4))>;
7054 def : Pat<(v8f64 (ftrunc VR512:$src)),
7055 (VRNDSCALEPDZrri VR512:$src, (i32 0x3))>;
7058 defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
7059 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
7060 defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
7061 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
7062 defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
7063 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
7064 defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
7065 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
7067 multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I> {
7068 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
7069 AVX512AIi8Base, EVEX_4V;
7072 defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info>,
7073 EVEX_CD8<32, CD8VF>;
7074 defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info>,
7075 EVEX_CD8<64, CD8VF>, VEX_W;
7077 multiclass avx512_vpalign_lowering<X86VectorVTInfo _ , list<Predicate> p>{
7078 let Predicates = p in
7079 def NAME#_.VTName#rri:
7080 Pat<(_.VT (X86PAlignr _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
7081 (!cast<Instruction>(NAME#_.ZSuffix#rri)
7082 _.RC:$src1, _.RC:$src2, imm:$imm)>;
7085 multiclass avx512_vpalign_lowering_common<AVX512VLVectorVTInfo _>:
7086 avx512_vpalign_lowering<_.info512, [HasBWI]>,
7087 avx512_vpalign_lowering<_.info128, [HasBWI, HasVLX]>,
7088 avx512_vpalign_lowering<_.info256, [HasBWI, HasVLX]>;
7090 defm VPALIGN: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr" ,
7091 avx512vl_i8_info, avx512vl_i8_info>,
7092 avx512_vpalign_lowering_common<avx512vl_i16_info>,
7093 avx512_vpalign_lowering_common<avx512vl_i32_info>,
7094 avx512_vpalign_lowering_common<avx512vl_f32_info>,
7095 avx512_vpalign_lowering_common<avx512vl_i64_info>,
7096 avx512_vpalign_lowering_common<avx512vl_f64_info>,
7099 defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw" ,
7100 avx512vl_i16_info, avx512vl_i8_info>, EVEX_CD8<8, CD8VF>;
7102 multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7103 X86VectorVTInfo _> {
7104 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7105 (ins _.RC:$src1), OpcodeStr,
7107 (_.VT (OpNode _.RC:$src1))>, EVEX, AVX5128IBase;
7110 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7111 (ins _.MemOp:$src1), OpcodeStr,
7113 (_.VT (OpNode (bitconvert (_.LdFrag addr:$src1))))>,
7114 EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>;
7117 multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
7118 X86VectorVTInfo _> :
7119 avx512_unary_rm<opc, OpcodeStr, OpNode, _> {
7121 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7122 (ins _.ScalarMemOp:$src1), OpcodeStr,
7123 "${src1}"##_.BroadcastStr,
7124 "${src1}"##_.BroadcastStr,
7125 (_.VT (OpNode (X86VBroadcast
7126 (_.ScalarLdFrag addr:$src1))))>,
7127 EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
7130 multiclass avx512_unary_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
7131 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
7132 let Predicates = [prd] in
7133 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
7135 let Predicates = [prd, HasVLX] in {
7136 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
7138 defm Z128 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info128>,
7143 multiclass avx512_unary_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
7144 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
7145 let Predicates = [prd] in
7146 defm Z : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
7149 let Predicates = [prd, HasVLX] in {
7150 defm Z256 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
7152 defm Z128 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
7157 multiclass avx512_unary_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
7158 SDNode OpNode, Predicate prd> {
7159 defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr#"q", OpNode, avx512vl_i64_info,
7161 defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr#"d", OpNode, avx512vl_i32_info,
7165 multiclass avx512_unary_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
7166 SDNode OpNode, Predicate prd> {
7167 defm W : avx512_unary_rm_vl<opc_w, OpcodeStr#"w", OpNode, avx512vl_i16_info, prd>;
7168 defm B : avx512_unary_rm_vl<opc_b, OpcodeStr#"b", OpNode, avx512vl_i8_info, prd>;
7171 multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
7172 bits<8> opc_d, bits<8> opc_q,
7173 string OpcodeStr, SDNode OpNode> {
7174 defm NAME : avx512_unary_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
7176 avx512_unary_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
7180 defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", X86Abs>;
7183 (bc_v16i32 (v16i1sextv16i32)),
7184 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
7185 (VPABSDZrr VR512:$src)>;
7187 (bc_v8i64 (v8i1sextv8i64)),
7188 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
7189 (VPABSQZrr VR512:$src)>;
7191 multiclass avx512_ctlz<bits<8> opc, string OpcodeStr, Predicate prd>{
7193 defm NAME : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr, ctlz, prd>;
7196 defm VPLZCNT : avx512_ctlz<0x44, "vplzcnt", HasCDI>;
7197 defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict, HasCDI>;
7199 //===---------------------------------------------------------------------===//
7200 // Replicate Single FP - MOVSHDUP and MOVSLDUP
7201 //===---------------------------------------------------------------------===//
7202 multiclass avx512_replicate<bits<8> opc, string OpcodeStr, SDNode OpNode>{
7203 defm NAME: avx512_unary_rm_vl<opc, OpcodeStr, OpNode, avx512vl_f32_info,
7207 defm VMOVSHDUP : avx512_replicate<0x16, "vmovshdup", X86Movshdup>;
7208 defm VMOVSLDUP : avx512_replicate<0x12, "vmovsldup", X86Movsldup>;
7210 //===----------------------------------------------------------------------===//
7211 // AVX-512 - MOVDDUP
7212 //===----------------------------------------------------------------------===//
7214 multiclass avx512_movddup_128<bits<8> opc, string OpcodeStr, SDNode OpNode,
7215 X86VectorVTInfo _> {
7216 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7217 (ins _.RC:$src), OpcodeStr, "$src", "$src",
7218 (_.VT (OpNode (_.VT _.RC:$src)))>, EVEX;
7220 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7221 (ins _.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
7222 (_.VT (OpNode (_.VT (scalar_to_vector
7223 (_.ScalarLdFrag addr:$src)))))>,
7224 EVEX, EVEX_CD8<_.EltSize, CD8VH>;
7227 multiclass avx512_movddup_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
7228 AVX512VLVectorVTInfo VTInfo> {
7230 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
7232 let Predicates = [HasAVX512, HasVLX] in {
7233 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
7235 defm Z128 : avx512_movddup_128<opc, OpcodeStr, OpNode, VTInfo.info128>,
7240 multiclass avx512_movddup<bits<8> opc, string OpcodeStr, SDNode OpNode>{
7241 defm NAME: avx512_movddup_common<opc, OpcodeStr, OpNode,
7242 avx512vl_f64_info>, XD, VEX_W;
7245 defm VMOVDDUP : avx512_movddup<0x12, "vmovddup", X86Movddup>;
7247 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
7248 (VMOVDDUPZ128rm addr:$src)>, Requires<[HasAVX512, HasVLX]>;
7249 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
7250 (VMOVDDUPZ128rm addr:$src)>, Requires<[HasAVX512, HasVLX]>;
7252 //===----------------------------------------------------------------------===//
7253 // AVX-512 - Unpack Instructions
7254 //===----------------------------------------------------------------------===//
7255 defm VUNPCKH : avx512_fp_binop_p<0x15, "vunpckh", X86Unpckh>;
7256 defm VUNPCKL : avx512_fp_binop_p<0x14, "vunpckl", X86Unpckl>;
7258 defm VPUNPCKLBW : avx512_binop_rm_vl_b<0x60, "vpunpcklbw", X86Unpckl,
7259 SSE_INTALU_ITINS_P, HasBWI>;
7260 defm VPUNPCKHBW : avx512_binop_rm_vl_b<0x68, "vpunpckhbw", X86Unpckh,
7261 SSE_INTALU_ITINS_P, HasBWI>;
7262 defm VPUNPCKLWD : avx512_binop_rm_vl_w<0x61, "vpunpcklwd", X86Unpckl,
7263 SSE_INTALU_ITINS_P, HasBWI>;
7264 defm VPUNPCKHWD : avx512_binop_rm_vl_w<0x69, "vpunpckhwd", X86Unpckh,
7265 SSE_INTALU_ITINS_P, HasBWI>;
7267 defm VPUNPCKLDQ : avx512_binop_rm_vl_d<0x62, "vpunpckldq", X86Unpckl,
7268 SSE_INTALU_ITINS_P, HasAVX512>;
7269 defm VPUNPCKHDQ : avx512_binop_rm_vl_d<0x6A, "vpunpckhdq", X86Unpckh,
7270 SSE_INTALU_ITINS_P, HasAVX512>;
7271 defm VPUNPCKLQDQ : avx512_binop_rm_vl_q<0x6C, "vpunpcklqdq", X86Unpckl,
7272 SSE_INTALU_ITINS_P, HasAVX512>;
7273 defm VPUNPCKHQDQ : avx512_binop_rm_vl_q<0x6D, "vpunpckhqdq", X86Unpckh,
7274 SSE_INTALU_ITINS_P, HasAVX512>;
7276 //===----------------------------------------------------------------------===//
7277 // AVX-512 - Extract & Insert Integer Instructions
7278 //===----------------------------------------------------------------------===//
7280 multiclass avx512_extract_elt_bw_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7281 X86VectorVTInfo _> {
7283 def mr : AVX512Ii8<opc, MRMDestMem, (outs),
7284 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7285 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7286 [(store (_.EltVT (trunc (assertzext (OpNode (_.VT _.RC:$src1),
7289 EVEX, EVEX_CD8<_.EltSize, CD8VT1>;
7292 multiclass avx512_extract_elt_b<string OpcodeStr, X86VectorVTInfo _> {
7293 let Predicates = [HasBWI] in {
7294 def rr : AVX512Ii8<0x14, MRMDestReg, (outs GR32orGR64:$dst),
7295 (ins _.RC:$src1, u8imm:$src2),
7296 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7297 [(set GR32orGR64:$dst,
7298 (X86pextrb (_.VT _.RC:$src1), imm:$src2))]>,
7301 defm NAME : avx512_extract_elt_bw_m<0x14, OpcodeStr, X86pextrb, _>, TAPD;
7305 multiclass avx512_extract_elt_w<string OpcodeStr, X86VectorVTInfo _> {
7306 let Predicates = [HasBWI] in {
7307 def rr : AVX512Ii8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst),
7308 (ins _.RC:$src1, u8imm:$src2),
7309 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7310 [(set GR32orGR64:$dst,
7311 (X86pextrw (_.VT _.RC:$src1), imm:$src2))]>,
7314 def rr_REV : AVX512Ii8<0x15, MRMDestReg, (outs GR32orGR64:$dst),
7315 (ins _.RC:$src1, u8imm:$src2),
7316 OpcodeStr#".s\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7319 defm NAME : avx512_extract_elt_bw_m<0x15, OpcodeStr, X86pextrw, _>, TAPD;
7323 multiclass avx512_extract_elt_dq<string OpcodeStr, X86VectorVTInfo _,
7324 RegisterClass GRC> {
7325 let Predicates = [HasDQI] in {
7326 def rr : AVX512Ii8<0x16, MRMDestReg, (outs GRC:$dst),
7327 (ins _.RC:$src1, u8imm:$src2),
7328 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7330 (extractelt (_.VT _.RC:$src1), imm:$src2))]>,
7334 def mr : AVX512Ii8<0x16, MRMDestMem, (outs),
7335 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7336 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7337 [(store (extractelt (_.VT _.RC:$src1),
7338 imm:$src2),addr:$dst)]>,
7339 EVEX, EVEX_CD8<_.EltSize, CD8VT1>, TAPD;
7343 defm VPEXTRBZ : avx512_extract_elt_b<"vpextrb", v16i8x_info>;
7344 defm VPEXTRWZ : avx512_extract_elt_w<"vpextrw", v8i16x_info>;
7345 defm VPEXTRDZ : avx512_extract_elt_dq<"vpextrd", v4i32x_info, GR32>;
7346 defm VPEXTRQZ : avx512_extract_elt_dq<"vpextrq", v2i64x_info, GR64>, VEX_W;
7348 multiclass avx512_insert_elt_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7349 X86VectorVTInfo _, PatFrag LdFrag> {
7350 def rm : AVX512Ii8<opc, MRMSrcMem, (outs _.RC:$dst),
7351 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
7352 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7354 (_.VT (OpNode _.RC:$src1, (LdFrag addr:$src2), imm:$src3)))]>,
7355 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
7358 multiclass avx512_insert_elt_bw<bits<8> opc, string OpcodeStr, SDNode OpNode,
7359 X86VectorVTInfo _, PatFrag LdFrag> {
7360 let Predicates = [HasBWI] in {
7361 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7362 (ins _.RC:$src1, GR32orGR64:$src2, u8imm:$src3),
7363 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7365 (OpNode _.RC:$src1, GR32orGR64:$src2, imm:$src3))]>, EVEX_4V;
7367 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, OpNode, _, LdFrag>;
7371 multiclass avx512_insert_elt_dq<bits<8> opc, string OpcodeStr,
7372 X86VectorVTInfo _, RegisterClass GRC> {
7373 let Predicates = [HasDQI] in {
7374 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7375 (ins _.RC:$src1, GRC:$src2, u8imm:$src3),
7376 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7378 (_.VT (insertelt _.RC:$src1, GRC:$src2, imm:$src3)))]>,
7381 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, insertelt, _,
7382 _.ScalarLdFrag>, TAPD;
7386 defm VPINSRBZ : avx512_insert_elt_bw<0x20, "vpinsrb", X86pinsrb, v16i8x_info,
7388 defm VPINSRWZ : avx512_insert_elt_bw<0xC4, "vpinsrw", X86pinsrw, v8i16x_info,
7390 defm VPINSRDZ : avx512_insert_elt_dq<0x22, "vpinsrd", v4i32x_info, GR32>;
7391 defm VPINSRQZ : avx512_insert_elt_dq<0x22, "vpinsrq", v2i64x_info, GR64>, VEX_W;
7392 //===----------------------------------------------------------------------===//
7393 // VSHUFPS - VSHUFPD Operations
7394 //===----------------------------------------------------------------------===//
7395 multiclass avx512_shufp<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
7396 AVX512VLVectorVTInfo VTInfo_FP>{
7397 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0xC6, X86Shufp>,
7398 EVEX_CD8<VTInfo_FP.info512.EltSize, CD8VF>,
7399 AVX512AIi8Base, EVEX_4V;
7402 defm VSHUFPS: avx512_shufp<"vshufps", avx512vl_i32_info, avx512vl_f32_info>, PS;
7403 defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_i64_info, avx512vl_f64_info>, PD, VEX_W;
7404 //===----------------------------------------------------------------------===//
7405 // AVX-512 - Byte shift Left/Right
7406 //===----------------------------------------------------------------------===//
7408 multiclass avx512_shift_packed<bits<8> opc, SDNode OpNode, Format MRMr,
7409 Format MRMm, string OpcodeStr, X86VectorVTInfo _>{
7410 def rr : AVX512<opc, MRMr,
7411 (outs _.RC:$dst), (ins _.RC:$src1, u8imm:$src2),
7412 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7413 [(set _.RC:$dst,(_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>;
7415 def rm : AVX512<opc, MRMm,
7416 (outs _.RC:$dst), (ins _.MemOp:$src1, u8imm:$src2),
7417 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7418 [(set _.RC:$dst,(_.VT (OpNode
7419 (_.LdFrag addr:$src1), (i8 imm:$src2))))]>;
7422 multiclass avx512_shift_packed_all<bits<8> opc, SDNode OpNode, Format MRMr,
7423 Format MRMm, string OpcodeStr, Predicate prd>{
7424 let Predicates = [prd] in
7425 defm Z512 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7426 OpcodeStr, v8i64_info>, EVEX_V512;
7427 let Predicates = [prd, HasVLX] in {
7428 defm Z256 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7429 OpcodeStr, v4i64x_info>, EVEX_V256;
7430 defm Z128 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7431 OpcodeStr, v2i64x_info>, EVEX_V128;
7434 defm VPSLLDQ : avx512_shift_packed_all<0x73, X86vshldq, MRM7r, MRM7m, "vpslldq",
7435 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7436 defm VPSRLDQ : avx512_shift_packed_all<0x73, X86vshrdq, MRM3r, MRM3m, "vpsrldq",
7437 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7440 multiclass avx512_psadbw_packed<bits<8> opc, SDNode OpNode,
7441 string OpcodeStr, X86VectorVTInfo _dst,
7442 X86VectorVTInfo _src>{
7443 def rr : AVX512BI<opc, MRMSrcReg,
7444 (outs _dst.RC:$dst), (ins _src.RC:$src1, _src.RC:$src2),
7445 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7446 [(set _dst.RC:$dst,(_dst.VT
7447 (OpNode (_src.VT _src.RC:$src1),
7448 (_src.VT _src.RC:$src2))))]>;
7450 def rm : AVX512BI<opc, MRMSrcMem,
7451 (outs _dst.RC:$dst), (ins _src.RC:$src1, _src.MemOp:$src2),
7452 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7453 [(set _dst.RC:$dst,(_dst.VT
7454 (OpNode (_src.VT _src.RC:$src1),
7455 (_src.VT (bitconvert
7456 (_src.LdFrag addr:$src2))))))]>;
7459 multiclass avx512_psadbw_packed_all<bits<8> opc, SDNode OpNode,
7460 string OpcodeStr, Predicate prd> {
7461 let Predicates = [prd] in
7462 defm Z512 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v8i64_info,
7463 v64i8_info>, EVEX_V512;
7464 let Predicates = [prd, HasVLX] in {
7465 defm Z256 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v4i64x_info,
7466 v32i8x_info>, EVEX_V256;
7467 defm Z128 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v2i64x_info,
7468 v16i8x_info>, EVEX_V128;
7472 defm VPSADBW : avx512_psadbw_packed_all<0xf6, X86psadbw, "vpsadbw",
7475 multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode,
7477 let Constraints = "$src1 = $dst" in {
7478 defm rri : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
7479 (ins _.RC:$src2, _.RC:$src3, u8imm:$src4),
7480 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src3",
7481 (OpNode (_.VT _.RC:$src1),
7484 (i8 imm:$src4))>, AVX512AIi8Base, EVEX_4V;
7485 let mayLoad = 1 in {
7486 defm rmi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7487 (ins _.RC:$src2, _.MemOp:$src3, u8imm:$src4),
7488 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src3",
7489 (OpNode (_.VT _.RC:$src1),
7491 (_.VT (bitconvert (_.LdFrag addr:$src3))),
7493 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7494 defm rmbi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7495 (ins _.RC:$src2, _.ScalarMemOp:$src3, u8imm:$src4),
7496 OpcodeStr, "$src4, ${src3}"##_.BroadcastStr##", $src2",
7497 "$src2, ${src3}"##_.BroadcastStr##", $src4",
7498 (OpNode (_.VT _.RC:$src1),
7500 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
7501 (i8 imm:$src4))>, EVEX_B,
7502 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7504 }// Constraints = "$src1 = $dst"
7507 multiclass avx512_common_ternlog<string OpcodeStr, AVX512VLVectorVTInfo _>{
7508 let Predicates = [HasAVX512] in
7509 defm Z : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info512>, EVEX_V512;
7510 let Predicates = [HasAVX512, HasVLX] in {
7511 defm Z128 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info128>, EVEX_V128;
7512 defm Z256 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info256>, EVEX_V256;
7516 defm VPTERNLOGD : avx512_common_ternlog<"vpternlogd", avx512vl_i32_info>;
7517 defm VPTERNLOGQ : avx512_common_ternlog<"vpternlogq", avx512vl_i64_info>, VEX_W;