1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def i32x_info : X86VectorVTInfo<1, i32, GR32, "si">;
149 def i64x_info : X86VectorVTInfo<1, i64, GR64, "sq">;
150 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
151 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
153 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
154 X86VectorVTInfo i128> {
155 X86VectorVTInfo info512 = i512;
156 X86VectorVTInfo info256 = i256;
157 X86VectorVTInfo info128 = i128;
160 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
162 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
164 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
166 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
168 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
170 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
173 // This multiclass generates the masking variants from the non-masking
174 // variant. It only provides the assembly pieces for the masking variants.
175 // It assumes custom ISel patterns for masking which can be provided as
176 // template arguments.
177 multiclass AVX512_maskable_custom<bits<8> O, Format F,
179 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
181 string AttSrcAsm, string IntelSrcAsm,
183 list<dag> MaskingPattern,
184 list<dag> ZeroMaskingPattern,
185 string MaskingConstraint = "",
186 InstrItinClass itin = NoItinerary,
187 bit IsCommutable = 0> {
188 let isCommutable = IsCommutable in
189 def NAME: AVX512<O, F, Outs, Ins,
190 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
191 "$dst , "#IntelSrcAsm#"}",
194 // Prefer over VMOV*rrk Pat<>
195 let AddedComplexity = 20 in
196 def NAME#k: AVX512<O, F, Outs, MaskingIns,
197 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
198 "$dst {${mask}}, "#IntelSrcAsm#"}",
199 MaskingPattern, itin>,
201 // In case of the 3src subclass this is overridden with a let.
202 string Constraints = MaskingConstraint;
204 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
205 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
206 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
207 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
214 // Common base class of AVX512_maskable and AVX512_maskable_3src.
215 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
217 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
219 string AttSrcAsm, string IntelSrcAsm,
220 dag RHS, dag MaskingRHS,
221 SDNode Select = vselect,
222 string MaskingConstraint = "",
223 InstrItinClass itin = NoItinerary,
224 bit IsCommutable = 0> :
225 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
226 AttSrcAsm, IntelSrcAsm,
227 [(set _.RC:$dst, RHS)],
228 [(set _.RC:$dst, MaskingRHS)],
230 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
231 MaskingConstraint, NoItinerary, IsCommutable>;
233 // This multiclass generates the unconditional/non-masking, the masking and
234 // the zero-masking variant of the vector instruction. In the masking case, the
235 // perserved vector elements come from a new dummy input operand tied to $dst.
236 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
237 dag Outs, dag Ins, string OpcodeStr,
238 string AttSrcAsm, string IntelSrcAsm,
240 InstrItinClass itin = NoItinerary,
241 bit IsCommutable = 0> :
242 AVX512_maskable_common<O, F, _, Outs, Ins,
243 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
244 !con((ins _.KRCWM:$mask), Ins),
245 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
246 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
247 "$src0 = $dst", itin, IsCommutable>;
249 // This multiclass generates the unconditional/non-masking, the masking and
250 // the zero-masking variant of the scalar instruction.
251 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
252 dag Outs, dag Ins, string OpcodeStr,
253 string AttSrcAsm, string IntelSrcAsm,
255 InstrItinClass itin = NoItinerary,
256 bit IsCommutable = 0> :
257 AVX512_maskable_common<O, F, _, Outs, Ins,
258 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
259 !con((ins _.KRCWM:$mask), Ins),
260 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
261 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
262 "$src0 = $dst", itin, IsCommutable>;
264 // Similar to AVX512_maskable but in this case one of the source operands
265 // ($src1) is already tied to $dst so we just use that for the preserved
266 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
268 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
269 dag Outs, dag NonTiedIns, string OpcodeStr,
270 string AttSrcAsm, string IntelSrcAsm,
272 AVX512_maskable_common<O, F, _, Outs,
273 !con((ins _.RC:$src1), NonTiedIns),
274 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
275 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
276 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
277 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
279 multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
280 dag Outs, dag NonTiedIns, string OpcodeStr,
281 string AttSrcAsm, string IntelSrcAsm,
283 AVX512_maskable_common<O, F, _, Outs,
284 !con((ins _.RC:$src1), NonTiedIns),
285 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
286 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
287 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
288 (X86select _.KRCWM:$mask, RHS, _.RC:$src1)>;
290 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
293 string AttSrcAsm, string IntelSrcAsm,
295 AVX512_maskable_custom<O, F, Outs, Ins,
296 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
297 !con((ins _.KRCWM:$mask), Ins),
298 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
302 // Instruction with mask that puts result in mask register,
303 // like "compare" and "vptest"
304 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
306 dag Ins, dag MaskingIns,
308 string AttSrcAsm, string IntelSrcAsm,
310 list<dag> MaskingPattern,
312 InstrItinClass itin = NoItinerary> {
313 def NAME: AVX512<O, F, Outs, Ins,
314 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
315 "$dst "#Round#", "#IntelSrcAsm#"}",
318 def NAME#k: AVX512<O, F, Outs, MaskingIns,
319 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
320 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
321 MaskingPattern, itin>, EVEX_K;
324 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
326 dag Ins, dag MaskingIns,
328 string AttSrcAsm, string IntelSrcAsm,
329 dag RHS, dag MaskingRHS,
331 InstrItinClass itin = NoItinerary> :
332 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
333 AttSrcAsm, IntelSrcAsm,
334 [(set _.KRC:$dst, RHS)],
335 [(set _.KRC:$dst, MaskingRHS)],
338 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
339 dag Outs, dag Ins, string OpcodeStr,
340 string AttSrcAsm, string IntelSrcAsm,
341 dag RHS, string Round = "",
342 InstrItinClass itin = NoItinerary> :
343 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
344 !con((ins _.KRCWM:$mask), Ins),
345 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
346 (and _.KRCWM:$mask, RHS),
349 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
350 dag Outs, dag Ins, string OpcodeStr,
351 string AttSrcAsm, string IntelSrcAsm> :
352 AVX512_maskable_custom_cmp<O, F, Outs,
353 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
354 AttSrcAsm, IntelSrcAsm,
355 [],[],"", NoItinerary>;
357 // Bitcasts between 512-bit vector types. Return the original type since
358 // no instruction is needed for the conversion
359 let Predicates = [HasAVX512] in {
360 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
361 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
362 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
363 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
364 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
365 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
366 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
367 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
368 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
369 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
370 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
371 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
372 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
373 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
374 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
375 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
376 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
377 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
378 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
379 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
380 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
381 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
382 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
383 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
384 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
385 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
386 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
387 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
388 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
389 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
390 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
392 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
393 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
394 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
395 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
396 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
397 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
398 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
399 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
400 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
401 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
402 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
403 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
404 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
405 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
406 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
407 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
408 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
409 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
410 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
411 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
412 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
413 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
414 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
415 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
416 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
417 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
418 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
419 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
420 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
421 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
423 // Bitcasts between 256-bit vector types. Return the original type since
424 // no instruction is needed for the conversion
425 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
426 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
427 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
428 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
429 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
430 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
431 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
432 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
433 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
434 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
435 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
436 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
437 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
438 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
439 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
440 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
441 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
442 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
443 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
444 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
445 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
446 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
447 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
448 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
449 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
450 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
451 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
452 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
453 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
454 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
458 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
461 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
462 isPseudo = 1, Predicates = [HasAVX512] in {
463 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
464 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
467 let Predicates = [HasAVX512] in {
468 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
469 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
470 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
473 //===----------------------------------------------------------------------===//
474 // AVX-512 - VECTOR INSERT
476 multiclass vinsert_for_size<int Opcode, X86VectorVTInfo From, X86VectorVTInfo To,
477 PatFrag vinsert_insert> {
478 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
479 defm rr : AVX512_maskable<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
480 (ins To.RC:$src1, From.RC:$src2, i32u8imm:$src3),
481 "vinsert" # From.EltTypeName # "x" # From.NumElts,
482 "$src3, $src2, $src1", "$src1, $src2, $src3",
483 (vinsert_insert:$src3 (To.VT To.RC:$src1),
484 (From.VT From.RC:$src2),
485 (iPTR imm))>, AVX512AIi8Base, EVEX_4V;
488 defm rm : AVX512_maskable<Opcode, MRMSrcMem, To, (outs To.RC:$dst),
489 (ins To.RC:$src1, From.MemOp:$src2, i32u8imm:$src3),
490 "vinsert" # From.EltTypeName # "x" # From.NumElts,
491 "$src3, $src2, $src1", "$src1, $src2, $src3",
492 (vinsert_insert:$src3 (To.VT To.RC:$src1),
493 (From.VT (bitconvert (From.LdFrag addr:$src2))),
494 (iPTR imm))>, AVX512AIi8Base, EVEX_4V,
495 EVEX_CD8<From.EltSize, From.CD8TupleForm>;
499 multiclass vinsert_for_size_lowering<string InstrStr, X86VectorVTInfo From,
500 X86VectorVTInfo To, PatFrag vinsert_insert,
501 SDNodeXForm INSERT_get_vinsert_imm , list<Predicate> p> {
502 let Predicates = p in {
503 def : Pat<(vinsert_insert:$ins
504 (To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
505 (To.VT (!cast<Instruction>(InstrStr#"rr")
506 To.RC:$src1, From.RC:$src2,
507 (INSERT_get_vinsert_imm To.RC:$ins)))>;
509 def : Pat<(vinsert_insert:$ins
511 (From.VT (bitconvert (From.LdFrag addr:$src2))),
513 (To.VT (!cast<Instruction>(InstrStr#"rm")
514 To.RC:$src1, addr:$src2,
515 (INSERT_get_vinsert_imm To.RC:$ins)))>;
519 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
520 ValueType EltVT64, int Opcode256> {
522 let Predicates = [HasVLX] in
523 defm NAME # "32x4Z256" : vinsert_for_size<Opcode128,
524 X86VectorVTInfo< 4, EltVT32, VR128X>,
525 X86VectorVTInfo< 8, EltVT32, VR256X>,
526 vinsert128_insert>, EVEX_V256;
528 defm NAME # "32x4Z" : vinsert_for_size<Opcode128,
529 X86VectorVTInfo< 4, EltVT32, VR128X>,
530 X86VectorVTInfo<16, EltVT32, VR512>,
531 vinsert128_insert>, EVEX_V512;
533 defm NAME # "64x4Z" : vinsert_for_size<Opcode256,
534 X86VectorVTInfo< 4, EltVT64, VR256X>,
535 X86VectorVTInfo< 8, EltVT64, VR512>,
536 vinsert256_insert>, VEX_W, EVEX_V512;
538 let Predicates = [HasVLX, HasDQI] in
539 defm NAME # "64x2Z256" : vinsert_for_size<Opcode128,
540 X86VectorVTInfo< 2, EltVT64, VR128X>,
541 X86VectorVTInfo< 4, EltVT64, VR256X>,
542 vinsert128_insert>, VEX_W, EVEX_V256;
544 let Predicates = [HasDQI] in {
545 defm NAME # "64x2Z" : vinsert_for_size<Opcode128,
546 X86VectorVTInfo< 2, EltVT64, VR128X>,
547 X86VectorVTInfo< 8, EltVT64, VR512>,
548 vinsert128_insert>, VEX_W, EVEX_V512;
550 defm NAME # "32x8Z" : vinsert_for_size<Opcode256,
551 X86VectorVTInfo< 8, EltVT32, VR256X>,
552 X86VectorVTInfo<16, EltVT32, VR512>,
553 vinsert256_insert>, EVEX_V512;
557 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
558 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
560 // Codegen pattern with the alternative types,
561 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
562 defm : vinsert_for_size_lowering<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info,
563 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
564 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info,
565 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
567 defm : vinsert_for_size_lowering<"VINSERTF32x4Z", v2f64x_info, v8f64_info,
568 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
569 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v2i64x_info, v8i64_info,
570 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
572 defm : vinsert_for_size_lowering<"VINSERTF64x4Z", v8f32x_info, v16f32_info,
573 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
574 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v8i32x_info, v16i32_info,
575 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
577 // Codegen pattern with the alternative types insert VEC128 into VEC256
578 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info,
579 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
580 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info,
581 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
582 // Codegen pattern with the alternative types insert VEC128 into VEC512
583 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v8i16x_info, v32i16_info,
584 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
585 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v16i8x_info, v64i8_info,
586 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
587 // Codegen pattern with the alternative types insert VEC256 into VEC512
588 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v16i16x_info, v32i16_info,
589 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
590 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v32i8x_info, v64i8_info,
591 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
593 // vinsertps - insert f32 to XMM
594 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
595 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
596 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
597 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
599 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
600 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
601 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
602 [(set VR128X:$dst, (X86insertps VR128X:$src1,
603 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
604 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
606 //===----------------------------------------------------------------------===//
607 // AVX-512 VECTOR EXTRACT
610 multiclass vextract_for_size_first_position_lowering<X86VectorVTInfo From,
611 X86VectorVTInfo To> {
612 // A subvector extract from the first vector position is
613 // a subregister copy that needs no instruction.
614 def NAME # To.NumElts:
615 Pat<(To.VT (extract_subvector (From.VT From.RC:$src),(iPTR 0))),
616 (To.VT (EXTRACT_SUBREG (From.VT From.RC:$src), To.SubRegIdx))>;
619 multiclass vextract_for_size<int Opcode,
620 X86VectorVTInfo From, X86VectorVTInfo To,
621 PatFrag vextract_extract> :
622 vextract_for_size_first_position_lowering<From, To> {
624 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
625 // use AVX512_maskable_in_asm (AVX512_maskable can't be used due to
626 // vextract_extract), we interesting only in patterns without mask,
627 // intrinsics pattern match generated bellow.
628 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
629 (ins From.RC:$src1, i32u8imm:$idx),
630 "vextract" # To.EltTypeName # "x" # To.NumElts,
631 "$idx, $src1", "$src1, $idx",
632 [(set To.RC:$dst, (vextract_extract:$idx (From.VT From.RC:$src1),
634 AVX512AIi8Base, EVEX;
635 let mayStore = 1 in {
636 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
637 (ins To.MemOp:$dst, From.RC:$src1, i32u8imm:$src2),
638 "vextract" # To.EltTypeName # "x" # To.NumElts #
639 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
642 def rmk : AVX512AIi8<Opcode, MRMDestMem, (outs),
643 (ins To.MemOp:$dst, To.KRCWM:$mask,
644 From.RC:$src1, i32u8imm:$src2),
645 "vextract" # To.EltTypeName # "x" # To.NumElts #
646 "\t{$src2, $src1, $dst {${mask}}|"
647 "$dst {${mask}}, $src1, $src2}",
652 // Intrinsic call with masking.
653 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
654 "x" # To.NumElts # "_" # From.Size)
655 From.RC:$src1, (iPTR imm:$idx), To.RC:$src0, To.MRC:$mask),
656 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
657 From.ZSuffix # "rrk")
659 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
660 From.RC:$src1, imm:$idx)>;
662 // Intrinsic call with zero-masking.
663 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
664 "x" # To.NumElts # "_" # From.Size)
665 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, To.MRC:$mask),
666 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
667 From.ZSuffix # "rrkz")
668 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
669 From.RC:$src1, imm:$idx)>;
671 // Intrinsic call without masking.
672 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
673 "x" # To.NumElts # "_" # From.Size)
674 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
675 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
677 From.RC:$src1, imm:$idx)>;
680 // Codegen pattern for the alternative types
681 multiclass vextract_for_size_lowering<string InstrStr, X86VectorVTInfo From,
682 X86VectorVTInfo To, PatFrag vextract_extract,
683 SDNodeXForm EXTRACT_get_vextract_imm, list<Predicate> p> :
684 vextract_for_size_first_position_lowering<From, To> {
686 let Predicates = p in
687 def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)),
688 (To.VT (!cast<Instruction>(InstrStr#"rr")
690 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
693 multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
694 ValueType EltVT64, int Opcode256> {
695 defm NAME # "32x4Z" : vextract_for_size<Opcode128,
696 X86VectorVTInfo<16, EltVT32, VR512>,
697 X86VectorVTInfo< 4, EltVT32, VR128X>,
698 vextract128_extract>,
699 EVEX_V512, EVEX_CD8<32, CD8VT4>;
700 defm NAME # "64x4Z" : vextract_for_size<Opcode256,
701 X86VectorVTInfo< 8, EltVT64, VR512>,
702 X86VectorVTInfo< 4, EltVT64, VR256X>,
703 vextract256_extract>,
704 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>;
705 let Predicates = [HasVLX] in
706 defm NAME # "32x4Z256" : vextract_for_size<Opcode128,
707 X86VectorVTInfo< 8, EltVT32, VR256X>,
708 X86VectorVTInfo< 4, EltVT32, VR128X>,
709 vextract128_extract>,
710 EVEX_V256, EVEX_CD8<32, CD8VT4>;
711 let Predicates = [HasVLX, HasDQI] in
712 defm NAME # "64x2Z256" : vextract_for_size<Opcode128,
713 X86VectorVTInfo< 4, EltVT64, VR256X>,
714 X86VectorVTInfo< 2, EltVT64, VR128X>,
715 vextract128_extract>,
716 VEX_W, EVEX_V256, EVEX_CD8<64, CD8VT2>;
717 let Predicates = [HasDQI] in {
718 defm NAME # "64x2Z" : vextract_for_size<Opcode128,
719 X86VectorVTInfo< 8, EltVT64, VR512>,
720 X86VectorVTInfo< 2, EltVT64, VR128X>,
721 vextract128_extract>,
722 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>;
723 defm NAME # "32x8Z" : vextract_for_size<Opcode256,
724 X86VectorVTInfo<16, EltVT32, VR512>,
725 X86VectorVTInfo< 8, EltVT32, VR256X>,
726 vextract256_extract>,
727 EVEX_V512, EVEX_CD8<32, CD8VT8>;
731 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
732 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
734 // extract_subvector codegen patterns with the alternative types.
735 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
736 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z", v8f64_info, v2f64x_info,
737 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
738 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v8i64_info, v2i64x_info,
739 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
741 defm : vextract_for_size_lowering<"VEXTRACTF64x4Z", v16f32_info, v8f32x_info,
742 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
743 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v16i32_info, v8i32x_info,
744 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
746 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z256", v4f64x_info, v2f64x_info,
747 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
748 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v4i64x_info, v2i64x_info,
749 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
751 // Codegen pattern with the alternative types extract VEC128 from VEC512
752 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v32i16_info, v8i16x_info,
753 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
754 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v64i8_info, v16i8x_info,
755 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
756 // Codegen pattern with the alternative types extract VEC256 from VEC512
757 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v32i16_info, v16i16x_info,
758 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
759 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v64i8_info, v32i8x_info,
760 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
762 // A 128-bit subvector insert to the first 512-bit vector position
763 // is a subregister copy that needs no instruction.
764 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
765 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
766 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
768 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
769 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
770 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
772 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
773 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
774 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
776 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
777 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
778 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
781 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
782 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
783 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
784 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
785 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
786 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
787 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
788 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
790 // vextractps - extract 32 bits from XMM
791 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
792 (ins VR128X:$src1, u8imm:$src2),
793 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
794 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
797 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
798 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
799 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
800 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
801 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
803 //===---------------------------------------------------------------------===//
806 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
807 ValueType svt, X86VectorVTInfo _> {
808 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
809 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
810 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
814 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
815 (ins _.ScalarMemOp:$src),
816 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
817 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
822 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
823 AVX512VLVectorVTInfo _> {
824 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
827 let Predicates = [HasVLX] in {
828 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
833 let ExeDomain = SSEPackedSingle in {
834 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
835 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
836 let Predicates = [HasVLX] in {
837 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
838 v4f32, v4f32x_info>, EVEX_V128,
839 EVEX_CD8<32, CD8VT1>;
843 let ExeDomain = SSEPackedDouble in {
844 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
845 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
848 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
849 // Later, we can canonize broadcast instructions before ISel phase and
850 // eliminate additional patterns on ISel.
851 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
852 // representations of source
853 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
854 X86VectorVTInfo _, RegisterClass SrcRC_v,
855 RegisterClass SrcRC_s> {
856 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
857 (!cast<Instruction>(InstName##"r")
858 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
860 let AddedComplexity = 30 in {
861 def : Pat<(_.VT (vselect _.KRCWM:$mask,
862 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
863 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
864 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
866 def : Pat<(_.VT(vselect _.KRCWM:$mask,
867 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
868 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
869 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
873 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
875 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
878 let Predicates = [HasVLX] in {
879 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
880 v8f32x_info, VR128X, FR32X>;
881 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
882 v4f32x_info, VR128X, FR32X>;
883 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
884 v4f64x_info, VR128X, FR64X>;
887 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
888 (VBROADCASTSSZm addr:$src)>;
889 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
890 (VBROADCASTSDZm addr:$src)>;
892 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
893 (VBROADCASTSSZm addr:$src)>;
894 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
895 (VBROADCASTSDZm addr:$src)>;
897 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
898 RegisterClass SrcRC> {
899 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
900 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
901 "$src", "$src", []>, T8PD, EVEX;
904 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
905 RegisterClass SrcRC, Predicate prd> {
906 let Predicates = [prd] in
907 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
908 let Predicates = [prd, HasVLX] in {
909 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
910 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
914 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
916 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
918 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
920 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
923 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
924 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
926 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
927 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
929 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
930 (VPBROADCASTDrZr GR32:$src)>;
931 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
932 (VPBROADCASTQrZr GR64:$src)>;
934 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
935 (VPBROADCASTDrZr GR32:$src)>;
936 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
937 (VPBROADCASTQrZr GR64:$src)>;
939 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
940 (v16i32 immAllZerosV), (i16 GR16:$mask))),
941 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
942 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
943 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
944 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
946 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
947 X86MemOperand x86memop, PatFrag ld_frag,
948 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
950 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
951 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
953 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
954 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
956 !strconcat(OpcodeStr,
957 "\t{$src, ${dst} {${mask}} |${dst} {${mask}}, $src}"),
959 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
961 !strconcat(OpcodeStr,
962 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
965 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
966 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
968 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
969 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
971 !strconcat(OpcodeStr,
972 "\t{$src, ${dst} {${mask}}|${dst} {${mask}} , $src}"),
974 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
976 !strconcat(OpcodeStr,
977 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
978 [(set DstRC:$dst, (OpVT (vselect KRC:$mask,
979 (X86VBroadcast (ld_frag addr:$src)),
980 (OpVT (bitconvert (v16i32 immAllZerosV))))))]>, EVEX, EVEX_KZ;
984 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
985 loadi32, VR512, v16i32, v4i32, VK16WM>,
986 EVEX_V512, EVEX_CD8<32, CD8VT1>;
987 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
988 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
989 EVEX_CD8<64, CD8VT1>;
991 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
992 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
994 def rm : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Src.MemOp:$src),
995 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
997 (_Dst.VT (X86SubVBroadcast
998 (_Src.VT (bitconvert (_Src.LdFrag addr:$src))))))]>, EVEX;
999 def rmk : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
1001 !strconcat(OpcodeStr,
1002 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
1004 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
1006 !strconcat(OpcodeStr,
1007 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1012 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1013 v16i32_info, v4i32x_info>,
1014 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1015 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1016 v16f32_info, v4f32x_info>,
1017 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1018 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
1019 v8i64_info, v4i64x_info>, VEX_W,
1020 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1021 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
1022 v8f64_info, v4f64x_info>, VEX_W,
1023 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1025 let Predicates = [HasVLX] in {
1026 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1027 v8i32x_info, v4i32x_info>,
1028 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1029 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1030 v8f32x_info, v4f32x_info>,
1031 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1033 let Predicates = [HasVLX, HasDQI] in {
1034 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1035 v4i64x_info, v2i64x_info>, VEX_W,
1036 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1037 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1038 v4f64x_info, v2f64x_info>, VEX_W,
1039 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1041 let Predicates = [HasDQI] in {
1042 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1043 v8i64_info, v2i64x_info>, VEX_W,
1044 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1045 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
1046 v16i32_info, v8i32x_info>,
1047 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1048 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1049 v8f64_info, v2f64x_info>, VEX_W,
1050 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1051 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
1052 v16f32_info, v8f32x_info>,
1053 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1056 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
1057 (VPBROADCASTDZrr VR128X:$src)>;
1058 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
1059 (VPBROADCASTQZrr VR128X:$src)>;
1061 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
1062 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
1063 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
1064 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
1066 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
1067 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
1068 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
1069 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
1071 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
1072 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
1073 def : Pat<(v16i32 (X86VBroadcast (v8i32 VR256X:$src))),
1074 (VPBROADCASTDZrr (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm))>;
1076 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
1077 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
1078 def : Pat<(v8i64 (X86VBroadcast (v4i64 VR256X:$src))),
1079 (VPBROADCASTQZrr (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm))>;
1081 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
1082 (VBROADCASTSSZr VR128X:$src)>;
1083 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
1084 (VBROADCASTSDZr VR128X:$src)>;
1086 // Provide fallback in case the load node that is used in the patterns above
1087 // is used by additional users, which prevents the pattern selection.
1088 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
1089 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
1090 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
1091 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
1094 //===----------------------------------------------------------------------===//
1095 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
1098 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
1099 RegisterClass KRC> {
1100 let Predicates = [HasCDI] in
1101 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
1102 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1103 []>, EVEX, EVEX_V512;
1105 let Predicates = [HasCDI, HasVLX] in {
1106 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
1107 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1108 []>, EVEX, EVEX_V128;
1109 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
1110 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1111 []>, EVEX, EVEX_V256;
1115 let Predicates = [HasCDI] in {
1116 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
1118 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1122 //===----------------------------------------------------------------------===//
1123 // -- VPERM2I - 3 source operands form --
1124 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr,
1125 SDNode OpNode, X86VectorVTInfo _> {
1126 let Constraints = "$src1 = $dst" in {
1127 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1128 (ins _.RC:$src2, _.RC:$src3),
1129 OpcodeStr, "$src3, $src2", "$src2, $src3",
1130 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>, EVEX_4V,
1134 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1135 (ins _.RC:$src2, _.MemOp:$src3),
1136 OpcodeStr, "$src3, $src2", "$src2, $src3",
1137 (_.VT (OpNode _.RC:$src1, _.RC:$src2,
1138 (_.VT (bitconvert (_.LdFrag addr:$src3)))))>,
1139 EVEX_4V, AVX5128IBase;
1142 multiclass avx512_perm_3src_mb<bits<8> opc, string OpcodeStr,
1143 SDNode OpNode, X86VectorVTInfo _> {
1144 let mayLoad = 1, Constraints = "$src1 = $dst" in
1145 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1146 (ins _.RC:$src2, _.ScalarMemOp:$src3),
1147 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1148 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1149 (_.VT (OpNode _.RC:$src1,
1150 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1151 AVX5128IBase, EVEX_4V, EVEX_B;
1154 multiclass avx512_perm_3src_sizes<bits<8> opc, string OpcodeStr,
1155 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1156 let Predicates = [HasAVX512] in
1157 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1158 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
1159 let Predicates = [HasVLX] in {
1160 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1161 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1163 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1164 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1168 multiclass avx512_perm_3src_sizes_w<bits<8> opc, string OpcodeStr,
1169 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1170 let Predicates = [HasBWI] in
1171 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1172 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1174 let Predicates = [HasBWI, HasVLX] in {
1175 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1176 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1178 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1179 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1183 defm VPERMI2D : avx512_perm_3src_sizes<0x76, "vpermi2d", X86VPermiv3,
1184 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1185 defm VPERMI2Q : avx512_perm_3src_sizes<0x76, "vpermi2q", X86VPermiv3,
1186 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1187 defm VPERMI2PS : avx512_perm_3src_sizes<0x77, "vpermi2ps", X86VPermiv3,
1188 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1189 defm VPERMI2PD : avx512_perm_3src_sizes<0x77, "vpermi2pd", X86VPermiv3,
1190 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1192 defm VPERMT2D : avx512_perm_3src_sizes<0x7E, "vpermt2d", X86VPermv3,
1193 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1194 defm VPERMT2Q : avx512_perm_3src_sizes<0x7E, "vpermt2q", X86VPermv3,
1195 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1196 defm VPERMT2PS : avx512_perm_3src_sizes<0x7F, "vpermt2ps", X86VPermv3,
1197 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1198 defm VPERMT2PD : avx512_perm_3src_sizes<0x7F, "vpermt2pd", X86VPermv3,
1199 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1201 defm VPERMT2W : avx512_perm_3src_sizes_w<0x7D, "vpermt2w", X86VPermv3,
1202 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1203 defm VPERMI2W : avx512_perm_3src_sizes_w<0x75, "vpermi2w", X86VPermiv3,
1204 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1206 //===----------------------------------------------------------------------===//
1207 // AVX-512 - BLEND using mask
1209 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1210 let ExeDomain = _.ExeDomain in {
1211 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1212 (ins _.RC:$src1, _.RC:$src2),
1213 !strconcat(OpcodeStr,
1214 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1216 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1217 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1218 !strconcat(OpcodeStr,
1219 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1220 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1221 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1222 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1223 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1224 !strconcat(OpcodeStr,
1225 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1226 []>, EVEX_4V, EVEX_KZ;
1227 let mayLoad = 1 in {
1228 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1229 (ins _.RC:$src1, _.MemOp:$src2),
1230 !strconcat(OpcodeStr,
1231 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1232 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1233 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1234 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1235 !strconcat(OpcodeStr,
1236 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1237 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1238 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1239 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1240 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1241 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1242 !strconcat(OpcodeStr,
1243 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1244 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1248 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1250 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1251 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1252 !strconcat(OpcodeStr,
1253 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1254 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1255 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1256 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1257 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1259 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1260 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1261 !strconcat(OpcodeStr,
1262 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1263 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1264 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1268 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1269 AVX512VLVectorVTInfo VTInfo> {
1270 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1271 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1273 let Predicates = [HasVLX] in {
1274 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1275 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1276 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1277 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1281 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1282 AVX512VLVectorVTInfo VTInfo> {
1283 let Predicates = [HasBWI] in
1284 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1286 let Predicates = [HasBWI, HasVLX] in {
1287 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1288 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1293 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1294 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1295 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1296 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1297 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1298 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1301 let Predicates = [HasAVX512] in {
1302 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1303 (v8f32 VR256X:$src2))),
1305 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1306 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1307 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1309 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1310 (v8i32 VR256X:$src2))),
1312 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1313 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1314 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1316 //===----------------------------------------------------------------------===//
1317 // Compare Instructions
1318 //===----------------------------------------------------------------------===//
1320 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1322 multiclass avx512_cmp_scalar<X86VectorVTInfo _, SDNode OpNode, SDNode OpNodeRnd>{
1324 defm rr_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1326 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1327 "vcmp${cc}"#_.Suffix,
1328 "$src2, $src1", "$src1, $src2",
1329 (OpNode (_.VT _.RC:$src1),
1333 defm rm_Int : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1335 (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1336 "vcmp${cc}"#_.Suffix,
1337 "$src2, $src1", "$src1, $src2",
1338 (OpNode (_.VT _.RC:$src1),
1339 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
1340 imm:$cc)>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1342 defm rrb_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1344 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1345 "vcmp${cc}"#_.Suffix,
1346 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1347 (OpNodeRnd (_.VT _.RC:$src1),
1350 (i32 FROUND_NO_EXC))>, EVEX_4V, EVEX_B;
1351 // Accept explicit immediate argument form instead of comparison code.
1352 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1353 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1355 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1357 "$cc, $src2, $src1", "$src1, $src2, $cc">, EVEX_4V;
1358 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1360 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1362 "$cc, $src2, $src1", "$src1, $src2, $cc">,
1363 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1365 defm rrb_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1367 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1369 "$cc,{sae}, $src2, $src1","$src1, $src2,{sae}, $cc">,
1371 }// let isAsmParserOnly = 1, hasSideEffects = 0
1373 let isCodeGenOnly = 1 in {
1374 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1375 (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, AVXCC:$cc),
1376 !strconcat("vcmp${cc}", _.Suffix,
1377 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1378 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1381 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1383 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1385 (ins _.FRC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1386 !strconcat("vcmp${cc}", _.Suffix,
1387 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1388 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1389 (_.ScalarLdFrag addr:$src2),
1391 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1395 let Predicates = [HasAVX512] in {
1396 defm VCMPSSZ : avx512_cmp_scalar<f32x_info, X86cmpms, X86cmpmsRnd>,
1398 defm VCMPSDZ : avx512_cmp_scalar<f64x_info, X86cmpms, X86cmpmsRnd>,
1399 AVX512XDIi8Base, VEX_W;
1402 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1403 X86VectorVTInfo _> {
1404 def rr : AVX512BI<opc, MRMSrcReg,
1405 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1406 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1407 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1408 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1410 def rm : AVX512BI<opc, MRMSrcMem,
1411 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1412 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1413 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1414 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1415 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1416 def rrk : AVX512BI<opc, MRMSrcReg,
1417 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1418 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1419 "$dst {${mask}}, $src1, $src2}"),
1420 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1421 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1422 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1424 def rmk : AVX512BI<opc, MRMSrcMem,
1425 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1426 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1427 "$dst {${mask}}, $src1, $src2}"),
1428 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1429 (OpNode (_.VT _.RC:$src1),
1431 (_.LdFrag addr:$src2))))))],
1432 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1435 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1436 X86VectorVTInfo _> :
1437 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1438 let mayLoad = 1 in {
1439 def rmb : AVX512BI<opc, MRMSrcMem,
1440 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1441 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1442 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1443 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1444 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1445 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1446 def rmbk : AVX512BI<opc, MRMSrcMem,
1447 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1448 _.ScalarMemOp:$src2),
1449 !strconcat(OpcodeStr,
1450 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1451 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1452 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1453 (OpNode (_.VT _.RC:$src1),
1455 (_.ScalarLdFrag addr:$src2)))))],
1456 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1460 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1461 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1462 let Predicates = [prd] in
1463 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1466 let Predicates = [prd, HasVLX] in {
1467 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1469 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1474 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1475 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1477 let Predicates = [prd] in
1478 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1481 let Predicates = [prd, HasVLX] in {
1482 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1484 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1489 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1490 avx512vl_i8_info, HasBWI>,
1493 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1494 avx512vl_i16_info, HasBWI>,
1495 EVEX_CD8<16, CD8VF>;
1497 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1498 avx512vl_i32_info, HasAVX512>,
1499 EVEX_CD8<32, CD8VF>;
1501 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1502 avx512vl_i64_info, HasAVX512>,
1503 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1505 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1506 avx512vl_i8_info, HasBWI>,
1509 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1510 avx512vl_i16_info, HasBWI>,
1511 EVEX_CD8<16, CD8VF>;
1513 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1514 avx512vl_i32_info, HasAVX512>,
1515 EVEX_CD8<32, CD8VF>;
1517 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1518 avx512vl_i64_info, HasAVX512>,
1519 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1521 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1522 (COPY_TO_REGCLASS (VPCMPGTDZrr
1523 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1524 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1526 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1527 (COPY_TO_REGCLASS (VPCMPEQDZrr
1528 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1529 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1531 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1532 X86VectorVTInfo _> {
1533 def rri : AVX512AIi8<opc, MRMSrcReg,
1534 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1535 !strconcat("vpcmp${cc}", Suffix,
1536 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1537 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1539 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1541 def rmi : AVX512AIi8<opc, MRMSrcMem,
1542 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1543 !strconcat("vpcmp${cc}", Suffix,
1544 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1545 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1546 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1548 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1549 def rrik : AVX512AIi8<opc, MRMSrcReg,
1550 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1552 !strconcat("vpcmp${cc}", Suffix,
1553 "\t{$src2, $src1, $dst {${mask}}|",
1554 "$dst {${mask}}, $src1, $src2}"),
1555 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1556 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1558 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1560 def rmik : AVX512AIi8<opc, MRMSrcMem,
1561 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1563 !strconcat("vpcmp${cc}", Suffix,
1564 "\t{$src2, $src1, $dst {${mask}}|",
1565 "$dst {${mask}}, $src1, $src2}"),
1566 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1567 (OpNode (_.VT _.RC:$src1),
1568 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1570 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1572 // Accept explicit immediate argument form instead of comparison code.
1573 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1574 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1575 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1576 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1577 "$dst, $src1, $src2, $cc}"),
1578 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1580 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1581 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1582 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1583 "$dst, $src1, $src2, $cc}"),
1584 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1585 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1586 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1588 !strconcat("vpcmp", Suffix,
1589 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1590 "$dst {${mask}}, $src1, $src2, $cc}"),
1591 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1593 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1594 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1596 !strconcat("vpcmp", Suffix,
1597 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1598 "$dst {${mask}}, $src1, $src2, $cc}"),
1599 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1603 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1604 X86VectorVTInfo _> :
1605 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1606 def rmib : AVX512AIi8<opc, MRMSrcMem,
1607 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1609 !strconcat("vpcmp${cc}", Suffix,
1610 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1611 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1612 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1613 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1615 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1616 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1617 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1618 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1619 !strconcat("vpcmp${cc}", Suffix,
1620 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1621 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1622 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1623 (OpNode (_.VT _.RC:$src1),
1624 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1626 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1628 // Accept explicit immediate argument form instead of comparison code.
1629 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1630 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1631 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1633 !strconcat("vpcmp", Suffix,
1634 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1635 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1636 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1637 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1638 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1639 _.ScalarMemOp:$src2, u8imm:$cc),
1640 !strconcat("vpcmp", Suffix,
1641 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1642 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1643 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1647 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1648 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1649 let Predicates = [prd] in
1650 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1652 let Predicates = [prd, HasVLX] in {
1653 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1654 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1658 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1659 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1660 let Predicates = [prd] in
1661 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1664 let Predicates = [prd, HasVLX] in {
1665 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1667 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1672 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1673 HasBWI>, EVEX_CD8<8, CD8VF>;
1674 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1675 HasBWI>, EVEX_CD8<8, CD8VF>;
1677 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1678 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1679 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1680 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1682 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1683 HasAVX512>, EVEX_CD8<32, CD8VF>;
1684 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1685 HasAVX512>, EVEX_CD8<32, CD8VF>;
1687 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1688 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1689 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1690 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1692 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1694 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1695 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1696 "vcmp${cc}"#_.Suffix,
1697 "$src2, $src1", "$src1, $src2",
1698 (X86cmpm (_.VT _.RC:$src1),
1702 let mayLoad = 1 in {
1703 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1704 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1705 "vcmp${cc}"#_.Suffix,
1706 "$src2, $src1", "$src1, $src2",
1707 (X86cmpm (_.VT _.RC:$src1),
1708 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1711 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1713 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1714 "vcmp${cc}"#_.Suffix,
1715 "${src2}"##_.BroadcastStr##", $src1",
1716 "$src1, ${src2}"##_.BroadcastStr,
1717 (X86cmpm (_.VT _.RC:$src1),
1718 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1721 // Accept explicit immediate argument form instead of comparison code.
1722 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1723 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1725 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1727 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1729 let mayLoad = 1 in {
1730 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1732 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1734 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1736 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1738 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1740 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1741 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1746 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1747 // comparison code form (VCMP[EQ/LT/LE/...]
1748 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1749 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1750 "vcmp${cc}"#_.Suffix,
1751 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1752 (X86cmpmRnd (_.VT _.RC:$src1),
1755 (i32 FROUND_NO_EXC))>, EVEX_B;
1757 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1758 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1760 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1762 "$cc,{sae}, $src2, $src1",
1763 "$src1, $src2,{sae}, $cc">, EVEX_B;
1767 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1768 let Predicates = [HasAVX512] in {
1769 defm Z : avx512_vcmp_common<_.info512>,
1770 avx512_vcmp_sae<_.info512>, EVEX_V512;
1773 let Predicates = [HasAVX512,HasVLX] in {
1774 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1775 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1779 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1780 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1781 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1782 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1784 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1785 (COPY_TO_REGCLASS (VCMPPSZrri
1786 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1787 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1789 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1790 (COPY_TO_REGCLASS (VPCMPDZrri
1791 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1792 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1794 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1795 (COPY_TO_REGCLASS (VPCMPUDZrri
1796 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1797 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1800 // ----------------------------------------------------------------
1802 //handle fpclass instruction mask = fpclass(reg_vec, reg_vec, imm)
1803 // fpclass(reg_vec, mem_vec, imm)
1804 // fpclass(reg_vec, broadcast(eltVt), imm)
1805 multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1806 X86VectorVTInfo _, string mem, string broadcast>{
1807 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1808 (ins _.RC:$src1, i32u8imm:$src2),
1809 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1810 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1811 (i32 imm:$src2)))], NoItinerary>;
1812 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1813 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1814 OpcodeStr##_.Suffix#
1815 "\t{$src2, $src1, $dst {${mask}}| $dst {${mask}}, $src1, $src2}",
1816 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1817 (OpNode (_.VT _.RC:$src1),
1818 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1819 let mayLoad = 1 in {
1820 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1821 (ins _.MemOp:$src1, i32u8imm:$src2),
1822 OpcodeStr##_.Suffix##mem#
1823 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1824 [(set _.KRC:$dst,(OpNode
1825 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1826 (i32 imm:$src2)))], NoItinerary>;
1827 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1828 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1829 OpcodeStr##_.Suffix##mem#
1830 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1831 [(set _.KRC:$dst, (or _.KRCWM:$mask, (OpNode
1832 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1833 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1834 def rmb : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1835 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
1836 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1837 _.BroadcastStr##", $dst | $dst, ${src1}"
1838 ##_.BroadcastStr##", $src2}",
1839 [(set _.KRC:$dst,(OpNode
1840 (_.VT (X86VBroadcast
1841 (_.ScalarLdFrag addr:$src1))),
1842 (i32 imm:$src2)))], NoItinerary>,EVEX_B;
1843 def rmbk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1844 (ins _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2),
1845 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1846 _.BroadcastStr##", $dst {${mask}} | $dst {${mask}}, ${src1}"##
1847 _.BroadcastStr##", $src2}",
1848 [(set _.KRC:$dst,(or _.KRCWM:$mask, (OpNode
1849 (_.VT (X86VBroadcast
1850 (_.ScalarLdFrag addr:$src1))),
1851 (i32 imm:$src2))))], NoItinerary>,
1856 multiclass avx512_vector_fpclass_all<string OpcodeStr,
1857 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd,
1859 let Predicates = [prd] in {
1860 defm Z : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info512, "{z}",
1861 broadcast>, EVEX_V512;
1863 let Predicates = [prd, HasVLX] in {
1864 defm Z128 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info128, "{x}",
1865 broadcast>, EVEX_V128;
1866 defm Z256 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info256, "{y}",
1867 broadcast>, EVEX_V256;
1871 multiclass avx512_fp_fpclass_all<string OpcodeStr, bits<8> opcVec,
1872 SDNode OpNode, Predicate prd>{
1873 defm PS : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f32_info, opcVec,
1874 OpNode, prd, "{l}">, EVEX_CD8<32, CD8VF>;
1875 defm PD : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f64_info, opcVec,
1876 OpNode, prd, "{q}">,EVEX_CD8<64, CD8VF> , VEX_W;
1879 defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, X86Vfpclass, HasDQI>,
1880 AVX512AIi8Base,EVEX;
1882 //-----------------------------------------------------------------
1883 // Mask register copy, including
1884 // - copy between mask registers
1885 // - load/store mask registers
1886 // - copy from GPR to mask register and vice versa
1888 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1889 string OpcodeStr, RegisterClass KRC,
1890 ValueType vvt, X86MemOperand x86memop> {
1891 let hasSideEffects = 0 in {
1892 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1893 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1895 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1896 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1897 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1899 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1900 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1901 [(store KRC:$src, addr:$dst)]>;
1905 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1907 RegisterClass KRC, RegisterClass GRC> {
1908 let hasSideEffects = 0 in {
1909 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1910 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1911 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1912 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1916 let Predicates = [HasDQI] in
1917 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1918 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1921 let Predicates = [HasAVX512] in
1922 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1923 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1926 let Predicates = [HasBWI] in {
1927 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1929 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1933 let Predicates = [HasBWI] in {
1934 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1936 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1940 // GR from/to mask register
1941 let Predicates = [HasDQI] in {
1942 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1943 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1944 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1945 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1947 let Predicates = [HasAVX512] in {
1948 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1949 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1950 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1951 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1953 let Predicates = [HasBWI] in {
1954 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1955 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1957 let Predicates = [HasBWI] in {
1958 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1959 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1963 let Predicates = [HasDQI] in {
1964 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1965 (KMOVBmk addr:$dst, VK8:$src)>;
1966 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1967 (KMOVBkm addr:$src)>;
1969 def : Pat<(store VK4:$src, addr:$dst),
1970 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK4:$src, VK8))>;
1971 def : Pat<(store VK2:$src, addr:$dst),
1972 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK2:$src, VK8))>;
1974 let Predicates = [HasAVX512, NoDQI] in {
1975 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1976 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1977 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1978 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1980 let Predicates = [HasAVX512] in {
1981 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1982 (KMOVWmk addr:$dst, VK16:$src)>;
1983 def : Pat<(i1 (load addr:$src)),
1984 (COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
1985 (MOV8rm addr:$src), sub_8bit)),
1987 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
1988 (KMOVWkm addr:$src)>;
1990 let Predicates = [HasBWI] in {
1991 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1992 (KMOVDmk addr:$dst, VK32:$src)>;
1993 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
1994 (KMOVDkm addr:$src)>;
1996 let Predicates = [HasBWI] in {
1997 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1998 (KMOVQmk addr:$dst, VK64:$src)>;
1999 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
2000 (KMOVQkm addr:$src)>;
2003 let Predicates = [HasAVX512] in {
2004 def : Pat<(i1 (trunc (i64 GR64:$src))),
2005 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
2008 def : Pat<(i1 (trunc (i32 GR32:$src))),
2009 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
2011 def : Pat<(i1 (trunc (i8 GR8:$src))),
2013 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
2015 def : Pat<(i1 (trunc (i16 GR16:$src))),
2017 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
2020 def : Pat<(i32 (zext VK1:$src)),
2021 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
2022 def : Pat<(i32 (anyext VK1:$src)),
2023 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
2025 def : Pat<(i8 (zext VK1:$src)),
2028 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
2029 def : Pat<(i8 (anyext VK1:$src)),
2031 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
2033 def : Pat<(i64 (zext VK1:$src)),
2034 (AND64ri8 (SUBREG_TO_REG (i64 0),
2035 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
2036 def : Pat<(i16 (zext VK1:$src)),
2038 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
2040 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
2041 (COPY_TO_REGCLASS VK1:$src, VK16)>;
2042 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
2043 (COPY_TO_REGCLASS VK1:$src, VK8)>;
2045 let Predicates = [HasBWI] in {
2046 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
2047 (COPY_TO_REGCLASS VK1:$src, VK32)>;
2048 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
2049 (COPY_TO_REGCLASS VK1:$src, VK64)>;
2053 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2054 let Predicates = [HasAVX512, NoDQI] in {
2055 // GR from/to 8-bit mask without native support
2056 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2058 (KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
2059 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2061 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
2065 let Predicates = [HasAVX512] in {
2066 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
2067 (COPY_TO_REGCLASS VK16:$src, VK1)>;
2068 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
2069 (COPY_TO_REGCLASS VK8:$src, VK1)>;
2071 let Predicates = [HasBWI] in {
2072 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
2073 (COPY_TO_REGCLASS VK32:$src, VK1)>;
2074 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
2075 (COPY_TO_REGCLASS VK64:$src, VK1)>;
2078 // Mask unary operation
2080 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
2081 RegisterClass KRC, SDPatternOperator OpNode,
2083 let Predicates = [prd] in
2084 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2085 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2086 [(set KRC:$dst, (OpNode KRC:$src))]>;
2089 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
2090 SDPatternOperator OpNode> {
2091 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2093 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2094 HasAVX512>, VEX, PS;
2095 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2096 HasBWI>, VEX, PD, VEX_W;
2097 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2098 HasBWI>, VEX, PS, VEX_W;
2101 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
2103 multiclass avx512_mask_unop_int<string IntName, string InstName> {
2104 let Predicates = [HasAVX512] in
2105 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2107 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2108 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
2110 defm : avx512_mask_unop_int<"knot", "KNOT">;
2112 let Predicates = [HasDQI] in
2113 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
2114 let Predicates = [HasAVX512] in
2115 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
2116 let Predicates = [HasBWI] in
2117 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
2118 let Predicates = [HasBWI] in
2119 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
2121 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
2122 let Predicates = [HasAVX512, NoDQI] in {
2123 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
2124 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
2125 def : Pat<(not VK8:$src),
2127 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
2129 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
2130 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
2131 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
2132 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
2134 // Mask binary operation
2135 // - KAND, KANDN, KOR, KXNOR, KXOR
2136 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
2137 RegisterClass KRC, SDPatternOperator OpNode,
2138 Predicate prd, bit IsCommutable> {
2139 let Predicates = [prd], isCommutable = IsCommutable in
2140 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2141 !strconcat(OpcodeStr,
2142 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2143 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
2146 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
2147 SDPatternOperator OpNode, bit IsCommutable,
2148 Predicate prdW = HasAVX512> {
2149 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2150 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
2151 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2152 prdW, IsCommutable>, VEX_4V, VEX_L, PS;
2153 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2154 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
2155 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2156 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
2159 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
2160 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
2162 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
2163 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
2164 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
2165 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
2166 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
2167 defm KADD : avx512_mask_binop_all<0x4A, "kadd", add, 1, HasDQI>;
2169 multiclass avx512_mask_binop_int<string IntName, string InstName> {
2170 let Predicates = [HasAVX512] in
2171 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2172 (i16 GR16:$src1), (i16 GR16:$src2)),
2173 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2174 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2175 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2178 defm : avx512_mask_binop_int<"kand", "KAND">;
2179 defm : avx512_mask_binop_int<"kandn", "KANDN">;
2180 defm : avx512_mask_binop_int<"kor", "KOR">;
2181 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
2182 defm : avx512_mask_binop_int<"kxor", "KXOR">;
2184 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
2185 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
2186 // for the DQI set, this type is legal and KxxxB instruction is used
2187 let Predicates = [NoDQI] in
2188 def : Pat<(OpNode VK8:$src1, VK8:$src2),
2190 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2191 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2193 // All types smaller than 8 bits require conversion anyway
2194 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2195 (COPY_TO_REGCLASS (Inst
2196 (COPY_TO_REGCLASS VK1:$src1, VK16),
2197 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2198 def : Pat<(OpNode VK2:$src1, VK2:$src2),
2199 (COPY_TO_REGCLASS (Inst
2200 (COPY_TO_REGCLASS VK2:$src1, VK16),
2201 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2202 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2203 (COPY_TO_REGCLASS (Inst
2204 (COPY_TO_REGCLASS VK4:$src1, VK16),
2205 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2208 defm : avx512_binop_pat<and, KANDWrr>;
2209 defm : avx512_binop_pat<andn, KANDNWrr>;
2210 defm : avx512_binop_pat<or, KORWrr>;
2211 defm : avx512_binop_pat<xnor, KXNORWrr>;
2212 defm : avx512_binop_pat<xor, KXORWrr>;
2214 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2215 (KXNORWrr VK16:$src1, VK16:$src2)>;
2216 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2217 (KXNORBrr VK8:$src1, VK8:$src2)>, Requires<[HasDQI]>;
2218 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2219 (KXNORDrr VK32:$src1, VK32:$src2)>, Requires<[HasBWI]>;
2220 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2221 (KXNORQrr VK64:$src1, VK64:$src2)>, Requires<[HasBWI]>;
2223 let Predicates = [NoDQI] in
2224 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2225 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2226 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2228 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2229 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2230 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2232 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2233 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2234 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2236 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2237 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2238 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2241 multiclass avx512_mask_unpck<string Suffix,RegisterClass KRC, ValueType VT,
2242 RegisterClass KRCSrc, Predicate prd> {
2243 let Predicates = [prd] in {
2244 def rr : I<0x4b, MRMSrcReg, (outs KRC:$dst),
2245 (ins KRC:$src1, KRC:$src2),
2246 "kunpck"#Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2249 def : Pat<(VT (concat_vectors KRCSrc:$src1, KRCSrc:$src2)),
2250 (!cast<Instruction>(NAME##rr)
2251 (COPY_TO_REGCLASS KRCSrc:$src2, KRC),
2252 (COPY_TO_REGCLASS KRCSrc:$src1, KRC))>;
2256 defm KUNPCKBW : avx512_mask_unpck<"bw", VK16, v16i1, VK8, HasAVX512>, PD;
2257 defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, HasBWI>, PS;
2258 defm KUNPCKDQ : avx512_mask_unpck<"dq", VK64, v64i1, VK32, HasBWI>, PS, VEX_W;
2260 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
2261 let Predicates = [HasAVX512] in
2262 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
2263 (i16 GR16:$src1), (i16 GR16:$src2)),
2264 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
2265 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2266 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2268 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
2271 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2272 SDNode OpNode, Predicate prd> {
2273 let Predicates = [prd], Defs = [EFLAGS] in
2274 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2275 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2276 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2279 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2280 Predicate prdW = HasAVX512> {
2281 defm B : avx512_mask_testop<opc, OpcodeStr#"b", VK8, OpNode, HasDQI>,
2283 defm W : avx512_mask_testop<opc, OpcodeStr#"w", VK16, OpNode, prdW>,
2285 defm Q : avx512_mask_testop<opc, OpcodeStr#"q", VK64, OpNode, HasBWI>,
2287 defm D : avx512_mask_testop<opc, OpcodeStr#"d", VK32, OpNode, HasBWI>,
2291 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2292 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest, HasDQI>;
2295 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2297 let Predicates = [HasAVX512] in
2298 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2299 !strconcat(OpcodeStr,
2300 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2301 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2304 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2306 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2308 let Predicates = [HasDQI] in
2309 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2311 let Predicates = [HasBWI] in {
2312 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2314 let Predicates = [HasDQI] in
2315 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2320 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2321 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2323 // Mask setting all 0s or 1s
2324 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2325 let Predicates = [HasAVX512] in
2326 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2327 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2328 [(set KRC:$dst, (VT Val))]>;
2331 multiclass avx512_mask_setop_w<PatFrag Val> {
2332 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2333 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2334 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2335 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2338 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2339 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2341 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2342 let Predicates = [HasAVX512] in {
2343 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2344 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2345 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2346 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2347 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2348 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2349 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2351 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2352 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2354 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2355 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2357 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2358 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2360 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
2361 (v32i1 (COPY_TO_REGCLASS VK64:$src, VK32))>;
2363 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2364 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2366 let Predicates = [HasVLX] in {
2367 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2368 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2369 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2370 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2371 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2372 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2373 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2374 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2375 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2376 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2379 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2380 (v8i1 (COPY_TO_REGCLASS
2381 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2382 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2384 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2385 (v8i1 (COPY_TO_REGCLASS
2386 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2387 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2389 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2390 (v4i1 (COPY_TO_REGCLASS
2391 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2392 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2394 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2395 (v4i1 (COPY_TO_REGCLASS
2396 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2397 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2399 //===----------------------------------------------------------------------===//
2400 // AVX-512 - Aligned and unaligned load and store
2404 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2405 PatFrag ld_frag, PatFrag mload,
2406 bit IsReMaterializable = 1> {
2407 let hasSideEffects = 0 in {
2408 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2409 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2411 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2412 (ins _.KRCWM:$mask, _.RC:$src),
2413 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2414 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2417 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2418 SchedRW = [WriteLoad] in
2419 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2420 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2421 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2424 let Constraints = "$src0 = $dst" in {
2425 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2426 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2427 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2428 "${dst} {${mask}}, $src1}"),
2429 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2431 (_.VT _.RC:$src0))))], _.ExeDomain>,
2433 let mayLoad = 1, SchedRW = [WriteLoad] in
2434 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2435 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2436 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2437 "${dst} {${mask}}, $src1}"),
2438 [(set _.RC:$dst, (_.VT
2439 (vselect _.KRCWM:$mask,
2440 (_.VT (bitconvert (ld_frag addr:$src1))),
2441 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2443 let mayLoad = 1, SchedRW = [WriteLoad] in
2444 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2445 (ins _.KRCWM:$mask, _.MemOp:$src),
2446 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2447 "${dst} {${mask}} {z}, $src}",
2448 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2449 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2450 _.ExeDomain>, EVEX, EVEX_KZ;
2452 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2453 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2455 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2456 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2458 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2459 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2460 _.KRCWM:$mask, addr:$ptr)>;
2463 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2464 AVX512VLVectorVTInfo _,
2466 bit IsReMaterializable = 1> {
2467 let Predicates = [prd] in
2468 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2469 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2471 let Predicates = [prd, HasVLX] in {
2472 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2473 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2474 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2475 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2479 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2480 AVX512VLVectorVTInfo _,
2482 bit IsReMaterializable = 1> {
2483 let Predicates = [prd] in
2484 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2485 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2487 let Predicates = [prd, HasVLX] in {
2488 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2489 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2490 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2491 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2495 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2496 PatFrag st_frag, PatFrag mstore> {
2497 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2498 def rr_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2499 OpcodeStr # "\t{$src, $dst|$dst, $src}", [],
2501 let Constraints = "$src1 = $dst" in
2502 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2503 (ins _.RC:$src1, _.KRCWM:$mask, _.RC:$src2),
2505 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}",
2506 [], _.ExeDomain>, EVEX, EVEX_K;
2507 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2508 (ins _.KRCWM:$mask, _.RC:$src),
2510 "\t{$src, ${dst} {${mask}} {z}|" #
2511 "${dst} {${mask}} {z}, $src}",
2512 [], _.ExeDomain>, EVEX, EVEX_KZ;
2514 let mayStore = 1 in {
2515 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2516 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2517 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2518 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2519 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2520 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2521 [], _.ExeDomain>, EVEX, EVEX_K;
2524 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2525 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2526 _.KRCWM:$mask, _.RC:$src)>;
2530 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2531 AVX512VLVectorVTInfo _, Predicate prd> {
2532 let Predicates = [prd] in
2533 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2534 masked_store_unaligned>, EVEX_V512;
2536 let Predicates = [prd, HasVLX] in {
2537 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2538 masked_store_unaligned>, EVEX_V256;
2539 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2540 masked_store_unaligned>, EVEX_V128;
2544 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2545 AVX512VLVectorVTInfo _, Predicate prd> {
2546 let Predicates = [prd] in
2547 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2548 masked_store_aligned512>, EVEX_V512;
2550 let Predicates = [prd, HasVLX] in {
2551 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2552 masked_store_aligned256>, EVEX_V256;
2553 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2554 masked_store_aligned128>, EVEX_V128;
2558 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2560 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2561 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2563 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2565 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2566 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2568 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2569 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2570 PS, EVEX_CD8<32, CD8VF>;
2572 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2573 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2574 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2576 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2577 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2578 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2580 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2581 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2582 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2584 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2585 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2586 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2588 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2589 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2590 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2592 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2593 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2594 (VMOVAPDZrm addr:$ptr)>;
2596 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2597 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2598 (VMOVAPSZrm addr:$ptr)>;
2600 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2602 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2604 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2606 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2609 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2611 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2613 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2615 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2618 let Predicates = [HasAVX512, NoVLX] in {
2619 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2620 (VMOVUPSZmrk addr:$ptr,
2621 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2622 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2624 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2625 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2626 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2628 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2629 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2630 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2631 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2634 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2636 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2637 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2639 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2641 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2642 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2644 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2645 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2646 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2648 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2649 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2650 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2652 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2653 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2654 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2656 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2657 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2658 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2660 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2661 (v16i32 immAllZerosV), GR16:$mask)),
2662 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2664 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2665 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2666 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2668 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2670 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2672 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2674 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2677 let AddedComplexity = 20 in {
2678 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2679 (bc_v8i64 (v16i32 immAllZerosV)))),
2680 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2682 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2683 (v8i64 VR512:$src))),
2684 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2687 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2688 (v16i32 immAllZerosV))),
2689 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2691 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2692 (v16i32 VR512:$src))),
2693 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2696 let Predicates = [HasAVX512, NoVLX] in {
2697 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2698 (VMOVDQU32Zmrk addr:$ptr,
2699 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2700 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2702 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2703 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2704 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2707 // Move Int Doubleword to Packed Double Int
2709 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2710 "vmovd\t{$src, $dst|$dst, $src}",
2712 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2714 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2715 "vmovd\t{$src, $dst|$dst, $src}",
2717 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2718 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2719 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2720 "vmovq\t{$src, $dst|$dst, $src}",
2722 (v2i64 (scalar_to_vector GR64:$src)))],
2723 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2724 let isCodeGenOnly = 1 in {
2725 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2726 "vmovq\t{$src, $dst|$dst, $src}",
2727 [(set FR64:$dst, (bitconvert GR64:$src))],
2728 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2729 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2730 "vmovq\t{$src, $dst|$dst, $src}",
2731 [(set GR64:$dst, (bitconvert FR64:$src))],
2732 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2734 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2735 "vmovq\t{$src, $dst|$dst, $src}",
2736 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2737 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2738 EVEX_CD8<64, CD8VT1>;
2740 // Move Int Doubleword to Single Scalar
2742 let isCodeGenOnly = 1 in {
2743 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2744 "vmovd\t{$src, $dst|$dst, $src}",
2745 [(set FR32X:$dst, (bitconvert GR32:$src))],
2746 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2748 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2749 "vmovd\t{$src, $dst|$dst, $src}",
2750 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2751 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2754 // Move doubleword from xmm register to r/m32
2756 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2757 "vmovd\t{$src, $dst|$dst, $src}",
2758 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2759 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2761 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2762 (ins i32mem:$dst, VR128X:$src),
2763 "vmovd\t{$src, $dst|$dst, $src}",
2764 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2765 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2766 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2768 // Move quadword from xmm1 register to r/m64
2770 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2771 "vmovq\t{$src, $dst|$dst, $src}",
2772 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2774 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2775 Requires<[HasAVX512, In64BitMode]>;
2777 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2778 (ins i64mem:$dst, VR128X:$src),
2779 "vmovq\t{$src, $dst|$dst, $src}",
2780 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2781 addr:$dst)], IIC_SSE_MOVDQ>,
2782 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2783 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2785 // Move Scalar Single to Double Int
2787 let isCodeGenOnly = 1 in {
2788 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2790 "vmovd\t{$src, $dst|$dst, $src}",
2791 [(set GR32:$dst, (bitconvert FR32X:$src))],
2792 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2793 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2794 (ins i32mem:$dst, FR32X:$src),
2795 "vmovd\t{$src, $dst|$dst, $src}",
2796 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2797 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2800 // Move Quadword Int to Packed Quadword Int
2802 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2804 "vmovq\t{$src, $dst|$dst, $src}",
2806 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2807 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2809 //===----------------------------------------------------------------------===//
2810 // AVX-512 MOVSS, MOVSD
2811 //===----------------------------------------------------------------------===//
2813 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2814 SDNode OpNode, ValueType vt,
2815 X86MemOperand x86memop, PatFrag mem_pat> {
2816 let hasSideEffects = 0 in {
2817 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2818 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2819 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2820 (scalar_to_vector RC:$src2))))],
2821 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2822 let Constraints = "$src1 = $dst" in
2823 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2824 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2826 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2827 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2828 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2829 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2830 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2832 let mayStore = 1 in {
2833 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2834 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2835 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2837 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2838 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2839 [], IIC_SSE_MOV_S_MR>,
2840 EVEX, VEX_LIG, EVEX_K;
2842 } //hasSideEffects = 0
2845 let ExeDomain = SSEPackedSingle in
2846 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2847 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2849 let ExeDomain = SSEPackedDouble in
2850 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2851 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2853 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2854 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2855 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2857 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2858 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2859 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2861 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2862 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2863 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2865 // For the disassembler
2866 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2867 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2868 (ins VR128X:$src1, FR32X:$src2),
2869 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2871 XS, EVEX_4V, VEX_LIG;
2872 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2873 (ins VR128X:$src1, FR64X:$src2),
2874 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2876 XD, EVEX_4V, VEX_LIG, VEX_W;
2879 let Predicates = [HasAVX512] in {
2880 let AddedComplexity = 15 in {
2881 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2882 // MOVS{S,D} to the lower bits.
2883 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2884 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2885 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2886 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2887 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2888 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2889 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2890 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2892 // Move low f32 and clear high bits.
2893 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2894 (SUBREG_TO_REG (i32 0),
2895 (VMOVSSZrr (v4f32 (V_SET0)),
2896 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2897 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2898 (SUBREG_TO_REG (i32 0),
2899 (VMOVSSZrr (v4i32 (V_SET0)),
2900 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2903 let AddedComplexity = 20 in {
2904 // MOVSSrm zeros the high parts of the register; represent this
2905 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2906 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2907 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2908 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2909 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2910 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2911 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2913 // MOVSDrm zeros the high parts of the register; represent this
2914 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2915 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2916 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2917 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2918 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2919 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2920 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2921 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2922 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2923 def : Pat<(v2f64 (X86vzload addr:$src)),
2924 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2926 // Represent the same patterns above but in the form they appear for
2928 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2929 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2930 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2931 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2932 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2933 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2934 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2935 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2936 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2938 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2939 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2940 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2941 FR32X:$src)), sub_xmm)>;
2942 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2943 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2944 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2945 FR64X:$src)), sub_xmm)>;
2946 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2947 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2948 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2950 // Move low f64 and clear high bits.
2951 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2952 (SUBREG_TO_REG (i32 0),
2953 (VMOVSDZrr (v2f64 (V_SET0)),
2954 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2956 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2957 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2958 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2960 // Extract and store.
2961 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2963 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2964 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2966 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2968 // Shuffle with VMOVSS
2969 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2970 (VMOVSSZrr (v4i32 VR128X:$src1),
2971 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2972 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2973 (VMOVSSZrr (v4f32 VR128X:$src1),
2974 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2977 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2978 (SUBREG_TO_REG (i32 0),
2979 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2980 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2982 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2983 (SUBREG_TO_REG (i32 0),
2984 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2985 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2988 // Shuffle with VMOVSD
2989 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2990 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2991 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2992 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2993 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2994 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2995 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2996 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2999 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3000 (SUBREG_TO_REG (i32 0),
3001 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
3002 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
3004 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3005 (SUBREG_TO_REG (i32 0),
3006 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
3007 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
3010 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3011 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3012 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3013 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3014 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3015 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3016 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3017 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3020 let AddedComplexity = 15 in
3021 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
3023 "vmovq\t{$src, $dst|$dst, $src}",
3024 [(set VR128X:$dst, (v2i64 (X86vzmovl
3025 (v2i64 VR128X:$src))))],
3026 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
3028 let AddedComplexity = 20 in
3029 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
3031 "vmovq\t{$src, $dst|$dst, $src}",
3032 [(set VR128X:$dst, (v2i64 (X86vzmovl
3033 (loadv2i64 addr:$src))))],
3034 IIC_SSE_MOVDQ>, EVEX, VEX_W,
3035 EVEX_CD8<8, CD8VT8>;
3037 let Predicates = [HasAVX512] in {
3038 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3039 let AddedComplexity = 20 in {
3040 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
3041 (VMOVDI2PDIZrm addr:$src)>;
3042 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
3043 (VMOV64toPQIZrr GR64:$src)>;
3044 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
3045 (VMOVDI2PDIZrr GR32:$src)>;
3047 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3048 (VMOVDI2PDIZrm addr:$src)>;
3049 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3050 (VMOVDI2PDIZrm addr:$src)>;
3051 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3052 (VMOVZPQILo2PQIZrm addr:$src)>;
3053 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
3054 (VMOVZPQILo2PQIZrr VR128X:$src)>;
3055 def : Pat<(v2i64 (X86vzload addr:$src)),
3056 (VMOVZPQILo2PQIZrm addr:$src)>;
3059 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3060 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3061 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
3062 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
3063 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3064 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
3065 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
3068 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
3069 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3071 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
3072 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3074 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
3075 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3077 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
3078 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3080 //===----------------------------------------------------------------------===//
3081 // AVX-512 - Non-temporals
3082 //===----------------------------------------------------------------------===//
3083 let SchedRW = [WriteLoad] in {
3084 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
3085 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
3086 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
3087 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
3088 EVEX_CD8<64, CD8VF>;
3090 let Predicates = [HasAVX512, HasVLX] in {
3091 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
3093 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3094 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
3095 EVEX_CD8<64, CD8VF>;
3097 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
3099 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3100 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
3101 EVEX_CD8<64, CD8VF>;
3105 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3106 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
3107 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
3108 let SchedRW = [WriteStore], mayStore = 1,
3109 AddedComplexity = 400 in
3110 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
3111 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3112 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
3115 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3116 string elty, string elsz, string vsz512,
3117 string vsz256, string vsz128, Domain d,
3118 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
3119 let Predicates = [prd] in
3120 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
3121 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
3122 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
3125 let Predicates = [prd, HasVLX] in {
3126 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
3127 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
3128 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
3131 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
3132 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
3133 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
3138 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
3139 "i", "64", "8", "4", "2", SSEPackedInt,
3140 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
3142 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
3143 "f", "64", "8", "4", "2", SSEPackedDouble,
3144 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3146 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
3147 "f", "32", "16", "8", "4", SSEPackedSingle,
3148 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
3150 //===----------------------------------------------------------------------===//
3151 // AVX-512 - Integer arithmetic
3153 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3154 X86VectorVTInfo _, OpndItins itins,
3155 bit IsCommutable = 0> {
3156 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3157 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3158 "$src2, $src1", "$src1, $src2",
3159 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3160 itins.rr, IsCommutable>,
3161 AVX512BIBase, EVEX_4V;
3164 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3165 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3166 "$src2, $src1", "$src1, $src2",
3167 (_.VT (OpNode _.RC:$src1,
3168 (bitconvert (_.LdFrag addr:$src2)))),
3170 AVX512BIBase, EVEX_4V;
3173 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3174 X86VectorVTInfo _, OpndItins itins,
3175 bit IsCommutable = 0> :
3176 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
3178 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3179 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3180 "${src2}"##_.BroadcastStr##", $src1",
3181 "$src1, ${src2}"##_.BroadcastStr,
3182 (_.VT (OpNode _.RC:$src1,
3184 (_.ScalarLdFrag addr:$src2)))),
3186 AVX512BIBase, EVEX_4V, EVEX_B;
3189 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3190 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3191 Predicate prd, bit IsCommutable = 0> {
3192 let Predicates = [prd] in
3193 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3194 IsCommutable>, EVEX_V512;
3196 let Predicates = [prd, HasVLX] in {
3197 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3198 IsCommutable>, EVEX_V256;
3199 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3200 IsCommutable>, EVEX_V128;
3204 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3205 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3206 Predicate prd, bit IsCommutable = 0> {
3207 let Predicates = [prd] in
3208 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3209 IsCommutable>, EVEX_V512;
3211 let Predicates = [prd, HasVLX] in {
3212 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3213 IsCommutable>, EVEX_V256;
3214 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3215 IsCommutable>, EVEX_V128;
3219 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3220 OpndItins itins, Predicate prd,
3221 bit IsCommutable = 0> {
3222 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3223 itins, prd, IsCommutable>,
3224 VEX_W, EVEX_CD8<64, CD8VF>;
3227 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3228 OpndItins itins, Predicate prd,
3229 bit IsCommutable = 0> {
3230 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3231 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3234 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3235 OpndItins itins, Predicate prd,
3236 bit IsCommutable = 0> {
3237 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3238 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3241 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3242 OpndItins itins, Predicate prd,
3243 bit IsCommutable = 0> {
3244 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3245 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3248 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3249 SDNode OpNode, OpndItins itins, Predicate prd,
3250 bit IsCommutable = 0> {
3251 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr#"q", OpNode, itins, prd,
3254 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr#"d", OpNode, itins, prd,
3258 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3259 SDNode OpNode, OpndItins itins, Predicate prd,
3260 bit IsCommutable = 0> {
3261 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr#"w", OpNode, itins, prd,
3264 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr#"b", OpNode, itins, prd,
3268 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3269 bits<8> opc_d, bits<8> opc_q,
3270 string OpcodeStr, SDNode OpNode,
3271 OpndItins itins, bit IsCommutable = 0> {
3272 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3273 itins, HasAVX512, IsCommutable>,
3274 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3275 itins, HasBWI, IsCommutable>;
3278 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3279 SDNode OpNode,X86VectorVTInfo _Src,
3280 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3281 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3282 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3283 "$src2, $src1","$src1, $src2",
3285 (_Src.VT _Src.RC:$src1),
3286 (_Src.VT _Src.RC:$src2))),
3287 itins.rr, IsCommutable>,
3288 AVX512BIBase, EVEX_4V;
3289 let mayLoad = 1 in {
3290 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3291 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3292 "$src2, $src1", "$src1, $src2",
3293 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3294 (bitconvert (_Src.LdFrag addr:$src2)))),
3296 AVX512BIBase, EVEX_4V;
3298 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3299 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3301 "${src2}"##_Dst.BroadcastStr##", $src1",
3302 "$src1, ${src2}"##_Dst.BroadcastStr,
3303 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3304 (_Dst.VT (X86VBroadcast
3305 (_Dst.ScalarLdFrag addr:$src2)))))),
3307 AVX512BIBase, EVEX_4V, EVEX_B;
3311 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3312 SSE_INTALU_ITINS_P, 1>;
3313 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3314 SSE_INTALU_ITINS_P, 0>;
3315 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3316 SSE_INTALU_ITINS_P, HasBWI, 1>;
3317 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3318 SSE_INTALU_ITINS_P, HasBWI, 0>;
3319 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3320 SSE_INTALU_ITINS_P, HasBWI, 1>;
3321 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3322 SSE_INTALU_ITINS_P, HasBWI, 0>;
3323 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmulld", mul,
3324 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3325 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmullw", mul,
3326 SSE_INTALU_ITINS_P, HasBWI, 1>;
3327 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmullq", mul,
3328 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3329 defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SSE_INTALU_ITINS_P,
3331 defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SSE_INTMUL_ITINS_P,
3333 defm VPMULHRSW : avx512_binop_rm_vl_w<0x0B, "vpmulhrsw", X86mulhrs, SSE_INTMUL_ITINS_P,
3335 defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg,
3336 SSE_INTALU_ITINS_P, HasBWI, 1>;
3338 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3339 SDNode OpNode, bit IsCommutable = 0> {
3341 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3342 v16i32_info, v8i64_info, IsCommutable>,
3343 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3344 let Predicates = [HasVLX] in {
3345 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3346 v8i32x_info, v4i64x_info, IsCommutable>,
3347 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3348 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3349 v4i32x_info, v2i64x_info, IsCommutable>,
3350 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3354 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3356 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3359 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3360 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3361 let mayLoad = 1 in {
3362 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3363 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3365 "${src2}"##_Src.BroadcastStr##", $src1",
3366 "$src1, ${src2}"##_Src.BroadcastStr,
3367 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3368 (_Src.VT (X86VBroadcast
3369 (_Src.ScalarLdFrag addr:$src2))))))>,
3370 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3374 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3375 SDNode OpNode,X86VectorVTInfo _Src,
3376 X86VectorVTInfo _Dst> {
3377 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3378 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3379 "$src2, $src1","$src1, $src2",
3381 (_Src.VT _Src.RC:$src1),
3382 (_Src.VT _Src.RC:$src2)))>,
3383 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3384 let mayLoad = 1 in {
3385 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3386 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3387 "$src2, $src1", "$src1, $src2",
3388 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3389 (bitconvert (_Src.LdFrag addr:$src2))))>,
3390 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3394 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3396 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3398 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3399 v32i16_info>, EVEX_V512;
3400 let Predicates = [HasVLX] in {
3401 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3403 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3404 v16i16x_info>, EVEX_V256;
3405 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3407 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3408 v8i16x_info>, EVEX_V128;
3411 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3413 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3414 v64i8_info>, EVEX_V512;
3415 let Predicates = [HasVLX] in {
3416 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3417 v32i8x_info>, EVEX_V256;
3418 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3419 v16i8x_info>, EVEX_V128;
3423 multiclass avx512_vpmadd<bits<8> opc, string OpcodeStr,
3424 SDNode OpNode, AVX512VLVectorVTInfo _Src,
3425 AVX512VLVectorVTInfo _Dst> {
3426 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info512,
3427 _Dst.info512>, EVEX_V512;
3428 let Predicates = [HasVLX] in {
3429 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info256,
3430 _Dst.info256>, EVEX_V256;
3431 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info128,
3432 _Dst.info128>, EVEX_V128;
3436 let Predicates = [HasBWI] in {
3437 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3438 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3439 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3440 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3442 defm VPMADDUBSW : avx512_vpmadd<0x04, "vpmaddubsw", X86vpmaddubsw,
3443 avx512vl_i8_info, avx512vl_i16_info>, AVX512BIBase, T8PD;
3444 defm VPMADDWD : avx512_vpmadd<0xF5, "vpmaddwd", X86vpmaddwd,
3445 avx512vl_i16_info, avx512vl_i32_info>, AVX512BIBase;
3448 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxsb", smax,
3449 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3450 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxsw", smax,
3451 SSE_INTALU_ITINS_P, HasBWI, 1>;
3452 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", smax,
3453 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3455 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxub", umax,
3456 SSE_INTALU_ITINS_P, HasBWI, 1>;
3457 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxuw", umax,
3458 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3459 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", umax,
3460 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3462 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpminsb", smin,
3463 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3464 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpminsw", smin,
3465 SSE_INTALU_ITINS_P, HasBWI, 1>;
3466 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", smin,
3467 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3469 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminub", umin,
3470 SSE_INTALU_ITINS_P, HasBWI, 1>;
3471 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin,
3472 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3473 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", umin,
3474 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3475 //===----------------------------------------------------------------------===//
3476 // AVX-512 Logical Instructions
3477 //===----------------------------------------------------------------------===//
3479 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3480 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3481 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3482 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3483 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3484 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3485 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3486 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3488 //===----------------------------------------------------------------------===//
3489 // AVX-512 FP arithmetic
3490 //===----------------------------------------------------------------------===//
3491 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3492 SDNode OpNode, SDNode VecNode, OpndItins itins,
3495 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3496 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3497 "$src2, $src1", "$src1, $src2",
3498 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3499 (i32 FROUND_CURRENT)),
3500 itins.rr, IsCommutable>;
3502 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3503 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3504 "$src2, $src1", "$src1, $src2",
3505 (VecNode (_.VT _.RC:$src1),
3506 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3507 (i32 FROUND_CURRENT)),
3508 itins.rm, IsCommutable>;
3509 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3510 Predicates = [HasAVX512] in {
3511 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3512 (ins _.FRC:$src1, _.FRC:$src2),
3513 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3514 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3516 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3517 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3518 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3519 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3520 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3524 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3525 SDNode VecNode, OpndItins itins, bit IsCommutable = 0> {
3527 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3528 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3529 "$rc, $src2, $src1", "$src1, $src2, $rc",
3530 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3531 (i32 imm:$rc)), itins.rr, IsCommutable>,
3534 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3535 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3537 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3538 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3539 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3540 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3541 (i32 FROUND_NO_EXC))>, EVEX_B;
3544 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3546 SizeItins itins, bit IsCommutable> {
3547 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3548 itins.s, IsCommutable>,
3549 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3550 itins.s, IsCommutable>,
3551 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3552 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3553 itins.d, IsCommutable>,
3554 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3555 itins.d, IsCommutable>,
3556 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3559 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3561 SizeItins itins, bit IsCommutable> {
3562 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3563 itins.s, IsCommutable>,
3564 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3565 itins.s, IsCommutable>,
3566 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3567 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3568 itins.d, IsCommutable>,
3569 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3570 itins.d, IsCommutable>,
3571 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3573 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3574 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3575 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3576 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3577 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3578 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3580 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3581 X86VectorVTInfo _, bit IsCommutable> {
3582 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3583 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3584 "$src2, $src1", "$src1, $src2",
3585 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3586 let mayLoad = 1 in {
3587 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3588 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3589 "$src2, $src1", "$src1, $src2",
3590 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3591 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3592 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3593 "${src2}"##_.BroadcastStr##", $src1",
3594 "$src1, ${src2}"##_.BroadcastStr,
3595 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3596 (_.ScalarLdFrag addr:$src2))))>,
3601 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3602 X86VectorVTInfo _> {
3603 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3604 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3605 "$rc, $src2, $src1", "$src1, $src2, $rc",
3606 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3607 EVEX_4V, EVEX_B, EVEX_RC;
3611 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3612 X86VectorVTInfo _> {
3613 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3614 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3615 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3616 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3620 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3621 bit IsCommutable = 0> {
3622 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3623 IsCommutable>, EVEX_V512, PS,
3624 EVEX_CD8<32, CD8VF>;
3625 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3626 IsCommutable>, EVEX_V512, PD, VEX_W,
3627 EVEX_CD8<64, CD8VF>;
3629 // Define only if AVX512VL feature is present.
3630 let Predicates = [HasVLX] in {
3631 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3632 IsCommutable>, EVEX_V128, PS,
3633 EVEX_CD8<32, CD8VF>;
3634 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3635 IsCommutable>, EVEX_V256, PS,
3636 EVEX_CD8<32, CD8VF>;
3637 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3638 IsCommutable>, EVEX_V128, PD, VEX_W,
3639 EVEX_CD8<64, CD8VF>;
3640 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3641 IsCommutable>, EVEX_V256, PD, VEX_W,
3642 EVEX_CD8<64, CD8VF>;
3646 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3647 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3648 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3649 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3650 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3653 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3654 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3655 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3656 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3657 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3660 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3661 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3662 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3663 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3664 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3665 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3666 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3667 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3668 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3669 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3670 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3671 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3672 let Predicates = [HasDQI] in {
3673 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3674 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3675 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3676 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3679 multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3680 X86VectorVTInfo _> {
3681 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3682 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3683 "$src2, $src1", "$src1, $src2",
3684 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>, EVEX_4V;
3685 let mayLoad = 1 in {
3686 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3687 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3688 "$src2, $src1", "$src1, $src2",
3689 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>, EVEX_4V;
3690 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3691 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3692 "${src2}"##_.BroadcastStr##", $src1",
3693 "$src1, ${src2}"##_.BroadcastStr,
3694 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3695 (_.ScalarLdFrag addr:$src2))), (i32 FROUND_CURRENT))>,
3700 multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
3701 X86VectorVTInfo _> {
3702 defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3703 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3704 "$src2, $src1", "$src1, $src2",
3705 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>;
3706 let mayLoad = 1 in {
3707 defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3708 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3709 "$src2, $src1", "$src1, $src2",
3710 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>;
3714 multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode> {
3715 defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v16f32_info>,
3716 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
3717 EVEX_V512, EVEX_CD8<32, CD8VF>;
3718 defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f64_info>,
3719 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v8f64_info>,
3720 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3721 defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f32x_info>,
3722 avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNode, SSE_ALU_ITINS_S.s>,
3723 EVEX_4V,EVEX_CD8<32, CD8VT1>;
3724 defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f64x_info>,
3725 avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNode, SSE_ALU_ITINS_S.d>,
3726 EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
3728 // Define only if AVX512VL feature is present.
3729 let Predicates = [HasVLX] in {
3730 defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f32x_info>,
3731 EVEX_V128, EVEX_CD8<32, CD8VF>;
3732 defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f32x_info>,
3733 EVEX_V256, EVEX_CD8<32, CD8VF>;
3734 defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v2f64x_info>,
3735 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
3736 defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f64x_info>,
3737 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
3740 defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef>, T8PD;
3742 //===----------------------------------------------------------------------===//
3743 // AVX-512 VPTESTM instructions
3744 //===----------------------------------------------------------------------===//
3746 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3747 X86VectorVTInfo _> {
3748 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3749 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3750 "$src2, $src1", "$src1, $src2",
3751 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3754 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3755 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3756 "$src2, $src1", "$src1, $src2",
3757 (OpNode (_.VT _.RC:$src1),
3758 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3760 EVEX_CD8<_.EltSize, CD8VF>;
3763 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3764 X86VectorVTInfo _> {
3766 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3767 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3768 "${src2}"##_.BroadcastStr##", $src1",
3769 "$src1, ${src2}"##_.BroadcastStr,
3770 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3771 (_.ScalarLdFrag addr:$src2))))>,
3772 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3774 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3775 AVX512VLVectorVTInfo _> {
3776 let Predicates = [HasAVX512] in
3777 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3778 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3780 let Predicates = [HasAVX512, HasVLX] in {
3781 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3782 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3783 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3784 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3788 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3789 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3791 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3792 avx512vl_i64_info>, VEX_W;
3795 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3797 let Predicates = [HasBWI] in {
3798 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3800 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3803 let Predicates = [HasVLX, HasBWI] in {
3805 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3807 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3809 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3811 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3816 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3818 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3819 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3821 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3822 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3824 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3825 (v16i32 VR512:$src2), (i16 -1))),
3826 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3828 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3829 (v8i64 VR512:$src2), (i8 -1))),
3830 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3832 //===----------------------------------------------------------------------===//
3833 // AVX-512 Shift instructions
3834 //===----------------------------------------------------------------------===//
3835 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3836 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3837 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3838 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3839 "$src2, $src1", "$src1, $src2",
3840 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3841 SSE_INTSHIFT_ITINS_P.rr>;
3843 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3844 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3845 "$src2, $src1", "$src1, $src2",
3846 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3848 SSE_INTSHIFT_ITINS_P.rm>;
3851 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3852 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3854 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3855 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3856 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3857 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3858 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
3861 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3862 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3863 // src2 is always 128-bit
3864 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3865 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3866 "$src2, $src1", "$src1, $src2",
3867 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3868 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3869 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3870 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3871 "$src2, $src1", "$src1, $src2",
3872 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3873 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
3877 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3878 ValueType SrcVT, PatFrag bc_frag,
3879 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
3880 let Predicates = [prd] in
3881 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3882 VTInfo.info512>, EVEX_V512,
3883 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
3884 let Predicates = [prd, HasVLX] in {
3885 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3886 VTInfo.info256>, EVEX_V256,
3887 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
3888 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3889 VTInfo.info128>, EVEX_V128,
3890 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
3894 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
3895 string OpcodeStr, SDNode OpNode> {
3896 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3897 avx512vl_i32_info, HasAVX512>;
3898 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3899 avx512vl_i64_info, HasAVX512>, VEX_W;
3900 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
3901 avx512vl_i16_info, HasBWI>;
3904 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3905 string OpcodeStr, SDNode OpNode,
3906 AVX512VLVectorVTInfo VTInfo> {
3907 let Predicates = [HasAVX512] in
3908 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3910 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3911 VTInfo.info512>, EVEX_V512;
3912 let Predicates = [HasAVX512, HasVLX] in {
3913 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3915 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3916 VTInfo.info256>, EVEX_V256;
3917 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3919 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3920 VTInfo.info128>, EVEX_V128;
3924 multiclass avx512_shift_rmi_w<bits<8> opcw,
3925 Format ImmFormR, Format ImmFormM,
3926 string OpcodeStr, SDNode OpNode> {
3927 let Predicates = [HasBWI] in
3928 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3929 v32i16_info>, EVEX_V512;
3930 let Predicates = [HasVLX, HasBWI] in {
3931 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3932 v16i16x_info>, EVEX_V256;
3933 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3934 v8i16x_info>, EVEX_V128;
3938 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
3939 Format ImmFormR, Format ImmFormM,
3940 string OpcodeStr, SDNode OpNode> {
3941 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
3942 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
3943 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
3944 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
3947 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
3948 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
3950 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
3951 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
3953 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
3954 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
3956 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>, AVX512BIi8Base, EVEX_4V;
3957 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
3959 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
3960 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
3961 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
3963 //===-------------------------------------------------------------------===//
3964 // Variable Bit Shifts
3965 //===-------------------------------------------------------------------===//
3966 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3967 X86VectorVTInfo _> {
3968 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3969 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3970 "$src2, $src1", "$src1, $src2",
3971 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3972 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3974 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3975 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3976 "$src2, $src1", "$src1, $src2",
3977 (_.VT (OpNode _.RC:$src1,
3978 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
3979 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
3980 EVEX_CD8<_.EltSize, CD8VF>;
3983 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3984 X86VectorVTInfo _> {
3986 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3987 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3988 "${src2}"##_.BroadcastStr##", $src1",
3989 "$src1, ${src2}"##_.BroadcastStr,
3990 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3991 (_.ScalarLdFrag addr:$src2))))),
3992 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
3993 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3995 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3996 AVX512VLVectorVTInfo _> {
3997 let Predicates = [HasAVX512] in
3998 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
3999 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4001 let Predicates = [HasAVX512, HasVLX] in {
4002 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4003 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4004 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
4005 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
4009 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
4011 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
4013 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
4014 avx512vl_i64_info>, VEX_W;
4017 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
4019 let Predicates = [HasBWI] in
4020 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
4022 let Predicates = [HasVLX, HasBWI] in {
4024 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
4026 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
4031 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
4032 avx512_var_shift_w<0x12, "vpsllvw", shl>;
4033 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
4034 avx512_var_shift_w<0x11, "vpsravw", sra>;
4035 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
4036 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
4037 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
4038 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
4040 //===-------------------------------------------------------------------===//
4041 // 1-src variable permutation VPERMW/D/Q
4042 //===-------------------------------------------------------------------===//
4043 multiclass avx512_vperm_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4044 AVX512VLVectorVTInfo _> {
4045 let Predicates = [HasAVX512] in
4046 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4047 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4049 let Predicates = [HasAVX512, HasVLX] in
4050 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4051 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4054 multiclass avx512_vpermi_dq_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4055 string OpcodeStr, SDNode OpNode,
4056 AVX512VLVectorVTInfo VTInfo> {
4057 let Predicates = [HasAVX512] in
4058 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4060 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4061 VTInfo.info512>, EVEX_V512;
4062 let Predicates = [HasAVX512, HasVLX] in
4063 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4065 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4066 VTInfo.info256>, EVEX_V256;
4070 defm VPERM : avx512_var_shift_w<0x8D, "vpermw", X86VPermv>;
4072 defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv,
4074 defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv,
4075 avx512vl_i64_info>, VEX_W;
4076 defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv,
4078 defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv,
4079 avx512vl_f64_info>, VEX_W;
4081 defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq",
4082 X86VPermi, avx512vl_i64_info>,
4083 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4084 defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
4085 X86VPermi, avx512vl_f64_info>,
4086 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4087 //===----------------------------------------------------------------------===//
4088 // AVX-512 - VPERMIL
4089 //===----------------------------------------------------------------------===//
4091 multiclass avx512_permil_vec<bits<8> OpcVar, string OpcodeStr, SDNode OpNode,
4092 X86VectorVTInfo _, X86VectorVTInfo Ctrl> {
4093 defm rr: AVX512_maskable<OpcVar, MRMSrcReg, _, (outs _.RC:$dst),
4094 (ins _.RC:$src1, Ctrl.RC:$src2), OpcodeStr,
4095 "$src2, $src1", "$src1, $src2",
4096 (_.VT (OpNode _.RC:$src1,
4097 (Ctrl.VT Ctrl.RC:$src2)))>,
4099 let mayLoad = 1 in {
4100 defm rm: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4101 (ins _.RC:$src1, Ctrl.MemOp:$src2), OpcodeStr,
4102 "$src2, $src1", "$src1, $src2",
4105 (Ctrl.VT (bitconvert(Ctrl.LdFrag addr:$src2)))))>,
4106 T8PD, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4107 defm rmb: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4108 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4109 "${src2}"##_.BroadcastStr##", $src1",
4110 "$src1, ${src2}"##_.BroadcastStr,
4113 (Ctrl.VT (X86VBroadcast
4114 (Ctrl.ScalarLdFrag addr:$src2)))))>,
4115 T8PD, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
4119 multiclass avx512_permil_vec_common<string OpcodeStr, bits<8> OpcVar,
4120 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4121 let Predicates = [HasAVX512] in {
4122 defm Z : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info512,
4123 Ctrl.info512>, EVEX_V512;
4125 let Predicates = [HasAVX512, HasVLX] in {
4126 defm Z128 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info128,
4127 Ctrl.info128>, EVEX_V128;
4128 defm Z256 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info256,
4129 Ctrl.info256>, EVEX_V256;
4133 multiclass avx512_permil<string OpcodeStr, bits<8> OpcImm, bits<8> OpcVar,
4134 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4136 defm NAME: avx512_permil_vec_common<OpcodeStr, OpcVar, _, Ctrl>;
4137 defm NAME: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem, OpcodeStr,
4139 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4141 let isCodeGenOnly = 1 in {
4142 // lowering implementation with the alternative types
4143 defm NAME#_I: avx512_permil_vec_common<OpcodeStr, OpcVar, Ctrl, Ctrl>;
4144 defm NAME#_I: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem,
4145 OpcodeStr, X86VPermilpi, Ctrl>,
4146 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4150 defm VPERMILPS : avx512_permil<"vpermilps", 0x04, 0x0C, avx512vl_f32_info,
4152 defm VPERMILPD : avx512_permil<"vpermilpd", 0x05, 0x0D, avx512vl_f64_info,
4153 avx512vl_i64_info>, VEX_W;
4154 //===----------------------------------------------------------------------===//
4155 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
4156 //===----------------------------------------------------------------------===//
4158 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
4159 X86PShufd, avx512vl_i32_info>,
4160 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
4161 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
4162 X86PShufhw>, EVEX, AVX512XSIi8Base;
4163 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
4164 X86PShuflw>, EVEX, AVX512XDIi8Base;
4166 multiclass avx512_pshufb_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4167 let Predicates = [HasBWI] in
4168 defm Z: avx512_var_shift<opc, OpcodeStr, OpNode, v64i8_info>, EVEX_V512;
4170 let Predicates = [HasVLX, HasBWI] in {
4171 defm Z256: avx512_var_shift<opc, OpcodeStr, OpNode, v32i8x_info>, EVEX_V256;
4172 defm Z128: avx512_var_shift<opc, OpcodeStr, OpNode, v16i8x_info>, EVEX_V128;
4176 defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb>;
4178 //===----------------------------------------------------------------------===//
4179 // AVX-512 - MOVDDUP
4180 //===----------------------------------------------------------------------===//
4182 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
4183 X86MemOperand x86memop, PatFrag memop_frag> {
4184 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4185 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4186 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
4187 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4188 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4190 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
4193 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
4194 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4195 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
4196 (VMOVDDUPZrm addr:$src)>;
4198 //===---------------------------------------------------------------------===//
4199 // Replicate Single FP - MOVSHDUP and MOVSLDUP
4200 //===---------------------------------------------------------------------===//
4201 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4202 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4203 X86MemOperand x86memop> {
4204 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4205 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4206 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
4208 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4209 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4210 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
4213 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4214 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
4215 EVEX_CD8<32, CD8VF>;
4216 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4217 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
4218 EVEX_CD8<32, CD8VF>;
4220 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
4221 def : Pat<(v16i32 (X86Movshdup (loadv16i32 addr:$src))),
4222 (VMOVSHDUPZrm addr:$src)>;
4223 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
4224 def : Pat<(v16i32 (X86Movsldup (loadv16i32 addr:$src))),
4225 (VMOVSLDUPZrm addr:$src)>;
4227 //===----------------------------------------------------------------------===//
4228 // Move Low to High and High to Low packed FP Instructions
4229 //===----------------------------------------------------------------------===//
4230 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
4231 (ins VR128X:$src1, VR128X:$src2),
4232 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4233 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
4234 IIC_SSE_MOV_LH>, EVEX_4V;
4235 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
4236 (ins VR128X:$src1, VR128X:$src2),
4237 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4238 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
4239 IIC_SSE_MOV_LH>, EVEX_4V;
4241 let Predicates = [HasAVX512] in {
4243 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4244 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
4245 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4246 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
4249 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
4250 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
4253 //===----------------------------------------------------------------------===//
4254 // FMA - Fused Multiply Operations
4257 let Constraints = "$src1 = $dst" in {
4258 multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4259 X86VectorVTInfo _> {
4260 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4261 (ins _.RC:$src2, _.RC:$src3),
4262 OpcodeStr, "$src3, $src2", "$src2, $src3",
4263 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4266 let mayLoad = 1 in {
4267 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4268 (ins _.RC:$src2, _.MemOp:$src3),
4269 OpcodeStr, "$src3, $src2", "$src2, $src3",
4270 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
4273 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4274 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4275 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
4276 !strconcat("$src2, ${src3}", _.BroadcastStr ),
4278 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
4279 AVX512FMA3Base, EVEX_B;
4283 multiclass avx512_fma3_213_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4284 X86VectorVTInfo _> {
4285 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4286 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4287 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4288 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4289 AVX512FMA3Base, EVEX_B, EVEX_RC;
4291 } // Constraints = "$src1 = $dst"
4293 multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4294 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4295 let Predicates = [HasAVX512] in {
4296 defm Z : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info512>,
4297 avx512_fma3_213_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4298 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4300 let Predicates = [HasVLX, HasAVX512] in {
4301 defm Z256 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info256>,
4302 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4303 defm Z128 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info128>,
4304 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4308 multiclass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4309 SDNode OpNodeRnd > {
4310 defm PS : avx512_fma3p_213_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4312 defm PD : avx512_fma3p_213_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4313 avx512vl_f64_info>, VEX_W;
4316 defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86Fmadd, X86FmaddRnd>;
4317 defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86Fmsub, X86FmsubRnd>;
4318 defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub, X86FmaddsubRnd>;
4319 defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd, X86FmsubaddRnd>;
4320 defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86Fnmadd, X86FnmaddRnd>;
4321 defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86Fnmsub, X86FnmsubRnd>;
4324 let Constraints = "$src1 = $dst" in {
4325 multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4326 X86VectorVTInfo _> {
4327 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4328 (ins _.RC:$src2, _.RC:$src3),
4329 OpcodeStr, "$src3, $src2", "$src2, $src3",
4330 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1))>,
4333 let mayLoad = 1 in {
4334 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4335 (ins _.RC:$src2, _.MemOp:$src3),
4336 OpcodeStr, "$src3, $src2", "$src2, $src3",
4337 (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1))>,
4340 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4341 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4342 OpcodeStr, "${src3}"##_.BroadcastStr##", $src2",
4343 "$src2, ${src3}"##_.BroadcastStr,
4344 (_.VT (OpNode _.RC:$src2,
4345 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
4346 _.RC:$src1))>, AVX512FMA3Base, EVEX_B;
4350 multiclass avx512_fma3_231_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4351 X86VectorVTInfo _> {
4352 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4353 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4354 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4355 (_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc)))>,
4356 AVX512FMA3Base, EVEX_B, EVEX_RC;
4358 } // Constraints = "$src1 = $dst"
4360 multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4361 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4362 let Predicates = [HasAVX512] in {
4363 defm Z : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info512>,
4364 avx512_fma3_231_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4365 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4367 let Predicates = [HasVLX, HasAVX512] in {
4368 defm Z256 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info256>,
4369 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4370 defm Z128 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info128>,
4371 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4375 multiclass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4376 SDNode OpNodeRnd > {
4377 defm PS : avx512_fma3p_231_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4379 defm PD : avx512_fma3p_231_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4380 avx512vl_f64_info>, VEX_W;
4383 defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86Fmadd, X86FmaddRnd>;
4384 defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86Fmsub, X86FmsubRnd>;
4385 defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub, X86FmaddsubRnd>;
4386 defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd, X86FmsubaddRnd>;
4387 defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86Fnmadd, X86FnmaddRnd>;
4388 defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86Fnmsub, X86FnmsubRnd>;
4390 let Constraints = "$src1 = $dst" in {
4391 multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4392 X86VectorVTInfo _> {
4393 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4394 (ins _.RC:$src3, _.RC:$src2),
4395 OpcodeStr, "$src2, $src3", "$src3, $src2",
4396 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4399 let mayLoad = 1 in {
4400 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4401 (ins _.RC:$src3, _.MemOp:$src2),
4402 OpcodeStr, "$src2, $src3", "$src3, $src2",
4403 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2), _.RC:$src3))>,
4406 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4407 (ins _.RC:$src3, _.ScalarMemOp:$src2),
4408 OpcodeStr, "${src2}"##_.BroadcastStr##", $src3",
4409 "$src3, ${src2}"##_.BroadcastStr,
4410 (_.VT (OpNode _.RC:$src1,
4411 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
4412 _.RC:$src3))>, AVX512FMA3Base, EVEX_B;
4416 multiclass avx512_fma3_132_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4417 X86VectorVTInfo _> {
4418 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4419 (ins _.RC:$src3, _.RC:$src2, AVX512RC:$rc),
4420 OpcodeStr, "$rc, $src2, $src3", "$src3, $src2, $rc",
4421 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4422 AVX512FMA3Base, EVEX_B, EVEX_RC;
4424 } // Constraints = "$src1 = $dst"
4426 multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4427 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4428 let Predicates = [HasAVX512] in {
4429 defm Z : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info512>,
4430 avx512_fma3_132_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4431 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4433 let Predicates = [HasVLX, HasAVX512] in {
4434 defm Z256 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info256>,
4435 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4436 defm Z128 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info128>,
4437 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4441 multiclass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4442 SDNode OpNodeRnd > {
4443 defm PS : avx512_fma3p_132_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4445 defm PD : avx512_fma3p_132_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4446 avx512vl_f64_info>, VEX_W;
4449 defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86Fmadd, X86FmaddRnd>;
4450 defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86Fmsub, X86FmsubRnd>;
4451 defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub, X86FmaddsubRnd>;
4452 defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd, X86FmsubaddRnd>;
4453 defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86Fnmadd, X86FnmaddRnd>;
4454 defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubRnd>;
4457 let Constraints = "$src1 = $dst" in {
4458 multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4459 dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
4460 dag RHS_r, dag RHS_m > {
4461 defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4462 (ins _.RC:$src2, _.RC:$src3), OpcodeStr,
4463 "$src3, $src2", "$src2, $src3", RHS_VEC_r>, AVX512FMA3Base;
4466 defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4467 (ins _.RC:$src2, _.MemOp:$src3), OpcodeStr,
4468 "$src3, $src2", "$src2, $src3", RHS_VEC_m>, AVX512FMA3Base;
4470 defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4471 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4472 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb>,
4473 AVX512FMA3Base, EVEX_B, EVEX_RC;
4475 let isCodeGenOnly = 1 in {
4476 def r : AVX512FMA3<opc, MRMSrcReg, (outs _.FRC:$dst),
4477 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
4478 !strconcat(OpcodeStr,
4479 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4482 def m : AVX512FMA3<opc, MRMSrcMem, (outs _.FRC:$dst),
4483 (ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
4484 !strconcat(OpcodeStr,
4485 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4487 }// isCodeGenOnly = 1
4489 }// Constraints = "$src1 = $dst"
4491 multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4492 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd, X86VectorVTInfo _ ,
4495 defm NAME#213#SUFF: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix , _ ,
4496 (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)),
4497 (_.VT (OpNode _.RC:$src2, _.RC:$src1,
4498 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))))),
4499 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src1, _.RC:$src3,
4501 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4503 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4504 (_.ScalarLdFrag addr:$src3))))>;
4506 defm NAME#231#SUFF: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix , _ ,
4507 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)),
4508 (_.VT (OpNode _.RC:$src2,
4509 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4511 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src3, _.RC:$src1,
4513 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
4515 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
4516 (_.ScalarLdFrag addr:$src3), _.FRC:$src1)))>;
4518 defm NAME#132#SUFF: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix , _ ,
4519 (_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)),
4520 (_.VT (OpNode _.RC:$src1,
4521 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4523 (_.VT ( OpNodeRnd _.RC:$src1, _.RC:$src3, _.RC:$src2,
4525 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
4527 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1,
4528 (_.ScalarLdFrag addr:$src3), _.FRC:$src2)))>;
4531 multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4532 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd>{
4533 let Predicates = [HasAVX512] in {
4534 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4535 OpNodeRnd, f32x_info, "SS">,
4536 EVEX_CD8<32, CD8VT1>, VEX_LIG;
4537 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4538 OpNodeRnd, f64x_info, "SD">,
4539 EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
4543 defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>;
4544 defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>;
4545 defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4546 defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4548 //===----------------------------------------------------------------------===//
4549 // AVX-512 Scalar convert from sign integer to float/double
4550 //===----------------------------------------------------------------------===//
4552 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4553 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4554 PatFrag ld_frag, string asm> {
4555 let hasSideEffects = 0 in {
4556 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
4557 (ins DstVT.FRC:$src1, SrcRC:$src),
4558 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4561 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
4562 (ins DstVT.FRC:$src1, x86memop:$src),
4563 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4565 } // hasSideEffects = 0
4566 let isCodeGenOnly = 1 in {
4567 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4568 (ins DstVT.RC:$src1, SrcRC:$src2),
4569 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4570 [(set DstVT.RC:$dst,
4571 (OpNode (DstVT.VT DstVT.RC:$src1),
4573 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4575 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
4576 (ins DstVT.RC:$src1, x86memop:$src2),
4577 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4578 [(set DstVT.RC:$dst,
4579 (OpNode (DstVT.VT DstVT.RC:$src1),
4580 (ld_frag addr:$src2),
4581 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4582 }//isCodeGenOnly = 1
4585 multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4586 X86VectorVTInfo DstVT, string asm> {
4587 def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4588 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
4590 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
4591 [(set DstVT.RC:$dst,
4592 (OpNode (DstVT.VT DstVT.RC:$src1),
4594 (i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
4597 multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4598 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4599 PatFrag ld_frag, string asm> {
4600 defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
4601 avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
4605 let Predicates = [HasAVX512] in {
4606 defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4607 v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
4608 XS, EVEX_CD8<32, CD8VT1>;
4609 defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4610 v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
4611 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4612 defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4613 v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
4614 XD, EVEX_CD8<32, CD8VT1>;
4615 defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4616 v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
4617 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4619 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4620 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4621 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4622 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4623 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4624 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4625 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4626 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4628 def : Pat<(f32 (sint_to_fp GR32:$src)),
4629 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4630 def : Pat<(f32 (sint_to_fp GR64:$src)),
4631 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4632 def : Pat<(f64 (sint_to_fp GR32:$src)),
4633 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4634 def : Pat<(f64 (sint_to_fp GR64:$src)),
4635 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4637 defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR32,
4638 v4f32x_info, i32mem, loadi32,
4639 "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
4640 defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4641 v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
4642 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4643 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86UintToFpRnd, GR32, v2f64x_info,
4644 i32mem, loadi32, "cvtusi2sd{l}">,
4645 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4646 defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4647 v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
4648 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4650 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4651 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4652 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4653 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4654 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4655 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4656 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4657 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4659 def : Pat<(f32 (uint_to_fp GR32:$src)),
4660 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4661 def : Pat<(f32 (uint_to_fp GR64:$src)),
4662 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4663 def : Pat<(f64 (uint_to_fp GR32:$src)),
4664 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4665 def : Pat<(f64 (uint_to_fp GR64:$src)),
4666 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4669 //===----------------------------------------------------------------------===//
4670 // AVX-512 Scalar convert from float/double to integer
4671 //===----------------------------------------------------------------------===//
4672 multiclass avx512_cvt_s_int_round<bits<8> opc, RegisterClass SrcRC,
4673 RegisterClass DstRC, Intrinsic Int,
4674 Operand memop, ComplexPattern mem_cpat, string asm> {
4675 let hasSideEffects = 0, Predicates = [HasAVX512] in {
4676 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4677 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4678 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
4679 def rb : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4680 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"), []>,
4681 EVEX, VEX_LIG, EVEX_B, EVEX_RC;
4683 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4684 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
4685 } // hasSideEffects = 0, Predicates = [HasAVX512]
4688 // Convert float/double to signed/unsigned int 32/64
4689 defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4690 ssmem, sse_load_f32, "cvtss2si">,
4691 XS, EVEX_CD8<32, CD8VT1>;
4692 defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4693 int_x86_sse_cvtss2si64,
4694 ssmem, sse_load_f32, "cvtss2si">,
4695 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4696 defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4697 int_x86_avx512_cvtss2usi,
4698 ssmem, sse_load_f32, "cvtss2usi">,
4699 XS, EVEX_CD8<32, CD8VT1>;
4700 defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4701 int_x86_avx512_cvtss2usi64, ssmem,
4702 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4703 EVEX_CD8<32, CD8VT1>;
4704 defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4705 sdmem, sse_load_f64, "cvtsd2si">,
4706 XD, EVEX_CD8<64, CD8VT1>;
4707 defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4708 int_x86_sse2_cvtsd2si64,
4709 sdmem, sse_load_f64, "cvtsd2si">,
4710 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4711 defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4712 int_x86_avx512_cvtsd2usi,
4713 sdmem, sse_load_f64, "cvtsd2usi">,
4714 XD, EVEX_CD8<64, CD8VT1>;
4715 defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4716 int_x86_avx512_cvtsd2usi64, sdmem,
4717 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4718 EVEX_CD8<64, CD8VT1>;
4720 let isCodeGenOnly = 1 , Predicates = [HasAVX512] in {
4721 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4722 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4723 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4724 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4725 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4726 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4727 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4728 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4729 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4730 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4731 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4732 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4734 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4735 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4736 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4737 } // isCodeGenOnly = 1, Predicates = [HasAVX512]
4739 // Convert float/double to signed/unsigned int 32/64 with truncation
4740 multiclass avx512_cvt_s_all<bits<8> opc, string asm, X86VectorVTInfo _SrcRC,
4741 X86VectorVTInfo _DstRC, SDNode OpNode,
4743 let Predicates = [HasAVX512] in {
4744 def rr : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4745 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4746 [(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))]>, EVEX;
4747 def rb : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4748 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4750 def rm : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.MemOp:$src),
4751 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4752 [(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src)))]>,
4755 let isCodeGenOnly = 1,hasSideEffects = 0 in {
4756 def rr_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4757 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4758 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4759 (i32 FROUND_CURRENT)))]>, EVEX, VEX_LIG;
4760 def rb_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4761 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4762 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4763 (i32 FROUND_NO_EXC)))]>,
4764 EVEX,VEX_LIG , EVEX_B;
4766 def rm_Int : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst),
4767 (ins _SrcRC.MemOp:$src),
4768 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4771 } // isCodeGenOnly = 1, hasSideEffects = 0
4776 defm VCVTTSS2SIZ: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i32x_info,
4777 fp_to_sint,X86cvttss2IntRnd>,
4778 XS, EVEX_CD8<32, CD8VT1>;
4779 defm VCVTTSS2SI64Z: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i64x_info,
4780 fp_to_sint,X86cvttss2IntRnd>,
4781 VEX_W, XS, EVEX_CD8<32, CD8VT1>;
4782 defm VCVTTSD2SIZ: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i32x_info,
4783 fp_to_sint,X86cvttsd2IntRnd>,
4784 XD, EVEX_CD8<64, CD8VT1>;
4785 defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i64x_info,
4786 fp_to_sint,X86cvttsd2IntRnd>,
4787 VEX_W, XD, EVEX_CD8<64, CD8VT1>;
4789 defm VCVTTSS2USIZ: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i32x_info,
4790 fp_to_uint,X86cvttss2UIntRnd>,
4791 XS, EVEX_CD8<32, CD8VT1>;
4792 defm VCVTTSS2USI64Z: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i64x_info,
4793 fp_to_uint,X86cvttss2UIntRnd>,
4794 XS,VEX_W, EVEX_CD8<32, CD8VT1>;
4795 defm VCVTTSD2USIZ: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i32x_info,
4796 fp_to_uint,X86cvttsd2UIntRnd>,
4797 XD, EVEX_CD8<64, CD8VT1>;
4798 defm VCVTTSD2USI64Z: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i64x_info,
4799 fp_to_uint,X86cvttsd2UIntRnd>,
4800 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4801 let Predicates = [HasAVX512] in {
4802 def : Pat<(i32 (int_x86_sse_cvttss2si (v4f32 VR128X:$src))),
4803 (VCVTTSS2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
4804 def : Pat<(i64 (int_x86_sse_cvttss2si64 (v4f32 VR128X:$src))),
4805 (VCVTTSS2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
4806 def : Pat<(i32 (int_x86_sse2_cvttsd2si (v2f64 VR128X:$src))),
4807 (VCVTTSD2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
4808 def : Pat<(i64 (int_x86_sse2_cvttsd2si64 (v2f64 VR128X:$src))),
4809 (VCVTTSD2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
4812 //===----------------------------------------------------------------------===//
4813 // AVX-512 Convert form float to double and back
4814 //===----------------------------------------------------------------------===//
4815 multiclass avx512_cvt_fp_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4816 X86VectorVTInfo _Src, SDNode OpNode> {
4817 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4818 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
4819 "$src2, $src1", "$src1, $src2",
4820 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
4821 (_Src.VT _Src.RC:$src2)))>,
4822 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
4823 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4824 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
4825 "$src2, $src1", "$src1, $src2",
4826 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
4827 (_Src.VT (scalar_to_vector
4828 (_Src.ScalarLdFrag addr:$src2)))))>,
4829 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>;
4832 // Scalar Coversion with SAE - suppress all exceptions
4833 multiclass avx512_cvt_fp_sae_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4834 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4835 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4836 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
4837 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
4838 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
4839 (_Src.VT _Src.RC:$src2),
4840 (i32 FROUND_NO_EXC)))>,
4841 EVEX_4V, VEX_LIG, EVEX_B;
4844 // Scalar Conversion with rounding control (RC)
4845 multiclass avx512_cvt_fp_rc_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4846 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4847 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4848 (ins _Src.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr,
4849 "$rc, $src2, $src1", "$src1, $src2, $rc",
4850 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
4851 (_Src.VT _Src.RC:$src2), (i32 imm:$rc)))>,
4852 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
4855 multiclass avx512_cvt_fp_scalar_sd2ss<bits<8> opc, string OpcodeStr, SDNode OpNode,
4856 SDNode OpNodeRnd, X86VectorVTInfo _src,
4857 X86VectorVTInfo _dst> {
4858 let Predicates = [HasAVX512] in {
4859 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
4860 avx512_cvt_fp_rc_scalar<opc, OpcodeStr, _dst, _src,
4861 OpNodeRnd>, VEX_W, EVEX_CD8<64, CD8VT1>,
4866 multiclass avx512_cvt_fp_scalar_ss2sd<bits<8> opc, string OpcodeStr, SDNode OpNode,
4867 SDNode OpNodeRnd, X86VectorVTInfo _src,
4868 X86VectorVTInfo _dst> {
4869 let Predicates = [HasAVX512] in {
4870 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
4871 avx512_cvt_fp_sae_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>,
4872 EVEX_CD8<32, CD8VT1>, XS, EVEX_V512;
4875 defm VCVTSD2SS : avx512_cvt_fp_scalar_sd2ss<0x5A, "vcvtsd2ss", X86fround,
4876 X86froundRnd, f64x_info, f32x_info>;
4877 defm VCVTSS2SD : avx512_cvt_fp_scalar_ss2sd<0x5A, "vcvtss2sd", X86fpext,
4878 X86fpextRnd,f32x_info, f64x_info >;
4880 def : Pat<(f64 (fextend FR32X:$src)),
4881 (COPY_TO_REGCLASS (VCVTSS2SDZrr (COPY_TO_REGCLASS FR32X:$src, VR128X),
4882 (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>,
4883 Requires<[HasAVX512]>;
4884 def : Pat<(f64 (fextend (loadf32 addr:$src))),
4885 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
4886 Requires<[HasAVX512]>;
4888 def : Pat<(f64 (extloadf32 addr:$src)),
4889 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
4890 Requires<[HasAVX512, OptForSize]>;
4892 def : Pat<(f64 (extloadf32 addr:$src)),
4893 (COPY_TO_REGCLASS (VCVTSS2SDZrr (v4f32 (IMPLICIT_DEF)),
4894 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)), VR128X)>,
4895 Requires<[HasAVX512, OptForSpeed]>;
4897 def : Pat<(f32 (fround FR64X:$src)),
4898 (COPY_TO_REGCLASS (VCVTSD2SSZrr (COPY_TO_REGCLASS FR64X:$src, VR128X),
4899 (COPY_TO_REGCLASS FR64X:$src, VR128X)), VR128X)>,
4900 Requires<[HasAVX512]>;
4901 //===----------------------------------------------------------------------===//
4902 // AVX-512 Vector convert from signed/unsigned integer to float/double
4903 // and from float/double to signed/unsigned integer
4904 //===----------------------------------------------------------------------===//
4906 multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4907 X86VectorVTInfo _Src, SDNode OpNode,
4908 string Broadcast = _.BroadcastStr,
4909 string Alias = ""> {
4911 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4912 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
4913 (_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
4915 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4916 (ins _Src.MemOp:$src), OpcodeStr#Alias, "$src", "$src",
4917 (_.VT (OpNode (_Src.VT
4918 (bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
4920 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4921 (ins _Src.MemOp:$src), OpcodeStr,
4922 "${src}"##Broadcast, "${src}"##Broadcast,
4923 (_.VT (OpNode (_Src.VT
4924 (X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
4927 // Coversion with SAE - suppress all exceptions
4928 multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4929 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4930 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4931 (ins _Src.RC:$src), OpcodeStr,
4932 "{sae}, $src", "$src, {sae}",
4933 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src),
4934 (i32 FROUND_NO_EXC)))>,
4938 // Conversion with rounding control (RC)
4939 multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4940 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4941 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4942 (ins _Src.RC:$src, AVX512RC:$rc), OpcodeStr,
4943 "$rc, $src", "$src, $rc",
4944 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc)))>,
4945 EVEX, EVEX_B, EVEX_RC;
4948 // Extend Float to Double
4949 multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
4950 let Predicates = [HasAVX512] in {
4951 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fextend>,
4952 avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
4953 X86vfpextRnd>, EVEX_V512;
4955 let Predicates = [HasVLX] in {
4956 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
4957 X86vfpext, "{1to2}">, EVEX_V128;
4958 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fextend>,
4963 // Truncate Double to Float
4964 multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
4965 let Predicates = [HasAVX512] in {
4966 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fround>,
4967 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
4968 X86vfproundRnd>, EVEX_V512;
4970 let Predicates = [HasVLX] in {
4971 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
4972 X86vfpround, "{1to2}", "{x}">, EVEX_V128;
4973 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fround,
4974 "{1to4}", "{y}">, EVEX_V256;
4978 defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps">,
4979 VEX_W, PD, EVEX_CD8<64, CD8VF>;
4980 defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd">,
4981 PS, EVEX_CD8<32, CD8VH>;
4983 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4984 (VCVTPS2PDZrm addr:$src)>;
4986 let Predicates = [HasVLX] in {
4987 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
4988 (VCVTPS2PDZ256rm addr:$src)>;
4991 // Convert Signed/Unsigned Doubleword to Double
4992 multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
4994 // No rounding in this op
4995 let Predicates = [HasAVX512] in
4996 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode>,
4999 let Predicates = [HasVLX] in {
5000 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
5001 OpNode128, "{1to2}">, EVEX_V128;
5002 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
5007 // Convert Signed/Unsigned Doubleword to Float
5008 multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
5010 let Predicates = [HasAVX512] in
5011 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode>,
5012 avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
5013 OpNodeRnd>, EVEX_V512;
5015 let Predicates = [HasVLX] in {
5016 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode>,
5018 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode>,
5023 // Convert Float to Signed/Unsigned Doubleword with truncation
5024 multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr,
5025 SDNode OpNode, SDNode OpNodeRnd> {
5026 let Predicates = [HasAVX512] in {
5027 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5028 avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
5029 OpNodeRnd>, EVEX_V512;
5031 let Predicates = [HasVLX] in {
5032 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5034 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5039 // Convert Float to Signed/Unsigned Doubleword
5040 multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr,
5041 SDNode OpNode, SDNode OpNodeRnd> {
5042 let Predicates = [HasAVX512] in {
5043 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5044 avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
5045 OpNodeRnd>, EVEX_V512;
5047 let Predicates = [HasVLX] in {
5048 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5050 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5055 // Convert Double to Signed/Unsigned Doubleword with truncation
5056 multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr,
5057 SDNode OpNode, SDNode OpNodeRnd> {
5058 let Predicates = [HasAVX512] in {
5059 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5060 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
5061 OpNodeRnd>, EVEX_V512;
5063 let Predicates = [HasVLX] in {
5064 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5065 // memory forms of these instructions in Asm Parcer. They have the same
5066 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5067 // due to the same reason.
5068 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5069 "{1to2}", "{x}">, EVEX_V128;
5070 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5071 "{1to4}", "{y}">, EVEX_V256;
5075 // Convert Double to Signed/Unsigned Doubleword
5076 multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr,
5077 SDNode OpNode, SDNode OpNodeRnd> {
5078 let Predicates = [HasAVX512] in {
5079 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5080 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
5081 OpNodeRnd>, EVEX_V512;
5083 let Predicates = [HasVLX] in {
5084 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5085 // memory forms of these instructions in Asm Parcer. They have the same
5086 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5087 // due to the same reason.
5088 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5089 "{1to2}", "{x}">, EVEX_V128;
5090 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5091 "{1to4}", "{y}">, EVEX_V256;
5095 // Convert Double to Signed/Unsigned Quardword
5096 multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr,
5097 SDNode OpNode, SDNode OpNodeRnd> {
5098 let Predicates = [HasDQI] in {
5099 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5100 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
5101 OpNodeRnd>, EVEX_V512;
5103 let Predicates = [HasDQI, HasVLX] in {
5104 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5106 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5111 // Convert Double to Signed/Unsigned Quardword with truncation
5112 multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr,
5113 SDNode OpNode, SDNode OpNodeRnd> {
5114 let Predicates = [HasDQI] in {
5115 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5116 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
5117 OpNodeRnd>, EVEX_V512;
5119 let Predicates = [HasDQI, HasVLX] in {
5120 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5122 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5127 // Convert Signed/Unsigned Quardword to Double
5128 multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr,
5129 SDNode OpNode, SDNode OpNodeRnd> {
5130 let Predicates = [HasDQI] in {
5131 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode>,
5132 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
5133 OpNodeRnd>, EVEX_V512;
5135 let Predicates = [HasDQI, HasVLX] in {
5136 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode>,
5138 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode>,
5143 // Convert Float to Signed/Unsigned Quardword
5144 multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr,
5145 SDNode OpNode, SDNode OpNodeRnd> {
5146 let Predicates = [HasDQI] in {
5147 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5148 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
5149 OpNodeRnd>, EVEX_V512;
5151 let Predicates = [HasDQI, HasVLX] in {
5152 // Explicitly specified broadcast string, since we take only 2 elements
5153 // from v4f32x_info source
5154 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5155 "{1to2}">, EVEX_V128;
5156 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5161 // Convert Float to Signed/Unsigned Quardword with truncation
5162 multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr,
5163 SDNode OpNode, SDNode OpNodeRnd> {
5164 let Predicates = [HasDQI] in {
5165 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5166 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
5167 OpNodeRnd>, EVEX_V512;
5169 let Predicates = [HasDQI, HasVLX] in {
5170 // Explicitly specified broadcast string, since we take only 2 elements
5171 // from v4f32x_info source
5172 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5173 "{1to2}">, EVEX_V128;
5174 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5179 // Convert Signed/Unsigned Quardword to Float
5180 multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
5181 SDNode OpNode, SDNode OpNodeRnd> {
5182 let Predicates = [HasDQI] in {
5183 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
5184 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
5185 OpNodeRnd>, EVEX_V512;
5187 let Predicates = [HasDQI, HasVLX] in {
5188 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5189 // memory forms of these instructions in Asm Parcer. They have the same
5190 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5191 // due to the same reason.
5192 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode,
5193 "{1to2}", "{x}">, EVEX_V128;
5194 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
5195 "{1to4}", "{y}">, EVEX_V256;
5199 defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>, XS,
5200 EVEX_CD8<32, CD8VH>;
5202 defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
5204 PS, EVEX_CD8<32, CD8VF>;
5206 defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
5208 XS, EVEX_CD8<32, CD8VF>;
5210 defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint,
5212 PD, VEX_W, EVEX_CD8<64, CD8VF>;
5214 defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint,
5215 X86VFpToUintRnd>, PS,
5216 EVEX_CD8<32, CD8VF>;
5218 defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
5219 X86VFpToUintRnd>, PS, VEX_W,
5220 EVEX_CD8<64, CD8VF>;
5222 defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86cvtudq2pd>,
5223 XS, EVEX_CD8<32, CD8VH>;
5225 defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
5226 X86VUintToFpRnd>, XD,
5227 EVEX_CD8<32, CD8VF>;
5229 defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtps2Int,
5230 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
5232 defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtpd2Int,
5233 X86cvtpd2IntRnd>, XD, VEX_W,
5234 EVEX_CD8<64, CD8VF>;
5236 defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtps2UInt,
5238 PS, EVEX_CD8<32, CD8VF>;
5239 defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtpd2UInt,
5240 X86cvtpd2UIntRnd>, VEX_W,
5241 PS, EVEX_CD8<64, CD8VF>;
5243 defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtpd2Int,
5244 X86cvtpd2IntRnd>, VEX_W,
5245 PD, EVEX_CD8<64, CD8VF>;
5247 defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtps2Int,
5248 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
5250 defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtpd2UInt,
5251 X86cvtpd2UIntRnd>, VEX_W,
5252 PD, EVEX_CD8<64, CD8VF>;
5254 defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtps2UInt,
5255 X86cvtps2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
5257 defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint,
5258 X86VFpToSlongRnd>, VEX_W,
5259 PD, EVEX_CD8<64, CD8VF>;
5261 defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint,
5262 X86VFpToSlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5264 defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint,
5265 X86VFpToUlongRnd>, VEX_W,
5266 PD, EVEX_CD8<64, CD8VF>;
5268 defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint,
5269 X86VFpToUlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5271 defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
5272 X86VSlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5274 defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
5275 X86VUlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5277 defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp,
5278 X86VSlongToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
5280 defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
5281 X86VUlongToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
5283 let Predicates = [NoVLX] in {
5284 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
5285 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5286 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5288 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
5289 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5290 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5292 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
5293 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5294 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5296 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
5297 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5298 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5300 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
5301 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
5302 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
5305 let Predicates = [HasAVX512] in {
5306 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
5307 (VCVTPD2PSZrm addr:$src)>;
5308 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5309 (VCVTPS2PDZrm addr:$src)>;
5312 //===----------------------------------------------------------------------===//
5313 // Half precision conversion instructions
5314 //===----------------------------------------------------------------------===//
5315 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
5316 X86MemOperand x86memop> {
5317 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
5318 "vcvtph2ps\t{$src, $dst|$dst, $src}",
5320 let hasSideEffects = 0, mayLoad = 1 in
5321 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
5322 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
5325 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
5326 X86MemOperand x86memop> {
5327 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
5328 (ins srcRC:$src1, i32u8imm:$src2),
5329 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5331 let hasSideEffects = 0, mayStore = 1 in
5332 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
5333 (ins x86memop:$dst, srcRC:$src1, i32u8imm:$src2),
5334 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
5337 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
5338 EVEX_CD8<32, CD8VH>;
5339 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
5340 EVEX_CD8<32, CD8VH>;
5342 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
5343 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
5344 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
5346 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
5347 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
5348 (VCVTPH2PSZrr VR256X:$src)>;
5350 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5351 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
5352 "ucomiss">, PS, EVEX, VEX_LIG,
5353 EVEX_CD8<32, CD8VT1>;
5354 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
5355 "ucomisd">, PD, EVEX,
5356 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5357 let Pattern = []<dag> in {
5358 defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32,
5359 "comiss">, PS, EVEX, VEX_LIG,
5360 EVEX_CD8<32, CD8VT1>;
5361 defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64,
5362 "comisd">, PD, EVEX,
5363 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5365 let isCodeGenOnly = 1 in {
5366 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
5367 load, "ucomiss">, PS, EVEX, VEX_LIG,
5368 EVEX_CD8<32, CD8VT1>;
5369 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
5370 load, "ucomisd">, PD, EVEX,
5371 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5373 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
5374 load, "comiss">, PS, EVEX, VEX_LIG,
5375 EVEX_CD8<32, CD8VT1>;
5376 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
5377 load, "comisd">, PD, EVEX,
5378 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5382 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
5383 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
5384 X86VectorVTInfo _> {
5385 let hasSideEffects = 0, AddedComplexity = 20 , Predicates = [HasAVX512] in {
5386 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5387 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5388 "$src2, $src1", "$src1, $src2",
5389 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>, EVEX_4V;
5390 let mayLoad = 1 in {
5391 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5392 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5393 "$src2, $src1", "$src1, $src2",
5394 (OpNode (_.VT _.RC:$src1),
5395 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))))>, EVEX_4V;
5400 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", X86frcp14s, f32x_info>,
5401 EVEX_CD8<32, CD8VT1>, T8PD;
5402 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", X86frcp14s, f64x_info>,
5403 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5404 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", X86frsqrt14s, f32x_info>,
5405 EVEX_CD8<32, CD8VT1>, T8PD;
5406 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", X86frsqrt14s, f64x_info>,
5407 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5409 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
5410 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
5411 X86VectorVTInfo _> {
5412 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5413 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5414 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
5415 let mayLoad = 1 in {
5416 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5417 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5419 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
5420 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5421 (ins _.ScalarMemOp:$src), OpcodeStr,
5422 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5424 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5429 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5430 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
5431 EVEX_V512, EVEX_CD8<32, CD8VF>;
5432 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
5433 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5435 // Define only if AVX512VL feature is present.
5436 let Predicates = [HasVLX] in {
5437 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5438 OpNode, v4f32x_info>,
5439 EVEX_V128, EVEX_CD8<32, CD8VF>;
5440 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5441 OpNode, v8f32x_info>,
5442 EVEX_V256, EVEX_CD8<32, CD8VF>;
5443 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5444 OpNode, v2f64x_info>,
5445 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
5446 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5447 OpNode, v4f64x_info>,
5448 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
5452 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
5453 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
5455 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
5456 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5457 (VRSQRT14PSZr VR512:$src)>;
5458 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
5459 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5460 (VRSQRT14PDZr VR512:$src)>;
5462 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
5463 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5464 (VRCP14PSZr VR512:$src)>;
5465 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
5466 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5467 (VRCP14PDZr VR512:$src)>;
5469 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
5470 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5473 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5474 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5475 "$src2, $src1", "$src1, $src2",
5476 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5477 (i32 FROUND_CURRENT))>;
5479 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5480 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5481 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5482 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5483 (i32 FROUND_NO_EXC))>, EVEX_B;
5485 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5486 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5487 "$src2, $src1", "$src1, $src2",
5488 (OpNode (_.VT _.RC:$src1),
5489 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5490 (i32 FROUND_CURRENT))>;
5493 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5494 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
5495 EVEX_CD8<32, CD8VT1>;
5496 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
5497 EVEX_CD8<64, CD8VT1>, VEX_W;
5500 let hasSideEffects = 0, Predicates = [HasERI] in {
5501 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
5502 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
5505 defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds>, T8PD, EVEX_4V;
5506 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
5508 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5511 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5512 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5513 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
5515 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5516 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5518 (bitconvert (_.LdFrag addr:$src))),
5519 (i32 FROUND_CURRENT))>;
5521 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5522 (ins _.MemOp:$src), OpcodeStr,
5523 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5525 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
5526 (i32 FROUND_CURRENT))>, EVEX_B;
5528 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5530 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5531 (ins _.RC:$src), OpcodeStr,
5532 "{sae}, $src", "$src, {sae}",
5533 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
5536 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5537 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5538 avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5539 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
5540 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5541 avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5542 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5545 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
5547 // Define only if AVX512VL feature is present.
5548 let Predicates = [HasVLX] in {
5549 defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
5550 EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;
5551 defm PSZ256 : avx512_fp28_p<opc, OpcodeStr#"ps", v8f32x_info, OpNode>,
5552 EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>;
5553 defm PDZ128 : avx512_fp28_p<opc, OpcodeStr#"pd", v2f64x_info, OpNode>,
5554 EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5555 defm PDZ256 : avx512_fp28_p<opc, OpcodeStr#"pd", v4f64x_info, OpNode>,
5556 EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5559 let Predicates = [HasERI], hasSideEffects = 0 in {
5561 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX;
5562 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX;
5563 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX;
5565 defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
5566 avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
5568 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
5569 SDNode OpNodeRnd, X86VectorVTInfo _>{
5570 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5571 (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
5572 (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
5573 EVEX, EVEX_B, EVEX_RC;
5576 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
5577 SDNode OpNode, X86VectorVTInfo _>{
5578 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5579 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5580 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
5581 let mayLoad = 1 in {
5582 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5583 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5585 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
5587 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5588 (ins _.ScalarMemOp:$src), OpcodeStr,
5589 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5591 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5596 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
5598 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
5600 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5601 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
5603 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5604 // Define only if AVX512VL feature is present.
5605 let Predicates = [HasVLX] in {
5606 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5607 OpNode, v4f32x_info>,
5608 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
5609 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5610 OpNode, v8f32x_info>,
5611 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
5612 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5613 OpNode, v2f64x_info>,
5614 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5615 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5616 OpNode, v4f64x_info>,
5617 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5621 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
5623 defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
5624 v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5625 defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
5626 v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5629 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5630 string SUFF, SDNode OpNode, SDNode OpNodeRnd> {
5632 defm r_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5633 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5634 "$src2, $src1", "$src1, $src2",
5635 (OpNodeRnd (_.VT _.RC:$src1),
5637 (i32 FROUND_CURRENT))>;
5639 defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5640 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5641 "$src2, $src1", "$src1, $src2",
5642 (OpNodeRnd (_.VT _.RC:$src1),
5643 (_.VT (scalar_to_vector
5644 (_.ScalarLdFrag addr:$src2))),
5645 (i32 FROUND_CURRENT))>;
5647 defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5648 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
5649 "$rc, $src2, $src1", "$src1, $src2, $rc",
5650 (OpNodeRnd (_.VT _.RC:$src1),
5655 let isCodeGenOnly = 1 in {
5656 def r : SI<opc, MRMSrcReg, (outs _.FRC:$dst),
5657 (ins _.FRC:$src1, _.FRC:$src2),
5658 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5661 def m : SI<opc, MRMSrcMem, (outs _.FRC:$dst),
5662 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
5663 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5666 def : Pat<(_.EltVT (OpNode _.FRC:$src)),
5667 (!cast<Instruction>(NAME#SUFF#Zr)
5668 (_.EltVT (IMPLICIT_DEF)), _.FRC:$src)>;
5670 def : Pat<(_.EltVT (OpNode (load addr:$src))),
5671 (!cast<Instruction>(NAME#SUFF#Zm)
5672 (_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[OptForSize]>;
5675 multiclass avx512_sqrt_scalar_all<bits<8> opc, string OpcodeStr> {
5676 defm SSZ : avx512_sqrt_scalar<opc, OpcodeStr#"ss", f32x_info, "SS", fsqrt,
5677 X86fsqrtRnds>, EVEX_CD8<32, CD8VT1>, EVEX_4V, XS;
5678 defm SDZ : avx512_sqrt_scalar<opc, OpcodeStr#"sd", f64x_info, "SD", fsqrt,
5679 X86fsqrtRnds>, EVEX_CD8<64, CD8VT1>, EVEX_4V, XD, VEX_W;
5682 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>,
5683 avx512_sqrt_packed_all_round<0x51, "vsqrt", X86fsqrtRnd>;
5685 defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt">, VEX_LIG;
5687 let Predicates = [HasAVX512] in {
5688 def : Pat<(f32 (X86frsqrt FR32X:$src)),
5689 (COPY_TO_REGCLASS (VRSQRT14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>;
5690 def : Pat<(f32 (X86frsqrt (load addr:$src))),
5691 (COPY_TO_REGCLASS (VRSQRT14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5692 Requires<[OptForSize]>;
5693 def : Pat<(f32 (X86frcp FR32X:$src)),
5694 (COPY_TO_REGCLASS (VRCP14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X )>;
5695 def : Pat<(f32 (X86frcp (load addr:$src))),
5696 (COPY_TO_REGCLASS (VRCP14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5697 Requires<[OptForSize]>;
5701 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5703 let ExeDomain = _.ExeDomain in {
5704 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5705 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5706 "$src3, $src2, $src1", "$src1, $src2, $src3",
5707 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5708 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5710 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5711 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5712 "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
5713 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5714 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5717 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5718 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5719 "$src3, $src2, $src1", "$src1, $src2, $src3",
5720 (_.VT (X86RndScales (_.VT _.RC:$src1),
5721 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5722 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5724 let Predicates = [HasAVX512] in {
5725 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5726 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5727 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5728 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5729 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5730 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5731 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5732 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5733 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5734 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5735 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5736 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5737 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5738 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5739 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
5741 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5742 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5743 addr:$src, (i32 0x1))), _.FRC)>;
5744 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5745 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5746 addr:$src, (i32 0x2))), _.FRC)>;
5747 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5748 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5749 addr:$src, (i32 0x3))), _.FRC)>;
5750 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5751 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5752 addr:$src, (i32 0x4))), _.FRC)>;
5753 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5754 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5755 addr:$src, (i32 0xc))), _.FRC)>;
5759 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
5760 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5762 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
5763 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
5765 //-------------------------------------------------
5766 // Integer truncate and extend operations
5767 //-------------------------------------------------
5769 multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
5770 X86VectorVTInfo SrcInfo, X86VectorVTInfo DestInfo,
5771 X86MemOperand x86memop> {
5773 defm rr : AVX512_maskable<opc, MRMDestReg, DestInfo, (outs DestInfo.RC:$dst),
5774 (ins SrcInfo.RC:$src1), OpcodeStr ,"$src1", "$src1",
5775 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1)))>,
5778 // for intrinsic patter match
5779 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5780 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5782 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
5785 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5786 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5787 DestInfo.ImmAllZerosV)),
5788 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
5791 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5792 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5793 DestInfo.RC:$src0)),
5794 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrk) DestInfo.RC:$src0,
5795 DestInfo.KRCWM:$mask ,
5798 let mayStore = 1 in {
5799 def mr : AVX512XS8I<opc, MRMDestMem, (outs),
5800 (ins x86memop:$dst, SrcInfo.RC:$src),
5801 OpcodeStr # "\t{$src, $dst |$dst, $src}",
5804 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
5805 (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
5806 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5811 multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,
5812 X86VectorVTInfo DestInfo,
5813 PatFrag truncFrag, PatFrag mtruncFrag > {
5815 def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
5816 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr)
5817 addr:$dst, SrcInfo.RC:$src)>;
5819 def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask,
5820 (SrcInfo.VT SrcInfo.RC:$src)),
5821 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk)
5822 addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
5825 multiclass avx512_trunc_sat_mr_lowering<X86VectorVTInfo SrcInfo,
5826 X86VectorVTInfo DestInfo, string sat > {
5828 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
5829 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
5830 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), SrcInfo.MRC:$mask),
5831 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk) addr:$ptr,
5832 (COPY_TO_REGCLASS SrcInfo.MRC:$mask, SrcInfo.KRCWM),
5833 (SrcInfo.VT SrcInfo.RC:$src))>;
5835 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
5836 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
5837 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), -1),
5838 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr) addr:$ptr,
5839 (SrcInfo.VT SrcInfo.RC:$src))>;
5842 multiclass avx512_trunc<bits<8> opc, string OpcodeStr, SDNode OpNode,
5843 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
5844 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
5845 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
5846 X86MemOperand x86memopZ, PatFrag truncFrag, PatFrag mtruncFrag,
5847 Predicate prd = HasAVX512>{
5849 let Predicates = [HasVLX, prd] in {
5850 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
5851 DestInfoZ128, x86memopZ128>,
5852 avx512_trunc_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
5853 truncFrag, mtruncFrag>, EVEX_V128;
5855 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
5856 DestInfoZ256, x86memopZ256>,
5857 avx512_trunc_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
5858 truncFrag, mtruncFrag>, EVEX_V256;
5860 let Predicates = [prd] in
5861 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
5862 DestInfoZ, x86memopZ>,
5863 avx512_trunc_mr_lowering<VTSrcInfo.info512, DestInfoZ,
5864 truncFrag, mtruncFrag>, EVEX_V512;
5867 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr, SDNode OpNode,
5868 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
5869 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
5870 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
5871 X86MemOperand x86memopZ, string sat, Predicate prd = HasAVX512>{
5873 let Predicates = [HasVLX, prd] in {
5874 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
5875 DestInfoZ128, x86memopZ128>,
5876 avx512_trunc_sat_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
5879 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
5880 DestInfoZ256, x86memopZ256>,
5881 avx512_trunc_sat_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
5884 let Predicates = [prd] in
5885 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
5886 DestInfoZ, x86memopZ>,
5887 avx512_trunc_sat_mr_lowering<VTSrcInfo.info512, DestInfoZ,
5891 multiclass avx512_trunc_qb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5892 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
5893 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
5894 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VO>;
5896 multiclass avx512_trunc_sat_qb<bits<8> opc, string sat, SDNode OpNode> {
5897 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qb", OpNode, avx512vl_i64_info,
5898 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
5899 sat>, EVEX_CD8<8, CD8VO>;
5902 multiclass avx512_trunc_qw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5903 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
5904 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
5905 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VQ>;
5907 multiclass avx512_trunc_sat_qw<bits<8> opc, string sat, SDNode OpNode> {
5908 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qw", OpNode, avx512vl_i64_info,
5909 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
5910 sat>, EVEX_CD8<16, CD8VQ>;
5913 multiclass avx512_trunc_qd<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5914 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
5915 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
5916 truncstorevi32, masked_truncstorevi32>, EVEX_CD8<32, CD8VH>;
5918 multiclass avx512_trunc_sat_qd<bits<8> opc, string sat, SDNode OpNode> {
5919 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qd", OpNode, avx512vl_i64_info,
5920 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
5921 sat>, EVEX_CD8<32, CD8VH>;
5924 multiclass avx512_trunc_db<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5925 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
5926 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
5927 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VQ>;
5929 multiclass avx512_trunc_sat_db<bits<8> opc, string sat, SDNode OpNode> {
5930 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"db", OpNode, avx512vl_i32_info,
5931 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
5932 sat>, EVEX_CD8<8, CD8VQ>;
5935 multiclass avx512_trunc_dw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5936 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
5937 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
5938 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VH>;
5940 multiclass avx512_trunc_sat_dw<bits<8> opc, string sat, SDNode OpNode> {
5941 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"dw", OpNode, avx512vl_i32_info,
5942 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
5943 sat>, EVEX_CD8<16, CD8VH>;
5946 multiclass avx512_trunc_wb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5947 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i16_info,
5948 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
5949 truncstorevi8, masked_truncstorevi8,HasBWI>, EVEX_CD8<16, CD8VH>;
5951 multiclass avx512_trunc_sat_wb<bits<8> opc, string sat, SDNode OpNode> {
5952 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"wb", OpNode, avx512vl_i16_info,
5953 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
5954 sat, HasBWI>, EVEX_CD8<16, CD8VH>;
5957 defm VPMOVQB : avx512_trunc_qb<0x32, "vpmovqb", X86vtrunc>;
5958 defm VPMOVSQB : avx512_trunc_sat_qb<0x22, "s", X86vtruncs>;
5959 defm VPMOVUSQB : avx512_trunc_sat_qb<0x12, "us", X86vtruncus>;
5961 defm VPMOVQW : avx512_trunc_qw<0x34, "vpmovqw", X86vtrunc>;
5962 defm VPMOVSQW : avx512_trunc_sat_qw<0x24, "s", X86vtruncs>;
5963 defm VPMOVUSQW : avx512_trunc_sat_qw<0x14, "us", X86vtruncus>;
5965 defm VPMOVQD : avx512_trunc_qd<0x35, "vpmovqd", X86vtrunc>;
5966 defm VPMOVSQD : avx512_trunc_sat_qd<0x25, "s", X86vtruncs>;
5967 defm VPMOVUSQD : avx512_trunc_sat_qd<0x15, "us", X86vtruncus>;
5969 defm VPMOVDB : avx512_trunc_db<0x31, "vpmovdb", X86vtrunc>;
5970 defm VPMOVSDB : avx512_trunc_sat_db<0x21, "s", X86vtruncs>;
5971 defm VPMOVUSDB : avx512_trunc_sat_db<0x11, "us", X86vtruncus>;
5973 defm VPMOVDW : avx512_trunc_dw<0x33, "vpmovdw", X86vtrunc>;
5974 defm VPMOVSDW : avx512_trunc_sat_dw<0x23, "s", X86vtruncs>;
5975 defm VPMOVUSDW : avx512_trunc_sat_dw<0x13, "us", X86vtruncus>;
5977 defm VPMOVWB : avx512_trunc_wb<0x30, "vpmovwb", X86vtrunc>;
5978 defm VPMOVSWB : avx512_trunc_sat_wb<0x20, "s", X86vtruncs>;
5979 defm VPMOVUSWB : avx512_trunc_sat_wb<0x10, "us", X86vtruncus>;
5981 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
5982 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
5983 X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{
5985 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
5986 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
5987 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
5990 let mayLoad = 1 in {
5991 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
5992 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
5993 (DestInfo.VT (LdFrag addr:$src))>,
5998 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode,
5999 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6000 let Predicates = [HasVLX, HasBWI] in {
6001 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
6002 v16i8x_info, i64mem, LdFrag, OpNode>,
6003 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
6005 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
6006 v16i8x_info, i128mem, LdFrag, OpNode>,
6007 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
6009 let Predicates = [HasBWI] in {
6010 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
6011 v32i8x_info, i256mem, LdFrag, OpNode>,
6012 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
6016 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6017 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6018 let Predicates = [HasVLX, HasAVX512] in {
6019 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6020 v16i8x_info, i32mem, LdFrag, OpNode>,
6021 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
6023 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6024 v16i8x_info, i64mem, LdFrag, OpNode>,
6025 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
6027 let Predicates = [HasAVX512] in {
6028 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6029 v16i8x_info, i128mem, LdFrag, OpNode>,
6030 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
6034 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6035 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6036 let Predicates = [HasVLX, HasAVX512] in {
6037 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6038 v16i8x_info, i16mem, LdFrag, OpNode>,
6039 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
6041 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6042 v16i8x_info, i32mem, LdFrag, OpNode>,
6043 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
6045 let Predicates = [HasAVX512] in {
6046 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6047 v16i8x_info, i64mem, LdFrag, OpNode>,
6048 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
6052 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6053 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6054 let Predicates = [HasVLX, HasAVX512] in {
6055 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6056 v8i16x_info, i64mem, LdFrag, OpNode>,
6057 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
6059 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6060 v8i16x_info, i128mem, LdFrag, OpNode>,
6061 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
6063 let Predicates = [HasAVX512] in {
6064 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6065 v16i16x_info, i256mem, LdFrag, OpNode>,
6066 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
6070 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6071 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6072 let Predicates = [HasVLX, HasAVX512] in {
6073 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6074 v8i16x_info, i32mem, LdFrag, OpNode>,
6075 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
6077 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6078 v8i16x_info, i64mem, LdFrag, OpNode>,
6079 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
6081 let Predicates = [HasAVX512] in {
6082 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6083 v8i16x_info, i128mem, LdFrag, OpNode>,
6084 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
6088 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6089 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
6091 let Predicates = [HasVLX, HasAVX512] in {
6092 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6093 v4i32x_info, i64mem, LdFrag, OpNode>,
6094 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
6096 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6097 v4i32x_info, i128mem, LdFrag, OpNode>,
6098 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
6100 let Predicates = [HasAVX512] in {
6101 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6102 v8i32x_info, i256mem, LdFrag, OpNode>,
6103 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
6107 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, "z">;
6108 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, "z">;
6109 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, "z">;
6110 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, "z">;
6111 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, "z">;
6112 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, "z">;
6115 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, "s">;
6116 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, "s">;
6117 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, "s">;
6118 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, "s">;
6119 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, "s">;
6120 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, "s">;
6122 //===----------------------------------------------------------------------===//
6123 // GATHER - SCATTER Operations
6125 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6126 X86MemOperand memop, PatFrag GatherNode> {
6127 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb",
6128 ExeDomain = _.ExeDomain in
6129 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
6130 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
6131 !strconcat(OpcodeStr#_.Suffix,
6132 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
6133 [(set _.RC:$dst, _.KRCWM:$mask_wb,
6134 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
6135 vectoraddr:$src2))]>, EVEX, EVEX_K,
6136 EVEX_CD8<_.EltSize, CD8VT1>;
6139 multiclass avx512_gather_q_pd<bits<8> dopc, bits<8> qopc,
6140 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6141 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512,
6142 vy32xmem, mgatherv8i32>, EVEX_V512, VEX_W;
6143 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info512,
6144 vz64mem, mgatherv8i64>, EVEX_V512, VEX_W;
6145 let Predicates = [HasVLX] in {
6146 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6147 vx32xmem, mgatherv4i32>, EVEX_V256, VEX_W;
6148 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info256,
6149 vy64xmem, mgatherv4i64>, EVEX_V256, VEX_W;
6150 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6151 vx32xmem, mgatherv4i32>, EVEX_V128, VEX_W;
6152 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6153 vx64xmem, mgatherv2i64>, EVEX_V128, VEX_W;
6157 multiclass avx512_gather_d_ps<bits<8> dopc, bits<8> qopc,
6158 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6159 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512, vz32mem,
6160 mgatherv16i32>, EVEX_V512;
6161 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info256, vz64mem,
6162 mgatherv8i64>, EVEX_V512;
6163 let Predicates = [HasVLX] in {
6164 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6165 vy32xmem, mgatherv8i32>, EVEX_V256;
6166 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6167 vy64xmem, mgatherv4i64>, EVEX_V256;
6168 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6169 vx32xmem, mgatherv4i32>, EVEX_V128;
6170 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6171 vx64xmem, mgatherv2i64>, EVEX_V128;
6176 defm VGATHER : avx512_gather_q_pd<0x92, 0x93, avx512vl_f64_info, "vgather", "PD">,
6177 avx512_gather_d_ps<0x92, 0x93, avx512vl_f32_info, "vgather", "PS">;
6179 defm VPGATHER : avx512_gather_q_pd<0x90, 0x91, avx512vl_i64_info, "vpgather", "Q">,
6180 avx512_gather_d_ps<0x90, 0x91, avx512vl_i32_info, "vpgather", "D">;
6182 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6183 X86MemOperand memop, PatFrag ScatterNode> {
6185 let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain in
6187 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
6188 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
6189 !strconcat(OpcodeStr#_.Suffix,
6190 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
6191 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
6192 _.KRCWM:$mask, vectoraddr:$dst))]>,
6193 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6196 multiclass avx512_scatter_q_pd<bits<8> dopc, bits<8> qopc,
6197 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6198 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512,
6199 vy32xmem, mscatterv8i32>, EVEX_V512, VEX_W;
6200 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info512,
6201 vz64mem, mscatterv8i64>, EVEX_V512, VEX_W;
6202 let Predicates = [HasVLX] in {
6203 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6204 vx32xmem, mscatterv4i32>, EVEX_V256, VEX_W;
6205 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info256,
6206 vy64xmem, mscatterv4i64>, EVEX_V256, VEX_W;
6207 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6208 vx32xmem, mscatterv4i32>, EVEX_V128, VEX_W;
6209 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6210 vx64xmem, mscatterv2i64>, EVEX_V128, VEX_W;
6214 multiclass avx512_scatter_d_ps<bits<8> dopc, bits<8> qopc,
6215 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6216 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512, vz32mem,
6217 mscatterv16i32>, EVEX_V512;
6218 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info256, vz64mem,
6219 mscatterv8i64>, EVEX_V512;
6220 let Predicates = [HasVLX] in {
6221 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6222 vy32xmem, mscatterv8i32>, EVEX_V256;
6223 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6224 vy64xmem, mscatterv4i64>, EVEX_V256;
6225 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6226 vx32xmem, mscatterv4i32>, EVEX_V128;
6227 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6228 vx64xmem, mscatterv2i64>, EVEX_V128;
6232 defm VSCATTER : avx512_scatter_q_pd<0xA2, 0xA3, avx512vl_f64_info, "vscatter", "PD">,
6233 avx512_scatter_d_ps<0xA2, 0xA3, avx512vl_f32_info, "vscatter", "PS">;
6235 defm VPSCATTER : avx512_scatter_q_pd<0xA0, 0xA1, avx512vl_i64_info, "vpscatter", "Q">,
6236 avx512_scatter_d_ps<0xA0, 0xA1, avx512vl_i32_info, "vpscatter", "D">;
6239 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
6240 RegisterClass KRC, X86MemOperand memop> {
6241 let Predicates = [HasPFI], hasSideEffects = 1 in
6242 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
6243 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
6247 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
6248 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6250 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
6251 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6253 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
6254 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6256 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
6257 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6259 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
6260 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6262 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
6263 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6265 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
6266 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6268 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
6269 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6271 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
6272 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6274 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
6275 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6277 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
6278 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6280 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
6281 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6283 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
6284 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6286 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
6287 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6289 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
6290 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6292 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
6293 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6295 // Helper fragments to match sext vXi1 to vXiY.
6296 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
6297 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
6299 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6300 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6301 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
6303 def : Pat<(store VK1:$src, addr:$dst),
6305 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
6306 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6308 def : Pat<(store VK8:$src, addr:$dst),
6310 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
6311 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6313 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
6314 (truncstore node:$val, node:$ptr), [{
6315 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
6318 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
6319 (MOV8mr addr:$dst, GR8:$src)>;
6321 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
6322 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
6323 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
6324 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
6327 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
6328 string OpcodeStr, Predicate prd> {
6329 let Predicates = [prd] in
6330 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6332 let Predicates = [prd, HasVLX] in {
6333 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6334 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6338 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
6339 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
6341 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
6343 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
6345 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
6349 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
6351 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
6352 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
6353 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6354 [(set _.KRC:$dst, (trunc (_.VT _.RC:$src)))]>, EVEX;
6357 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
6358 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6359 let Predicates = [prd] in
6360 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
6363 let Predicates = [prd, HasVLX] in {
6364 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
6366 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
6371 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
6372 avx512vl_i8_info, HasBWI>;
6373 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
6374 avx512vl_i16_info, HasBWI>, VEX_W;
6375 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
6376 avx512vl_i32_info, HasDQI>;
6377 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
6378 avx512vl_i64_info, HasDQI>, VEX_W;
6380 //===----------------------------------------------------------------------===//
6381 // AVX-512 - COMPRESS and EXPAND
6384 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6386 defm rr : AVX512_maskable<opc, MRMDestReg, _, (outs _.RC:$dst),
6387 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6388 (_.VT (X86compress _.RC:$src1))>, AVX5128IBase;
6390 let mayStore = 1 in {
6391 def mr : AVX5128I<opc, MRMDestMem, (outs),
6392 (ins _.MemOp:$dst, _.RC:$src),
6393 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6394 []>, EVEX_CD8<_.EltSize, CD8VT1>;
6396 def mrk : AVX5128I<opc, MRMDestMem, (outs),
6397 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
6398 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6399 [(store (_.VT (vselect _.KRCWM:$mask,
6400 (_.VT (X86compress _.RC:$src)), _.ImmAllZerosV)),
6402 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6406 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
6407 AVX512VLVectorVTInfo VTInfo> {
6408 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6410 let Predicates = [HasVLX] in {
6411 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6412 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6416 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
6418 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
6420 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
6422 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
6426 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6428 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6429 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6430 (_.VT (X86expand _.RC:$src1))>, AVX5128IBase;
6433 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6434 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
6435 (_.VT (X86expand (_.VT (bitconvert
6436 (_.LdFrag addr:$src1)))))>,
6437 AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>;
6440 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
6441 AVX512VLVectorVTInfo VTInfo> {
6442 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6444 let Predicates = [HasVLX] in {
6445 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6446 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6450 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
6452 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
6454 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
6456 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
6459 //handle instruction reg_vec1 = op(reg_vec,imm)
6461 // op(broadcast(eltVt),imm)
6462 //all instruction created with FROUND_CURRENT
6463 multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6465 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6466 (ins _.RC:$src1, i32u8imm:$src2),
6467 OpcodeStr##_.Suffix, "$src2, $src1", "$src2, $src2",
6468 (OpNode (_.VT _.RC:$src1),
6470 (i32 FROUND_CURRENT))>;
6471 let mayLoad = 1 in {
6472 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6473 (ins _.MemOp:$src1, i32u8imm:$src2),
6474 OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
6475 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
6477 (i32 FROUND_CURRENT))>;
6478 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6479 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
6480 OpcodeStr##_.Suffix, "$src2, ${src1}"##_.BroadcastStr,
6481 "${src1}"##_.BroadcastStr##", $src2",
6482 (OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src1))),
6484 (i32 FROUND_CURRENT))>, EVEX_B;
6488 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6489 multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6490 SDNode OpNode, X86VectorVTInfo _>{
6491 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6492 (ins _.RC:$src1, i32u8imm:$src2),
6493 OpcodeStr##_.Suffix, "$src2,{sae}, $src1",
6494 "$src1, {sae}, $src2",
6495 (OpNode (_.VT _.RC:$src1),
6497 (i32 FROUND_NO_EXC))>, EVEX_B;
6500 multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
6501 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6502 let Predicates = [prd] in {
6503 defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6504 avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6507 let Predicates = [prd, HasVLX] in {
6508 defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6510 defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6515 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6516 // op(reg_vec2,mem_vec,imm)
6517 // op(reg_vec2,broadcast(eltVt),imm)
6518 //all instruction created with FROUND_CURRENT
6519 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6521 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6522 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6523 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6524 (OpNode (_.VT _.RC:$src1),
6527 (i32 FROUND_CURRENT))>;
6528 let mayLoad = 1 in {
6529 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6530 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6531 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6532 (OpNode (_.VT _.RC:$src1),
6533 (_.VT (bitconvert (_.LdFrag addr:$src2))),
6535 (i32 FROUND_CURRENT))>;
6536 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6537 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
6538 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6539 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6540 (OpNode (_.VT _.RC:$src1),
6541 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6543 (i32 FROUND_CURRENT))>, EVEX_B;
6547 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6548 // op(reg_vec2,mem_vec,imm)
6549 multiclass avx512_3Op_rm_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6550 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo>{
6552 defm rri : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6553 (ins SrcInfo.RC:$src1, SrcInfo.RC:$src2, u8imm:$src3),
6554 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6555 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6556 (SrcInfo.VT SrcInfo.RC:$src2),
6559 defm rmi : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6560 (ins SrcInfo.RC:$src1, SrcInfo.MemOp:$src2, u8imm:$src3),
6561 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6562 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6563 (SrcInfo.VT (bitconvert
6564 (SrcInfo.LdFrag addr:$src2))),
6568 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6569 // op(reg_vec2,mem_vec,imm)
6570 // op(reg_vec2,broadcast(eltVt),imm)
6571 multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6573 avx512_3Op_rm_imm8<opc, OpcodeStr, OpNode, _, _>{
6576 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6577 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6578 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6579 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6580 (OpNode (_.VT _.RC:$src1),
6581 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6582 (i8 imm:$src3))>, EVEX_B;
6585 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6586 // op(reg_vec2,mem_scalar,imm)
6587 //all instruction created with FROUND_CURRENT
6588 multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6589 X86VectorVTInfo _> {
6591 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6592 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6593 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6594 (OpNode (_.VT _.RC:$src1),
6597 (i32 FROUND_CURRENT))>;
6598 let mayLoad = 1 in {
6599 defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6600 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6601 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6602 (OpNode (_.VT _.RC:$src1),
6603 (_.VT (scalar_to_vector
6604 (_.ScalarLdFrag addr:$src2))),
6606 (i32 FROUND_CURRENT))>;
6608 let isAsmParserOnly = 1 in {
6609 defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
6610 (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6611 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6617 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6618 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6619 SDNode OpNode, X86VectorVTInfo _>{
6620 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6621 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6622 OpcodeStr, "$src3,{sae}, $src2, $src1",
6623 "$src1, $src2,{sae}, $src3",
6624 (OpNode (_.VT _.RC:$src1),
6627 (i32 FROUND_NO_EXC))>, EVEX_B;
6629 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6630 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
6631 SDNode OpNode, X86VectorVTInfo _> {
6632 defm NAME#rrib : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6633 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6634 OpcodeStr, "$src3,{sae}, $src2, $src1",
6635 "$src1, $src2,{sae}, $src3",
6636 (OpNode (_.VT _.RC:$src1),
6639 (i32 FROUND_NO_EXC))>, EVEX_B;
6642 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
6643 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6644 let Predicates = [prd] in {
6645 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6646 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6650 let Predicates = [prd, HasVLX] in {
6651 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6653 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6658 multiclass avx512_common_3Op_rm_imm8<bits<8> opc, SDNode OpNode, string OpStr,
6659 AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo>{
6660 let Predicates = [HasBWI] in {
6661 defm Z : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info512,
6662 SrcInfo.info512>, EVEX_V512, AVX512AIi8Base, EVEX_4V;
6664 let Predicates = [HasBWI, HasVLX] in {
6665 defm Z128 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info128,
6666 SrcInfo.info128>, EVEX_V128, AVX512AIi8Base, EVEX_4V;
6667 defm Z256 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info256,
6668 SrcInfo.info256>, EVEX_V256, AVX512AIi8Base, EVEX_4V;
6672 multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
6673 bits<8> opc, SDNode OpNode>{
6674 let Predicates = [HasAVX512] in {
6675 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6677 let Predicates = [HasAVX512, HasVLX] in {
6678 defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
6679 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6683 multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
6684 X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6685 let Predicates = [prd] in {
6686 defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
6687 avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
6691 multiclass avx512_common_unary_fp_sae_packed_imm_all<string OpcodeStr,
6692 bits<8> opcPs, bits<8> opcPd, SDNode OpNode, Predicate prd>{
6693 defm PS : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f32_info,
6694 opcPs, OpNode, prd>, EVEX_CD8<32, CD8VF>;
6695 defm PD : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f64_info,
6696 opcPd, OpNode, prd>, EVEX_CD8<64, CD8VF>, VEX_W;
6699 defm VFIXUPIMMPD : avx512_common_fp_sae_packed_imm<"vfixupimmpd",
6700 avx512vl_f64_info, 0x54, X86VFixupimm, HasAVX512>,
6701 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6702 defm VFIXUPIMMPS : avx512_common_fp_sae_packed_imm<"vfixupimmps",
6703 avx512vl_f32_info, 0x54, X86VFixupimm, HasAVX512>,
6704 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6706 defm VFIXUPIMMSD: avx512_common_fp_sae_scalar_imm<"vfixupimmsd", f64x_info,
6707 0x55, X86VFixupimm, HasAVX512>,
6708 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6709 defm VFIXUPIMMSS: avx512_common_fp_sae_scalar_imm<"vfixupimmss", f32x_info,
6710 0x55, X86VFixupimm, HasAVX512>,
6711 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6713 defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56,
6714 X86VReduce, HasDQI>, AVX512AIi8Base, EVEX;
6715 defm VRNDSCALE : avx512_common_unary_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09,
6716 X86VRndScale, HasAVX512>, AVX512AIi8Base, EVEX;
6717 defm VGETMANT : avx512_common_unary_fp_sae_packed_imm_all<"vgetmant", 0x26, 0x26,
6718 X86VGetMant, HasAVX512>, AVX512AIi8Base, EVEX;
6721 defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
6722 0x50, X86VRange, HasDQI>,
6723 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6724 defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
6725 0x50, X86VRange, HasDQI>,
6726 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6728 defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
6729 0x51, X86VRange, HasDQI>,
6730 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6731 defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
6732 0x51, X86VRange, HasDQI>,
6733 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6735 defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info,
6736 0x57, X86Reduces, HasDQI>,
6737 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6738 defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info,
6739 0x57, X86Reduces, HasDQI>,
6740 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6742 defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info,
6743 0x27, X86GetMants, HasAVX512>,
6744 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6745 defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info,
6746 0x27, X86GetMants, HasAVX512>,
6747 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6749 multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
6750 bits<8> opc, SDNode OpNode = X86Shuf128>{
6751 let Predicates = [HasAVX512] in {
6752 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6755 let Predicates = [HasAVX512, HasVLX] in {
6756 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6759 let Predicates = [HasAVX512] in {
6760 def : Pat<(v16f32 (ffloor VR512:$src)),
6761 (VRNDSCALEPSZrri VR512:$src, (i32 0x1))>;
6762 def : Pat<(v16f32 (fnearbyint VR512:$src)),
6763 (VRNDSCALEPSZrri VR512:$src, (i32 0xC))>;
6764 def : Pat<(v16f32 (fceil VR512:$src)),
6765 (VRNDSCALEPSZrri VR512:$src, (i32 0x2))>;
6766 def : Pat<(v16f32 (frint VR512:$src)),
6767 (VRNDSCALEPSZrri VR512:$src, (i32 0x4))>;
6768 def : Pat<(v16f32 (ftrunc VR512:$src)),
6769 (VRNDSCALEPSZrri VR512:$src, (i32 0x3))>;
6771 def : Pat<(v8f64 (ffloor VR512:$src)),
6772 (VRNDSCALEPDZrri VR512:$src, (i32 0x1))>;
6773 def : Pat<(v8f64 (fnearbyint VR512:$src)),
6774 (VRNDSCALEPDZrri VR512:$src, (i32 0xC))>;
6775 def : Pat<(v8f64 (fceil VR512:$src)),
6776 (VRNDSCALEPDZrri VR512:$src, (i32 0x2))>;
6777 def : Pat<(v8f64 (frint VR512:$src)),
6778 (VRNDSCALEPDZrri VR512:$src, (i32 0x4))>;
6779 def : Pat<(v8f64 (ftrunc VR512:$src)),
6780 (VRNDSCALEPDZrri VR512:$src, (i32 0x3))>;
6783 defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
6784 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6785 defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
6786 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6787 defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
6788 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6789 defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
6790 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6792 multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
6793 AVX512VLVectorVTInfo VTInfo_FP>{
6794 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
6795 AVX512AIi8Base, EVEX_4V;
6796 let isCodeGenOnly = 1 in {
6797 defm NAME#_FP: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0x03, X86VAlign>,
6798 AVX512AIi8Base, EVEX_4V;
6802 defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info, avx512vl_f32_info>,
6803 EVEX_CD8<32, CD8VF>;
6804 defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info, avx512vl_f64_info>,
6805 EVEX_CD8<64, CD8VF>, VEX_W;
6807 multiclass avx512_vpalign_lowering<X86VectorVTInfo _ , list<Predicate> p>{
6808 let Predicates = p in
6809 def NAME#_.VTName#rri:
6810 Pat<(_.VT (X86PAlignr _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
6811 (!cast<Instruction>(NAME#_.ZSuffix#rri)
6812 _.RC:$src1, _.RC:$src2, imm:$imm)>;
6815 multiclass avx512_vpalign_lowering_common<AVX512VLVectorVTInfo _>:
6816 avx512_vpalign_lowering<_.info512, [HasBWI]>,
6817 avx512_vpalign_lowering<_.info128, [HasBWI, HasVLX]>,
6818 avx512_vpalign_lowering<_.info256, [HasBWI, HasVLX]>;
6820 defm VPALIGN: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr" ,
6821 avx512vl_i8_info, avx512vl_i8_info>,
6822 avx512_vpalign_lowering_common<avx512vl_i16_info>,
6823 avx512_vpalign_lowering_common<avx512vl_i32_info>,
6824 avx512_vpalign_lowering_common<avx512vl_f32_info>,
6825 avx512_vpalign_lowering_common<avx512vl_i64_info>,
6826 avx512_vpalign_lowering_common<avx512vl_f64_info>,
6829 defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw" ,
6830 avx512vl_i16_info, avx512vl_i8_info>, EVEX_CD8<8, CD8VF>;
6832 multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6833 X86VectorVTInfo _> {
6834 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6835 (ins _.RC:$src1), OpcodeStr##_.Suffix,
6837 (_.VT (OpNode _.RC:$src1))>, EVEX, AVX5128IBase;
6840 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6841 (ins _.MemOp:$src1), OpcodeStr##_.Suffix,
6843 (_.VT (OpNode (bitconvert (_.LdFrag addr:$src1))))>,
6844 EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>;
6847 multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
6848 X86VectorVTInfo _> :
6849 avx512_unary_rm<opc, OpcodeStr, OpNode, _> {
6851 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6852 (ins _.ScalarMemOp:$src1), OpcodeStr##_.Suffix,
6853 "${src1}"##_.BroadcastStr,
6854 "${src1}"##_.BroadcastStr,
6855 (_.VT (OpNode (X86VBroadcast
6856 (_.ScalarLdFrag addr:$src1))))>,
6857 EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
6860 multiclass avx512_unary_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
6861 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6862 let Predicates = [prd] in
6863 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
6865 let Predicates = [prd, HasVLX] in {
6866 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
6868 defm Z128 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info128>,
6873 multiclass avx512_unary_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
6874 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6875 let Predicates = [prd] in
6876 defm Z : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
6879 let Predicates = [prd, HasVLX] in {
6880 defm Z256 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
6882 defm Z128 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
6887 multiclass avx512_unary_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
6888 SDNode OpNode, Predicate prd> {
6889 defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr, OpNode, avx512vl_i64_info,
6891 defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr, OpNode, avx512vl_i32_info, prd>;
6894 multiclass avx512_unary_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
6895 SDNode OpNode, Predicate prd> {
6896 defm W : avx512_unary_rm_vl<opc_w, OpcodeStr, OpNode, avx512vl_i16_info, prd>;
6897 defm B : avx512_unary_rm_vl<opc_b, OpcodeStr, OpNode, avx512vl_i8_info, prd>;
6900 multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
6901 bits<8> opc_d, bits<8> opc_q,
6902 string OpcodeStr, SDNode OpNode> {
6903 defm NAME : avx512_unary_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
6905 avx512_unary_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
6909 defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", X86Abs>;
6912 (bc_v16i32 (v16i1sextv16i32)),
6913 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
6914 (VPABSDZrr VR512:$src)>;
6916 (bc_v8i64 (v8i1sextv8i64)),
6917 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
6918 (VPABSQZrr VR512:$src)>;
6920 multiclass avx512_ctlz<bits<8> opc, string OpcodeStr, Predicate prd>{
6922 defm NAME : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr, ctlz, prd>;
6923 let isCodeGenOnly = 1 in
6924 defm NAME#_UNDEF : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr,
6925 ctlz_zero_undef, prd>;
6928 defm VPLZCNT : avx512_ctlz<0x44, "vplzcnt", HasCDI>;
6929 defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict, HasCDI>;
6931 //===----------------------------------------------------------------------===//
6932 // AVX-512 - Unpack Instructions
6933 //===----------------------------------------------------------------------===//
6934 defm VUNPCKH : avx512_fp_binop_p<0x15, "vunpckh", X86Unpckh>;
6935 defm VUNPCKL : avx512_fp_binop_p<0x14, "vunpckl", X86Unpckl>;
6937 defm VPUNPCKLBW : avx512_binop_rm_vl_b<0x60, "vpunpcklbw", X86Unpckl,
6938 SSE_INTALU_ITINS_P, HasBWI>;
6939 defm VPUNPCKHBW : avx512_binop_rm_vl_b<0x68, "vpunpckhbw", X86Unpckh,
6940 SSE_INTALU_ITINS_P, HasBWI>;
6941 defm VPUNPCKLWD : avx512_binop_rm_vl_w<0x61, "vpunpcklwd", X86Unpckl,
6942 SSE_INTALU_ITINS_P, HasBWI>;
6943 defm VPUNPCKHWD : avx512_binop_rm_vl_w<0x69, "vpunpckhwd", X86Unpckh,
6944 SSE_INTALU_ITINS_P, HasBWI>;
6946 defm VPUNPCKLDQ : avx512_binop_rm_vl_d<0x62, "vpunpckldq", X86Unpckl,
6947 SSE_INTALU_ITINS_P, HasAVX512>;
6948 defm VPUNPCKHDQ : avx512_binop_rm_vl_d<0x6A, "vpunpckhdq", X86Unpckh,
6949 SSE_INTALU_ITINS_P, HasAVX512>;
6950 defm VPUNPCKLQDQ : avx512_binop_rm_vl_q<0x6C, "vpunpcklqdq", X86Unpckl,
6951 SSE_INTALU_ITINS_P, HasAVX512>;
6952 defm VPUNPCKHQDQ : avx512_binop_rm_vl_q<0x6D, "vpunpckhqdq", X86Unpckh,
6953 SSE_INTALU_ITINS_P, HasAVX512>;
6955 //===----------------------------------------------------------------------===//
6956 // AVX-512 - Extract & Insert Integer Instructions
6957 //===----------------------------------------------------------------------===//
6959 multiclass avx512_extract_elt_bw_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
6960 X86VectorVTInfo _> {
6962 def mr : AVX512Ii8<opc, MRMDestMem, (outs),
6963 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
6964 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6965 [(store (_.EltVT (trunc (assertzext (OpNode (_.VT _.RC:$src1),
6968 EVEX, EVEX_CD8<_.EltSize, CD8VT1>;
6971 multiclass avx512_extract_elt_b<string OpcodeStr, X86VectorVTInfo _> {
6972 let Predicates = [HasBWI] in {
6973 def rr : AVX512Ii8<0x14, MRMDestReg, (outs GR32orGR64:$dst),
6974 (ins _.RC:$src1, u8imm:$src2),
6975 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6976 [(set GR32orGR64:$dst,
6977 (X86pextrb (_.VT _.RC:$src1), imm:$src2))]>,
6980 defm NAME : avx512_extract_elt_bw_m<0x14, OpcodeStr, X86pextrb, _>, TAPD;
6984 multiclass avx512_extract_elt_w<string OpcodeStr, X86VectorVTInfo _> {
6985 let Predicates = [HasBWI] in {
6986 def rr : AVX512Ii8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst),
6987 (ins _.RC:$src1, u8imm:$src2),
6988 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6989 [(set GR32orGR64:$dst,
6990 (X86pextrw (_.VT _.RC:$src1), imm:$src2))]>,
6993 defm NAME : avx512_extract_elt_bw_m<0x15, OpcodeStr, X86pextrw, _>, TAPD;
6997 multiclass avx512_extract_elt_dq<string OpcodeStr, X86VectorVTInfo _,
6998 RegisterClass GRC> {
6999 let Predicates = [HasDQI] in {
7000 def rr : AVX512Ii8<0x16, MRMDestReg, (outs GRC:$dst),
7001 (ins _.RC:$src1, u8imm:$src2),
7002 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7004 (extractelt (_.VT _.RC:$src1), imm:$src2))]>,
7008 def mr : AVX512Ii8<0x16, MRMDestMem, (outs),
7009 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7010 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7011 [(store (extractelt (_.VT _.RC:$src1),
7012 imm:$src2),addr:$dst)]>,
7013 EVEX, EVEX_CD8<_.EltSize, CD8VT1>, TAPD;
7017 defm VPEXTRBZ : avx512_extract_elt_b<"vpextrb", v16i8x_info>;
7018 defm VPEXTRWZ : avx512_extract_elt_w<"vpextrw", v8i16x_info>;
7019 defm VPEXTRDZ : avx512_extract_elt_dq<"vpextrd", v4i32x_info, GR32>;
7020 defm VPEXTRQZ : avx512_extract_elt_dq<"vpextrq", v2i64x_info, GR64>, VEX_W;
7022 multiclass avx512_insert_elt_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7023 X86VectorVTInfo _, PatFrag LdFrag> {
7024 def rm : AVX512Ii8<opc, MRMSrcMem, (outs _.RC:$dst),
7025 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
7026 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7028 (_.VT (OpNode _.RC:$src1, (LdFrag addr:$src2), imm:$src3)))]>,
7029 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
7032 multiclass avx512_insert_elt_bw<bits<8> opc, string OpcodeStr, SDNode OpNode,
7033 X86VectorVTInfo _, PatFrag LdFrag> {
7034 let Predicates = [HasBWI] in {
7035 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7036 (ins _.RC:$src1, GR32orGR64:$src2, u8imm:$src3),
7037 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7039 (OpNode _.RC:$src1, GR32orGR64:$src2, imm:$src3))]>, EVEX_4V;
7041 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, OpNode, _, LdFrag>;
7045 multiclass avx512_insert_elt_dq<bits<8> opc, string OpcodeStr,
7046 X86VectorVTInfo _, RegisterClass GRC> {
7047 let Predicates = [HasDQI] in {
7048 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7049 (ins _.RC:$src1, GRC:$src2, u8imm:$src3),
7050 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7052 (_.VT (insertelt _.RC:$src1, GRC:$src2, imm:$src3)))]>,
7055 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, insertelt, _,
7056 _.ScalarLdFrag>, TAPD;
7060 defm VPINSRBZ : avx512_insert_elt_bw<0x20, "vpinsrb", X86pinsrb, v16i8x_info,
7062 defm VPINSRWZ : avx512_insert_elt_bw<0xC4, "vpinsrw", X86pinsrw, v8i16x_info,
7064 defm VPINSRDZ : avx512_insert_elt_dq<0x22, "vpinsrd", v4i32x_info, GR32>;
7065 defm VPINSRQZ : avx512_insert_elt_dq<0x22, "vpinsrq", v2i64x_info, GR64>, VEX_W;
7066 //===----------------------------------------------------------------------===//
7067 // VSHUFPS - VSHUFPD Operations
7068 //===----------------------------------------------------------------------===//
7069 multiclass avx512_shufp<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
7070 AVX512VLVectorVTInfo VTInfo_FP>{
7071 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0xC6, X86Shufp>,
7072 EVEX_CD8<VTInfo_FP.info512.EltSize, CD8VF>,
7073 AVX512AIi8Base, EVEX_4V;
7074 let isCodeGenOnly = 1 in {
7075 defm NAME#_I: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0xC6, X86Shufp>,
7076 EVEX_CD8<VTInfo_I.info512.EltSize, CD8VF>,
7077 AVX512AIi8Base, EVEX_4V;
7081 defm VSHUFPS: avx512_shufp<"vshufps", avx512vl_i32_info, avx512vl_f32_info>, PS;
7082 defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_i64_info, avx512vl_f64_info>, PD, VEX_W;
7083 //===----------------------------------------------------------------------===//
7084 // AVX-512 - Byte shift Left/Right
7085 //===----------------------------------------------------------------------===//
7087 multiclass avx512_shift_packed<bits<8> opc, SDNode OpNode, Format MRMr,
7088 Format MRMm, string OpcodeStr, X86VectorVTInfo _>{
7089 def rr : AVX512<opc, MRMr,
7090 (outs _.RC:$dst), (ins _.RC:$src1, u8imm:$src2),
7091 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7092 [(set _.RC:$dst,(_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>;
7094 def rm : AVX512<opc, MRMm,
7095 (outs _.RC:$dst), (ins _.MemOp:$src1, u8imm:$src2),
7096 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7097 [(set _.RC:$dst,(_.VT (OpNode
7098 (_.LdFrag addr:$src1), (i8 imm:$src2))))]>;
7101 multiclass avx512_shift_packed_all<bits<8> opc, SDNode OpNode, Format MRMr,
7102 Format MRMm, string OpcodeStr, Predicate prd>{
7103 let Predicates = [prd] in
7104 defm Z512 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7105 OpcodeStr, v8i64_info>, EVEX_V512;
7106 let Predicates = [prd, HasVLX] in {
7107 defm Z256 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7108 OpcodeStr, v4i64x_info>, EVEX_V256;
7109 defm Z128 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7110 OpcodeStr, v2i64x_info>, EVEX_V128;
7113 defm VPSLLDQ : avx512_shift_packed_all<0x73, X86vshldq, MRM7r, MRM7m, "vpslldq",
7114 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7115 defm VPSRLDQ : avx512_shift_packed_all<0x73, X86vshrdq, MRM3r, MRM3m, "vpsrldq",
7116 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7119 multiclass avx512_psadbw_packed<bits<8> opc, SDNode OpNode,
7120 string OpcodeStr, X86VectorVTInfo _src>{
7121 def rr : AVX512BI<opc, MRMSrcReg,
7122 (outs _src.RC:$dst), (ins _src.RC:$src1, _src.RC:$src2),
7123 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7124 [(set _src.RC:$dst,(_src.VT
7125 (OpNode _src.RC:$src1, _src.RC:$src2)))]>;
7127 def rm : AVX512BI<opc, MRMSrcMem,
7128 (outs _src.RC:$dst), (ins _src.RC:$src1, _src.MemOp:$src2),
7129 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7130 [(set _src.RC:$dst,(_src.VT
7131 (OpNode _src.RC:$src1,
7132 (_src.VT (bitconvert
7133 (_src.LdFrag addr:$src2))))))]>;
7136 multiclass avx512_psadbw_packed_all<bits<8> opc, SDNode OpNode,
7137 string OpcodeStr, Predicate prd> {
7138 let Predicates = [prd] in
7139 defm Z512 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v64i8_info>,
7141 let Predicates = [prd, HasVLX] in {
7142 defm Z256 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v32i8x_info>,
7144 defm Z128 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v16i8x_info>,
7149 defm VPSADBW : avx512_psadbw_packed_all<0xf6, X86psadbw, "vpsadbw",