1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def i32x_info : X86VectorVTInfo<1, i32, GR32, "si">;
149 def i64x_info : X86VectorVTInfo<1, i64, GR64, "sq">;
150 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
151 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
153 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
154 X86VectorVTInfo i128> {
155 X86VectorVTInfo info512 = i512;
156 X86VectorVTInfo info256 = i256;
157 X86VectorVTInfo info128 = i128;
160 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
162 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
164 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
166 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
168 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
170 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
173 // This multiclass generates the masking variants from the non-masking
174 // variant. It only provides the assembly pieces for the masking variants.
175 // It assumes custom ISel patterns for masking which can be provided as
176 // template arguments.
177 multiclass AVX512_maskable_custom<bits<8> O, Format F,
179 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
181 string AttSrcAsm, string IntelSrcAsm,
183 list<dag> MaskingPattern,
184 list<dag> ZeroMaskingPattern,
185 string MaskingConstraint = "",
186 InstrItinClass itin = NoItinerary,
187 bit IsCommutable = 0> {
188 let isCommutable = IsCommutable in
189 def NAME: AVX512<O, F, Outs, Ins,
190 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
191 "$dst , "#IntelSrcAsm#"}",
194 // Prefer over VMOV*rrk Pat<>
195 let AddedComplexity = 20 in
196 def NAME#k: AVX512<O, F, Outs, MaskingIns,
197 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
198 "$dst {${mask}}, "#IntelSrcAsm#"}",
199 MaskingPattern, itin>,
201 // In case of the 3src subclass this is overridden with a let.
202 string Constraints = MaskingConstraint;
204 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
205 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
206 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
207 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
214 // Common base class of AVX512_maskable and AVX512_maskable_3src.
215 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
217 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
219 string AttSrcAsm, string IntelSrcAsm,
220 dag RHS, dag MaskingRHS,
221 SDNode Select = vselect,
222 string MaskingConstraint = "",
223 InstrItinClass itin = NoItinerary,
224 bit IsCommutable = 0> :
225 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
226 AttSrcAsm, IntelSrcAsm,
227 [(set _.RC:$dst, RHS)],
228 [(set _.RC:$dst, MaskingRHS)],
230 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
231 MaskingConstraint, NoItinerary, IsCommutable>;
233 // This multiclass generates the unconditional/non-masking, the masking and
234 // the zero-masking variant of the vector instruction. In the masking case, the
235 // perserved vector elements come from a new dummy input operand tied to $dst.
236 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
237 dag Outs, dag Ins, string OpcodeStr,
238 string AttSrcAsm, string IntelSrcAsm,
240 InstrItinClass itin = NoItinerary,
241 bit IsCommutable = 0> :
242 AVX512_maskable_common<O, F, _, Outs, Ins,
243 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
244 !con((ins _.KRCWM:$mask), Ins),
245 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
246 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
247 "$src0 = $dst", itin, IsCommutable>;
249 // This multiclass generates the unconditional/non-masking, the masking and
250 // the zero-masking variant of the scalar instruction.
251 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
252 dag Outs, dag Ins, string OpcodeStr,
253 string AttSrcAsm, string IntelSrcAsm,
255 InstrItinClass itin = NoItinerary,
256 bit IsCommutable = 0> :
257 AVX512_maskable_common<O, F, _, Outs, Ins,
258 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
259 !con((ins _.KRCWM:$mask), Ins),
260 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
261 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
262 "$src0 = $dst", itin, IsCommutable>;
264 // Similar to AVX512_maskable but in this case one of the source operands
265 // ($src1) is already tied to $dst so we just use that for the preserved
266 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
268 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
269 dag Outs, dag NonTiedIns, string OpcodeStr,
270 string AttSrcAsm, string IntelSrcAsm,
272 AVX512_maskable_common<O, F, _, Outs,
273 !con((ins _.RC:$src1), NonTiedIns),
274 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
275 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
276 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
277 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
279 multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
280 dag Outs, dag NonTiedIns, string OpcodeStr,
281 string AttSrcAsm, string IntelSrcAsm,
283 AVX512_maskable_common<O, F, _, Outs,
284 !con((ins _.RC:$src1), NonTiedIns),
285 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
286 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
287 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
288 (X86select _.KRCWM:$mask, RHS, _.RC:$src1)>;
290 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
293 string AttSrcAsm, string IntelSrcAsm,
295 AVX512_maskable_custom<O, F, Outs, Ins,
296 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
297 !con((ins _.KRCWM:$mask), Ins),
298 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
302 // Instruction with mask that puts result in mask register,
303 // like "compare" and "vptest"
304 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
306 dag Ins, dag MaskingIns,
308 string AttSrcAsm, string IntelSrcAsm,
310 list<dag> MaskingPattern,
312 InstrItinClass itin = NoItinerary> {
313 def NAME: AVX512<O, F, Outs, Ins,
314 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
315 "$dst "#Round#", "#IntelSrcAsm#"}",
318 def NAME#k: AVX512<O, F, Outs, MaskingIns,
319 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
320 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
321 MaskingPattern, itin>, EVEX_K;
324 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
326 dag Ins, dag MaskingIns,
328 string AttSrcAsm, string IntelSrcAsm,
329 dag RHS, dag MaskingRHS,
331 InstrItinClass itin = NoItinerary> :
332 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
333 AttSrcAsm, IntelSrcAsm,
334 [(set _.KRC:$dst, RHS)],
335 [(set _.KRC:$dst, MaskingRHS)],
338 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
339 dag Outs, dag Ins, string OpcodeStr,
340 string AttSrcAsm, string IntelSrcAsm,
341 dag RHS, string Round = "",
342 InstrItinClass itin = NoItinerary> :
343 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
344 !con((ins _.KRCWM:$mask), Ins),
345 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
346 (and _.KRCWM:$mask, RHS),
349 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
350 dag Outs, dag Ins, string OpcodeStr,
351 string AttSrcAsm, string IntelSrcAsm> :
352 AVX512_maskable_custom_cmp<O, F, Outs,
353 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
354 AttSrcAsm, IntelSrcAsm,
355 [],[],"", NoItinerary>;
357 // Bitcasts between 512-bit vector types. Return the original type since
358 // no instruction is needed for the conversion
359 let Predicates = [HasAVX512] in {
360 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
361 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
362 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
363 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
364 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
365 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
366 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
367 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
368 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
369 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
370 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
371 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
372 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
373 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
374 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
375 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
376 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
377 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
378 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
379 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
380 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
381 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
382 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
383 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
384 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
385 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
386 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
387 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
388 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
389 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
390 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
392 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
393 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
394 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
395 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
396 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
397 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
398 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
399 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
400 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
401 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
402 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
403 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
404 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
405 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
406 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
407 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
408 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
409 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
410 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
411 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
412 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
413 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
414 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
415 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
416 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
417 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
418 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
419 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
420 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
421 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
423 // Bitcasts between 256-bit vector types. Return the original type since
424 // no instruction is needed for the conversion
425 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
426 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
427 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
428 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
429 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
430 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
431 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
432 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
433 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
434 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
435 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
436 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
437 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
438 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
439 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
440 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
441 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
442 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
443 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
444 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
445 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
446 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
447 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
448 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
449 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
450 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
451 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
452 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
453 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
454 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
458 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
461 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
462 isPseudo = 1, Predicates = [HasAVX512] in {
463 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
464 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
467 let Predicates = [HasAVX512] in {
468 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
469 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
470 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
473 //===----------------------------------------------------------------------===//
474 // AVX-512 - VECTOR INSERT
476 multiclass vinsert_for_size<int Opcode, X86VectorVTInfo From, X86VectorVTInfo To,
477 PatFrag vinsert_insert> {
478 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
479 defm rr : AVX512_maskable<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
480 (ins To.RC:$src1, From.RC:$src2, i32u8imm:$src3),
481 "vinsert" # From.EltTypeName # "x" # From.NumElts,
482 "$src3, $src2, $src1", "$src1, $src2, $src3",
483 (vinsert_insert:$src3 (To.VT To.RC:$src1),
484 (From.VT From.RC:$src2),
485 (iPTR imm))>, AVX512AIi8Base, EVEX_4V;
488 defm rm : AVX512_maskable<Opcode, MRMSrcMem, To, (outs To.RC:$dst),
489 (ins To.RC:$src1, From.MemOp:$src2, i32u8imm:$src3),
490 "vinsert" # From.EltTypeName # "x" # From.NumElts,
491 "$src3, $src2, $src1", "$src1, $src2, $src3",
492 (vinsert_insert:$src3 (To.VT To.RC:$src1),
493 (From.VT (bitconvert (From.LdFrag addr:$src2))),
494 (iPTR imm))>, AVX512AIi8Base, EVEX_4V,
495 EVEX_CD8<From.EltSize, From.CD8TupleForm>;
499 multiclass vinsert_for_size_lowering<string InstrStr, X86VectorVTInfo From,
500 X86VectorVTInfo To, PatFrag vinsert_insert,
501 SDNodeXForm INSERT_get_vinsert_imm , list<Predicate> p> {
502 let Predicates = p in {
503 def : Pat<(vinsert_insert:$ins
504 (To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
505 (To.VT (!cast<Instruction>(InstrStr#"rr")
506 To.RC:$src1, From.RC:$src2,
507 (INSERT_get_vinsert_imm To.RC:$ins)))>;
509 def : Pat<(vinsert_insert:$ins
511 (From.VT (bitconvert (From.LdFrag addr:$src2))),
513 (To.VT (!cast<Instruction>(InstrStr#"rm")
514 To.RC:$src1, addr:$src2,
515 (INSERT_get_vinsert_imm To.RC:$ins)))>;
519 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
520 ValueType EltVT64, int Opcode256> {
522 let Predicates = [HasVLX] in
523 defm NAME # "32x4Z256" : vinsert_for_size<Opcode128,
524 X86VectorVTInfo< 4, EltVT32, VR128X>,
525 X86VectorVTInfo< 8, EltVT32, VR256X>,
526 vinsert128_insert>, EVEX_V256;
528 defm NAME # "32x4Z" : vinsert_for_size<Opcode128,
529 X86VectorVTInfo< 4, EltVT32, VR128X>,
530 X86VectorVTInfo<16, EltVT32, VR512>,
531 vinsert128_insert>, EVEX_V512;
533 defm NAME # "64x4Z" : vinsert_for_size<Opcode256,
534 X86VectorVTInfo< 4, EltVT64, VR256X>,
535 X86VectorVTInfo< 8, EltVT64, VR512>,
536 vinsert256_insert>, VEX_W, EVEX_V512;
538 let Predicates = [HasVLX, HasDQI] in
539 defm NAME # "64x2Z256" : vinsert_for_size<Opcode128,
540 X86VectorVTInfo< 2, EltVT64, VR128X>,
541 X86VectorVTInfo< 4, EltVT64, VR256X>,
542 vinsert128_insert>, VEX_W, EVEX_V256;
544 let Predicates = [HasDQI] in {
545 defm NAME # "64x2Z" : vinsert_for_size<Opcode128,
546 X86VectorVTInfo< 2, EltVT64, VR128X>,
547 X86VectorVTInfo< 8, EltVT64, VR512>,
548 vinsert128_insert>, VEX_W, EVEX_V512;
550 defm NAME # "32x8Z" : vinsert_for_size<Opcode256,
551 X86VectorVTInfo< 8, EltVT32, VR256X>,
552 X86VectorVTInfo<16, EltVT32, VR512>,
553 vinsert256_insert>, EVEX_V512;
557 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
558 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
560 // Codegen pattern with the alternative types,
561 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
562 defm : vinsert_for_size_lowering<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info,
563 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
564 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info,
565 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
567 defm : vinsert_for_size_lowering<"VINSERTF32x4Z", v2f64x_info, v8f64_info,
568 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
569 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v2i64x_info, v8i64_info,
570 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
572 defm : vinsert_for_size_lowering<"VINSERTF64x4Z", v8f32x_info, v16f32_info,
573 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
574 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v8i32x_info, v16i32_info,
575 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
577 // Codegen pattern with the alternative types insert VEC128 into VEC256
578 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info,
579 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
580 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info,
581 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
582 // Codegen pattern with the alternative types insert VEC128 into VEC512
583 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v8i16x_info, v32i16_info,
584 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
585 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v16i8x_info, v64i8_info,
586 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
587 // Codegen pattern with the alternative types insert VEC256 into VEC512
588 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v16i16x_info, v32i16_info,
589 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
590 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v32i8x_info, v64i8_info,
591 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
593 // vinsertps - insert f32 to XMM
594 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
595 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
596 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
597 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
599 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
600 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
601 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
602 [(set VR128X:$dst, (X86insertps VR128X:$src1,
603 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
604 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
606 //===----------------------------------------------------------------------===//
607 // AVX-512 VECTOR EXTRACT
610 multiclass vextract_for_size_first_position_lowering<X86VectorVTInfo From,
611 X86VectorVTInfo To> {
612 // A subvector extract from the first vector position is
613 // a subregister copy that needs no instruction.
614 def NAME # To.NumElts:
615 Pat<(To.VT (extract_subvector (From.VT From.RC:$src),(iPTR 0))),
616 (To.VT (EXTRACT_SUBREG (From.VT From.RC:$src), To.SubRegIdx))>;
619 multiclass vextract_for_size<int Opcode,
620 X86VectorVTInfo From, X86VectorVTInfo To,
621 PatFrag vextract_extract> :
622 vextract_for_size_first_position_lowering<From, To> {
624 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
625 // use AVX512_maskable_in_asm (AVX512_maskable can't be used due to
626 // vextract_extract), we interesting only in patterns without mask,
627 // intrinsics pattern match generated bellow.
628 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
629 (ins From.RC:$src1, i32u8imm:$idx),
630 "vextract" # To.EltTypeName # "x" # To.NumElts,
631 "$idx, $src1", "$src1, $idx",
632 [(set To.RC:$dst, (vextract_extract:$idx (From.VT From.RC:$src1),
634 AVX512AIi8Base, EVEX;
635 let mayStore = 1 in {
636 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
637 (ins To.MemOp:$dst, From.RC:$src1, i32u8imm:$src2),
638 "vextract" # To.EltTypeName # "x" # To.NumElts #
639 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
642 def rmk : AVX512AIi8<Opcode, MRMDestMem, (outs),
643 (ins To.MemOp:$dst, To.KRCWM:$mask,
644 From.RC:$src1, i32u8imm:$src2),
645 "vextract" # To.EltTypeName # "x" # To.NumElts #
646 "\t{$src2, $src1, $dst {${mask}}|"
647 "$dst {${mask}}, $src1, $src2}",
652 // Intrinsic call with masking.
653 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
654 "x" # To.NumElts # "_" # From.Size)
655 From.RC:$src1, (iPTR imm:$idx), To.RC:$src0, To.MRC:$mask),
656 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
657 From.ZSuffix # "rrk")
659 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
660 From.RC:$src1, imm:$idx)>;
662 // Intrinsic call with zero-masking.
663 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
664 "x" # To.NumElts # "_" # From.Size)
665 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, To.MRC:$mask),
666 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
667 From.ZSuffix # "rrkz")
668 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
669 From.RC:$src1, imm:$idx)>;
671 // Intrinsic call without masking.
672 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
673 "x" # To.NumElts # "_" # From.Size)
674 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
675 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
677 From.RC:$src1, imm:$idx)>;
680 // Codegen pattern for the alternative types
681 multiclass vextract_for_size_lowering<string InstrStr, X86VectorVTInfo From,
682 X86VectorVTInfo To, PatFrag vextract_extract,
683 SDNodeXForm EXTRACT_get_vextract_imm, list<Predicate> p> :
684 vextract_for_size_first_position_lowering<From, To> {
686 let Predicates = p in
687 def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)),
688 (To.VT (!cast<Instruction>(InstrStr#"rr")
690 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
693 multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
694 ValueType EltVT64, int Opcode256> {
695 defm NAME # "32x4Z" : vextract_for_size<Opcode128,
696 X86VectorVTInfo<16, EltVT32, VR512>,
697 X86VectorVTInfo< 4, EltVT32, VR128X>,
698 vextract128_extract>,
699 EVEX_V512, EVEX_CD8<32, CD8VT4>;
700 defm NAME # "64x4Z" : vextract_for_size<Opcode256,
701 X86VectorVTInfo< 8, EltVT64, VR512>,
702 X86VectorVTInfo< 4, EltVT64, VR256X>,
703 vextract256_extract>,
704 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>;
705 let Predicates = [HasVLX] in
706 defm NAME # "32x4Z256" : vextract_for_size<Opcode128,
707 X86VectorVTInfo< 8, EltVT32, VR256X>,
708 X86VectorVTInfo< 4, EltVT32, VR128X>,
709 vextract128_extract>,
710 EVEX_V256, EVEX_CD8<32, CD8VT4>;
711 let Predicates = [HasVLX, HasDQI] in
712 defm NAME # "64x2Z256" : vextract_for_size<Opcode128,
713 X86VectorVTInfo< 4, EltVT64, VR256X>,
714 X86VectorVTInfo< 2, EltVT64, VR128X>,
715 vextract128_extract>,
716 VEX_W, EVEX_V256, EVEX_CD8<64, CD8VT2>;
717 let Predicates = [HasDQI] in {
718 defm NAME # "64x2Z" : vextract_for_size<Opcode128,
719 X86VectorVTInfo< 8, EltVT64, VR512>,
720 X86VectorVTInfo< 2, EltVT64, VR128X>,
721 vextract128_extract>,
722 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>;
723 defm NAME # "32x8Z" : vextract_for_size<Opcode256,
724 X86VectorVTInfo<16, EltVT32, VR512>,
725 X86VectorVTInfo< 8, EltVT32, VR256X>,
726 vextract256_extract>,
727 EVEX_V512, EVEX_CD8<32, CD8VT8>;
731 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
732 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
734 // extract_subvector codegen patterns with the alternative types.
735 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
736 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z", v8f64_info, v2f64x_info,
737 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
738 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v8i64_info, v2i64x_info,
739 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
741 defm : vextract_for_size_lowering<"VEXTRACTF64x4Z", v16f32_info, v8f32x_info,
742 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
743 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v16i32_info, v8i32x_info,
744 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
746 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z256", v4f64x_info, v2f64x_info,
747 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
748 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v4i64x_info, v2i64x_info,
749 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
751 // Codegen pattern with the alternative types extract VEC128 from VEC512
752 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v32i16_info, v8i16x_info,
753 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
754 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v64i8_info, v16i8x_info,
755 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
756 // Codegen pattern with the alternative types extract VEC256 from VEC512
757 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v32i16_info, v16i16x_info,
758 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
759 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v64i8_info, v32i8x_info,
760 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
762 // A 128-bit subvector insert to the first 512-bit vector position
763 // is a subregister copy that needs no instruction.
764 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
765 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
766 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
768 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
769 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
770 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
772 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
773 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
774 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
776 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
777 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
778 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
781 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
782 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
783 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
784 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
785 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
786 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
787 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
788 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
789 def : Pat<(insert_subvector undef, (v16i16 VR256X:$src), (iPTR 0)),
790 (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
791 def : Pat<(insert_subvector undef, (v32i8 VR256X:$src), (iPTR 0)),
792 (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
794 // vextractps - extract 32 bits from XMM
795 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
796 (ins VR128X:$src1, u8imm:$src2),
797 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
798 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
801 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
802 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
803 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
804 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
805 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
807 //===---------------------------------------------------------------------===//
811 multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr,
812 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo> {
814 defm r : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
815 (ins SrcInfo.RC:$src), OpcodeStr, "$src", "$src",
816 (DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src)))>,
819 defm m : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
820 (ins SrcInfo.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
821 (DestInfo.VT (X86VBroadcast
822 (SrcInfo.ScalarLdFrag addr:$src)))>,
823 T8PD, EVEX, EVEX_CD8<SrcInfo.EltSize, CD8VT1>;
826 multiclass avx512_fp_broadcast_vl<bits<8> opc, string OpcodeStr,
827 AVX512VLVectorVTInfo _> {
828 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
831 let Predicates = [HasVLX] in {
832 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
837 let ExeDomain = SSEPackedSingle in {
838 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, "vbroadcastss",
840 let Predicates = [HasVLX] in {
841 defm VBROADCASTSSZ128 : avx512_broadcast_rm<0x18, "vbroadcastss",
842 v4f32x_info, v4f32x_info>, EVEX_V128;
846 let ExeDomain = SSEPackedDouble in {
847 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, "vbroadcastsd",
848 avx512vl_f64_info>, VEX_W;
851 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
852 // Later, we can canonize broadcast instructions before ISel phase and
853 // eliminate additional patterns on ISel.
854 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
855 // representations of source
856 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
857 X86VectorVTInfo _, RegisterClass SrcRC_v,
858 RegisterClass SrcRC_s> {
859 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
860 (!cast<Instruction>(InstName##"r")
861 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
863 let AddedComplexity = 30 in {
864 def : Pat<(_.VT (vselect _.KRCWM:$mask,
865 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
866 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
867 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
869 def : Pat<(_.VT(vselect _.KRCWM:$mask,
870 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
871 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
872 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
876 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
878 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
881 let Predicates = [HasVLX] in {
882 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
883 v8f32x_info, VR128X, FR32X>;
884 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
885 v4f32x_info, VR128X, FR32X>;
886 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
887 v4f64x_info, VR128X, FR64X>;
890 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
891 (VBROADCASTSSZm addr:$src)>;
892 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
893 (VBROADCASTSDZm addr:$src)>;
895 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
896 (VBROADCASTSSZm addr:$src)>;
897 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
898 (VBROADCASTSDZm addr:$src)>;
900 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
901 RegisterClass SrcRC> {
902 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
903 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
904 "$src", "$src", []>, T8PD, EVEX;
907 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
908 RegisterClass SrcRC, Predicate prd> {
909 let Predicates = [prd] in
910 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
911 let Predicates = [prd, HasVLX] in {
912 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
913 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
917 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
919 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
921 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
923 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
926 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
927 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
929 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
930 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
932 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
933 (VPBROADCASTDrZr GR32:$src)>;
934 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
935 (VPBROADCASTQrZr GR64:$src)>;
937 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
938 (VPBROADCASTDrZr GR32:$src)>;
939 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
940 (VPBROADCASTQrZr GR64:$src)>;
942 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
943 (v16i32 immAllZerosV), (i16 GR16:$mask))),
944 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
945 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
946 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
947 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
949 // Provide aliases for broadcast from the same register class that
950 // automatically does the extract.
951 multiclass avx512_int_broadcast_rm_lowering<X86VectorVTInfo DestInfo,
952 X86VectorVTInfo SrcInfo> {
953 def : Pat<(DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src))),
954 (!cast<Instruction>(NAME#DestInfo.ZSuffix#"r")
955 (EXTRACT_SUBREG (SrcInfo.VT SrcInfo.RC:$src), sub_xmm))>;
958 multiclass avx512_int_broadcast_rm_vl<bits<8> opc, string OpcodeStr,
959 AVX512VLVectorVTInfo _, Predicate prd> {
960 let Predicates = [prd] in {
961 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
962 avx512_int_broadcast_rm_lowering<_.info512, _.info256>,
964 // Defined separately to avoid redefinition.
965 defm Z_Alt : avx512_int_broadcast_rm_lowering<_.info512, _.info512>;
967 let Predicates = [prd, HasVLX] in {
968 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
969 avx512_int_broadcast_rm_lowering<_.info256, _.info256>,
971 defm Z128 : avx512_broadcast_rm<opc, OpcodeStr, _.info128, _.info128>,
976 defm VPBROADCASTB : avx512_int_broadcast_rm_vl<0x78, "vpbroadcastb",
977 avx512vl_i8_info, HasBWI>;
978 defm VPBROADCASTW : avx512_int_broadcast_rm_vl<0x79, "vpbroadcastw",
979 avx512vl_i16_info, HasBWI>;
980 defm VPBROADCASTD : avx512_int_broadcast_rm_vl<0x58, "vpbroadcastd",
981 avx512vl_i32_info, HasAVX512>;
982 defm VPBROADCASTQ : avx512_int_broadcast_rm_vl<0x59, "vpbroadcastq",
983 avx512vl_i64_info, HasAVX512>, VEX_W;
985 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
986 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
988 def rm : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Src.MemOp:$src),
989 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
991 (_Dst.VT (X86SubVBroadcast
992 (_Src.VT (bitconvert (_Src.LdFrag addr:$src))))))]>, EVEX;
993 def rmk : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
995 !strconcat(OpcodeStr,
996 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
998 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
1000 !strconcat(OpcodeStr,
1001 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1006 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1007 v16i32_info, v4i32x_info>,
1008 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1009 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1010 v16f32_info, v4f32x_info>,
1011 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1012 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
1013 v8i64_info, v4i64x_info>, VEX_W,
1014 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1015 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
1016 v8f64_info, v4f64x_info>, VEX_W,
1017 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1019 let Predicates = [HasVLX] in {
1020 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1021 v8i32x_info, v4i32x_info>,
1022 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1023 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1024 v8f32x_info, v4f32x_info>,
1025 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1027 let Predicates = [HasVLX, HasDQI] in {
1028 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1029 v4i64x_info, v2i64x_info>, VEX_W,
1030 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1031 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1032 v4f64x_info, v2f64x_info>, VEX_W,
1033 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1035 let Predicates = [HasDQI] in {
1036 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1037 v8i64_info, v2i64x_info>, VEX_W,
1038 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1039 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
1040 v16i32_info, v8i32x_info>,
1041 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1042 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1043 v8f64_info, v2f64x_info>, VEX_W,
1044 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1045 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
1046 v16f32_info, v8f32x_info>,
1047 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1050 multiclass avx512_broadcast_32x2<bits<8> opc, string OpcodeStr,
1051 X86VectorVTInfo _Dst, X86VectorVTInfo _Src,
1052 SDNode OpNode = X86SubVBroadcast> {
1054 defm r : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
1055 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
1056 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src)))>,
1059 defm m : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
1060 (ins _Src.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
1062 (_Src.VT (scalar_to_vector(loadi64 addr:$src)))))>,
1063 T8PD, EVEX, EVEX_CD8<_Src.EltSize, CD8VT2>;
1066 multiclass avx512_common_broadcast_32x2<bits<8> opc, string OpcodeStr,
1067 AVX512VLVectorVTInfo _> {
1068 let Predicates = [HasDQI] in
1069 defm Z : avx512_broadcast_32x2<opc, OpcodeStr, _.info512, _.info128>,
1071 let Predicates = [HasDQI, HasVLX] in
1072 defm Z256 : avx512_broadcast_32x2<opc, OpcodeStr, _.info256, _.info128>,
1076 multiclass avx512_common_broadcast_i32x2<bits<8> opc, string OpcodeStr,
1077 AVX512VLVectorVTInfo _> :
1078 avx512_common_broadcast_32x2<opc, OpcodeStr, _> {
1080 let Predicates = [HasDQI, HasVLX] in
1081 defm Z128 : avx512_broadcast_32x2<opc, OpcodeStr, _.info128, _.info128,
1082 X86SubV32x2Broadcast>, EVEX_V128;
1085 defm VPBROADCASTI32X2 : avx512_common_broadcast_i32x2<0x59, "vbroadcasti32x2",
1087 defm VPBROADCASTF32X2 : avx512_common_broadcast_32x2<0x19, "vbroadcastf32x2",
1090 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
1091 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
1092 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
1093 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
1095 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
1096 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
1097 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
1098 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
1100 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
1101 (VBROADCASTSSZr VR128X:$src)>;
1102 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
1103 (VBROADCASTSDZr VR128X:$src)>;
1105 // Provide fallback in case the load node that is used in the patterns above
1106 // is used by additional users, which prevents the pattern selection.
1107 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
1108 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
1109 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
1110 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
1113 //===----------------------------------------------------------------------===//
1114 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
1116 multiclass avx512_mask_broadcastm<bits<8> opc, string OpcodeStr,
1117 X86VectorVTInfo _, RegisterClass KRC> {
1118 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.RC:$dst), (ins KRC:$src),
1119 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1120 [(set _.RC:$dst, (_.VT (X86VBroadcastm KRC:$src)))]>, EVEX;
1123 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
1124 AVX512VLVectorVTInfo VTInfo, RegisterClass KRC> {
1125 let Predicates = [HasCDI] in
1126 defm Z : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info512, KRC>, EVEX_V512;
1127 let Predicates = [HasCDI, HasVLX] in {
1128 defm Z256 : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info256, KRC>, EVEX_V256;
1129 defm Z128 : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info128, KRC>, EVEX_V128;
1133 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
1134 avx512vl_i32_info, VK16>;
1135 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1136 avx512vl_i64_info, VK8>, VEX_W;
1138 //===----------------------------------------------------------------------===//
1139 // -- VPERM2I - 3 source operands form --
1140 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr,
1141 SDNode OpNode, X86VectorVTInfo _> {
1142 let Constraints = "$src1 = $dst" in {
1143 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1144 (ins _.RC:$src2, _.RC:$src3),
1145 OpcodeStr, "$src3, $src2", "$src2, $src3",
1146 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>, EVEX_4V,
1150 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1151 (ins _.RC:$src2, _.MemOp:$src3),
1152 OpcodeStr, "$src3, $src2", "$src2, $src3",
1153 (_.VT (OpNode _.RC:$src1, _.RC:$src2,
1154 (_.VT (bitconvert (_.LdFrag addr:$src3)))))>,
1155 EVEX_4V, AVX5128IBase;
1158 multiclass avx512_perm_3src_mb<bits<8> opc, string OpcodeStr,
1159 SDNode OpNode, X86VectorVTInfo _> {
1160 let mayLoad = 1, Constraints = "$src1 = $dst" in
1161 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1162 (ins _.RC:$src2, _.ScalarMemOp:$src3),
1163 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1164 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1165 (_.VT (OpNode _.RC:$src1,
1166 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1167 AVX5128IBase, EVEX_4V, EVEX_B;
1170 multiclass avx512_perm_3src_sizes<bits<8> opc, string OpcodeStr,
1171 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1172 let Predicates = [HasAVX512] in
1173 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1174 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
1175 let Predicates = [HasVLX] in {
1176 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1177 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1179 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1180 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1184 multiclass avx512_perm_3src_sizes_w<bits<8> opc, string OpcodeStr,
1185 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1186 let Predicates = [HasBWI] in
1187 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1188 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1190 let Predicates = [HasBWI, HasVLX] in {
1191 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1192 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1194 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1195 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1199 defm VPERMI2D : avx512_perm_3src_sizes<0x76, "vpermi2d", X86VPermiv3,
1200 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1201 defm VPERMI2Q : avx512_perm_3src_sizes<0x76, "vpermi2q", X86VPermiv3,
1202 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1203 defm VPERMI2PS : avx512_perm_3src_sizes<0x77, "vpermi2ps", X86VPermiv3,
1204 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1205 defm VPERMI2PD : avx512_perm_3src_sizes<0x77, "vpermi2pd", X86VPermiv3,
1206 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1208 defm VPERMT2D : avx512_perm_3src_sizes<0x7E, "vpermt2d", X86VPermv3,
1209 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1210 defm VPERMT2Q : avx512_perm_3src_sizes<0x7E, "vpermt2q", X86VPermv3,
1211 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1212 defm VPERMT2PS : avx512_perm_3src_sizes<0x7F, "vpermt2ps", X86VPermv3,
1213 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1214 defm VPERMT2PD : avx512_perm_3src_sizes<0x7F, "vpermt2pd", X86VPermv3,
1215 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1217 defm VPERMT2W : avx512_perm_3src_sizes_w<0x7D, "vpermt2w", X86VPermv3,
1218 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1219 defm VPERMI2W : avx512_perm_3src_sizes_w<0x75, "vpermi2w", X86VPermiv3,
1220 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1222 //===----------------------------------------------------------------------===//
1223 // AVX-512 - BLEND using mask
1225 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1226 let ExeDomain = _.ExeDomain in {
1227 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1228 (ins _.RC:$src1, _.RC:$src2),
1229 !strconcat(OpcodeStr,
1230 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1232 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1233 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1234 !strconcat(OpcodeStr,
1235 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1236 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1237 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1238 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1239 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1240 !strconcat(OpcodeStr,
1241 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1242 []>, EVEX_4V, EVEX_KZ;
1243 let mayLoad = 1 in {
1244 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1245 (ins _.RC:$src1, _.MemOp:$src2),
1246 !strconcat(OpcodeStr,
1247 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1248 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1249 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1250 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1251 !strconcat(OpcodeStr,
1252 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1253 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1254 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1255 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1256 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1257 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1258 !strconcat(OpcodeStr,
1259 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1260 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1264 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1266 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1267 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1268 !strconcat(OpcodeStr,
1269 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1270 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1271 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1272 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1273 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1275 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1276 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1277 !strconcat(OpcodeStr,
1278 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1279 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1280 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1284 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1285 AVX512VLVectorVTInfo VTInfo> {
1286 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1287 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1289 let Predicates = [HasVLX] in {
1290 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1291 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1292 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1293 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1297 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1298 AVX512VLVectorVTInfo VTInfo> {
1299 let Predicates = [HasBWI] in
1300 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1302 let Predicates = [HasBWI, HasVLX] in {
1303 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1304 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1309 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1310 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1311 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1312 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1313 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1314 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1317 let Predicates = [HasAVX512] in {
1318 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1319 (v8f32 VR256X:$src2))),
1321 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1322 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1323 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1325 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1326 (v8i32 VR256X:$src2))),
1328 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1329 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1330 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1332 //===----------------------------------------------------------------------===//
1333 // Compare Instructions
1334 //===----------------------------------------------------------------------===//
1336 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1338 multiclass avx512_cmp_scalar<X86VectorVTInfo _, SDNode OpNode, SDNode OpNodeRnd>{
1340 defm rr_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1342 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1343 "vcmp${cc}"#_.Suffix,
1344 "$src2, $src1", "$src1, $src2",
1345 (OpNode (_.VT _.RC:$src1),
1349 defm rm_Int : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1351 (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1352 "vcmp${cc}"#_.Suffix,
1353 "$src2, $src1", "$src1, $src2",
1354 (OpNode (_.VT _.RC:$src1),
1355 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
1356 imm:$cc)>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1358 defm rrb_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1360 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1361 "vcmp${cc}"#_.Suffix,
1362 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1363 (OpNodeRnd (_.VT _.RC:$src1),
1366 (i32 FROUND_NO_EXC))>, EVEX_4V, EVEX_B;
1367 // Accept explicit immediate argument form instead of comparison code.
1368 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1369 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1371 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1373 "$cc, $src2, $src1", "$src1, $src2, $cc">, EVEX_4V;
1374 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1376 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1378 "$cc, $src2, $src1", "$src1, $src2, $cc">,
1379 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1381 defm rrb_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1383 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1385 "$cc,{sae}, $src2, $src1","$src1, $src2,{sae}, $cc">,
1387 }// let isAsmParserOnly = 1, hasSideEffects = 0
1389 let isCodeGenOnly = 1 in {
1390 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1391 (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, AVXCC:$cc),
1392 !strconcat("vcmp${cc}", _.Suffix,
1393 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1394 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1397 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1399 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1401 (ins _.FRC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1402 !strconcat("vcmp${cc}", _.Suffix,
1403 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1404 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1405 (_.ScalarLdFrag addr:$src2),
1407 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1411 let Predicates = [HasAVX512] in {
1412 defm VCMPSSZ : avx512_cmp_scalar<f32x_info, X86cmpms, X86cmpmsRnd>,
1414 defm VCMPSDZ : avx512_cmp_scalar<f64x_info, X86cmpms, X86cmpmsRnd>,
1415 AVX512XDIi8Base, VEX_W;
1418 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1419 X86VectorVTInfo _> {
1420 def rr : AVX512BI<opc, MRMSrcReg,
1421 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1422 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1423 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1424 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1426 def rm : AVX512BI<opc, MRMSrcMem,
1427 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1428 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1429 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1430 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1431 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1432 def rrk : AVX512BI<opc, MRMSrcReg,
1433 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1434 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1435 "$dst {${mask}}, $src1, $src2}"),
1436 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1437 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1438 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1440 def rmk : AVX512BI<opc, MRMSrcMem,
1441 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1442 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1443 "$dst {${mask}}, $src1, $src2}"),
1444 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1445 (OpNode (_.VT _.RC:$src1),
1447 (_.LdFrag addr:$src2))))))],
1448 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1451 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1452 X86VectorVTInfo _> :
1453 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1454 let mayLoad = 1 in {
1455 def rmb : AVX512BI<opc, MRMSrcMem,
1456 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1457 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1458 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1459 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1460 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1461 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1462 def rmbk : AVX512BI<opc, MRMSrcMem,
1463 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1464 _.ScalarMemOp:$src2),
1465 !strconcat(OpcodeStr,
1466 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1467 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1468 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1469 (OpNode (_.VT _.RC:$src1),
1471 (_.ScalarLdFrag addr:$src2)))))],
1472 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1476 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1477 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1478 let Predicates = [prd] in
1479 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1482 let Predicates = [prd, HasVLX] in {
1483 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1485 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1490 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1491 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1493 let Predicates = [prd] in
1494 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1497 let Predicates = [prd, HasVLX] in {
1498 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1500 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1505 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1506 avx512vl_i8_info, HasBWI>,
1509 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1510 avx512vl_i16_info, HasBWI>,
1511 EVEX_CD8<16, CD8VF>;
1513 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1514 avx512vl_i32_info, HasAVX512>,
1515 EVEX_CD8<32, CD8VF>;
1517 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1518 avx512vl_i64_info, HasAVX512>,
1519 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1521 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1522 avx512vl_i8_info, HasBWI>,
1525 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1526 avx512vl_i16_info, HasBWI>,
1527 EVEX_CD8<16, CD8VF>;
1529 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1530 avx512vl_i32_info, HasAVX512>,
1531 EVEX_CD8<32, CD8VF>;
1533 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1534 avx512vl_i64_info, HasAVX512>,
1535 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1537 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1538 (COPY_TO_REGCLASS (VPCMPGTDZrr
1539 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1540 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1542 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1543 (COPY_TO_REGCLASS (VPCMPEQDZrr
1544 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1545 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1547 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1548 X86VectorVTInfo _> {
1549 def rri : AVX512AIi8<opc, MRMSrcReg,
1550 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1551 !strconcat("vpcmp${cc}", Suffix,
1552 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1553 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1555 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1557 def rmi : AVX512AIi8<opc, MRMSrcMem,
1558 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1559 !strconcat("vpcmp${cc}", Suffix,
1560 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1561 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1562 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1564 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1565 def rrik : AVX512AIi8<opc, MRMSrcReg,
1566 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1568 !strconcat("vpcmp${cc}", Suffix,
1569 "\t{$src2, $src1, $dst {${mask}}|",
1570 "$dst {${mask}}, $src1, $src2}"),
1571 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1572 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1574 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1576 def rmik : AVX512AIi8<opc, MRMSrcMem,
1577 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1579 !strconcat("vpcmp${cc}", Suffix,
1580 "\t{$src2, $src1, $dst {${mask}}|",
1581 "$dst {${mask}}, $src1, $src2}"),
1582 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1583 (OpNode (_.VT _.RC:$src1),
1584 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1586 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1588 // Accept explicit immediate argument form instead of comparison code.
1589 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1590 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1591 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1592 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1593 "$dst, $src1, $src2, $cc}"),
1594 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1596 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1597 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1598 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1599 "$dst, $src1, $src2, $cc}"),
1600 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1601 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1602 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1604 !strconcat("vpcmp", Suffix,
1605 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1606 "$dst {${mask}}, $src1, $src2, $cc}"),
1607 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1609 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1610 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1612 !strconcat("vpcmp", Suffix,
1613 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1614 "$dst {${mask}}, $src1, $src2, $cc}"),
1615 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1619 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1620 X86VectorVTInfo _> :
1621 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1622 def rmib : AVX512AIi8<opc, MRMSrcMem,
1623 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1625 !strconcat("vpcmp${cc}", Suffix,
1626 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1627 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1628 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1629 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1631 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1632 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1633 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1634 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1635 !strconcat("vpcmp${cc}", Suffix,
1636 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1637 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1638 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1639 (OpNode (_.VT _.RC:$src1),
1640 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1642 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1644 // Accept explicit immediate argument form instead of comparison code.
1645 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1646 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1647 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1649 !strconcat("vpcmp", Suffix,
1650 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1651 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1652 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1653 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1654 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1655 _.ScalarMemOp:$src2, u8imm:$cc),
1656 !strconcat("vpcmp", Suffix,
1657 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1658 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1659 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1663 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1664 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1665 let Predicates = [prd] in
1666 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1668 let Predicates = [prd, HasVLX] in {
1669 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1670 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1674 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1675 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1676 let Predicates = [prd] in
1677 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1680 let Predicates = [prd, HasVLX] in {
1681 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1683 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1688 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1689 HasBWI>, EVEX_CD8<8, CD8VF>;
1690 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1691 HasBWI>, EVEX_CD8<8, CD8VF>;
1693 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1694 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1695 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1696 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1698 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1699 HasAVX512>, EVEX_CD8<32, CD8VF>;
1700 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1701 HasAVX512>, EVEX_CD8<32, CD8VF>;
1703 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1704 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1705 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1706 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1708 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1710 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1711 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1712 "vcmp${cc}"#_.Suffix,
1713 "$src2, $src1", "$src1, $src2",
1714 (X86cmpm (_.VT _.RC:$src1),
1718 let mayLoad = 1 in {
1719 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1720 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1721 "vcmp${cc}"#_.Suffix,
1722 "$src2, $src1", "$src1, $src2",
1723 (X86cmpm (_.VT _.RC:$src1),
1724 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1727 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1729 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1730 "vcmp${cc}"#_.Suffix,
1731 "${src2}"##_.BroadcastStr##", $src1",
1732 "$src1, ${src2}"##_.BroadcastStr,
1733 (X86cmpm (_.VT _.RC:$src1),
1734 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1737 // Accept explicit immediate argument form instead of comparison code.
1738 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1739 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1741 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1743 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1745 let mayLoad = 1 in {
1746 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1748 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1750 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1752 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1754 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1756 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1757 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1762 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1763 // comparison code form (VCMP[EQ/LT/LE/...]
1764 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1765 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1766 "vcmp${cc}"#_.Suffix,
1767 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1768 (X86cmpmRnd (_.VT _.RC:$src1),
1771 (i32 FROUND_NO_EXC))>, EVEX_B;
1773 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1774 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1776 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1778 "$cc,{sae}, $src2, $src1",
1779 "$src1, $src2,{sae}, $cc">, EVEX_B;
1783 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1784 let Predicates = [HasAVX512] in {
1785 defm Z : avx512_vcmp_common<_.info512>,
1786 avx512_vcmp_sae<_.info512>, EVEX_V512;
1789 let Predicates = [HasAVX512,HasVLX] in {
1790 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1791 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1795 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1796 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1797 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1798 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1800 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1801 (COPY_TO_REGCLASS (VCMPPSZrri
1802 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1803 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1805 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1806 (COPY_TO_REGCLASS (VPCMPDZrri
1807 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1808 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1810 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1811 (COPY_TO_REGCLASS (VPCMPUDZrri
1812 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1813 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1816 // ----------------------------------------------------------------
1818 //handle fpclass instruction mask = op(reg_scalar,imm)
1819 // op(mem_scalar,imm)
1820 multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1821 X86VectorVTInfo _, Predicate prd> {
1822 let Predicates = [prd] in {
1823 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),//_.KRC:$dst),
1824 (ins _.RC:$src1, i32u8imm:$src2),
1825 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1826 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1827 (i32 imm:$src2)))], NoItinerary>;
1828 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1829 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1830 OpcodeStr##_.Suffix#
1831 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1832 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1833 (OpNode (_.VT _.RC:$src1),
1834 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1835 let mayLoad = 1, AddedComplexity = 20 in {
1836 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1837 (ins _.MemOp:$src1, i32u8imm:$src2),
1838 OpcodeStr##_.Suffix##
1839 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1841 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1842 (i32 imm:$src2)))], NoItinerary>;
1843 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1844 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1845 OpcodeStr##_.Suffix##
1846 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1847 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1848 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1849 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1854 //handle fpclass instruction mask = fpclass(reg_vec, reg_vec, imm)
1855 // fpclass(reg_vec, mem_vec, imm)
1856 // fpclass(reg_vec, broadcast(eltVt), imm)
1857 multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1858 X86VectorVTInfo _, string mem, string broadcast>{
1859 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1860 (ins _.RC:$src1, i32u8imm:$src2),
1861 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1862 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1863 (i32 imm:$src2)))], NoItinerary>;
1864 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1865 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1866 OpcodeStr##_.Suffix#
1867 "\t{$src2, $src1, $dst {${mask}}| $dst {${mask}}, $src1, $src2}",
1868 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1869 (OpNode (_.VT _.RC:$src1),
1870 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1871 let mayLoad = 1 in {
1872 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1873 (ins _.MemOp:$src1, i32u8imm:$src2),
1874 OpcodeStr##_.Suffix##mem#
1875 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1876 [(set _.KRC:$dst,(OpNode
1877 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1878 (i32 imm:$src2)))], NoItinerary>;
1879 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1880 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1881 OpcodeStr##_.Suffix##mem#
1882 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1883 [(set _.KRC:$dst, (or _.KRCWM:$mask, (OpNode
1884 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1885 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1886 def rmb : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1887 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
1888 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1889 _.BroadcastStr##", $dst | $dst, ${src1}"
1890 ##_.BroadcastStr##", $src2}",
1891 [(set _.KRC:$dst,(OpNode
1892 (_.VT (X86VBroadcast
1893 (_.ScalarLdFrag addr:$src1))),
1894 (i32 imm:$src2)))], NoItinerary>,EVEX_B;
1895 def rmbk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1896 (ins _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2),
1897 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1898 _.BroadcastStr##", $dst {${mask}} | $dst {${mask}}, ${src1}"##
1899 _.BroadcastStr##", $src2}",
1900 [(set _.KRC:$dst,(or _.KRCWM:$mask, (OpNode
1901 (_.VT (X86VBroadcast
1902 (_.ScalarLdFrag addr:$src1))),
1903 (i32 imm:$src2))))], NoItinerary>,
1908 multiclass avx512_vector_fpclass_all<string OpcodeStr,
1909 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd,
1911 let Predicates = [prd] in {
1912 defm Z : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info512, "{z}",
1913 broadcast>, EVEX_V512;
1915 let Predicates = [prd, HasVLX] in {
1916 defm Z128 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info128, "{x}",
1917 broadcast>, EVEX_V128;
1918 defm Z256 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info256, "{y}",
1919 broadcast>, EVEX_V256;
1923 multiclass avx512_fp_fpclass_all<string OpcodeStr, bits<8> opcVec,
1924 bits<8> opcScalar, SDNode VecOpNode, SDNode ScalarOpNode, Predicate prd>{
1925 defm PS : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f32_info, opcVec,
1926 VecOpNode, prd, "{l}">, EVEX_CD8<32, CD8VF>;
1927 defm PD : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f64_info, opcVec,
1928 VecOpNode, prd, "{q}">,EVEX_CD8<64, CD8VF> , VEX_W;
1929 defm SS : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
1930 f32x_info, prd>, EVEX_CD8<32, CD8VT1>;
1931 defm SD : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
1932 f64x_info, prd>, EVEX_CD8<64, CD8VT1>, VEX_W;
1935 defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass,
1936 X86Vfpclasss, HasDQI>, AVX512AIi8Base,EVEX;
1938 //-----------------------------------------------------------------
1939 // Mask register copy, including
1940 // - copy between mask registers
1941 // - load/store mask registers
1942 // - copy from GPR to mask register and vice versa
1944 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1945 string OpcodeStr, RegisterClass KRC,
1946 ValueType vvt, X86MemOperand x86memop> {
1947 let hasSideEffects = 0 in {
1948 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1949 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1951 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1952 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1953 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1955 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1956 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1957 [(store KRC:$src, addr:$dst)]>;
1961 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1963 RegisterClass KRC, RegisterClass GRC> {
1964 let hasSideEffects = 0 in {
1965 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1966 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1967 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1968 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1972 let Predicates = [HasDQI] in
1973 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1974 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1977 let Predicates = [HasAVX512] in
1978 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1979 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1982 let Predicates = [HasBWI] in {
1983 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1985 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1989 let Predicates = [HasBWI] in {
1990 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1992 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1996 // GR from/to mask register
1997 let Predicates = [HasDQI] in {
1998 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1999 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
2000 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2001 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
2003 let Predicates = [HasAVX512] in {
2004 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
2005 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
2006 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
2007 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
2009 let Predicates = [HasBWI] in {
2010 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
2011 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
2013 let Predicates = [HasBWI] in {
2014 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
2015 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
2019 let Predicates = [HasDQI] in {
2020 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2021 (KMOVBmk addr:$dst, VK8:$src)>;
2022 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2023 (KMOVBkm addr:$src)>;
2025 def : Pat<(store VK4:$src, addr:$dst),
2026 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK4:$src, VK8))>;
2027 def : Pat<(store VK2:$src, addr:$dst),
2028 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK2:$src, VK8))>;
2030 let Predicates = [HasAVX512, NoDQI] in {
2031 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2032 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
2033 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2034 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
2036 let Predicates = [HasAVX512] in {
2037 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
2038 (KMOVWmk addr:$dst, VK16:$src)>;
2039 def : Pat<(i1 (load addr:$src)),
2040 (COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
2041 (MOV8rm addr:$src), sub_8bit)),
2043 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
2044 (KMOVWkm addr:$src)>;
2046 let Predicates = [HasBWI] in {
2047 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
2048 (KMOVDmk addr:$dst, VK32:$src)>;
2049 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
2050 (KMOVDkm addr:$src)>;
2052 let Predicates = [HasBWI] in {
2053 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
2054 (KMOVQmk addr:$dst, VK64:$src)>;
2055 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
2056 (KMOVQkm addr:$src)>;
2059 let Predicates = [HasAVX512] in {
2060 def : Pat<(i1 (trunc (i64 GR64:$src))),
2061 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
2064 def : Pat<(i1 (trunc (i32 GR32:$src))),
2065 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
2067 def : Pat<(i1 (trunc (i8 GR8:$src))),
2069 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
2071 def : Pat<(i1 (trunc (i16 GR16:$src))),
2073 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
2076 def : Pat<(i32 (zext VK1:$src)),
2077 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
2078 def : Pat<(i32 (anyext VK1:$src)),
2079 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
2081 def : Pat<(i8 (zext VK1:$src)),
2084 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
2085 def : Pat<(i8 (anyext VK1:$src)),
2087 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
2089 def : Pat<(i64 (zext VK1:$src)),
2090 (AND64ri8 (SUBREG_TO_REG (i64 0),
2091 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
2092 def : Pat<(i16 (zext VK1:$src)),
2094 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
2096 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
2097 (COPY_TO_REGCLASS VK1:$src, VK16)>;
2098 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
2099 (COPY_TO_REGCLASS VK1:$src, VK8)>;
2101 let Predicates = [HasBWI] in {
2102 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
2103 (COPY_TO_REGCLASS VK1:$src, VK32)>;
2104 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
2105 (COPY_TO_REGCLASS VK1:$src, VK64)>;
2109 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2110 let Predicates = [HasAVX512, NoDQI] in {
2111 // GR from/to 8-bit mask without native support
2112 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2114 (KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
2115 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2117 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
2121 let Predicates = [HasAVX512] in {
2122 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
2123 (COPY_TO_REGCLASS VK16:$src, VK1)>;
2124 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
2125 (COPY_TO_REGCLASS VK8:$src, VK1)>;
2127 let Predicates = [HasBWI] in {
2128 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
2129 (COPY_TO_REGCLASS VK32:$src, VK1)>;
2130 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
2131 (COPY_TO_REGCLASS VK64:$src, VK1)>;
2134 // Mask unary operation
2136 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
2137 RegisterClass KRC, SDPatternOperator OpNode,
2139 let Predicates = [prd] in
2140 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2141 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2142 [(set KRC:$dst, (OpNode KRC:$src))]>;
2145 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
2146 SDPatternOperator OpNode> {
2147 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2149 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2150 HasAVX512>, VEX, PS;
2151 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2152 HasBWI>, VEX, PD, VEX_W;
2153 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2154 HasBWI>, VEX, PS, VEX_W;
2157 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
2159 multiclass avx512_mask_unop_int<string IntName, string InstName> {
2160 let Predicates = [HasAVX512] in
2161 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2163 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2164 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
2166 defm : avx512_mask_unop_int<"knot", "KNOT">;
2168 let Predicates = [HasDQI] in
2169 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
2170 let Predicates = [HasAVX512] in
2171 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
2172 let Predicates = [HasBWI] in
2173 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
2174 let Predicates = [HasBWI] in
2175 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
2177 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
2178 let Predicates = [HasAVX512, NoDQI] in {
2179 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
2180 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
2181 def : Pat<(not VK8:$src),
2183 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
2185 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
2186 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
2187 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
2188 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
2190 // Mask binary operation
2191 // - KAND, KANDN, KOR, KXNOR, KXOR
2192 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
2193 RegisterClass KRC, SDPatternOperator OpNode,
2194 Predicate prd, bit IsCommutable> {
2195 let Predicates = [prd], isCommutable = IsCommutable in
2196 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2197 !strconcat(OpcodeStr,
2198 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2199 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
2202 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
2203 SDPatternOperator OpNode, bit IsCommutable,
2204 Predicate prdW = HasAVX512> {
2205 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2206 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
2207 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2208 prdW, IsCommutable>, VEX_4V, VEX_L, PS;
2209 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2210 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
2211 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2212 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
2215 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
2216 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
2218 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
2219 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
2220 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
2221 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
2222 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
2223 defm KADD : avx512_mask_binop_all<0x4A, "kadd", add, 1, HasDQI>;
2225 multiclass avx512_mask_binop_int<string IntName, string InstName> {
2226 let Predicates = [HasAVX512] in
2227 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2228 (i16 GR16:$src1), (i16 GR16:$src2)),
2229 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2230 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2231 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2234 defm : avx512_mask_binop_int<"kand", "KAND">;
2235 defm : avx512_mask_binop_int<"kandn", "KANDN">;
2236 defm : avx512_mask_binop_int<"kor", "KOR">;
2237 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
2238 defm : avx512_mask_binop_int<"kxor", "KXOR">;
2240 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
2241 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
2242 // for the DQI set, this type is legal and KxxxB instruction is used
2243 let Predicates = [NoDQI] in
2244 def : Pat<(OpNode VK8:$src1, VK8:$src2),
2246 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2247 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2249 // All types smaller than 8 bits require conversion anyway
2250 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2251 (COPY_TO_REGCLASS (Inst
2252 (COPY_TO_REGCLASS VK1:$src1, VK16),
2253 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2254 def : Pat<(OpNode VK2:$src1, VK2:$src2),
2255 (COPY_TO_REGCLASS (Inst
2256 (COPY_TO_REGCLASS VK2:$src1, VK16),
2257 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2258 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2259 (COPY_TO_REGCLASS (Inst
2260 (COPY_TO_REGCLASS VK4:$src1, VK16),
2261 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2264 defm : avx512_binop_pat<and, KANDWrr>;
2265 defm : avx512_binop_pat<andn, KANDNWrr>;
2266 defm : avx512_binop_pat<or, KORWrr>;
2267 defm : avx512_binop_pat<xnor, KXNORWrr>;
2268 defm : avx512_binop_pat<xor, KXORWrr>;
2270 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2271 (KXNORWrr VK16:$src1, VK16:$src2)>;
2272 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2273 (KXNORBrr VK8:$src1, VK8:$src2)>, Requires<[HasDQI]>;
2274 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2275 (KXNORDrr VK32:$src1, VK32:$src2)>, Requires<[HasBWI]>;
2276 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2277 (KXNORQrr VK64:$src1, VK64:$src2)>, Requires<[HasBWI]>;
2279 let Predicates = [NoDQI] in
2280 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2281 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2282 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2284 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2285 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2286 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2288 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2289 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2290 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2292 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2293 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2294 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2297 multiclass avx512_mask_unpck<string Suffix,RegisterClass KRC, ValueType VT,
2298 RegisterClass KRCSrc, Predicate prd> {
2299 let Predicates = [prd] in {
2300 def rr : I<0x4b, MRMSrcReg, (outs KRC:$dst),
2301 (ins KRC:$src1, KRC:$src2),
2302 "kunpck"#Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2305 def : Pat<(VT (concat_vectors KRCSrc:$src1, KRCSrc:$src2)),
2306 (!cast<Instruction>(NAME##rr)
2307 (COPY_TO_REGCLASS KRCSrc:$src2, KRC),
2308 (COPY_TO_REGCLASS KRCSrc:$src1, KRC))>;
2312 defm KUNPCKBW : avx512_mask_unpck<"bw", VK16, v16i1, VK8, HasAVX512>, PD;
2313 defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, HasBWI>, PS;
2314 defm KUNPCKDQ : avx512_mask_unpck<"dq", VK64, v64i1, VK32, HasBWI>, PS, VEX_W;
2316 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
2317 let Predicates = [HasAVX512] in
2318 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
2319 (i16 GR16:$src1), (i16 GR16:$src2)),
2320 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
2321 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2322 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2324 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
2327 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2328 SDNode OpNode, Predicate prd> {
2329 let Predicates = [prd], Defs = [EFLAGS] in
2330 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2331 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2332 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2335 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2336 Predicate prdW = HasAVX512> {
2337 defm B : avx512_mask_testop<opc, OpcodeStr#"b", VK8, OpNode, HasDQI>,
2339 defm W : avx512_mask_testop<opc, OpcodeStr#"w", VK16, OpNode, prdW>,
2341 defm Q : avx512_mask_testop<opc, OpcodeStr#"q", VK64, OpNode, HasBWI>,
2343 defm D : avx512_mask_testop<opc, OpcodeStr#"d", VK32, OpNode, HasBWI>,
2347 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2348 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest, HasDQI>;
2351 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2353 let Predicates = [HasAVX512] in
2354 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2355 !strconcat(OpcodeStr,
2356 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2357 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2360 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2362 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2364 let Predicates = [HasDQI] in
2365 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2367 let Predicates = [HasBWI] in {
2368 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2370 let Predicates = [HasDQI] in
2371 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2376 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2377 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2379 // Mask setting all 0s or 1s
2380 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2381 let Predicates = [HasAVX512] in
2382 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2383 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2384 [(set KRC:$dst, (VT Val))]>;
2387 multiclass avx512_mask_setop_w<PatFrag Val> {
2388 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2389 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2390 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2391 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2394 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2395 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2397 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2398 let Predicates = [HasAVX512] in {
2399 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2400 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2401 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2402 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2403 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2404 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2405 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2407 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2408 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2410 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2411 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2413 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2414 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2416 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
2417 (v32i1 (COPY_TO_REGCLASS VK64:$src, VK32))>;
2419 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2420 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2422 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2423 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2424 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2425 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2427 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2428 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2430 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2431 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2432 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2433 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2435 def : Pat<(v32i1 (insert_subvector undef, VK2:$src, (iPTR 0))),
2436 (v32i1 (COPY_TO_REGCLASS VK2:$src, VK32))>;
2437 def : Pat<(v32i1 (insert_subvector undef, VK4:$src, (iPTR 0))),
2438 (v32i1 (COPY_TO_REGCLASS VK4:$src, VK32))>;
2439 def : Pat<(v32i1 (insert_subvector undef, VK8:$src, (iPTR 0))),
2440 (v32i1 (COPY_TO_REGCLASS VK8:$src, VK32))>;
2441 def : Pat<(v32i1 (insert_subvector undef, VK16:$src, (iPTR 0))),
2442 (v32i1 (COPY_TO_REGCLASS VK16:$src, VK32))>;
2444 def : Pat<(v64i1 (insert_subvector undef, VK2:$src, (iPTR 0))),
2445 (v64i1 (COPY_TO_REGCLASS VK2:$src, VK64))>;
2446 def : Pat<(v64i1 (insert_subvector undef, VK4:$src, (iPTR 0))),
2447 (v64i1 (COPY_TO_REGCLASS VK4:$src, VK64))>;
2448 def : Pat<(v64i1 (insert_subvector undef, VK8:$src, (iPTR 0))),
2449 (v64i1 (COPY_TO_REGCLASS VK8:$src, VK64))>;
2450 def : Pat<(v64i1 (insert_subvector undef, VK16:$src, (iPTR 0))),
2451 (v64i1 (COPY_TO_REGCLASS VK16:$src, VK64))>;
2452 def : Pat<(v64i1 (insert_subvector undef, VK32:$src, (iPTR 0))),
2453 (v64i1 (COPY_TO_REGCLASS VK32:$src, VK64))>;
2456 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2457 (v8i1 (COPY_TO_REGCLASS
2458 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2459 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2461 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2462 (v8i1 (COPY_TO_REGCLASS
2463 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2464 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2466 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2467 (v4i1 (COPY_TO_REGCLASS
2468 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2469 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2471 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2472 (v4i1 (COPY_TO_REGCLASS
2473 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2474 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2476 //===----------------------------------------------------------------------===//
2477 // AVX-512 - Aligned and unaligned load and store
2481 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2482 PatFrag ld_frag, PatFrag mload,
2483 bit IsReMaterializable = 1> {
2484 let hasSideEffects = 0 in {
2485 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2486 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2488 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2489 (ins _.KRCWM:$mask, _.RC:$src),
2490 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2491 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2494 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2495 SchedRW = [WriteLoad] in
2496 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2497 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2498 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2501 let Constraints = "$src0 = $dst" in {
2502 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2503 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2504 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2505 "${dst} {${mask}}, $src1}"),
2506 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2508 (_.VT _.RC:$src0))))], _.ExeDomain>,
2510 let mayLoad = 1, SchedRW = [WriteLoad] in
2511 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2512 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2513 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2514 "${dst} {${mask}}, $src1}"),
2515 [(set _.RC:$dst, (_.VT
2516 (vselect _.KRCWM:$mask,
2517 (_.VT (bitconvert (ld_frag addr:$src1))),
2518 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2520 let mayLoad = 1, SchedRW = [WriteLoad] in
2521 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2522 (ins _.KRCWM:$mask, _.MemOp:$src),
2523 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2524 "${dst} {${mask}} {z}, $src}",
2525 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2526 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2527 _.ExeDomain>, EVEX, EVEX_KZ;
2529 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2530 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2532 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2533 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2535 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2536 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2537 _.KRCWM:$mask, addr:$ptr)>;
2540 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2541 AVX512VLVectorVTInfo _,
2543 bit IsReMaterializable = 1> {
2544 let Predicates = [prd] in
2545 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2546 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2548 let Predicates = [prd, HasVLX] in {
2549 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2550 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2551 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2552 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2556 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2557 AVX512VLVectorVTInfo _,
2559 bit IsReMaterializable = 1> {
2560 let Predicates = [prd] in
2561 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2562 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2564 let Predicates = [prd, HasVLX] in {
2565 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2566 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2567 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2568 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2572 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2573 PatFrag st_frag, PatFrag mstore> {
2575 def rr_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2576 OpcodeStr # ".s\t{$src, $dst|$dst, $src}",
2577 [], _.ExeDomain>, EVEX;
2578 def rrk_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2579 (ins _.KRCWM:$mask, _.RC:$src),
2580 OpcodeStr # ".s\t{$src, ${dst} {${mask}}|"#
2581 "${dst} {${mask}}, $src}",
2582 [], _.ExeDomain>, EVEX, EVEX_K;
2583 def rrkz_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2584 (ins _.KRCWM:$mask, _.RC:$src),
2585 OpcodeStr # ".s\t{$src, ${dst} {${mask}} {z}|" #
2586 "${dst} {${mask}} {z}, $src}",
2587 [], _.ExeDomain>, EVEX, EVEX_KZ;
2589 let mayStore = 1 in {
2590 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2591 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2592 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2593 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2594 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2595 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2596 [], _.ExeDomain>, EVEX, EVEX_K;
2599 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2600 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2601 _.KRCWM:$mask, _.RC:$src)>;
2605 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2606 AVX512VLVectorVTInfo _, Predicate prd> {
2607 let Predicates = [prd] in
2608 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2609 masked_store_unaligned>, EVEX_V512;
2611 let Predicates = [prd, HasVLX] in {
2612 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2613 masked_store_unaligned>, EVEX_V256;
2614 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2615 masked_store_unaligned>, EVEX_V128;
2619 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2620 AVX512VLVectorVTInfo _, Predicate prd> {
2621 let Predicates = [prd] in
2622 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2623 masked_store_aligned512>, EVEX_V512;
2625 let Predicates = [prd, HasVLX] in {
2626 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2627 masked_store_aligned256>, EVEX_V256;
2628 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2629 masked_store_aligned128>, EVEX_V128;
2633 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2635 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2636 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2638 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2640 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2641 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2643 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2644 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2645 PS, EVEX_CD8<32, CD8VF>;
2647 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2648 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2649 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2651 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2652 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2653 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2655 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2656 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2657 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2659 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2660 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2661 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2663 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2664 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2665 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2667 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2668 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2669 (VMOVAPDZrm addr:$ptr)>;
2671 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2672 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2673 (VMOVAPSZrm addr:$ptr)>;
2675 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2677 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2679 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2681 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2684 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2686 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2688 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2690 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2693 let Predicates = [HasAVX512, NoVLX] in {
2694 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2695 (VMOVUPSZmrk addr:$ptr,
2696 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2697 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2699 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2700 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2701 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2703 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2704 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2705 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2706 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2709 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2711 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2712 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2714 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2716 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2717 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2719 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2720 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2721 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2723 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2724 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2725 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2727 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2728 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2729 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2731 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2732 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2733 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2735 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2736 (v16i32 immAllZerosV), GR16:$mask)),
2737 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2739 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2740 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2741 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2743 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2745 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2747 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2749 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2752 let AddedComplexity = 20 in {
2753 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2754 (bc_v8i64 (v16i32 immAllZerosV)))),
2755 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2757 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2758 (v8i64 VR512:$src))),
2759 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2762 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2763 (v16i32 immAllZerosV))),
2764 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2766 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2767 (v16i32 VR512:$src))),
2768 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2771 let Predicates = [HasAVX512, NoVLX] in {
2772 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2773 (VMOVDQU32Zmrk addr:$ptr,
2774 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2775 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2777 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2778 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2779 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2782 // Move Int Doubleword to Packed Double Int
2784 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2785 "vmovd\t{$src, $dst|$dst, $src}",
2787 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2789 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2790 "vmovd\t{$src, $dst|$dst, $src}",
2792 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2793 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2794 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2795 "vmovq\t{$src, $dst|$dst, $src}",
2797 (v2i64 (scalar_to_vector GR64:$src)))],
2798 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2799 let isCodeGenOnly = 1 in {
2800 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2801 "vmovq\t{$src, $dst|$dst, $src}",
2802 [(set FR64:$dst, (bitconvert GR64:$src))],
2803 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2804 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2805 "vmovq\t{$src, $dst|$dst, $src}",
2806 [(set GR64:$dst, (bitconvert FR64:$src))],
2807 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2809 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2810 "vmovq\t{$src, $dst|$dst, $src}",
2811 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2812 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2813 EVEX_CD8<64, CD8VT1>;
2815 // Move Int Doubleword to Single Scalar
2817 let isCodeGenOnly = 1 in {
2818 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2819 "vmovd\t{$src, $dst|$dst, $src}",
2820 [(set FR32X:$dst, (bitconvert GR32:$src))],
2821 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2823 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2824 "vmovd\t{$src, $dst|$dst, $src}",
2825 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2826 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2829 // Move doubleword from xmm register to r/m32
2831 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2832 "vmovd\t{$src, $dst|$dst, $src}",
2833 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2834 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2836 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2837 (ins i32mem:$dst, VR128X:$src),
2838 "vmovd\t{$src, $dst|$dst, $src}",
2839 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2840 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2841 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2843 // Move quadword from xmm1 register to r/m64
2845 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2846 "vmovq\t{$src, $dst|$dst, $src}",
2847 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2849 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2850 Requires<[HasAVX512, In64BitMode]>;
2852 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2853 (ins i64mem:$dst, VR128X:$src),
2854 "vmovq\t{$src, $dst|$dst, $src}",
2855 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2856 addr:$dst)], IIC_SSE_MOVDQ>,
2857 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2858 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2860 // Move Scalar Single to Double Int
2862 let isCodeGenOnly = 1 in {
2863 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2865 "vmovd\t{$src, $dst|$dst, $src}",
2866 [(set GR32:$dst, (bitconvert FR32X:$src))],
2867 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2868 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2869 (ins i32mem:$dst, FR32X:$src),
2870 "vmovd\t{$src, $dst|$dst, $src}",
2871 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2872 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2875 // Move Quadword Int to Packed Quadword Int
2877 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2879 "vmovq\t{$src, $dst|$dst, $src}",
2881 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2882 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2884 //===----------------------------------------------------------------------===//
2885 // AVX-512 MOVSS, MOVSD
2886 //===----------------------------------------------------------------------===//
2888 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2889 SDNode OpNode, ValueType vt,
2890 X86MemOperand x86memop, PatFrag mem_pat> {
2891 let hasSideEffects = 0 in {
2892 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2893 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2894 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2895 (scalar_to_vector RC:$src2))))],
2896 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2897 let Constraints = "$src1 = $dst" in
2898 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2899 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2901 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2902 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2903 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2904 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2905 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2907 let mayStore = 1 in {
2908 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2909 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2910 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2912 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2913 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2914 [], IIC_SSE_MOV_S_MR>,
2915 EVEX, VEX_LIG, EVEX_K;
2917 } //hasSideEffects = 0
2920 let ExeDomain = SSEPackedSingle in
2921 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2922 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2924 let ExeDomain = SSEPackedDouble in
2925 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2926 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2928 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2929 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2930 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2932 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2933 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2934 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2936 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2937 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2938 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2940 defm VMOVSSZrr_REV : AVX512_maskable_in_asm<0x11, MRMDestReg, f32x_info,
2941 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2),
2942 "vmovss.s", "$src2, $src1", "$src1, $src2", []>,
2943 XS, EVEX_4V, VEX_LIG;
2945 defm VMOVSSDrr_REV : AVX512_maskable_in_asm<0x11, MRMDestReg, f64x_info,
2946 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2),
2947 "vmovsd.s", "$src2, $src1", "$src1, $src2", []>,
2948 XD, EVEX_4V, VEX_LIG, VEX_W;
2950 let Predicates = [HasAVX512] in {
2951 let AddedComplexity = 15 in {
2952 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2953 // MOVS{S,D} to the lower bits.
2954 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2955 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2956 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2957 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2958 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2959 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2960 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2961 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2963 // Move low f32 and clear high bits.
2964 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2965 (SUBREG_TO_REG (i32 0),
2966 (VMOVSSZrr (v4f32 (V_SET0)),
2967 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2968 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2969 (SUBREG_TO_REG (i32 0),
2970 (VMOVSSZrr (v4i32 (V_SET0)),
2971 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2974 let AddedComplexity = 20 in {
2975 // MOVSSrm zeros the high parts of the register; represent this
2976 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2977 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2978 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2979 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2980 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2981 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2982 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2984 // MOVSDrm zeros the high parts of the register; represent this
2985 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2986 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2987 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2988 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2989 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2990 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2991 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2992 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2993 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2994 def : Pat<(v2f64 (X86vzload addr:$src)),
2995 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2997 // Represent the same patterns above but in the form they appear for
2999 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3000 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
3001 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
3002 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
3003 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
3004 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
3005 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
3006 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
3007 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
3009 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
3010 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
3011 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
3012 FR32X:$src)), sub_xmm)>;
3013 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
3014 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
3015 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
3016 FR64X:$src)), sub_xmm)>;
3017 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3018 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
3019 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
3021 // Move low f64 and clear high bits.
3022 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
3023 (SUBREG_TO_REG (i32 0),
3024 (VMOVSDZrr (v2f64 (V_SET0)),
3025 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
3027 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
3028 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
3029 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
3031 // Extract and store.
3032 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
3034 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
3035 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
3037 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
3039 // Shuffle with VMOVSS
3040 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
3041 (VMOVSSZrr (v4i32 VR128X:$src1),
3042 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
3043 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
3044 (VMOVSSZrr (v4f32 VR128X:$src1),
3045 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
3048 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
3049 (SUBREG_TO_REG (i32 0),
3050 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
3051 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
3053 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
3054 (SUBREG_TO_REG (i32 0),
3055 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
3056 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
3059 // Shuffle with VMOVSD
3060 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3061 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3062 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3063 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3064 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3065 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3066 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3067 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3070 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3071 (SUBREG_TO_REG (i32 0),
3072 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
3073 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
3075 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3076 (SUBREG_TO_REG (i32 0),
3077 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
3078 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
3081 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3082 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3083 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3084 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3085 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3086 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3087 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3088 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3091 let AddedComplexity = 15 in
3092 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
3094 "vmovq\t{$src, $dst|$dst, $src}",
3095 [(set VR128X:$dst, (v2i64 (X86vzmovl
3096 (v2i64 VR128X:$src))))],
3097 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
3099 let AddedComplexity = 20 , isCodeGenOnly = 1 in
3100 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
3102 "vmovq\t{$src, $dst|$dst, $src}",
3103 [(set VR128X:$dst, (v2i64 (X86vzmovl
3104 (loadv2i64 addr:$src))))],
3105 IIC_SSE_MOVDQ>, EVEX, VEX_W,
3106 EVEX_CD8<8, CD8VT8>;
3108 let Predicates = [HasAVX512] in {
3109 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3110 let AddedComplexity = 20 in {
3111 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
3112 (VMOVDI2PDIZrm addr:$src)>;
3113 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
3114 (VMOV64toPQIZrr GR64:$src)>;
3115 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
3116 (VMOVDI2PDIZrr GR32:$src)>;
3118 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3119 (VMOVDI2PDIZrm addr:$src)>;
3120 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3121 (VMOVDI2PDIZrm addr:$src)>;
3122 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3123 (VMOVZPQILo2PQIZrm addr:$src)>;
3124 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
3125 (VMOVZPQILo2PQIZrr VR128X:$src)>;
3126 def : Pat<(v2i64 (X86vzload addr:$src)),
3127 (VMOVZPQILo2PQIZrm addr:$src)>;
3130 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3131 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3132 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
3133 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
3134 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3135 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
3136 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
3139 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
3140 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3142 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
3143 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3145 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
3146 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3148 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
3149 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3151 //===----------------------------------------------------------------------===//
3152 // AVX-512 - Non-temporals
3153 //===----------------------------------------------------------------------===//
3154 let SchedRW = [WriteLoad] in {
3155 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
3156 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
3157 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
3158 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
3159 EVEX_CD8<64, CD8VF>;
3161 let Predicates = [HasAVX512, HasVLX] in {
3162 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
3164 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3165 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
3166 EVEX_CD8<64, CD8VF>;
3168 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
3170 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3171 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
3172 EVEX_CD8<64, CD8VF>;
3176 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3177 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
3178 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
3179 let SchedRW = [WriteStore], mayStore = 1,
3180 AddedComplexity = 400 in
3181 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
3182 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3183 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
3186 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3187 string elty, string elsz, string vsz512,
3188 string vsz256, string vsz128, Domain d,
3189 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
3190 let Predicates = [prd] in
3191 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
3192 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
3193 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
3196 let Predicates = [prd, HasVLX] in {
3197 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
3198 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
3199 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
3202 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
3203 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
3204 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
3209 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
3210 "i", "64", "8", "4", "2", SSEPackedInt,
3211 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
3213 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
3214 "f", "64", "8", "4", "2", SSEPackedDouble,
3215 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3217 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
3218 "f", "32", "16", "8", "4", SSEPackedSingle,
3219 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
3221 //===----------------------------------------------------------------------===//
3222 // AVX-512 - Integer arithmetic
3224 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3225 X86VectorVTInfo _, OpndItins itins,
3226 bit IsCommutable = 0> {
3227 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3228 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3229 "$src2, $src1", "$src1, $src2",
3230 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3231 itins.rr, IsCommutable>,
3232 AVX512BIBase, EVEX_4V;
3235 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3236 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3237 "$src2, $src1", "$src1, $src2",
3238 (_.VT (OpNode _.RC:$src1,
3239 (bitconvert (_.LdFrag addr:$src2)))),
3241 AVX512BIBase, EVEX_4V;
3244 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3245 X86VectorVTInfo _, OpndItins itins,
3246 bit IsCommutable = 0> :
3247 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
3249 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3250 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3251 "${src2}"##_.BroadcastStr##", $src1",
3252 "$src1, ${src2}"##_.BroadcastStr,
3253 (_.VT (OpNode _.RC:$src1,
3255 (_.ScalarLdFrag addr:$src2)))),
3257 AVX512BIBase, EVEX_4V, EVEX_B;
3260 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3261 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3262 Predicate prd, bit IsCommutable = 0> {
3263 let Predicates = [prd] in
3264 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3265 IsCommutable>, EVEX_V512;
3267 let Predicates = [prd, HasVLX] in {
3268 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3269 IsCommutable>, EVEX_V256;
3270 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3271 IsCommutable>, EVEX_V128;
3275 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3276 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3277 Predicate prd, bit IsCommutable = 0> {
3278 let Predicates = [prd] in
3279 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3280 IsCommutable>, EVEX_V512;
3282 let Predicates = [prd, HasVLX] in {
3283 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3284 IsCommutable>, EVEX_V256;
3285 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3286 IsCommutable>, EVEX_V128;
3290 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3291 OpndItins itins, Predicate prd,
3292 bit IsCommutable = 0> {
3293 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3294 itins, prd, IsCommutable>,
3295 VEX_W, EVEX_CD8<64, CD8VF>;
3298 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3299 OpndItins itins, Predicate prd,
3300 bit IsCommutable = 0> {
3301 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3302 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3305 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3306 OpndItins itins, Predicate prd,
3307 bit IsCommutable = 0> {
3308 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3309 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3312 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3313 OpndItins itins, Predicate prd,
3314 bit IsCommutable = 0> {
3315 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3316 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3319 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3320 SDNode OpNode, OpndItins itins, Predicate prd,
3321 bit IsCommutable = 0> {
3322 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr#"q", OpNode, itins, prd,
3325 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr#"d", OpNode, itins, prd,
3329 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3330 SDNode OpNode, OpndItins itins, Predicate prd,
3331 bit IsCommutable = 0> {
3332 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr#"w", OpNode, itins, prd,
3335 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr#"b", OpNode, itins, prd,
3339 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3340 bits<8> opc_d, bits<8> opc_q,
3341 string OpcodeStr, SDNode OpNode,
3342 OpndItins itins, bit IsCommutable = 0> {
3343 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3344 itins, HasAVX512, IsCommutable>,
3345 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3346 itins, HasBWI, IsCommutable>;
3349 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3350 SDNode OpNode,X86VectorVTInfo _Src,
3351 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3352 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3353 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3354 "$src2, $src1","$src1, $src2",
3356 (_Src.VT _Src.RC:$src1),
3357 (_Src.VT _Src.RC:$src2))),
3358 itins.rr, IsCommutable>,
3359 AVX512BIBase, EVEX_4V;
3360 let mayLoad = 1 in {
3361 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3362 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3363 "$src2, $src1", "$src1, $src2",
3364 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3365 (bitconvert (_Src.LdFrag addr:$src2)))),
3367 AVX512BIBase, EVEX_4V;
3369 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3370 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3372 "${src2}"##_Dst.BroadcastStr##", $src1",
3373 "$src1, ${src2}"##_Dst.BroadcastStr,
3374 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3375 (_Dst.VT (X86VBroadcast
3376 (_Dst.ScalarLdFrag addr:$src2)))))),
3378 AVX512BIBase, EVEX_4V, EVEX_B;
3382 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3383 SSE_INTALU_ITINS_P, 1>;
3384 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3385 SSE_INTALU_ITINS_P, 0>;
3386 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3387 SSE_INTALU_ITINS_P, HasBWI, 1>;
3388 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3389 SSE_INTALU_ITINS_P, HasBWI, 0>;
3390 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3391 SSE_INTALU_ITINS_P, HasBWI, 1>;
3392 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3393 SSE_INTALU_ITINS_P, HasBWI, 0>;
3394 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmulld", mul,
3395 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3396 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmullw", mul,
3397 SSE_INTALU_ITINS_P, HasBWI, 1>;
3398 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmullq", mul,
3399 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3400 defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SSE_INTALU_ITINS_P,
3402 defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SSE_INTMUL_ITINS_P,
3404 defm VPMULHRSW : avx512_binop_rm_vl_w<0x0B, "vpmulhrsw", X86mulhrs, SSE_INTMUL_ITINS_P,
3406 defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg,
3407 SSE_INTALU_ITINS_P, HasBWI, 1>;
3409 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3410 SDNode OpNode, bit IsCommutable = 0> {
3412 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3413 v16i32_info, v8i64_info, IsCommutable>,
3414 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3415 let Predicates = [HasVLX] in {
3416 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3417 v8i32x_info, v4i64x_info, IsCommutable>,
3418 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3419 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3420 v4i32x_info, v2i64x_info, IsCommutable>,
3421 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3425 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3427 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3430 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3431 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3432 let mayLoad = 1 in {
3433 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3434 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3436 "${src2}"##_Src.BroadcastStr##", $src1",
3437 "$src1, ${src2}"##_Src.BroadcastStr,
3438 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3439 (_Src.VT (X86VBroadcast
3440 (_Src.ScalarLdFrag addr:$src2))))))>,
3441 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3445 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3446 SDNode OpNode,X86VectorVTInfo _Src,
3447 X86VectorVTInfo _Dst> {
3448 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3449 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3450 "$src2, $src1","$src1, $src2",
3452 (_Src.VT _Src.RC:$src1),
3453 (_Src.VT _Src.RC:$src2)))>,
3454 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3455 let mayLoad = 1 in {
3456 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3457 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3458 "$src2, $src1", "$src1, $src2",
3459 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3460 (bitconvert (_Src.LdFrag addr:$src2))))>,
3461 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3465 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3467 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3469 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3470 v32i16_info>, EVEX_V512;
3471 let Predicates = [HasVLX] in {
3472 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3474 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3475 v16i16x_info>, EVEX_V256;
3476 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3478 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3479 v8i16x_info>, EVEX_V128;
3482 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3484 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3485 v64i8_info>, EVEX_V512;
3486 let Predicates = [HasVLX] in {
3487 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3488 v32i8x_info>, EVEX_V256;
3489 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3490 v16i8x_info>, EVEX_V128;
3494 multiclass avx512_vpmadd<bits<8> opc, string OpcodeStr,
3495 SDNode OpNode, AVX512VLVectorVTInfo _Src,
3496 AVX512VLVectorVTInfo _Dst> {
3497 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info512,
3498 _Dst.info512>, EVEX_V512;
3499 let Predicates = [HasVLX] in {
3500 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info256,
3501 _Dst.info256>, EVEX_V256;
3502 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info128,
3503 _Dst.info128>, EVEX_V128;
3507 let Predicates = [HasBWI] in {
3508 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3509 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3510 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3511 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3513 defm VPMADDUBSW : avx512_vpmadd<0x04, "vpmaddubsw", X86vpmaddubsw,
3514 avx512vl_i8_info, avx512vl_i16_info>, AVX512BIBase, T8PD;
3515 defm VPMADDWD : avx512_vpmadd<0xF5, "vpmaddwd", X86vpmaddwd,
3516 avx512vl_i16_info, avx512vl_i32_info>, AVX512BIBase;
3519 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxsb", smax,
3520 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3521 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxsw", smax,
3522 SSE_INTALU_ITINS_P, HasBWI, 1>;
3523 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", smax,
3524 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3526 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxub", umax,
3527 SSE_INTALU_ITINS_P, HasBWI, 1>;
3528 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxuw", umax,
3529 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3530 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", umax,
3531 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3533 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpminsb", smin,
3534 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3535 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpminsw", smin,
3536 SSE_INTALU_ITINS_P, HasBWI, 1>;
3537 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", smin,
3538 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3540 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminub", umin,
3541 SSE_INTALU_ITINS_P, HasBWI, 1>;
3542 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin,
3543 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3544 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", umin,
3545 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3546 //===----------------------------------------------------------------------===//
3547 // AVX-512 Logical Instructions
3548 //===----------------------------------------------------------------------===//
3550 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3551 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3552 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3553 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3554 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3555 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3556 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3557 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3559 //===----------------------------------------------------------------------===//
3560 // AVX-512 FP arithmetic
3561 //===----------------------------------------------------------------------===//
3562 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3563 SDNode OpNode, SDNode VecNode, OpndItins itins,
3566 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3567 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3568 "$src2, $src1", "$src1, $src2",
3569 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3570 (i32 FROUND_CURRENT)),
3571 itins.rr, IsCommutable>;
3573 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3574 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3575 "$src2, $src1", "$src1, $src2",
3576 (VecNode (_.VT _.RC:$src1),
3577 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3578 (i32 FROUND_CURRENT)),
3579 itins.rm, IsCommutable>;
3580 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3581 Predicates = [HasAVX512] in {
3582 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3583 (ins _.FRC:$src1, _.FRC:$src2),
3584 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3585 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3587 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3588 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3589 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3590 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3591 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3595 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3596 SDNode VecNode, OpndItins itins, bit IsCommutable = 0> {
3598 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3599 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3600 "$rc, $src2, $src1", "$src1, $src2, $rc",
3601 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3602 (i32 imm:$rc)), itins.rr, IsCommutable>,
3605 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3606 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3608 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3609 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3610 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3611 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3612 (i32 FROUND_NO_EXC))>, EVEX_B;
3615 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3617 SizeItins itins, bit IsCommutable> {
3618 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3619 itins.s, IsCommutable>,
3620 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3621 itins.s, IsCommutable>,
3622 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3623 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3624 itins.d, IsCommutable>,
3625 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3626 itins.d, IsCommutable>,
3627 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3630 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3632 SizeItins itins, bit IsCommutable> {
3633 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3634 itins.s, IsCommutable>,
3635 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3636 itins.s, IsCommutable>,
3637 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3638 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3639 itins.d, IsCommutable>,
3640 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3641 itins.d, IsCommutable>,
3642 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3644 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3645 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3646 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3647 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3648 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3649 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3651 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3652 X86VectorVTInfo _, bit IsCommutable> {
3653 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3654 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3655 "$src2, $src1", "$src1, $src2",
3656 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3657 let mayLoad = 1 in {
3658 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3659 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3660 "$src2, $src1", "$src1, $src2",
3661 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3662 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3663 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3664 "${src2}"##_.BroadcastStr##", $src1",
3665 "$src1, ${src2}"##_.BroadcastStr,
3666 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3667 (_.ScalarLdFrag addr:$src2))))>,
3672 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3673 X86VectorVTInfo _> {
3674 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3675 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3676 "$rc, $src2, $src1", "$src1, $src2, $rc",
3677 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3678 EVEX_4V, EVEX_B, EVEX_RC;
3682 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3683 X86VectorVTInfo _> {
3684 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3685 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3686 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3687 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3691 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3692 bit IsCommutable = 0> {
3693 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3694 IsCommutable>, EVEX_V512, PS,
3695 EVEX_CD8<32, CD8VF>;
3696 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3697 IsCommutable>, EVEX_V512, PD, VEX_W,
3698 EVEX_CD8<64, CD8VF>;
3700 // Define only if AVX512VL feature is present.
3701 let Predicates = [HasVLX] in {
3702 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3703 IsCommutable>, EVEX_V128, PS,
3704 EVEX_CD8<32, CD8VF>;
3705 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3706 IsCommutable>, EVEX_V256, PS,
3707 EVEX_CD8<32, CD8VF>;
3708 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3709 IsCommutable>, EVEX_V128, PD, VEX_W,
3710 EVEX_CD8<64, CD8VF>;
3711 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3712 IsCommutable>, EVEX_V256, PD, VEX_W,
3713 EVEX_CD8<64, CD8VF>;
3717 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3718 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3719 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3720 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3721 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3724 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3725 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3726 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3727 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3728 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3731 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3732 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3733 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3734 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3735 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3736 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3737 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3738 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3739 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3740 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3741 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3742 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3743 let Predicates = [HasDQI] in {
3744 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3745 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3746 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3747 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3750 multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3751 X86VectorVTInfo _> {
3752 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3753 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3754 "$src2, $src1", "$src1, $src2",
3755 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>, EVEX_4V;
3756 let mayLoad = 1 in {
3757 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3758 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3759 "$src2, $src1", "$src1, $src2",
3760 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>, EVEX_4V;
3761 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3762 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3763 "${src2}"##_.BroadcastStr##", $src1",
3764 "$src1, ${src2}"##_.BroadcastStr,
3765 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3766 (_.ScalarLdFrag addr:$src2))), (i32 FROUND_CURRENT))>,
3771 multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
3772 X86VectorVTInfo _> {
3773 defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3774 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3775 "$src2, $src1", "$src1, $src2",
3776 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>;
3777 let mayLoad = 1 in {
3778 defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3779 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3780 "$src2, $src1", "$src1, $src2",
3781 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>;
3785 multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode> {
3786 defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v16f32_info>,
3787 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
3788 EVEX_V512, EVEX_CD8<32, CD8VF>;
3789 defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f64_info>,
3790 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v8f64_info>,
3791 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3792 defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f32x_info>,
3793 avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNode, SSE_ALU_ITINS_S.s>,
3794 EVEX_4V,EVEX_CD8<32, CD8VT1>;
3795 defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f64x_info>,
3796 avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNode, SSE_ALU_ITINS_S.d>,
3797 EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
3799 // Define only if AVX512VL feature is present.
3800 let Predicates = [HasVLX] in {
3801 defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f32x_info>,
3802 EVEX_V128, EVEX_CD8<32, CD8VF>;
3803 defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f32x_info>,
3804 EVEX_V256, EVEX_CD8<32, CD8VF>;
3805 defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v2f64x_info>,
3806 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
3807 defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f64x_info>,
3808 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
3811 defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef>, T8PD;
3813 //===----------------------------------------------------------------------===//
3814 // AVX-512 VPTESTM instructions
3815 //===----------------------------------------------------------------------===//
3817 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3818 X86VectorVTInfo _> {
3819 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3820 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3821 "$src2, $src1", "$src1, $src2",
3822 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3825 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3826 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3827 "$src2, $src1", "$src1, $src2",
3828 (OpNode (_.VT _.RC:$src1),
3829 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3831 EVEX_CD8<_.EltSize, CD8VF>;
3834 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3835 X86VectorVTInfo _> {
3837 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3838 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3839 "${src2}"##_.BroadcastStr##", $src1",
3840 "$src1, ${src2}"##_.BroadcastStr,
3841 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3842 (_.ScalarLdFrag addr:$src2))))>,
3843 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3845 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3846 AVX512VLVectorVTInfo _> {
3847 let Predicates = [HasAVX512] in
3848 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3849 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3851 let Predicates = [HasAVX512, HasVLX] in {
3852 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3853 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3854 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3855 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3859 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3860 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3862 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3863 avx512vl_i64_info>, VEX_W;
3866 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3868 let Predicates = [HasBWI] in {
3869 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3871 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3874 let Predicates = [HasVLX, HasBWI] in {
3876 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3878 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3880 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3882 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3887 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3889 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3890 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3892 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3893 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3895 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3896 (v16i32 VR512:$src2), (i16 -1))),
3897 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3899 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3900 (v8i64 VR512:$src2), (i8 -1))),
3901 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3903 //===----------------------------------------------------------------------===//
3904 // AVX-512 Shift instructions
3905 //===----------------------------------------------------------------------===//
3906 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3907 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3908 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3909 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3910 "$src2, $src1", "$src1, $src2",
3911 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3912 SSE_INTSHIFT_ITINS_P.rr>;
3914 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3915 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3916 "$src2, $src1", "$src1, $src2",
3917 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3919 SSE_INTSHIFT_ITINS_P.rm>;
3922 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3923 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3925 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3926 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3927 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3928 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3929 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
3932 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3933 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3934 // src2 is always 128-bit
3935 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3936 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3937 "$src2, $src1", "$src1, $src2",
3938 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3939 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3940 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3941 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3942 "$src2, $src1", "$src1, $src2",
3943 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3944 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
3948 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3949 ValueType SrcVT, PatFrag bc_frag,
3950 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
3951 let Predicates = [prd] in
3952 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3953 VTInfo.info512>, EVEX_V512,
3954 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
3955 let Predicates = [prd, HasVLX] in {
3956 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3957 VTInfo.info256>, EVEX_V256,
3958 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
3959 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3960 VTInfo.info128>, EVEX_V128,
3961 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
3965 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
3966 string OpcodeStr, SDNode OpNode> {
3967 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3968 avx512vl_i32_info, HasAVX512>;
3969 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3970 avx512vl_i64_info, HasAVX512>, VEX_W;
3971 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
3972 avx512vl_i16_info, HasBWI>;
3975 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3976 string OpcodeStr, SDNode OpNode,
3977 AVX512VLVectorVTInfo VTInfo> {
3978 let Predicates = [HasAVX512] in
3979 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3981 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3982 VTInfo.info512>, EVEX_V512;
3983 let Predicates = [HasAVX512, HasVLX] in {
3984 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3986 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3987 VTInfo.info256>, EVEX_V256;
3988 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3990 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3991 VTInfo.info128>, EVEX_V128;
3995 multiclass avx512_shift_rmi_w<bits<8> opcw,
3996 Format ImmFormR, Format ImmFormM,
3997 string OpcodeStr, SDNode OpNode> {
3998 let Predicates = [HasBWI] in
3999 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4000 v32i16_info>, EVEX_V512;
4001 let Predicates = [HasVLX, HasBWI] in {
4002 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4003 v16i16x_info>, EVEX_V256;
4004 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4005 v8i16x_info>, EVEX_V128;
4009 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
4010 Format ImmFormR, Format ImmFormM,
4011 string OpcodeStr, SDNode OpNode> {
4012 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
4013 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
4014 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
4015 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
4018 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
4019 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
4021 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
4022 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
4024 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
4025 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
4027 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>, AVX512BIi8Base, EVEX_4V;
4028 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
4030 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
4031 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
4032 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
4034 //===-------------------------------------------------------------------===//
4035 // Variable Bit Shifts
4036 //===-------------------------------------------------------------------===//
4037 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
4038 X86VectorVTInfo _> {
4039 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4040 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4041 "$src2, $src1", "$src1, $src2",
4042 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
4043 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
4045 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4046 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4047 "$src2, $src1", "$src1, $src2",
4048 (_.VT (OpNode _.RC:$src1,
4049 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
4050 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
4051 EVEX_CD8<_.EltSize, CD8VF>;
4054 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
4055 X86VectorVTInfo _> {
4057 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4058 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4059 "${src2}"##_.BroadcastStr##", $src1",
4060 "$src1, ${src2}"##_.BroadcastStr,
4061 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4062 (_.ScalarLdFrag addr:$src2))))),
4063 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
4064 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4066 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4067 AVX512VLVectorVTInfo _> {
4068 let Predicates = [HasAVX512] in
4069 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4070 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4072 let Predicates = [HasAVX512, HasVLX] in {
4073 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4074 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4075 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
4076 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
4080 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
4082 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
4084 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
4085 avx512vl_i64_info>, VEX_W;
4088 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
4090 let Predicates = [HasBWI] in
4091 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
4093 let Predicates = [HasVLX, HasBWI] in {
4095 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
4097 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
4102 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
4103 avx512_var_shift_w<0x12, "vpsllvw", shl>;
4104 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
4105 avx512_var_shift_w<0x11, "vpsravw", sra>;
4106 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
4107 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
4108 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
4109 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
4111 //===-------------------------------------------------------------------===//
4112 // 1-src variable permutation VPERMW/D/Q
4113 //===-------------------------------------------------------------------===//
4114 multiclass avx512_vperm_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4115 AVX512VLVectorVTInfo _> {
4116 let Predicates = [HasAVX512] in
4117 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4118 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4120 let Predicates = [HasAVX512, HasVLX] in
4121 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4122 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4125 multiclass avx512_vpermi_dq_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4126 string OpcodeStr, SDNode OpNode,
4127 AVX512VLVectorVTInfo VTInfo> {
4128 let Predicates = [HasAVX512] in
4129 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4131 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4132 VTInfo.info512>, EVEX_V512;
4133 let Predicates = [HasAVX512, HasVLX] in
4134 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4136 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4137 VTInfo.info256>, EVEX_V256;
4141 defm VPERM : avx512_var_shift_w<0x8D, "vpermw", X86VPermv>;
4143 defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv,
4145 defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv,
4146 avx512vl_i64_info>, VEX_W;
4147 defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv,
4149 defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv,
4150 avx512vl_f64_info>, VEX_W;
4152 defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq",
4153 X86VPermi, avx512vl_i64_info>,
4154 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4155 defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
4156 X86VPermi, avx512vl_f64_info>,
4157 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4158 //===----------------------------------------------------------------------===//
4159 // AVX-512 - VPERMIL
4160 //===----------------------------------------------------------------------===//
4162 multiclass avx512_permil_vec<bits<8> OpcVar, string OpcodeStr, SDNode OpNode,
4163 X86VectorVTInfo _, X86VectorVTInfo Ctrl> {
4164 defm rr: AVX512_maskable<OpcVar, MRMSrcReg, _, (outs _.RC:$dst),
4165 (ins _.RC:$src1, Ctrl.RC:$src2), OpcodeStr,
4166 "$src2, $src1", "$src1, $src2",
4167 (_.VT (OpNode _.RC:$src1,
4168 (Ctrl.VT Ctrl.RC:$src2)))>,
4170 let mayLoad = 1 in {
4171 defm rm: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4172 (ins _.RC:$src1, Ctrl.MemOp:$src2), OpcodeStr,
4173 "$src2, $src1", "$src1, $src2",
4176 (Ctrl.VT (bitconvert(Ctrl.LdFrag addr:$src2)))))>,
4177 T8PD, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4178 defm rmb: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4179 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4180 "${src2}"##_.BroadcastStr##", $src1",
4181 "$src1, ${src2}"##_.BroadcastStr,
4184 (Ctrl.VT (X86VBroadcast
4185 (Ctrl.ScalarLdFrag addr:$src2)))))>,
4186 T8PD, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
4190 multiclass avx512_permil_vec_common<string OpcodeStr, bits<8> OpcVar,
4191 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4192 let Predicates = [HasAVX512] in {
4193 defm Z : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info512,
4194 Ctrl.info512>, EVEX_V512;
4196 let Predicates = [HasAVX512, HasVLX] in {
4197 defm Z128 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info128,
4198 Ctrl.info128>, EVEX_V128;
4199 defm Z256 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info256,
4200 Ctrl.info256>, EVEX_V256;
4204 multiclass avx512_permil<string OpcodeStr, bits<8> OpcImm, bits<8> OpcVar,
4205 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4207 defm NAME: avx512_permil_vec_common<OpcodeStr, OpcVar, _, Ctrl>;
4208 defm NAME: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem, OpcodeStr,
4210 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4212 let isCodeGenOnly = 1 in {
4213 // lowering implementation with the alternative types
4214 defm NAME#_I: avx512_permil_vec_common<OpcodeStr, OpcVar, Ctrl, Ctrl>;
4215 defm NAME#_I: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem,
4216 OpcodeStr, X86VPermilpi, Ctrl>,
4217 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4221 defm VPERMILPS : avx512_permil<"vpermilps", 0x04, 0x0C, avx512vl_f32_info,
4223 defm VPERMILPD : avx512_permil<"vpermilpd", 0x05, 0x0D, avx512vl_f64_info,
4224 avx512vl_i64_info>, VEX_W;
4225 //===----------------------------------------------------------------------===//
4226 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
4227 //===----------------------------------------------------------------------===//
4229 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
4230 X86PShufd, avx512vl_i32_info>,
4231 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
4232 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
4233 X86PShufhw>, EVEX, AVX512XSIi8Base;
4234 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
4235 X86PShuflw>, EVEX, AVX512XDIi8Base;
4237 multiclass avx512_pshufb_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4238 let Predicates = [HasBWI] in
4239 defm Z: avx512_var_shift<opc, OpcodeStr, OpNode, v64i8_info>, EVEX_V512;
4241 let Predicates = [HasVLX, HasBWI] in {
4242 defm Z256: avx512_var_shift<opc, OpcodeStr, OpNode, v32i8x_info>, EVEX_V256;
4243 defm Z128: avx512_var_shift<opc, OpcodeStr, OpNode, v16i8x_info>, EVEX_V128;
4247 defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb>;
4249 //===----------------------------------------------------------------------===//
4250 // Move Low to High and High to Low packed FP Instructions
4251 //===----------------------------------------------------------------------===//
4252 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
4253 (ins VR128X:$src1, VR128X:$src2),
4254 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4255 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
4256 IIC_SSE_MOV_LH>, EVEX_4V;
4257 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
4258 (ins VR128X:$src1, VR128X:$src2),
4259 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4260 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
4261 IIC_SSE_MOV_LH>, EVEX_4V;
4263 let Predicates = [HasAVX512] in {
4265 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4266 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
4267 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4268 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
4271 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
4272 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
4275 //===----------------------------------------------------------------------===//
4276 // VMOVHPS/PD VMOVLPS Instructions
4277 // All patterns was taken from SSS implementation.
4278 //===----------------------------------------------------------------------===//
4279 multiclass avx512_mov_hilo_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
4280 X86VectorVTInfo _> {
4282 def rm : AVX512<opc, MRMSrcMem, (outs _.RC:$dst),
4283 (ins _.RC:$src1, f64mem:$src2),
4284 !strconcat(OpcodeStr,
4285 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4289 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))))))],
4290 IIC_SSE_MOV_LH>, EVEX_4V;
4293 defm VMOVHPSZ128 : avx512_mov_hilo_packed<0x16, "vmovhps", X86Movlhps,
4294 v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS;
4295 defm VMOVHPDZ128 : avx512_mov_hilo_packed<0x16, "vmovhpd", X86Movlhpd,
4296 v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W;
4297 defm VMOVLPSZ128 : avx512_mov_hilo_packed<0x12, "vmovlps", X86Movlps,
4298 v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS;
4299 defm VMOVLPDZ128 : avx512_mov_hilo_packed<0x12, "vmovlpd", X86Movlpd,
4300 v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W;
4302 let Predicates = [HasAVX512] in {
4304 def : Pat<(X86Movlhps VR128X:$src1,
4305 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
4306 (VMOVHPSZ128rm VR128X:$src1, addr:$src2)>;
4307 def : Pat<(X86Movlhps VR128X:$src1,
4308 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
4309 (VMOVHPSZ128rm VR128X:$src1, addr:$src2)>;
4311 def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
4312 (scalar_to_vector (loadf64 addr:$src2)))),
4313 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
4314 def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
4315 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
4316 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
4318 def : Pat<(v4f32 (X86Movlps VR128X:$src1, (load addr:$src2))),
4319 (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
4320 def : Pat<(v4i32 (X86Movlps VR128X:$src1, (load addr:$src2))),
4321 (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
4323 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, (load addr:$src2))),
4324 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4325 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, (load addr:$src2))),
4326 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4327 def : Pat<(v2f64 (X86Movsd VR128X:$src1,
4328 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
4329 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4332 let mayStore = 1 in {
4333 def VMOVHPSZ128mr : AVX512PSI<0x17, MRMDestMem, (outs),
4334 (ins f64mem:$dst, VR128X:$src),
4335 "vmovhps\t{$src, $dst|$dst, $src}",
4336 [(store (f64 (vector_extract
4337 (X86Unpckh (bc_v2f64 (v4f32 VR128X:$src)),
4338 (bc_v2f64 (v4f32 VR128X:$src))),
4339 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>,
4340 EVEX, EVEX_CD8<32, CD8VT2>;
4341 def VMOVHPDZ128mr : AVX512PDI<0x17, MRMDestMem, (outs),
4342 (ins f64mem:$dst, VR128X:$src),
4343 "vmovhpd\t{$src, $dst|$dst, $src}",
4344 [(store (f64 (vector_extract
4345 (v2f64 (X86Unpckh VR128X:$src, VR128X:$src)),
4346 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>,
4347 EVEX, EVEX_CD8<64, CD8VT1>, VEX_W;
4348 def VMOVLPSZ128mr : AVX512PSI<0x13, MRMDestMem, (outs),
4349 (ins f64mem:$dst, VR128X:$src),
4350 "vmovlps\t{$src, $dst|$dst, $src}",
4351 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128X:$src)),
4352 (iPTR 0))), addr:$dst)],
4354 EVEX, EVEX_CD8<32, CD8VT2>;
4355 def VMOVLPDZ128mr : AVX512PDI<0x13, MRMDestMem, (outs),
4356 (ins f64mem:$dst, VR128X:$src),
4357 "vmovlpd\t{$src, $dst|$dst, $src}",
4358 [(store (f64 (vector_extract (v2f64 VR128X:$src),
4359 (iPTR 0))), addr:$dst)],
4361 EVEX, EVEX_CD8<64, CD8VT1>, VEX_W;
4363 let Predicates = [HasAVX512] in {
4365 def : Pat<(store (f64 (vector_extract
4366 (v2f64 (X86VPermilpi VR128X:$src, (i8 1))),
4367 (iPTR 0))), addr:$dst),
4368 (VMOVHPDZ128mr addr:$dst, VR128X:$src)>;
4370 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128X:$src2)),
4372 (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
4373 def : Pat<(store (v4i32 (X86Movlps
4374 (bc_v4i32 (loadv2i64 addr:$src1)), VR128X:$src2)), addr:$src1),
4375 (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
4377 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128X:$src2)),
4379 (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
4380 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128X:$src2)),
4382 (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
4384 //===----------------------------------------------------------------------===//
4385 // FMA - Fused Multiply Operations
4388 let Constraints = "$src1 = $dst" in {
4389 multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4390 X86VectorVTInfo _> {
4391 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4392 (ins _.RC:$src2, _.RC:$src3),
4393 OpcodeStr, "$src3, $src2", "$src2, $src3",
4394 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4397 let mayLoad = 1 in {
4398 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4399 (ins _.RC:$src2, _.MemOp:$src3),
4400 OpcodeStr, "$src3, $src2", "$src2, $src3",
4401 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
4404 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4405 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4406 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
4407 !strconcat("$src2, ${src3}", _.BroadcastStr ),
4409 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
4410 AVX512FMA3Base, EVEX_B;
4414 multiclass avx512_fma3_213_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4415 X86VectorVTInfo _> {
4416 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4417 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4418 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4419 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4420 AVX512FMA3Base, EVEX_B, EVEX_RC;
4422 } // Constraints = "$src1 = $dst"
4424 multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4425 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4426 let Predicates = [HasAVX512] in {
4427 defm Z : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info512>,
4428 avx512_fma3_213_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4429 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4431 let Predicates = [HasVLX, HasAVX512] in {
4432 defm Z256 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info256>,
4433 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4434 defm Z128 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info128>,
4435 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4439 multiclass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4440 SDNode OpNodeRnd > {
4441 defm PS : avx512_fma3p_213_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4443 defm PD : avx512_fma3p_213_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4444 avx512vl_f64_info>, VEX_W;
4447 defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86Fmadd, X86FmaddRnd>;
4448 defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86Fmsub, X86FmsubRnd>;
4449 defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub, X86FmaddsubRnd>;
4450 defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd, X86FmsubaddRnd>;
4451 defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86Fnmadd, X86FnmaddRnd>;
4452 defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86Fnmsub, X86FnmsubRnd>;
4455 let Constraints = "$src1 = $dst" in {
4456 multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4457 X86VectorVTInfo _> {
4458 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4459 (ins _.RC:$src2, _.RC:$src3),
4460 OpcodeStr, "$src3, $src2", "$src2, $src3",
4461 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1))>,
4464 let mayLoad = 1 in {
4465 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4466 (ins _.RC:$src2, _.MemOp:$src3),
4467 OpcodeStr, "$src3, $src2", "$src2, $src3",
4468 (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1))>,
4471 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4472 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4473 OpcodeStr, "${src3}"##_.BroadcastStr##", $src2",
4474 "$src2, ${src3}"##_.BroadcastStr,
4475 (_.VT (OpNode _.RC:$src2,
4476 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
4477 _.RC:$src1))>, AVX512FMA3Base, EVEX_B;
4481 multiclass avx512_fma3_231_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4482 X86VectorVTInfo _> {
4483 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4484 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4485 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4486 (_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc)))>,
4487 AVX512FMA3Base, EVEX_B, EVEX_RC;
4489 } // Constraints = "$src1 = $dst"
4491 multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4492 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4493 let Predicates = [HasAVX512] in {
4494 defm Z : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info512>,
4495 avx512_fma3_231_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4496 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4498 let Predicates = [HasVLX, HasAVX512] in {
4499 defm Z256 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info256>,
4500 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4501 defm Z128 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info128>,
4502 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4506 multiclass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4507 SDNode OpNodeRnd > {
4508 defm PS : avx512_fma3p_231_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4510 defm PD : avx512_fma3p_231_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4511 avx512vl_f64_info>, VEX_W;
4514 defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86Fmadd, X86FmaddRnd>;
4515 defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86Fmsub, X86FmsubRnd>;
4516 defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub, X86FmaddsubRnd>;
4517 defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd, X86FmsubaddRnd>;
4518 defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86Fnmadd, X86FnmaddRnd>;
4519 defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86Fnmsub, X86FnmsubRnd>;
4521 let Constraints = "$src1 = $dst" in {
4522 multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4523 X86VectorVTInfo _> {
4524 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4525 (ins _.RC:$src3, _.RC:$src2),
4526 OpcodeStr, "$src2, $src3", "$src3, $src2",
4527 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4530 let mayLoad = 1 in {
4531 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4532 (ins _.RC:$src3, _.MemOp:$src2),
4533 OpcodeStr, "$src2, $src3", "$src3, $src2",
4534 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2), _.RC:$src3))>,
4537 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4538 (ins _.RC:$src3, _.ScalarMemOp:$src2),
4539 OpcodeStr, "${src2}"##_.BroadcastStr##", $src3",
4540 "$src3, ${src2}"##_.BroadcastStr,
4541 (_.VT (OpNode _.RC:$src1,
4542 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
4543 _.RC:$src3))>, AVX512FMA3Base, EVEX_B;
4547 multiclass avx512_fma3_132_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4548 X86VectorVTInfo _> {
4549 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4550 (ins _.RC:$src3, _.RC:$src2, AVX512RC:$rc),
4551 OpcodeStr, "$rc, $src2, $src3", "$src3, $src2, $rc",
4552 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4553 AVX512FMA3Base, EVEX_B, EVEX_RC;
4555 } // Constraints = "$src1 = $dst"
4557 multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4558 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4559 let Predicates = [HasAVX512] in {
4560 defm Z : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info512>,
4561 avx512_fma3_132_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4562 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4564 let Predicates = [HasVLX, HasAVX512] in {
4565 defm Z256 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info256>,
4566 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4567 defm Z128 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info128>,
4568 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4572 multiclass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4573 SDNode OpNodeRnd > {
4574 defm PS : avx512_fma3p_132_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4576 defm PD : avx512_fma3p_132_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4577 avx512vl_f64_info>, VEX_W;
4580 defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86Fmadd, X86FmaddRnd>;
4581 defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86Fmsub, X86FmsubRnd>;
4582 defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub, X86FmaddsubRnd>;
4583 defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd, X86FmsubaddRnd>;
4584 defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86Fnmadd, X86FnmaddRnd>;
4585 defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubRnd>;
4588 let Constraints = "$src1 = $dst" in {
4589 multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4590 dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
4591 dag RHS_r, dag RHS_m > {
4592 defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4593 (ins _.RC:$src2, _.RC:$src3), OpcodeStr,
4594 "$src3, $src2", "$src2, $src3", RHS_VEC_r>, AVX512FMA3Base;
4597 defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4598 (ins _.RC:$src2, _.MemOp:$src3), OpcodeStr,
4599 "$src3, $src2", "$src2, $src3", RHS_VEC_m>, AVX512FMA3Base;
4601 defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4602 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4603 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb>,
4604 AVX512FMA3Base, EVEX_B, EVEX_RC;
4606 let isCodeGenOnly = 1 in {
4607 def r : AVX512FMA3<opc, MRMSrcReg, (outs _.FRC:$dst),
4608 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
4609 !strconcat(OpcodeStr,
4610 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4613 def m : AVX512FMA3<opc, MRMSrcMem, (outs _.FRC:$dst),
4614 (ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
4615 !strconcat(OpcodeStr,
4616 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4618 }// isCodeGenOnly = 1
4620 }// Constraints = "$src1 = $dst"
4622 multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4623 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd, X86VectorVTInfo _ ,
4626 defm NAME#213#SUFF: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix , _ ,
4627 (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)),
4628 (_.VT (OpNode _.RC:$src2, _.RC:$src1,
4629 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))))),
4630 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src1, _.RC:$src3,
4632 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4634 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4635 (_.ScalarLdFrag addr:$src3))))>;
4637 defm NAME#231#SUFF: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix , _ ,
4638 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)),
4639 (_.VT (OpNode _.RC:$src2,
4640 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4642 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src3, _.RC:$src1,
4644 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
4646 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
4647 (_.ScalarLdFrag addr:$src3), _.FRC:$src1)))>;
4649 defm NAME#132#SUFF: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix , _ ,
4650 (_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)),
4651 (_.VT (OpNode _.RC:$src1,
4652 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4654 (_.VT ( OpNodeRnd _.RC:$src1, _.RC:$src3, _.RC:$src2,
4656 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
4658 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1,
4659 (_.ScalarLdFrag addr:$src3), _.FRC:$src2)))>;
4662 multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4663 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd>{
4664 let Predicates = [HasAVX512] in {
4665 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4666 OpNodeRnd, f32x_info, "SS">,
4667 EVEX_CD8<32, CD8VT1>, VEX_LIG;
4668 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4669 OpNodeRnd, f64x_info, "SD">,
4670 EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
4674 defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>;
4675 defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>;
4676 defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4677 defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4679 //===----------------------------------------------------------------------===//
4680 // AVX-512 Scalar convert from sign integer to float/double
4681 //===----------------------------------------------------------------------===//
4683 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4684 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4685 PatFrag ld_frag, string asm> {
4686 let hasSideEffects = 0 in {
4687 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
4688 (ins DstVT.FRC:$src1, SrcRC:$src),
4689 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4692 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
4693 (ins DstVT.FRC:$src1, x86memop:$src),
4694 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4696 } // hasSideEffects = 0
4697 let isCodeGenOnly = 1 in {
4698 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4699 (ins DstVT.RC:$src1, SrcRC:$src2),
4700 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4701 [(set DstVT.RC:$dst,
4702 (OpNode (DstVT.VT DstVT.RC:$src1),
4704 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4706 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
4707 (ins DstVT.RC:$src1, x86memop:$src2),
4708 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4709 [(set DstVT.RC:$dst,
4710 (OpNode (DstVT.VT DstVT.RC:$src1),
4711 (ld_frag addr:$src2),
4712 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4713 }//isCodeGenOnly = 1
4716 multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4717 X86VectorVTInfo DstVT, string asm> {
4718 def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4719 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
4721 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
4722 [(set DstVT.RC:$dst,
4723 (OpNode (DstVT.VT DstVT.RC:$src1),
4725 (i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
4728 multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4729 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4730 PatFrag ld_frag, string asm> {
4731 defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
4732 avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
4736 let Predicates = [HasAVX512] in {
4737 defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4738 v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
4739 XS, EVEX_CD8<32, CD8VT1>;
4740 defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4741 v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
4742 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4743 defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4744 v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
4745 XD, EVEX_CD8<32, CD8VT1>;
4746 defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4747 v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
4748 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4750 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4751 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4752 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4753 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4754 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4755 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4756 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4757 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4759 def : Pat<(f32 (sint_to_fp GR32:$src)),
4760 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4761 def : Pat<(f32 (sint_to_fp GR64:$src)),
4762 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4763 def : Pat<(f64 (sint_to_fp GR32:$src)),
4764 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4765 def : Pat<(f64 (sint_to_fp GR64:$src)),
4766 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4768 defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR32,
4769 v4f32x_info, i32mem, loadi32,
4770 "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
4771 defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4772 v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
4773 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4774 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86UintToFpRnd, GR32, v2f64x_info,
4775 i32mem, loadi32, "cvtusi2sd{l}">,
4776 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4777 defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4778 v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
4779 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4781 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4782 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4783 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4784 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4785 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4786 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4787 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4788 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4790 def : Pat<(f32 (uint_to_fp GR32:$src)),
4791 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4792 def : Pat<(f32 (uint_to_fp GR64:$src)),
4793 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4794 def : Pat<(f64 (uint_to_fp GR32:$src)),
4795 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4796 def : Pat<(f64 (uint_to_fp GR64:$src)),
4797 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4800 //===----------------------------------------------------------------------===//
4801 // AVX-512 Scalar convert from float/double to integer
4802 //===----------------------------------------------------------------------===//
4803 multiclass avx512_cvt_s_int_round<bits<8> opc, RegisterClass SrcRC,
4804 RegisterClass DstRC, Intrinsic Int,
4805 Operand memop, ComplexPattern mem_cpat, string asm> {
4806 let hasSideEffects = 0, Predicates = [HasAVX512] in {
4807 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4808 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4809 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
4810 def rb : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4811 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"), []>,
4812 EVEX, VEX_LIG, EVEX_B, EVEX_RC;
4814 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4815 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
4816 } // hasSideEffects = 0, Predicates = [HasAVX512]
4819 // Convert float/double to signed/unsigned int 32/64
4820 defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4821 ssmem, sse_load_f32, "cvtss2si">,
4822 XS, EVEX_CD8<32, CD8VT1>;
4823 defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4824 int_x86_sse_cvtss2si64,
4825 ssmem, sse_load_f32, "cvtss2si">,
4826 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4827 defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4828 int_x86_avx512_cvtss2usi,
4829 ssmem, sse_load_f32, "cvtss2usi">,
4830 XS, EVEX_CD8<32, CD8VT1>;
4831 defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4832 int_x86_avx512_cvtss2usi64, ssmem,
4833 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4834 EVEX_CD8<32, CD8VT1>;
4835 defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4836 sdmem, sse_load_f64, "cvtsd2si">,
4837 XD, EVEX_CD8<64, CD8VT1>;
4838 defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4839 int_x86_sse2_cvtsd2si64,
4840 sdmem, sse_load_f64, "cvtsd2si">,
4841 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4842 defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4843 int_x86_avx512_cvtsd2usi,
4844 sdmem, sse_load_f64, "cvtsd2usi">,
4845 XD, EVEX_CD8<64, CD8VT1>;
4846 defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4847 int_x86_avx512_cvtsd2usi64, sdmem,
4848 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4849 EVEX_CD8<64, CD8VT1>;
4851 let isCodeGenOnly = 1 , Predicates = [HasAVX512] in {
4852 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4853 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4854 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4855 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4856 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4857 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4858 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4859 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4860 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4861 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4862 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4863 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4865 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4866 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4867 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4868 } // isCodeGenOnly = 1, Predicates = [HasAVX512]
4870 // Convert float/double to signed/unsigned int 32/64 with truncation
4871 multiclass avx512_cvt_s_all<bits<8> opc, string asm, X86VectorVTInfo _SrcRC,
4872 X86VectorVTInfo _DstRC, SDNode OpNode,
4874 let Predicates = [HasAVX512] in {
4875 def rr : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4876 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4877 [(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))]>, EVEX;
4878 def rb : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4879 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4881 def rm : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.MemOp:$src),
4882 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4883 [(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src)))]>,
4886 let isCodeGenOnly = 1,hasSideEffects = 0 in {
4887 def rr_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4888 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4889 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4890 (i32 FROUND_CURRENT)))]>, EVEX, VEX_LIG;
4891 def rb_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4892 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4893 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4894 (i32 FROUND_NO_EXC)))]>,
4895 EVEX,VEX_LIG , EVEX_B;
4897 def rm_Int : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst),
4898 (ins _SrcRC.MemOp:$src),
4899 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4902 } // isCodeGenOnly = 1, hasSideEffects = 0
4907 defm VCVTTSS2SIZ: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i32x_info,
4908 fp_to_sint,X86cvttss2IntRnd>,
4909 XS, EVEX_CD8<32, CD8VT1>;
4910 defm VCVTTSS2SI64Z: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i64x_info,
4911 fp_to_sint,X86cvttss2IntRnd>,
4912 VEX_W, XS, EVEX_CD8<32, CD8VT1>;
4913 defm VCVTTSD2SIZ: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i32x_info,
4914 fp_to_sint,X86cvttsd2IntRnd>,
4915 XD, EVEX_CD8<64, CD8VT1>;
4916 defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i64x_info,
4917 fp_to_sint,X86cvttsd2IntRnd>,
4918 VEX_W, XD, EVEX_CD8<64, CD8VT1>;
4920 defm VCVTTSS2USIZ: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i32x_info,
4921 fp_to_uint,X86cvttss2UIntRnd>,
4922 XS, EVEX_CD8<32, CD8VT1>;
4923 defm VCVTTSS2USI64Z: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i64x_info,
4924 fp_to_uint,X86cvttss2UIntRnd>,
4925 XS,VEX_W, EVEX_CD8<32, CD8VT1>;
4926 defm VCVTTSD2USIZ: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i32x_info,
4927 fp_to_uint,X86cvttsd2UIntRnd>,
4928 XD, EVEX_CD8<64, CD8VT1>;
4929 defm VCVTTSD2USI64Z: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i64x_info,
4930 fp_to_uint,X86cvttsd2UIntRnd>,
4931 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4932 let Predicates = [HasAVX512] in {
4933 def : Pat<(i32 (int_x86_sse_cvttss2si (v4f32 VR128X:$src))),
4934 (VCVTTSS2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
4935 def : Pat<(i64 (int_x86_sse_cvttss2si64 (v4f32 VR128X:$src))),
4936 (VCVTTSS2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
4937 def : Pat<(i32 (int_x86_sse2_cvttsd2si (v2f64 VR128X:$src))),
4938 (VCVTTSD2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
4939 def : Pat<(i64 (int_x86_sse2_cvttsd2si64 (v2f64 VR128X:$src))),
4940 (VCVTTSD2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
4943 //===----------------------------------------------------------------------===//
4944 // AVX-512 Convert form float to double and back
4945 //===----------------------------------------------------------------------===//
4946 multiclass avx512_cvt_fp_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4947 X86VectorVTInfo _Src, SDNode OpNode> {
4948 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4949 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
4950 "$src2, $src1", "$src1, $src2",
4951 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
4952 (_Src.VT _Src.RC:$src2)))>,
4953 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
4954 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4955 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
4956 "$src2, $src1", "$src1, $src2",
4957 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
4958 (_Src.VT (scalar_to_vector
4959 (_Src.ScalarLdFrag addr:$src2)))))>,
4960 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>;
4963 // Scalar Coversion with SAE - suppress all exceptions
4964 multiclass avx512_cvt_fp_sae_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4965 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4966 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4967 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
4968 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
4969 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
4970 (_Src.VT _Src.RC:$src2),
4971 (i32 FROUND_NO_EXC)))>,
4972 EVEX_4V, VEX_LIG, EVEX_B;
4975 // Scalar Conversion with rounding control (RC)
4976 multiclass avx512_cvt_fp_rc_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4977 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4978 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4979 (ins _Src.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr,
4980 "$rc, $src2, $src1", "$src1, $src2, $rc",
4981 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
4982 (_Src.VT _Src.RC:$src2), (i32 imm:$rc)))>,
4983 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
4986 multiclass avx512_cvt_fp_scalar_sd2ss<bits<8> opc, string OpcodeStr, SDNode OpNode,
4987 SDNode OpNodeRnd, X86VectorVTInfo _src,
4988 X86VectorVTInfo _dst> {
4989 let Predicates = [HasAVX512] in {
4990 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
4991 avx512_cvt_fp_rc_scalar<opc, OpcodeStr, _dst, _src,
4992 OpNodeRnd>, VEX_W, EVEX_CD8<64, CD8VT1>,
4997 multiclass avx512_cvt_fp_scalar_ss2sd<bits<8> opc, string OpcodeStr, SDNode OpNode,
4998 SDNode OpNodeRnd, X86VectorVTInfo _src,
4999 X86VectorVTInfo _dst> {
5000 let Predicates = [HasAVX512] in {
5001 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
5002 avx512_cvt_fp_sae_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>,
5003 EVEX_CD8<32, CD8VT1>, XS, EVEX_V512;
5006 defm VCVTSD2SS : avx512_cvt_fp_scalar_sd2ss<0x5A, "vcvtsd2ss", X86fround,
5007 X86froundRnd, f64x_info, f32x_info>;
5008 defm VCVTSS2SD : avx512_cvt_fp_scalar_ss2sd<0x5A, "vcvtss2sd", X86fpext,
5009 X86fpextRnd,f32x_info, f64x_info >;
5011 def : Pat<(f64 (fextend FR32X:$src)),
5012 (COPY_TO_REGCLASS (VCVTSS2SDZrr (COPY_TO_REGCLASS FR32X:$src, VR128X),
5013 (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>,
5014 Requires<[HasAVX512]>;
5015 def : Pat<(f64 (fextend (loadf32 addr:$src))),
5016 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5017 Requires<[HasAVX512]>;
5019 def : Pat<(f64 (extloadf32 addr:$src)),
5020 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5021 Requires<[HasAVX512, OptForSize]>;
5023 def : Pat<(f64 (extloadf32 addr:$src)),
5024 (COPY_TO_REGCLASS (VCVTSS2SDZrr (v4f32 (IMPLICIT_DEF)),
5025 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)), VR128X)>,
5026 Requires<[HasAVX512, OptForSpeed]>;
5028 def : Pat<(f32 (fround FR64X:$src)),
5029 (COPY_TO_REGCLASS (VCVTSD2SSZrr (COPY_TO_REGCLASS FR64X:$src, VR128X),
5030 (COPY_TO_REGCLASS FR64X:$src, VR128X)), VR128X)>,
5031 Requires<[HasAVX512]>;
5032 //===----------------------------------------------------------------------===//
5033 // AVX-512 Vector convert from signed/unsigned integer to float/double
5034 // and from float/double to signed/unsigned integer
5035 //===----------------------------------------------------------------------===//
5037 multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5038 X86VectorVTInfo _Src, SDNode OpNode,
5039 string Broadcast = _.BroadcastStr,
5040 string Alias = ""> {
5042 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5043 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
5044 (_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
5046 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5047 (ins _Src.MemOp:$src), OpcodeStr#Alias, "$src", "$src",
5048 (_.VT (OpNode (_Src.VT
5049 (bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
5051 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5052 (ins _Src.MemOp:$src), OpcodeStr,
5053 "${src}"##Broadcast, "${src}"##Broadcast,
5054 (_.VT (OpNode (_Src.VT
5055 (X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
5058 // Coversion with SAE - suppress all exceptions
5059 multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5060 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5061 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5062 (ins _Src.RC:$src), OpcodeStr,
5063 "{sae}, $src", "$src, {sae}",
5064 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src),
5065 (i32 FROUND_NO_EXC)))>,
5069 // Conversion with rounding control (RC)
5070 multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5071 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5072 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5073 (ins _Src.RC:$src, AVX512RC:$rc), OpcodeStr,
5074 "$rc, $src", "$src, $rc",
5075 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc)))>,
5076 EVEX, EVEX_B, EVEX_RC;
5079 // Extend Float to Double
5080 multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
5081 let Predicates = [HasAVX512] in {
5082 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fextend>,
5083 avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
5084 X86vfpextRnd>, EVEX_V512;
5086 let Predicates = [HasVLX] in {
5087 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
5088 X86vfpext, "{1to2}">, EVEX_V128;
5089 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fextend>,
5094 // Truncate Double to Float
5095 multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
5096 let Predicates = [HasAVX512] in {
5097 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fround>,
5098 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
5099 X86vfproundRnd>, EVEX_V512;
5101 let Predicates = [HasVLX] in {
5102 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
5103 X86vfpround, "{1to2}", "{x}">, EVEX_V128;
5104 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fround,
5105 "{1to4}", "{y}">, EVEX_V256;
5109 defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps">,
5110 VEX_W, PD, EVEX_CD8<64, CD8VF>;
5111 defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd">,
5112 PS, EVEX_CD8<32, CD8VH>;
5114 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5115 (VCVTPS2PDZrm addr:$src)>;
5117 let Predicates = [HasVLX] in {
5118 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
5119 (VCVTPS2PDZ256rm addr:$src)>;
5122 // Convert Signed/Unsigned Doubleword to Double
5123 multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
5125 // No rounding in this op
5126 let Predicates = [HasAVX512] in
5127 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode>,
5130 let Predicates = [HasVLX] in {
5131 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
5132 OpNode128, "{1to2}">, EVEX_V128;
5133 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
5138 // Convert Signed/Unsigned Doubleword to Float
5139 multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
5141 let Predicates = [HasAVX512] in
5142 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode>,
5143 avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
5144 OpNodeRnd>, EVEX_V512;
5146 let Predicates = [HasVLX] in {
5147 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode>,
5149 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode>,
5154 // Convert Float to Signed/Unsigned Doubleword with truncation
5155 multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr,
5156 SDNode OpNode, SDNode OpNodeRnd> {
5157 let Predicates = [HasAVX512] in {
5158 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5159 avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
5160 OpNodeRnd>, EVEX_V512;
5162 let Predicates = [HasVLX] in {
5163 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5165 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5170 // Convert Float to Signed/Unsigned Doubleword
5171 multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr,
5172 SDNode OpNode, SDNode OpNodeRnd> {
5173 let Predicates = [HasAVX512] in {
5174 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5175 avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
5176 OpNodeRnd>, EVEX_V512;
5178 let Predicates = [HasVLX] in {
5179 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5181 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5186 // Convert Double to Signed/Unsigned Doubleword with truncation
5187 multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr,
5188 SDNode OpNode, SDNode OpNodeRnd> {
5189 let Predicates = [HasAVX512] in {
5190 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5191 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
5192 OpNodeRnd>, EVEX_V512;
5194 let Predicates = [HasVLX] in {
5195 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5196 // memory forms of these instructions in Asm Parcer. They have the same
5197 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5198 // due to the same reason.
5199 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5200 "{1to2}", "{x}">, EVEX_V128;
5201 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5202 "{1to4}", "{y}">, EVEX_V256;
5206 // Convert Double to Signed/Unsigned Doubleword
5207 multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr,
5208 SDNode OpNode, SDNode OpNodeRnd> {
5209 let Predicates = [HasAVX512] in {
5210 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5211 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
5212 OpNodeRnd>, EVEX_V512;
5214 let Predicates = [HasVLX] in {
5215 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5216 // memory forms of these instructions in Asm Parcer. They have the same
5217 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5218 // due to the same reason.
5219 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5220 "{1to2}", "{x}">, EVEX_V128;
5221 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5222 "{1to4}", "{y}">, EVEX_V256;
5226 // Convert Double to Signed/Unsigned Quardword
5227 multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr,
5228 SDNode OpNode, SDNode OpNodeRnd> {
5229 let Predicates = [HasDQI] in {
5230 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5231 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
5232 OpNodeRnd>, EVEX_V512;
5234 let Predicates = [HasDQI, HasVLX] in {
5235 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5237 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5242 // Convert Double to Signed/Unsigned Quardword with truncation
5243 multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr,
5244 SDNode OpNode, SDNode OpNodeRnd> {
5245 let Predicates = [HasDQI] in {
5246 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5247 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
5248 OpNodeRnd>, EVEX_V512;
5250 let Predicates = [HasDQI, HasVLX] in {
5251 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5253 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5258 // Convert Signed/Unsigned Quardword to Double
5259 multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr,
5260 SDNode OpNode, SDNode OpNodeRnd> {
5261 let Predicates = [HasDQI] in {
5262 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode>,
5263 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
5264 OpNodeRnd>, EVEX_V512;
5266 let Predicates = [HasDQI, HasVLX] in {
5267 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode>,
5269 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode>,
5274 // Convert Float to Signed/Unsigned Quardword
5275 multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr,
5276 SDNode OpNode, SDNode OpNodeRnd> {
5277 let Predicates = [HasDQI] in {
5278 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5279 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
5280 OpNodeRnd>, EVEX_V512;
5282 let Predicates = [HasDQI, HasVLX] in {
5283 // Explicitly specified broadcast string, since we take only 2 elements
5284 // from v4f32x_info source
5285 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5286 "{1to2}">, EVEX_V128;
5287 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5292 // Convert Float to Signed/Unsigned Quardword with truncation
5293 multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr,
5294 SDNode OpNode, SDNode OpNodeRnd> {
5295 let Predicates = [HasDQI] in {
5296 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5297 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
5298 OpNodeRnd>, EVEX_V512;
5300 let Predicates = [HasDQI, HasVLX] in {
5301 // Explicitly specified broadcast string, since we take only 2 elements
5302 // from v4f32x_info source
5303 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5304 "{1to2}">, EVEX_V128;
5305 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5310 // Convert Signed/Unsigned Quardword to Float
5311 multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
5312 SDNode OpNode, SDNode OpNodeRnd> {
5313 let Predicates = [HasDQI] in {
5314 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
5315 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
5316 OpNodeRnd>, EVEX_V512;
5318 let Predicates = [HasDQI, HasVLX] in {
5319 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5320 // memory forms of these instructions in Asm Parcer. They have the same
5321 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5322 // due to the same reason.
5323 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode,
5324 "{1to2}", "{x}">, EVEX_V128;
5325 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
5326 "{1to4}", "{y}">, EVEX_V256;
5330 defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>, XS,
5331 EVEX_CD8<32, CD8VH>;
5333 defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
5335 PS, EVEX_CD8<32, CD8VF>;
5337 defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
5339 XS, EVEX_CD8<32, CD8VF>;
5341 defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint,
5343 PD, VEX_W, EVEX_CD8<64, CD8VF>;
5345 defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint,
5346 X86VFpToUintRnd>, PS,
5347 EVEX_CD8<32, CD8VF>;
5349 defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
5350 X86VFpToUintRnd>, PS, VEX_W,
5351 EVEX_CD8<64, CD8VF>;
5353 defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86cvtudq2pd>,
5354 XS, EVEX_CD8<32, CD8VH>;
5356 defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
5357 X86VUintToFpRnd>, XD,
5358 EVEX_CD8<32, CD8VF>;
5360 defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtps2Int,
5361 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
5363 defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtpd2Int,
5364 X86cvtpd2IntRnd>, XD, VEX_W,
5365 EVEX_CD8<64, CD8VF>;
5367 defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtps2UInt,
5369 PS, EVEX_CD8<32, CD8VF>;
5370 defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtpd2UInt,
5371 X86cvtpd2UIntRnd>, VEX_W,
5372 PS, EVEX_CD8<64, CD8VF>;
5374 defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtpd2Int,
5375 X86cvtpd2IntRnd>, VEX_W,
5376 PD, EVEX_CD8<64, CD8VF>;
5378 defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtps2Int,
5379 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
5381 defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtpd2UInt,
5382 X86cvtpd2UIntRnd>, VEX_W,
5383 PD, EVEX_CD8<64, CD8VF>;
5385 defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtps2UInt,
5386 X86cvtps2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
5388 defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint,
5389 X86VFpToSlongRnd>, VEX_W,
5390 PD, EVEX_CD8<64, CD8VF>;
5392 defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint,
5393 X86VFpToSlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5395 defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint,
5396 X86VFpToUlongRnd>, VEX_W,
5397 PD, EVEX_CD8<64, CD8VF>;
5399 defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint,
5400 X86VFpToUlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5402 defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
5403 X86VSlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5405 defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
5406 X86VUlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5408 defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp,
5409 X86VSlongToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
5411 defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
5412 X86VUlongToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
5414 let Predicates = [NoVLX] in {
5415 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
5416 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5417 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5419 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
5420 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5421 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5423 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
5424 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5425 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5427 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
5428 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5429 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5431 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
5432 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
5433 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
5436 let Predicates = [HasAVX512] in {
5437 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
5438 (VCVTPD2PSZrm addr:$src)>;
5439 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5440 (VCVTPS2PDZrm addr:$src)>;
5443 //===----------------------------------------------------------------------===//
5444 // Half precision conversion instructions
5445 //===----------------------------------------------------------------------===//
5446 multiclass avx512_cvtph2ps<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5447 X86MemOperand x86memop, PatFrag ld_frag> {
5448 defm rr : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5449 "vcvtph2ps", "$src", "$src",
5450 (X86cvtph2ps (_src.VT _src.RC:$src),
5451 (i32 FROUND_CURRENT))>, T8PD;
5452 let hasSideEffects = 0, mayLoad = 1 in {
5453 defm rm : AVX512_maskable<0x13, MRMSrcMem, _dest, (outs _dest.RC:$dst), (ins x86memop:$src),
5454 "vcvtph2ps", "$src", "$src",
5455 (X86cvtph2ps (_src.VT (bitconvert (ld_frag addr:$src))),
5456 (i32 FROUND_CURRENT))>, T8PD;
5460 multiclass avx512_cvtph2ps_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
5461 defm rb : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5462 "vcvtph2ps", "{sae}, $src", "$src, {sae}",
5463 (X86cvtph2ps (_src.VT _src.RC:$src),
5464 (i32 FROUND_NO_EXC))>, T8PD, EVEX_B;
5468 let Predicates = [HasAVX512] in {
5469 defm VCVTPH2PSZ : avx512_cvtph2ps<v16f32_info, v16i16x_info, f256mem, loadv4i64>,
5470 avx512_cvtph2ps_sae<v16f32_info, v16i16x_info>,
5471 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5472 let Predicates = [HasVLX] in {
5473 defm VCVTPH2PSZ256 : avx512_cvtph2ps<v8f32x_info, v8i16x_info, f128mem,
5474 loadv2i64>,EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5475 defm VCVTPH2PSZ128 : avx512_cvtph2ps<v4f32x_info, v8i16x_info, f64mem,
5476 loadv2i64>, EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5480 multiclass avx512_cvtps2ph<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5481 X86MemOperand x86memop> {
5482 defm rr : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
5483 (ins _src.RC:$src1, i32u8imm:$src2),
5484 "vcvtps2ph", "$src2, $src1", "$src1, $src2",
5485 (X86cvtps2ph (_src.VT _src.RC:$src1),
5487 (i32 FROUND_CURRENT))>, AVX512AIi8Base;
5488 let hasSideEffects = 0, mayStore = 1 in {
5489 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
5490 (ins x86memop:$dst, _src.RC:$src1, i32u8imm:$src2),
5491 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5492 [(store (_dest.VT (X86cvtps2ph (_src.VT _src.RC:$src1),
5493 (i32 imm:$src2), (i32 FROUND_CURRENT) )),
5495 def mrk : AVX512AIi8<0x1D, MRMDestMem, (outs),
5496 (ins x86memop:$dst, _dest.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2),
5497 "vcvtps2ph\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
5501 multiclass avx512_cvtps2ph_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
5502 defm rb : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
5503 (ins _src.RC:$src1, i32u8imm:$src2),
5504 "vcvtps2ph", "$src2, {sae}, $src1", "$src1, $src2, {sae}",
5505 (X86cvtps2ph (_src.VT _src.RC:$src1),
5507 (i32 FROUND_NO_EXC))>, EVEX_B, AVX512AIi8Base;
5509 let Predicates = [HasAVX512] in {
5510 defm VCVTPS2PHZ : avx512_cvtps2ph<v16i16x_info, v16f32_info, f256mem>,
5511 avx512_cvtps2ph_sae<v16i16x_info, v16f32_info>,
5512 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5513 let Predicates = [HasVLX] in {
5514 defm VCVTPS2PHZ256 : avx512_cvtps2ph<v8i16x_info, v8f32x_info, f128mem>,
5515 EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5516 defm VCVTPS2PHZ128 : avx512_cvtps2ph<v8i16x_info, v4f32x_info, f128mem>,
5517 EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5520 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5521 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
5522 "ucomiss">, PS, EVEX, VEX_LIG,
5523 EVEX_CD8<32, CD8VT1>;
5524 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
5525 "ucomisd">, PD, EVEX,
5526 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5527 let Pattern = []<dag> in {
5528 defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32,
5529 "comiss">, PS, EVEX, VEX_LIG,
5530 EVEX_CD8<32, CD8VT1>;
5531 defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64,
5532 "comisd">, PD, EVEX,
5533 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5535 let isCodeGenOnly = 1 in {
5536 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
5537 load, "ucomiss">, PS, EVEX, VEX_LIG,
5538 EVEX_CD8<32, CD8VT1>;
5539 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
5540 load, "ucomisd">, PD, EVEX,
5541 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5543 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
5544 load, "comiss">, PS, EVEX, VEX_LIG,
5545 EVEX_CD8<32, CD8VT1>;
5546 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
5547 load, "comisd">, PD, EVEX,
5548 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5552 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
5553 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
5554 X86VectorVTInfo _> {
5555 let hasSideEffects = 0, AddedComplexity = 20 , Predicates = [HasAVX512] in {
5556 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5557 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5558 "$src2, $src1", "$src1, $src2",
5559 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>, EVEX_4V;
5560 let mayLoad = 1 in {
5561 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5562 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5563 "$src2, $src1", "$src1, $src2",
5564 (OpNode (_.VT _.RC:$src1),
5565 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))))>, EVEX_4V;
5570 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", X86frcp14s, f32x_info>,
5571 EVEX_CD8<32, CD8VT1>, T8PD;
5572 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", X86frcp14s, f64x_info>,
5573 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5574 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", X86frsqrt14s, f32x_info>,
5575 EVEX_CD8<32, CD8VT1>, T8PD;
5576 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", X86frsqrt14s, f64x_info>,
5577 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5579 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
5580 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
5581 X86VectorVTInfo _> {
5582 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5583 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5584 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
5585 let mayLoad = 1 in {
5586 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5587 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5589 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
5590 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5591 (ins _.ScalarMemOp:$src), OpcodeStr,
5592 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5594 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5599 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5600 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
5601 EVEX_V512, EVEX_CD8<32, CD8VF>;
5602 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
5603 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5605 // Define only if AVX512VL feature is present.
5606 let Predicates = [HasVLX] in {
5607 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5608 OpNode, v4f32x_info>,
5609 EVEX_V128, EVEX_CD8<32, CD8VF>;
5610 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5611 OpNode, v8f32x_info>,
5612 EVEX_V256, EVEX_CD8<32, CD8VF>;
5613 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5614 OpNode, v2f64x_info>,
5615 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
5616 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5617 OpNode, v4f64x_info>,
5618 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
5622 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
5623 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
5625 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
5626 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5627 (VRSQRT14PSZr VR512:$src)>;
5628 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
5629 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5630 (VRSQRT14PDZr VR512:$src)>;
5632 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
5633 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5634 (VRCP14PSZr VR512:$src)>;
5635 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
5636 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5637 (VRCP14PDZr VR512:$src)>;
5639 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
5640 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5643 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5644 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5645 "$src2, $src1", "$src1, $src2",
5646 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5647 (i32 FROUND_CURRENT))>;
5649 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5650 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5651 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5652 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5653 (i32 FROUND_NO_EXC))>, EVEX_B;
5655 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5656 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5657 "$src2, $src1", "$src1, $src2",
5658 (OpNode (_.VT _.RC:$src1),
5659 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5660 (i32 FROUND_CURRENT))>;
5663 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5664 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
5665 EVEX_CD8<32, CD8VT1>;
5666 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
5667 EVEX_CD8<64, CD8VT1>, VEX_W;
5670 let hasSideEffects = 0, Predicates = [HasERI] in {
5671 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
5672 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
5675 defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds>, T8PD, EVEX_4V;
5676 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
5678 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5681 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5682 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5683 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
5685 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5686 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5688 (bitconvert (_.LdFrag addr:$src))),
5689 (i32 FROUND_CURRENT))>;
5691 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5692 (ins _.MemOp:$src), OpcodeStr,
5693 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5695 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
5696 (i32 FROUND_CURRENT))>, EVEX_B;
5698 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5700 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5701 (ins _.RC:$src), OpcodeStr,
5702 "{sae}, $src", "$src, {sae}",
5703 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
5706 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5707 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5708 avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5709 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
5710 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5711 avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5712 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5715 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
5717 // Define only if AVX512VL feature is present.
5718 let Predicates = [HasVLX] in {
5719 defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
5720 EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;
5721 defm PSZ256 : avx512_fp28_p<opc, OpcodeStr#"ps", v8f32x_info, OpNode>,
5722 EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>;
5723 defm PDZ128 : avx512_fp28_p<opc, OpcodeStr#"pd", v2f64x_info, OpNode>,
5724 EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5725 defm PDZ256 : avx512_fp28_p<opc, OpcodeStr#"pd", v4f64x_info, OpNode>,
5726 EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5729 let Predicates = [HasERI], hasSideEffects = 0 in {
5731 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX;
5732 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX;
5733 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX;
5735 defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
5736 avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
5738 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
5739 SDNode OpNodeRnd, X86VectorVTInfo _>{
5740 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5741 (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
5742 (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
5743 EVEX, EVEX_B, EVEX_RC;
5746 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
5747 SDNode OpNode, X86VectorVTInfo _>{
5748 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5749 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5750 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
5751 let mayLoad = 1 in {
5752 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5753 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5755 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
5757 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5758 (ins _.ScalarMemOp:$src), OpcodeStr,
5759 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5761 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5766 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
5768 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
5770 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5771 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
5773 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5774 // Define only if AVX512VL feature is present.
5775 let Predicates = [HasVLX] in {
5776 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5777 OpNode, v4f32x_info>,
5778 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
5779 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5780 OpNode, v8f32x_info>,
5781 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
5782 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5783 OpNode, v2f64x_info>,
5784 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5785 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5786 OpNode, v4f64x_info>,
5787 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5791 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
5793 defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
5794 v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5795 defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
5796 v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5799 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5800 string SUFF, SDNode OpNode, SDNode OpNodeRnd> {
5802 defm r_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5803 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5804 "$src2, $src1", "$src1, $src2",
5805 (OpNodeRnd (_.VT _.RC:$src1),
5807 (i32 FROUND_CURRENT))>;
5809 defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5810 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5811 "$src2, $src1", "$src1, $src2",
5812 (OpNodeRnd (_.VT _.RC:$src1),
5813 (_.VT (scalar_to_vector
5814 (_.ScalarLdFrag addr:$src2))),
5815 (i32 FROUND_CURRENT))>;
5817 defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5818 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
5819 "$rc, $src2, $src1", "$src1, $src2, $rc",
5820 (OpNodeRnd (_.VT _.RC:$src1),
5825 let isCodeGenOnly = 1 in {
5826 def r : SI<opc, MRMSrcReg, (outs _.FRC:$dst),
5827 (ins _.FRC:$src1, _.FRC:$src2),
5828 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5831 def m : SI<opc, MRMSrcMem, (outs _.FRC:$dst),
5832 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
5833 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5836 def : Pat<(_.EltVT (OpNode _.FRC:$src)),
5837 (!cast<Instruction>(NAME#SUFF#Zr)
5838 (_.EltVT (IMPLICIT_DEF)), _.FRC:$src)>;
5840 def : Pat<(_.EltVT (OpNode (load addr:$src))),
5841 (!cast<Instruction>(NAME#SUFF#Zm)
5842 (_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[OptForSize]>;
5845 multiclass avx512_sqrt_scalar_all<bits<8> opc, string OpcodeStr> {
5846 defm SSZ : avx512_sqrt_scalar<opc, OpcodeStr#"ss", f32x_info, "SS", fsqrt,
5847 X86fsqrtRnds>, EVEX_CD8<32, CD8VT1>, EVEX_4V, XS;
5848 defm SDZ : avx512_sqrt_scalar<opc, OpcodeStr#"sd", f64x_info, "SD", fsqrt,
5849 X86fsqrtRnds>, EVEX_CD8<64, CD8VT1>, EVEX_4V, XD, VEX_W;
5852 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>,
5853 avx512_sqrt_packed_all_round<0x51, "vsqrt", X86fsqrtRnd>;
5855 defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt">, VEX_LIG;
5857 let Predicates = [HasAVX512] in {
5858 def : Pat<(f32 (X86frsqrt FR32X:$src)),
5859 (COPY_TO_REGCLASS (VRSQRT14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>;
5860 def : Pat<(f32 (X86frsqrt (load addr:$src))),
5861 (COPY_TO_REGCLASS (VRSQRT14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5862 Requires<[OptForSize]>;
5863 def : Pat<(f32 (X86frcp FR32X:$src)),
5864 (COPY_TO_REGCLASS (VRCP14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X )>;
5865 def : Pat<(f32 (X86frcp (load addr:$src))),
5866 (COPY_TO_REGCLASS (VRCP14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5867 Requires<[OptForSize]>;
5871 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5873 let ExeDomain = _.ExeDomain in {
5874 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5875 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5876 "$src3, $src2, $src1", "$src1, $src2, $src3",
5877 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5878 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5880 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5881 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5882 "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
5883 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5884 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5887 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5888 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5889 "$src3, $src2, $src1", "$src1, $src2, $src3",
5890 (_.VT (X86RndScales (_.VT _.RC:$src1),
5891 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5892 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5894 let Predicates = [HasAVX512] in {
5895 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5896 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5897 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5898 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5899 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5900 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5901 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5902 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5903 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5904 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5905 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5906 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5907 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5908 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5909 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
5911 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5912 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5913 addr:$src, (i32 0x1))), _.FRC)>;
5914 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5915 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5916 addr:$src, (i32 0x2))), _.FRC)>;
5917 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5918 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5919 addr:$src, (i32 0x3))), _.FRC)>;
5920 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5921 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5922 addr:$src, (i32 0x4))), _.FRC)>;
5923 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5924 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5925 addr:$src, (i32 0xc))), _.FRC)>;
5929 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
5930 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5932 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
5933 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
5935 //-------------------------------------------------
5936 // Integer truncate and extend operations
5937 //-------------------------------------------------
5939 multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
5940 X86VectorVTInfo SrcInfo, X86VectorVTInfo DestInfo,
5941 X86MemOperand x86memop> {
5943 defm rr : AVX512_maskable<opc, MRMDestReg, DestInfo, (outs DestInfo.RC:$dst),
5944 (ins SrcInfo.RC:$src1), OpcodeStr ,"$src1", "$src1",
5945 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1)))>,
5948 // for intrinsic patter match
5949 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5950 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5952 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
5955 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5956 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5957 DestInfo.ImmAllZerosV)),
5958 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
5961 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5962 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5963 DestInfo.RC:$src0)),
5964 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrk) DestInfo.RC:$src0,
5965 DestInfo.KRCWM:$mask ,
5968 let mayStore = 1 in {
5969 def mr : AVX512XS8I<opc, MRMDestMem, (outs),
5970 (ins x86memop:$dst, SrcInfo.RC:$src),
5971 OpcodeStr # "\t{$src, $dst |$dst, $src}",
5974 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
5975 (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
5976 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5981 multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,
5982 X86VectorVTInfo DestInfo,
5983 PatFrag truncFrag, PatFrag mtruncFrag > {
5985 def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
5986 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr)
5987 addr:$dst, SrcInfo.RC:$src)>;
5989 def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask,
5990 (SrcInfo.VT SrcInfo.RC:$src)),
5991 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk)
5992 addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
5995 multiclass avx512_trunc_sat_mr_lowering<X86VectorVTInfo SrcInfo,
5996 X86VectorVTInfo DestInfo, string sat > {
5998 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
5999 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
6000 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), SrcInfo.MRC:$mask),
6001 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk) addr:$ptr,
6002 (COPY_TO_REGCLASS SrcInfo.MRC:$mask, SrcInfo.KRCWM),
6003 (SrcInfo.VT SrcInfo.RC:$src))>;
6005 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
6006 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
6007 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), -1),
6008 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr) addr:$ptr,
6009 (SrcInfo.VT SrcInfo.RC:$src))>;
6012 multiclass avx512_trunc<bits<8> opc, string OpcodeStr, SDNode OpNode,
6013 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
6014 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
6015 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
6016 X86MemOperand x86memopZ, PatFrag truncFrag, PatFrag mtruncFrag,
6017 Predicate prd = HasAVX512>{
6019 let Predicates = [HasVLX, prd] in {
6020 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
6021 DestInfoZ128, x86memopZ128>,
6022 avx512_trunc_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
6023 truncFrag, mtruncFrag>, EVEX_V128;
6025 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
6026 DestInfoZ256, x86memopZ256>,
6027 avx512_trunc_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
6028 truncFrag, mtruncFrag>, EVEX_V256;
6030 let Predicates = [prd] in
6031 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
6032 DestInfoZ, x86memopZ>,
6033 avx512_trunc_mr_lowering<VTSrcInfo.info512, DestInfoZ,
6034 truncFrag, mtruncFrag>, EVEX_V512;
6037 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr, SDNode OpNode,
6038 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
6039 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
6040 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
6041 X86MemOperand x86memopZ, string sat, Predicate prd = HasAVX512>{
6043 let Predicates = [HasVLX, prd] in {
6044 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
6045 DestInfoZ128, x86memopZ128>,
6046 avx512_trunc_sat_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
6049 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
6050 DestInfoZ256, x86memopZ256>,
6051 avx512_trunc_sat_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
6054 let Predicates = [prd] in
6055 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
6056 DestInfoZ, x86memopZ>,
6057 avx512_trunc_sat_mr_lowering<VTSrcInfo.info512, DestInfoZ,
6061 multiclass avx512_trunc_qb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6062 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6063 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
6064 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VO>;
6066 multiclass avx512_trunc_sat_qb<bits<8> opc, string sat, SDNode OpNode> {
6067 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qb", OpNode, avx512vl_i64_info,
6068 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
6069 sat>, EVEX_CD8<8, CD8VO>;
6072 multiclass avx512_trunc_qw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6073 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6074 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
6075 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VQ>;
6077 multiclass avx512_trunc_sat_qw<bits<8> opc, string sat, SDNode OpNode> {
6078 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qw", OpNode, avx512vl_i64_info,
6079 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
6080 sat>, EVEX_CD8<16, CD8VQ>;
6083 multiclass avx512_trunc_qd<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6084 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6085 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
6086 truncstorevi32, masked_truncstorevi32>, EVEX_CD8<32, CD8VH>;
6088 multiclass avx512_trunc_sat_qd<bits<8> opc, string sat, SDNode OpNode> {
6089 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qd", OpNode, avx512vl_i64_info,
6090 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
6091 sat>, EVEX_CD8<32, CD8VH>;
6094 multiclass avx512_trunc_db<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6095 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
6096 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
6097 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VQ>;
6099 multiclass avx512_trunc_sat_db<bits<8> opc, string sat, SDNode OpNode> {
6100 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"db", OpNode, avx512vl_i32_info,
6101 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
6102 sat>, EVEX_CD8<8, CD8VQ>;
6105 multiclass avx512_trunc_dw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6106 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
6107 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
6108 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VH>;
6110 multiclass avx512_trunc_sat_dw<bits<8> opc, string sat, SDNode OpNode> {
6111 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"dw", OpNode, avx512vl_i32_info,
6112 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
6113 sat>, EVEX_CD8<16, CD8VH>;
6116 multiclass avx512_trunc_wb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6117 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i16_info,
6118 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
6119 truncstorevi8, masked_truncstorevi8,HasBWI>, EVEX_CD8<16, CD8VH>;
6121 multiclass avx512_trunc_sat_wb<bits<8> opc, string sat, SDNode OpNode> {
6122 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"wb", OpNode, avx512vl_i16_info,
6123 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
6124 sat, HasBWI>, EVEX_CD8<16, CD8VH>;
6127 defm VPMOVQB : avx512_trunc_qb<0x32, "vpmovqb", X86vtrunc>;
6128 defm VPMOVSQB : avx512_trunc_sat_qb<0x22, "s", X86vtruncs>;
6129 defm VPMOVUSQB : avx512_trunc_sat_qb<0x12, "us", X86vtruncus>;
6131 defm VPMOVQW : avx512_trunc_qw<0x34, "vpmovqw", X86vtrunc>;
6132 defm VPMOVSQW : avx512_trunc_sat_qw<0x24, "s", X86vtruncs>;
6133 defm VPMOVUSQW : avx512_trunc_sat_qw<0x14, "us", X86vtruncus>;
6135 defm VPMOVQD : avx512_trunc_qd<0x35, "vpmovqd", X86vtrunc>;
6136 defm VPMOVSQD : avx512_trunc_sat_qd<0x25, "s", X86vtruncs>;
6137 defm VPMOVUSQD : avx512_trunc_sat_qd<0x15, "us", X86vtruncus>;
6139 defm VPMOVDB : avx512_trunc_db<0x31, "vpmovdb", X86vtrunc>;
6140 defm VPMOVSDB : avx512_trunc_sat_db<0x21, "s", X86vtruncs>;
6141 defm VPMOVUSDB : avx512_trunc_sat_db<0x11, "us", X86vtruncus>;
6143 defm VPMOVDW : avx512_trunc_dw<0x33, "vpmovdw", X86vtrunc>;
6144 defm VPMOVSDW : avx512_trunc_sat_dw<0x23, "s", X86vtruncs>;
6145 defm VPMOVUSDW : avx512_trunc_sat_dw<0x13, "us", X86vtruncus>;
6147 defm VPMOVWB : avx512_trunc_wb<0x30, "vpmovwb", X86vtrunc>;
6148 defm VPMOVSWB : avx512_trunc_sat_wb<0x20, "s", X86vtruncs>;
6149 defm VPMOVUSWB : avx512_trunc_sat_wb<0x10, "us", X86vtruncus>;
6151 let Predicates = [HasAVX512, NoVLX] in {
6152 def: Pat<(v8i16 (X86vtrunc (v8i32 VR256X:$src))),
6153 (v8i16 (EXTRACT_SUBREG
6154 (v16i16 (VPMOVDWZrr (v16i32 (SUBREG_TO_REG (i32 0),
6155 VR256X:$src, sub_ymm)))), sub_xmm))>;
6156 def: Pat<(v4i32 (X86vtrunc (v4i64 VR256X:$src))),
6157 (v4i32 (EXTRACT_SUBREG
6158 (v8i32 (VPMOVQDZrr (v8i64 (SUBREG_TO_REG (i32 0),
6159 VR256X:$src, sub_ymm)))), sub_xmm))>;
6162 let Predicates = [HasBWI, NoVLX] in {
6163 def: Pat<(v16i8 (X86vtrunc (v16i16 VR256X:$src))),
6164 (v16i8 (EXTRACT_SUBREG (VPMOVWBZrr (v32i16 (SUBREG_TO_REG (i32 0),
6165 VR256X:$src, sub_ymm))), sub_xmm))>;
6168 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
6169 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
6170 X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{
6172 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6173 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
6174 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
6177 let mayLoad = 1 in {
6178 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6179 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
6180 (DestInfo.VT (LdFrag addr:$src))>,
6185 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode,
6186 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6187 let Predicates = [HasVLX, HasBWI] in {
6188 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
6189 v16i8x_info, i64mem, LdFrag, OpNode>,
6190 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
6192 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
6193 v16i8x_info, i128mem, LdFrag, OpNode>,
6194 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
6196 let Predicates = [HasBWI] in {
6197 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
6198 v32i8x_info, i256mem, LdFrag, OpNode>,
6199 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
6203 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6204 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6205 let Predicates = [HasVLX, HasAVX512] in {
6206 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6207 v16i8x_info, i32mem, LdFrag, OpNode>,
6208 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
6210 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6211 v16i8x_info, i64mem, LdFrag, OpNode>,
6212 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
6214 let Predicates = [HasAVX512] in {
6215 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6216 v16i8x_info, i128mem, LdFrag, OpNode>,
6217 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
6221 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6222 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6223 let Predicates = [HasVLX, HasAVX512] in {
6224 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6225 v16i8x_info, i16mem, LdFrag, OpNode>,
6226 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
6228 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6229 v16i8x_info, i32mem, LdFrag, OpNode>,
6230 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
6232 let Predicates = [HasAVX512] in {
6233 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6234 v16i8x_info, i64mem, LdFrag, OpNode>,
6235 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
6239 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6240 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6241 let Predicates = [HasVLX, HasAVX512] in {
6242 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6243 v8i16x_info, i64mem, LdFrag, OpNode>,
6244 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
6246 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6247 v8i16x_info, i128mem, LdFrag, OpNode>,
6248 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
6250 let Predicates = [HasAVX512] in {
6251 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6252 v16i16x_info, i256mem, LdFrag, OpNode>,
6253 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
6257 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6258 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6259 let Predicates = [HasVLX, HasAVX512] in {
6260 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6261 v8i16x_info, i32mem, LdFrag, OpNode>,
6262 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
6264 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6265 v8i16x_info, i64mem, LdFrag, OpNode>,
6266 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
6268 let Predicates = [HasAVX512] in {
6269 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6270 v8i16x_info, i128mem, LdFrag, OpNode>,
6271 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
6275 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6276 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
6278 let Predicates = [HasVLX, HasAVX512] in {
6279 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6280 v4i32x_info, i64mem, LdFrag, OpNode>,
6281 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
6283 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6284 v4i32x_info, i128mem, LdFrag, OpNode>,
6285 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
6287 let Predicates = [HasAVX512] in {
6288 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6289 v8i32x_info, i256mem, LdFrag, OpNode>,
6290 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
6294 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, "z">;
6295 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, "z">;
6296 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, "z">;
6297 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, "z">;
6298 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, "z">;
6299 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, "z">;
6302 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, "s">;
6303 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, "s">;
6304 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, "s">;
6305 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, "s">;
6306 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, "s">;
6307 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, "s">;
6309 //===----------------------------------------------------------------------===//
6310 // GATHER - SCATTER Operations
6312 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6313 X86MemOperand memop, PatFrag GatherNode> {
6314 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb",
6315 ExeDomain = _.ExeDomain in
6316 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
6317 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
6318 !strconcat(OpcodeStr#_.Suffix,
6319 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
6320 [(set _.RC:$dst, _.KRCWM:$mask_wb,
6321 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
6322 vectoraddr:$src2))]>, EVEX, EVEX_K,
6323 EVEX_CD8<_.EltSize, CD8VT1>;
6326 multiclass avx512_gather_q_pd<bits<8> dopc, bits<8> qopc,
6327 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6328 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512,
6329 vy32xmem, mgatherv8i32>, EVEX_V512, VEX_W;
6330 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info512,
6331 vz64mem, mgatherv8i64>, EVEX_V512, VEX_W;
6332 let Predicates = [HasVLX] in {
6333 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6334 vx32xmem, mgatherv4i32>, EVEX_V256, VEX_W;
6335 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info256,
6336 vy64xmem, mgatherv4i64>, EVEX_V256, VEX_W;
6337 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6338 vx32xmem, mgatherv4i32>, EVEX_V128, VEX_W;
6339 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6340 vx64xmem, mgatherv2i64>, EVEX_V128, VEX_W;
6344 multiclass avx512_gather_d_ps<bits<8> dopc, bits<8> qopc,
6345 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6346 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512, vz32mem,
6347 mgatherv16i32>, EVEX_V512;
6348 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info256, vz64mem,
6349 mgatherv8i64>, EVEX_V512;
6350 let Predicates = [HasVLX] in {
6351 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6352 vy32xmem, mgatherv8i32>, EVEX_V256;
6353 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6354 vy64xmem, mgatherv4i64>, EVEX_V256;
6355 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6356 vx32xmem, mgatherv4i32>, EVEX_V128;
6357 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6358 vx64xmem, mgatherv2i64>, EVEX_V128;
6363 defm VGATHER : avx512_gather_q_pd<0x92, 0x93, avx512vl_f64_info, "vgather", "PD">,
6364 avx512_gather_d_ps<0x92, 0x93, avx512vl_f32_info, "vgather", "PS">;
6366 defm VPGATHER : avx512_gather_q_pd<0x90, 0x91, avx512vl_i64_info, "vpgather", "Q">,
6367 avx512_gather_d_ps<0x90, 0x91, avx512vl_i32_info, "vpgather", "D">;
6369 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6370 X86MemOperand memop, PatFrag ScatterNode> {
6372 let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain in
6374 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
6375 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
6376 !strconcat(OpcodeStr#_.Suffix,
6377 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
6378 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
6379 _.KRCWM:$mask, vectoraddr:$dst))]>,
6380 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6383 multiclass avx512_scatter_q_pd<bits<8> dopc, bits<8> qopc,
6384 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6385 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512,
6386 vy32xmem, mscatterv8i32>, EVEX_V512, VEX_W;
6387 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info512,
6388 vz64mem, mscatterv8i64>, EVEX_V512, VEX_W;
6389 let Predicates = [HasVLX] in {
6390 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6391 vx32xmem, mscatterv4i32>, EVEX_V256, VEX_W;
6392 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info256,
6393 vy64xmem, mscatterv4i64>, EVEX_V256, VEX_W;
6394 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6395 vx32xmem, mscatterv4i32>, EVEX_V128, VEX_W;
6396 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6397 vx64xmem, mscatterv2i64>, EVEX_V128, VEX_W;
6401 multiclass avx512_scatter_d_ps<bits<8> dopc, bits<8> qopc,
6402 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6403 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512, vz32mem,
6404 mscatterv16i32>, EVEX_V512;
6405 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info256, vz64mem,
6406 mscatterv8i64>, EVEX_V512;
6407 let Predicates = [HasVLX] in {
6408 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6409 vy32xmem, mscatterv8i32>, EVEX_V256;
6410 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6411 vy64xmem, mscatterv4i64>, EVEX_V256;
6412 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6413 vx32xmem, mscatterv4i32>, EVEX_V128;
6414 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6415 vx64xmem, mscatterv2i64>, EVEX_V128;
6419 defm VSCATTER : avx512_scatter_q_pd<0xA2, 0xA3, avx512vl_f64_info, "vscatter", "PD">,
6420 avx512_scatter_d_ps<0xA2, 0xA3, avx512vl_f32_info, "vscatter", "PS">;
6422 defm VPSCATTER : avx512_scatter_q_pd<0xA0, 0xA1, avx512vl_i64_info, "vpscatter", "Q">,
6423 avx512_scatter_d_ps<0xA0, 0xA1, avx512vl_i32_info, "vpscatter", "D">;
6426 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
6427 RegisterClass KRC, X86MemOperand memop> {
6428 let Predicates = [HasPFI], hasSideEffects = 1 in
6429 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
6430 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
6434 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
6435 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6437 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
6438 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6440 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
6441 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6443 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
6444 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6446 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
6447 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6449 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
6450 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6452 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
6453 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6455 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
6456 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6458 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
6459 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6461 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
6462 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6464 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
6465 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6467 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
6468 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6470 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
6471 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6473 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
6474 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6476 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
6477 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6479 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
6480 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6482 // Helper fragments to match sext vXi1 to vXiY.
6483 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
6484 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
6486 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6487 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6488 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
6490 def : Pat<(store VK1:$src, addr:$dst),
6492 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
6493 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6495 def : Pat<(store VK8:$src, addr:$dst),
6497 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
6498 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6500 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
6501 (truncstore node:$val, node:$ptr), [{
6502 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
6505 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
6506 (MOV8mr addr:$dst, GR8:$src)>;
6508 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
6509 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
6510 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
6511 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
6514 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
6515 string OpcodeStr, Predicate prd> {
6516 let Predicates = [prd] in
6517 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6519 let Predicates = [prd, HasVLX] in {
6520 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6521 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6525 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
6526 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
6528 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
6530 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
6532 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
6536 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
6538 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
6539 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
6540 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6541 [(set _.KRC:$dst, (trunc (_.VT _.RC:$src)))]>, EVEX;
6544 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
6545 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6546 let Predicates = [prd] in
6547 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
6550 let Predicates = [prd, HasVLX] in {
6551 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
6553 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
6558 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
6559 avx512vl_i8_info, HasBWI>;
6560 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
6561 avx512vl_i16_info, HasBWI>, VEX_W;
6562 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
6563 avx512vl_i32_info, HasDQI>;
6564 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
6565 avx512vl_i64_info, HasDQI>, VEX_W;
6567 //===----------------------------------------------------------------------===//
6568 // AVX-512 - COMPRESS and EXPAND
6571 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6573 defm rr : AVX512_maskable<opc, MRMDestReg, _, (outs _.RC:$dst),
6574 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6575 (_.VT (X86compress _.RC:$src1))>, AVX5128IBase;
6577 let mayStore = 1 in {
6578 def mr : AVX5128I<opc, MRMDestMem, (outs),
6579 (ins _.MemOp:$dst, _.RC:$src),
6580 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6581 []>, EVEX_CD8<_.EltSize, CD8VT1>;
6583 def mrk : AVX5128I<opc, MRMDestMem, (outs),
6584 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
6585 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6586 [(store (_.VT (vselect _.KRCWM:$mask,
6587 (_.VT (X86compress _.RC:$src)), _.ImmAllZerosV)),
6589 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6593 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
6594 AVX512VLVectorVTInfo VTInfo> {
6595 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6597 let Predicates = [HasVLX] in {
6598 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6599 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6603 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
6605 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
6607 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
6609 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
6613 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6615 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6616 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6617 (_.VT (X86expand _.RC:$src1))>, AVX5128IBase;
6620 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6621 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
6622 (_.VT (X86expand (_.VT (bitconvert
6623 (_.LdFrag addr:$src1)))))>,
6624 AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>;
6627 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
6628 AVX512VLVectorVTInfo VTInfo> {
6629 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6631 let Predicates = [HasVLX] in {
6632 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6633 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6637 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
6639 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
6641 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
6643 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
6646 //handle instruction reg_vec1 = op(reg_vec,imm)
6648 // op(broadcast(eltVt),imm)
6649 //all instruction created with FROUND_CURRENT
6650 multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6652 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6653 (ins _.RC:$src1, i32u8imm:$src2),
6654 OpcodeStr##_.Suffix, "$src2, $src1", "$src2, $src2",
6655 (OpNode (_.VT _.RC:$src1),
6657 (i32 FROUND_CURRENT))>;
6658 let mayLoad = 1 in {
6659 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6660 (ins _.MemOp:$src1, i32u8imm:$src2),
6661 OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
6662 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
6664 (i32 FROUND_CURRENT))>;
6665 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6666 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
6667 OpcodeStr##_.Suffix, "$src2, ${src1}"##_.BroadcastStr,
6668 "${src1}"##_.BroadcastStr##", $src2",
6669 (OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src1))),
6671 (i32 FROUND_CURRENT))>, EVEX_B;
6675 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6676 multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6677 SDNode OpNode, X86VectorVTInfo _>{
6678 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6679 (ins _.RC:$src1, i32u8imm:$src2),
6680 OpcodeStr##_.Suffix, "$src2,{sae}, $src1",
6681 "$src1, {sae}, $src2",
6682 (OpNode (_.VT _.RC:$src1),
6684 (i32 FROUND_NO_EXC))>, EVEX_B;
6687 multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
6688 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6689 let Predicates = [prd] in {
6690 defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6691 avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6694 let Predicates = [prd, HasVLX] in {
6695 defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6697 defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6702 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6703 // op(reg_vec2,mem_vec,imm)
6704 // op(reg_vec2,broadcast(eltVt),imm)
6705 //all instruction created with FROUND_CURRENT
6706 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6708 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6709 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6710 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6711 (OpNode (_.VT _.RC:$src1),
6714 (i32 FROUND_CURRENT))>;
6715 let mayLoad = 1 in {
6716 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6717 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6718 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6719 (OpNode (_.VT _.RC:$src1),
6720 (_.VT (bitconvert (_.LdFrag addr:$src2))),
6722 (i32 FROUND_CURRENT))>;
6723 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6724 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
6725 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6726 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6727 (OpNode (_.VT _.RC:$src1),
6728 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6730 (i32 FROUND_CURRENT))>, EVEX_B;
6734 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6735 // op(reg_vec2,mem_vec,imm)
6736 multiclass avx512_3Op_rm_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6737 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo>{
6739 defm rri : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6740 (ins SrcInfo.RC:$src1, SrcInfo.RC:$src2, u8imm:$src3),
6741 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6742 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6743 (SrcInfo.VT SrcInfo.RC:$src2),
6746 defm rmi : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6747 (ins SrcInfo.RC:$src1, SrcInfo.MemOp:$src2, u8imm:$src3),
6748 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6749 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6750 (SrcInfo.VT (bitconvert
6751 (SrcInfo.LdFrag addr:$src2))),
6755 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6756 // op(reg_vec2,mem_vec,imm)
6757 // op(reg_vec2,broadcast(eltVt),imm)
6758 multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6760 avx512_3Op_rm_imm8<opc, OpcodeStr, OpNode, _, _>{
6763 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6764 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6765 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6766 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6767 (OpNode (_.VT _.RC:$src1),
6768 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6769 (i8 imm:$src3))>, EVEX_B;
6772 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6773 // op(reg_vec2,mem_scalar,imm)
6774 //all instruction created with FROUND_CURRENT
6775 multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6776 X86VectorVTInfo _> {
6778 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6779 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6780 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6781 (OpNode (_.VT _.RC:$src1),
6784 (i32 FROUND_CURRENT))>;
6785 let mayLoad = 1 in {
6786 defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6787 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6788 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6789 (OpNode (_.VT _.RC:$src1),
6790 (_.VT (scalar_to_vector
6791 (_.ScalarLdFrag addr:$src2))),
6793 (i32 FROUND_CURRENT))>;
6795 let isAsmParserOnly = 1 in {
6796 defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
6797 (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6798 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6804 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6805 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6806 SDNode OpNode, X86VectorVTInfo _>{
6807 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6808 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6809 OpcodeStr, "$src3,{sae}, $src2, $src1",
6810 "$src1, $src2,{sae}, $src3",
6811 (OpNode (_.VT _.RC:$src1),
6814 (i32 FROUND_NO_EXC))>, EVEX_B;
6816 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6817 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
6818 SDNode OpNode, X86VectorVTInfo _> {
6819 defm NAME#rrib : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6820 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6821 OpcodeStr, "$src3,{sae}, $src2, $src1",
6822 "$src1, $src2,{sae}, $src3",
6823 (OpNode (_.VT _.RC:$src1),
6826 (i32 FROUND_NO_EXC))>, EVEX_B;
6829 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
6830 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6831 let Predicates = [prd] in {
6832 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6833 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6837 let Predicates = [prd, HasVLX] in {
6838 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6840 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6845 multiclass avx512_common_3Op_rm_imm8<bits<8> opc, SDNode OpNode, string OpStr,
6846 AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo>{
6847 let Predicates = [HasBWI] in {
6848 defm Z : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info512,
6849 SrcInfo.info512>, EVEX_V512, AVX512AIi8Base, EVEX_4V;
6851 let Predicates = [HasBWI, HasVLX] in {
6852 defm Z128 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info128,
6853 SrcInfo.info128>, EVEX_V128, AVX512AIi8Base, EVEX_4V;
6854 defm Z256 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info256,
6855 SrcInfo.info256>, EVEX_V256, AVX512AIi8Base, EVEX_4V;
6859 multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
6860 bits<8> opc, SDNode OpNode>{
6861 let Predicates = [HasAVX512] in {
6862 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6864 let Predicates = [HasAVX512, HasVLX] in {
6865 defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
6866 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6870 multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
6871 X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6872 let Predicates = [prd] in {
6873 defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
6874 avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
6878 multiclass avx512_common_unary_fp_sae_packed_imm_all<string OpcodeStr,
6879 bits<8> opcPs, bits<8> opcPd, SDNode OpNode, Predicate prd>{
6880 defm PS : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f32_info,
6881 opcPs, OpNode, prd>, EVEX_CD8<32, CD8VF>;
6882 defm PD : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f64_info,
6883 opcPd, OpNode, prd>, EVEX_CD8<64, CD8VF>, VEX_W;
6886 defm VFIXUPIMMPD : avx512_common_fp_sae_packed_imm<"vfixupimmpd",
6887 avx512vl_f64_info, 0x54, X86VFixupimm, HasAVX512>,
6888 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6889 defm VFIXUPIMMPS : avx512_common_fp_sae_packed_imm<"vfixupimmps",
6890 avx512vl_f32_info, 0x54, X86VFixupimm, HasAVX512>,
6891 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6893 defm VFIXUPIMMSD: avx512_common_fp_sae_scalar_imm<"vfixupimmsd", f64x_info,
6894 0x55, X86VFixupimm, HasAVX512>,
6895 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6896 defm VFIXUPIMMSS: avx512_common_fp_sae_scalar_imm<"vfixupimmss", f32x_info,
6897 0x55, X86VFixupimm, HasAVX512>,
6898 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6900 defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56,
6901 X86VReduce, HasDQI>, AVX512AIi8Base, EVEX;
6902 defm VRNDSCALE : avx512_common_unary_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09,
6903 X86VRndScale, HasAVX512>, AVX512AIi8Base, EVEX;
6904 defm VGETMANT : avx512_common_unary_fp_sae_packed_imm_all<"vgetmant", 0x26, 0x26,
6905 X86VGetMant, HasAVX512>, AVX512AIi8Base, EVEX;
6908 defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
6909 0x50, X86VRange, HasDQI>,
6910 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6911 defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
6912 0x50, X86VRange, HasDQI>,
6913 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6915 defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
6916 0x51, X86VRange, HasDQI>,
6917 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6918 defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
6919 0x51, X86VRange, HasDQI>,
6920 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6922 defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info,
6923 0x57, X86Reduces, HasDQI>,
6924 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6925 defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info,
6926 0x57, X86Reduces, HasDQI>,
6927 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6929 defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info,
6930 0x27, X86GetMants, HasAVX512>,
6931 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6932 defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info,
6933 0x27, X86GetMants, HasAVX512>,
6934 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6936 multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
6937 bits<8> opc, SDNode OpNode = X86Shuf128>{
6938 let Predicates = [HasAVX512] in {
6939 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6942 let Predicates = [HasAVX512, HasVLX] in {
6943 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6946 let Predicates = [HasAVX512] in {
6947 def : Pat<(v16f32 (ffloor VR512:$src)),
6948 (VRNDSCALEPSZrri VR512:$src, (i32 0x1))>;
6949 def : Pat<(v16f32 (fnearbyint VR512:$src)),
6950 (VRNDSCALEPSZrri VR512:$src, (i32 0xC))>;
6951 def : Pat<(v16f32 (fceil VR512:$src)),
6952 (VRNDSCALEPSZrri VR512:$src, (i32 0x2))>;
6953 def : Pat<(v16f32 (frint VR512:$src)),
6954 (VRNDSCALEPSZrri VR512:$src, (i32 0x4))>;
6955 def : Pat<(v16f32 (ftrunc VR512:$src)),
6956 (VRNDSCALEPSZrri VR512:$src, (i32 0x3))>;
6958 def : Pat<(v8f64 (ffloor VR512:$src)),
6959 (VRNDSCALEPDZrri VR512:$src, (i32 0x1))>;
6960 def : Pat<(v8f64 (fnearbyint VR512:$src)),
6961 (VRNDSCALEPDZrri VR512:$src, (i32 0xC))>;
6962 def : Pat<(v8f64 (fceil VR512:$src)),
6963 (VRNDSCALEPDZrri VR512:$src, (i32 0x2))>;
6964 def : Pat<(v8f64 (frint VR512:$src)),
6965 (VRNDSCALEPDZrri VR512:$src, (i32 0x4))>;
6966 def : Pat<(v8f64 (ftrunc VR512:$src)),
6967 (VRNDSCALEPDZrri VR512:$src, (i32 0x3))>;
6970 defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
6971 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6972 defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
6973 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6974 defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
6975 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6976 defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
6977 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6979 multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
6980 AVX512VLVectorVTInfo VTInfo_FP>{
6981 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
6982 AVX512AIi8Base, EVEX_4V;
6983 let isCodeGenOnly = 1 in {
6984 defm NAME#_FP: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0x03, X86VAlign>,
6985 AVX512AIi8Base, EVEX_4V;
6989 defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info, avx512vl_f32_info>,
6990 EVEX_CD8<32, CD8VF>;
6991 defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info, avx512vl_f64_info>,
6992 EVEX_CD8<64, CD8VF>, VEX_W;
6994 multiclass avx512_vpalign_lowering<X86VectorVTInfo _ , list<Predicate> p>{
6995 let Predicates = p in
6996 def NAME#_.VTName#rri:
6997 Pat<(_.VT (X86PAlignr _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
6998 (!cast<Instruction>(NAME#_.ZSuffix#rri)
6999 _.RC:$src1, _.RC:$src2, imm:$imm)>;
7002 multiclass avx512_vpalign_lowering_common<AVX512VLVectorVTInfo _>:
7003 avx512_vpalign_lowering<_.info512, [HasBWI]>,
7004 avx512_vpalign_lowering<_.info128, [HasBWI, HasVLX]>,
7005 avx512_vpalign_lowering<_.info256, [HasBWI, HasVLX]>;
7007 defm VPALIGN: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr" ,
7008 avx512vl_i8_info, avx512vl_i8_info>,
7009 avx512_vpalign_lowering_common<avx512vl_i16_info>,
7010 avx512_vpalign_lowering_common<avx512vl_i32_info>,
7011 avx512_vpalign_lowering_common<avx512vl_f32_info>,
7012 avx512_vpalign_lowering_common<avx512vl_i64_info>,
7013 avx512_vpalign_lowering_common<avx512vl_f64_info>,
7016 defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw" ,
7017 avx512vl_i16_info, avx512vl_i8_info>, EVEX_CD8<8, CD8VF>;
7019 multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7020 X86VectorVTInfo _> {
7021 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7022 (ins _.RC:$src1), OpcodeStr,
7024 (_.VT (OpNode _.RC:$src1))>, EVEX, AVX5128IBase;
7027 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7028 (ins _.MemOp:$src1), OpcodeStr,
7030 (_.VT (OpNode (bitconvert (_.LdFrag addr:$src1))))>,
7031 EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>;
7034 multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
7035 X86VectorVTInfo _> :
7036 avx512_unary_rm<opc, OpcodeStr, OpNode, _> {
7038 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7039 (ins _.ScalarMemOp:$src1), OpcodeStr,
7040 "${src1}"##_.BroadcastStr,
7041 "${src1}"##_.BroadcastStr,
7042 (_.VT (OpNode (X86VBroadcast
7043 (_.ScalarLdFrag addr:$src1))))>,
7044 EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
7047 multiclass avx512_unary_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
7048 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
7049 let Predicates = [prd] in
7050 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
7052 let Predicates = [prd, HasVLX] in {
7053 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
7055 defm Z128 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info128>,
7060 multiclass avx512_unary_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
7061 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
7062 let Predicates = [prd] in
7063 defm Z : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
7066 let Predicates = [prd, HasVLX] in {
7067 defm Z256 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
7069 defm Z128 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
7074 multiclass avx512_unary_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
7075 SDNode OpNode, Predicate prd> {
7076 defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr#"q", OpNode, avx512vl_i64_info,
7078 defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr#"d", OpNode, avx512vl_i32_info,
7082 multiclass avx512_unary_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
7083 SDNode OpNode, Predicate prd> {
7084 defm W : avx512_unary_rm_vl<opc_w, OpcodeStr#"w", OpNode, avx512vl_i16_info, prd>;
7085 defm B : avx512_unary_rm_vl<opc_b, OpcodeStr#"b", OpNode, avx512vl_i8_info, prd>;
7088 multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
7089 bits<8> opc_d, bits<8> opc_q,
7090 string OpcodeStr, SDNode OpNode> {
7091 defm NAME : avx512_unary_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
7093 avx512_unary_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
7097 defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", X86Abs>;
7100 (bc_v16i32 (v16i1sextv16i32)),
7101 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
7102 (VPABSDZrr VR512:$src)>;
7104 (bc_v8i64 (v8i1sextv8i64)),
7105 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
7106 (VPABSQZrr VR512:$src)>;
7108 multiclass avx512_ctlz<bits<8> opc, string OpcodeStr, Predicate prd>{
7110 defm NAME : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr, ctlz, prd>;
7111 let isCodeGenOnly = 1 in
7112 defm NAME#_UNDEF : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr,
7113 ctlz_zero_undef, prd>;
7116 defm VPLZCNT : avx512_ctlz<0x44, "vplzcnt", HasCDI>;
7117 defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict, HasCDI>;
7119 //===---------------------------------------------------------------------===//
7120 // Replicate Single FP - MOVSHDUP and MOVSLDUP
7121 //===---------------------------------------------------------------------===//
7122 multiclass avx512_replicate<bits<8> opc, string OpcodeStr, SDNode OpNode>{
7123 defm NAME: avx512_unary_rm_vl<opc, OpcodeStr, OpNode, avx512vl_f32_info,
7125 let isCodeGenOnly = 1 in
7126 defm NAME#_I: avx512_unary_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
7130 defm VMOVSHDUP : avx512_replicate<0x16, "vmovshdup", X86Movshdup>;
7131 defm VMOVSLDUP : avx512_replicate<0x12, "vmovsldup", X86Movsldup>;
7133 //===----------------------------------------------------------------------===//
7134 // AVX-512 - MOVDDUP
7135 //===----------------------------------------------------------------------===//
7137 multiclass avx512_movddup_128<bits<8> opc, string OpcodeStr, SDNode OpNode,
7138 X86VectorVTInfo _> {
7139 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7140 (ins _.RC:$src), OpcodeStr, "$src", "$src",
7141 (_.VT (OpNode (_.VT _.RC:$src)))>, EVEX;
7143 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7144 (ins _.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
7145 (_.VT (OpNode (_.VT (scalar_to_vector
7146 (_.ScalarLdFrag addr:$src)))))>,
7147 EVEX, EVEX_CD8<_.EltSize, CD8VH>;
7150 multiclass avx512_movddup_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
7151 AVX512VLVectorVTInfo VTInfo> {
7153 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
7155 let Predicates = [HasAVX512, HasVLX] in {
7156 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
7158 defm Z128 : avx512_movddup_128<opc, OpcodeStr, OpNode, VTInfo.info128>,
7163 multiclass avx512_movddup<bits<8> opc, string OpcodeStr, SDNode OpNode>{
7164 defm NAME: avx512_movddup_common<opc, OpcodeStr, OpNode,
7165 avx512vl_f64_info>, XD, VEX_W;
7166 let isCodeGenOnly = 1 in
7167 defm NAME#_I: avx512_movddup_common<opc, OpcodeStr, OpNode,
7171 defm VMOVDDUP : avx512_movddup<0x12, "vmovddup", X86Movddup>;
7173 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
7174 (VMOVDDUPZ128rm addr:$src)>, Requires<[HasAVX512, HasVLX]>;
7175 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
7176 (VMOVDDUPZ128rm addr:$src)>, Requires<[HasAVX512, HasVLX]>;
7178 //===----------------------------------------------------------------------===//
7179 // AVX-512 - Unpack Instructions
7180 //===----------------------------------------------------------------------===//
7181 defm VUNPCKH : avx512_fp_binop_p<0x15, "vunpckh", X86Unpckh>;
7182 defm VUNPCKL : avx512_fp_binop_p<0x14, "vunpckl", X86Unpckl>;
7184 defm VPUNPCKLBW : avx512_binop_rm_vl_b<0x60, "vpunpcklbw", X86Unpckl,
7185 SSE_INTALU_ITINS_P, HasBWI>;
7186 defm VPUNPCKHBW : avx512_binop_rm_vl_b<0x68, "vpunpckhbw", X86Unpckh,
7187 SSE_INTALU_ITINS_P, HasBWI>;
7188 defm VPUNPCKLWD : avx512_binop_rm_vl_w<0x61, "vpunpcklwd", X86Unpckl,
7189 SSE_INTALU_ITINS_P, HasBWI>;
7190 defm VPUNPCKHWD : avx512_binop_rm_vl_w<0x69, "vpunpckhwd", X86Unpckh,
7191 SSE_INTALU_ITINS_P, HasBWI>;
7193 defm VPUNPCKLDQ : avx512_binop_rm_vl_d<0x62, "vpunpckldq", X86Unpckl,
7194 SSE_INTALU_ITINS_P, HasAVX512>;
7195 defm VPUNPCKHDQ : avx512_binop_rm_vl_d<0x6A, "vpunpckhdq", X86Unpckh,
7196 SSE_INTALU_ITINS_P, HasAVX512>;
7197 defm VPUNPCKLQDQ : avx512_binop_rm_vl_q<0x6C, "vpunpcklqdq", X86Unpckl,
7198 SSE_INTALU_ITINS_P, HasAVX512>;
7199 defm VPUNPCKHQDQ : avx512_binop_rm_vl_q<0x6D, "vpunpckhqdq", X86Unpckh,
7200 SSE_INTALU_ITINS_P, HasAVX512>;
7202 //===----------------------------------------------------------------------===//
7203 // AVX-512 - Extract & Insert Integer Instructions
7204 //===----------------------------------------------------------------------===//
7206 multiclass avx512_extract_elt_bw_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7207 X86VectorVTInfo _> {
7209 def mr : AVX512Ii8<opc, MRMDestMem, (outs),
7210 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7211 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7212 [(store (_.EltVT (trunc (assertzext (OpNode (_.VT _.RC:$src1),
7215 EVEX, EVEX_CD8<_.EltSize, CD8VT1>;
7218 multiclass avx512_extract_elt_b<string OpcodeStr, X86VectorVTInfo _> {
7219 let Predicates = [HasBWI] in {
7220 def rr : AVX512Ii8<0x14, MRMDestReg, (outs GR32orGR64:$dst),
7221 (ins _.RC:$src1, u8imm:$src2),
7222 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7223 [(set GR32orGR64:$dst,
7224 (X86pextrb (_.VT _.RC:$src1), imm:$src2))]>,
7227 defm NAME : avx512_extract_elt_bw_m<0x14, OpcodeStr, X86pextrb, _>, TAPD;
7231 multiclass avx512_extract_elt_w<string OpcodeStr, X86VectorVTInfo _> {
7232 let Predicates = [HasBWI] in {
7233 def rr : AVX512Ii8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst),
7234 (ins _.RC:$src1, u8imm:$src2),
7235 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7236 [(set GR32orGR64:$dst,
7237 (X86pextrw (_.VT _.RC:$src1), imm:$src2))]>,
7240 def rr_REV : AVX512Ii8<0x15, MRMDestReg, (outs GR32orGR64:$dst),
7241 (ins _.RC:$src1, u8imm:$src2),
7242 OpcodeStr#".s\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7245 defm NAME : avx512_extract_elt_bw_m<0x15, OpcodeStr, X86pextrw, _>, TAPD;
7249 multiclass avx512_extract_elt_dq<string OpcodeStr, X86VectorVTInfo _,
7250 RegisterClass GRC> {
7251 let Predicates = [HasDQI] in {
7252 def rr : AVX512Ii8<0x16, MRMDestReg, (outs GRC:$dst),
7253 (ins _.RC:$src1, u8imm:$src2),
7254 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7256 (extractelt (_.VT _.RC:$src1), imm:$src2))]>,
7260 def mr : AVX512Ii8<0x16, MRMDestMem, (outs),
7261 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7262 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7263 [(store (extractelt (_.VT _.RC:$src1),
7264 imm:$src2),addr:$dst)]>,
7265 EVEX, EVEX_CD8<_.EltSize, CD8VT1>, TAPD;
7269 defm VPEXTRBZ : avx512_extract_elt_b<"vpextrb", v16i8x_info>;
7270 defm VPEXTRWZ : avx512_extract_elt_w<"vpextrw", v8i16x_info>;
7271 defm VPEXTRDZ : avx512_extract_elt_dq<"vpextrd", v4i32x_info, GR32>;
7272 defm VPEXTRQZ : avx512_extract_elt_dq<"vpextrq", v2i64x_info, GR64>, VEX_W;
7274 multiclass avx512_insert_elt_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7275 X86VectorVTInfo _, PatFrag LdFrag> {
7276 def rm : AVX512Ii8<opc, MRMSrcMem, (outs _.RC:$dst),
7277 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
7278 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7280 (_.VT (OpNode _.RC:$src1, (LdFrag addr:$src2), imm:$src3)))]>,
7281 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
7284 multiclass avx512_insert_elt_bw<bits<8> opc, string OpcodeStr, SDNode OpNode,
7285 X86VectorVTInfo _, PatFrag LdFrag> {
7286 let Predicates = [HasBWI] in {
7287 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7288 (ins _.RC:$src1, GR32orGR64:$src2, u8imm:$src3),
7289 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7291 (OpNode _.RC:$src1, GR32orGR64:$src2, imm:$src3))]>, EVEX_4V;
7293 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, OpNode, _, LdFrag>;
7297 multiclass avx512_insert_elt_dq<bits<8> opc, string OpcodeStr,
7298 X86VectorVTInfo _, RegisterClass GRC> {
7299 let Predicates = [HasDQI] in {
7300 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7301 (ins _.RC:$src1, GRC:$src2, u8imm:$src3),
7302 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7304 (_.VT (insertelt _.RC:$src1, GRC:$src2, imm:$src3)))]>,
7307 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, insertelt, _,
7308 _.ScalarLdFrag>, TAPD;
7312 defm VPINSRBZ : avx512_insert_elt_bw<0x20, "vpinsrb", X86pinsrb, v16i8x_info,
7314 defm VPINSRWZ : avx512_insert_elt_bw<0xC4, "vpinsrw", X86pinsrw, v8i16x_info,
7316 defm VPINSRDZ : avx512_insert_elt_dq<0x22, "vpinsrd", v4i32x_info, GR32>;
7317 defm VPINSRQZ : avx512_insert_elt_dq<0x22, "vpinsrq", v2i64x_info, GR64>, VEX_W;
7318 //===----------------------------------------------------------------------===//
7319 // VSHUFPS - VSHUFPD Operations
7320 //===----------------------------------------------------------------------===//
7321 multiclass avx512_shufp<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
7322 AVX512VLVectorVTInfo VTInfo_FP>{
7323 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0xC6, X86Shufp>,
7324 EVEX_CD8<VTInfo_FP.info512.EltSize, CD8VF>,
7325 AVX512AIi8Base, EVEX_4V;
7326 let isCodeGenOnly = 1 in {
7327 defm NAME#_I: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0xC6, X86Shufp>,
7328 EVEX_CD8<VTInfo_I.info512.EltSize, CD8VF>,
7329 AVX512AIi8Base, EVEX_4V;
7333 defm VSHUFPS: avx512_shufp<"vshufps", avx512vl_i32_info, avx512vl_f32_info>, PS;
7334 defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_i64_info, avx512vl_f64_info>, PD, VEX_W;
7335 //===----------------------------------------------------------------------===//
7336 // AVX-512 - Byte shift Left/Right
7337 //===----------------------------------------------------------------------===//
7339 multiclass avx512_shift_packed<bits<8> opc, SDNode OpNode, Format MRMr,
7340 Format MRMm, string OpcodeStr, X86VectorVTInfo _>{
7341 def rr : AVX512<opc, MRMr,
7342 (outs _.RC:$dst), (ins _.RC:$src1, u8imm:$src2),
7343 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7344 [(set _.RC:$dst,(_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>;
7346 def rm : AVX512<opc, MRMm,
7347 (outs _.RC:$dst), (ins _.MemOp:$src1, u8imm:$src2),
7348 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7349 [(set _.RC:$dst,(_.VT (OpNode
7350 (_.LdFrag addr:$src1), (i8 imm:$src2))))]>;
7353 multiclass avx512_shift_packed_all<bits<8> opc, SDNode OpNode, Format MRMr,
7354 Format MRMm, string OpcodeStr, Predicate prd>{
7355 let Predicates = [prd] in
7356 defm Z512 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7357 OpcodeStr, v8i64_info>, EVEX_V512;
7358 let Predicates = [prd, HasVLX] in {
7359 defm Z256 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7360 OpcodeStr, v4i64x_info>, EVEX_V256;
7361 defm Z128 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7362 OpcodeStr, v2i64x_info>, EVEX_V128;
7365 defm VPSLLDQ : avx512_shift_packed_all<0x73, X86vshldq, MRM7r, MRM7m, "vpslldq",
7366 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7367 defm VPSRLDQ : avx512_shift_packed_all<0x73, X86vshrdq, MRM3r, MRM3m, "vpsrldq",
7368 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7371 multiclass avx512_psadbw_packed<bits<8> opc, SDNode OpNode,
7372 string OpcodeStr, X86VectorVTInfo _dst,
7373 X86VectorVTInfo _src>{
7374 def rr : AVX512BI<opc, MRMSrcReg,
7375 (outs _dst.RC:$dst), (ins _src.RC:$src1, _src.RC:$src2),
7376 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7377 [(set _dst.RC:$dst,(_dst.VT
7378 (OpNode (_src.VT _src.RC:$src1),
7379 (_src.VT _src.RC:$src2))))]>;
7381 def rm : AVX512BI<opc, MRMSrcMem,
7382 (outs _dst.RC:$dst), (ins _src.RC:$src1, _src.MemOp:$src2),
7383 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7384 [(set _dst.RC:$dst,(_dst.VT
7385 (OpNode (_src.VT _src.RC:$src1),
7386 (_src.VT (bitconvert
7387 (_src.LdFrag addr:$src2))))))]>;
7390 multiclass avx512_psadbw_packed_all<bits<8> opc, SDNode OpNode,
7391 string OpcodeStr, Predicate prd> {
7392 let Predicates = [prd] in
7393 defm Z512 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v8i64_info,
7394 v64i8_info>, EVEX_V512;
7395 let Predicates = [prd, HasVLX] in {
7396 defm Z256 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v4i64x_info,
7397 v32i8x_info>, EVEX_V256;
7398 defm Z128 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v2i64x_info,
7399 v16i8x_info>, EVEX_V128;
7403 defm VPSADBW : avx512_psadbw_packed_all<0xf6, X86psadbw, "vpsadbw",
7406 multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode,
7408 let Constraints = "$src1 = $dst" in {
7409 defm rri : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
7410 (ins _.RC:$src2, _.RC:$src3, u8imm:$src4),
7411 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src3",
7412 (OpNode (_.VT _.RC:$src1),
7415 (i8 imm:$src4))>, AVX512AIi8Base, EVEX_4V;
7416 let mayLoad = 1 in {
7417 defm rmi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7418 (ins _.RC:$src2, _.MemOp:$src3, u8imm:$src4),
7419 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src3",
7420 (OpNode (_.VT _.RC:$src1),
7422 (_.VT (bitconvert (_.LdFrag addr:$src3))),
7424 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7425 defm rmbi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7426 (ins _.RC:$src2, _.ScalarMemOp:$src3, u8imm:$src4),
7427 OpcodeStr, "$src4, ${src3}"##_.BroadcastStr##", $src2",
7428 "$src2, ${src3}"##_.BroadcastStr##", $src4",
7429 (OpNode (_.VT _.RC:$src1),
7431 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
7432 (i8 imm:$src4))>, EVEX_B,
7433 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7435 }// Constraints = "$src1 = $dst"
7438 multiclass avx512_common_ternlog<string OpcodeStr, AVX512VLVectorVTInfo _>{
7439 let Predicates = [HasAVX512] in
7440 defm Z : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info512>, EVEX_V512;
7441 let Predicates = [HasAVX512, HasVLX] in {
7442 defm Z128 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info128>, EVEX_V128;
7443 defm Z256 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info256>, EVEX_V256;
7447 defm VPTERNLOGD : avx512_common_ternlog<"vpternlogd", avx512vl_i32_info>;
7448 defm VPTERNLOGQ : avx512_common_ternlog<"vpternlogq", avx512vl_i64_info>, VEX_W;