1 // Bitcasts between 512-bit vector types. Return the original type since
2 // no instruction is needed for the conversion
3 let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
49 // Bitcasts between 256-bit vector types. Return the original type since
50 // no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
84 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
87 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
93 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96 def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
98 //===----------------------------------------------------------------------===//
99 // AVX-512 - VECTOR INSERT
102 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103 def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
108 def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
114 // -- 64x4 fp form --
115 let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116 def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
121 def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
126 // -- 32x4 integer form --
127 let neverHasSideEffects = 1 in {
128 def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
133 def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
140 let neverHasSideEffects = 1 in {
142 def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
147 def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
153 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
166 def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173 def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
180 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186 def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189 def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
193 def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196 def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199 def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202 def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
207 // vinsertps - insert f32 to XMM
208 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
213 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
220 //===----------------------------------------------------------------------===//
221 // AVX-512 VECTOR EXTRACT
223 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
225 def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229 def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
235 def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
240 def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
246 let neverHasSideEffects = 1 in {
248 def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252 def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
258 def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
263 def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
269 def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
273 def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
277 def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
281 def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
286 def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
290 def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
294 def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
298 def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
302 // A 256-bit subvector extract from the first 512-bit vector position
303 // is a subregister copy that needs no instruction.
304 def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306 def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308 def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310 def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
314 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316 def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318 def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
324 // A 128-bit subvector insert to the first 512-bit vector position
325 // is a subregister copy that needs no instruction.
326 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
330 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
334 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
338 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
343 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
352 // vextractps - extract 32 bits from XMM
353 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
359 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
365 //===---------------------------------------------------------------------===//
368 multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
377 let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
383 let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
389 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
394 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
395 (VBROADCASTSSZrm addr:$src)>;
396 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
397 (VBROADCASTSDZrm addr:$src)>;
399 multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
400 RegisterClass SrcRC, RegisterClass KRC> {
401 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
402 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
403 []>, EVEX, EVEX_V512;
404 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
405 (ins KRC:$mask, SrcRC:$src),
406 !strconcat(OpcodeStr,
407 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
408 []>, EVEX, EVEX_V512, EVEX_KZ;
411 defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
412 defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
415 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
416 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
418 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
419 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
421 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
422 (VPBROADCASTDrZrr GR32:$src)>;
423 def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
424 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
425 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
426 (VPBROADCASTQrZrr GR64:$src)>;
427 def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
428 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
430 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
431 (VPBROADCASTDrZrr GR32:$src)>;
432 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
433 (VPBROADCASTQrZrr GR64:$src)>;
435 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
436 X86MemOperand x86memop, PatFrag ld_frag,
437 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
439 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
440 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
442 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
443 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
445 !strconcat(OpcodeStr,
446 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
448 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
451 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
452 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
454 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
455 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
457 !strconcat(OpcodeStr,
458 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
459 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
460 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
464 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
465 loadi32, VR512, v16i32, v4i32, VK16WM>,
466 EVEX_V512, EVEX_CD8<32, CD8VT1>;
467 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
468 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
469 EVEX_CD8<64, CD8VT1>;
471 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
472 (VPBROADCASTDZrr VR128X:$src)>;
473 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
474 (VPBROADCASTQZrr VR128X:$src)>;
476 def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
477 (VBROADCASTSSZrr VR128X:$src)>;
478 def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
479 (VBROADCASTSDZrr VR128X:$src)>;
481 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
482 (VBROADCASTSSZrr VR128X:$src)>;
483 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
484 (VBROADCASTSDZrr VR128X:$src)>;
486 // Provide fallback in case the load node that is used in the patterns above
487 // is used by additional users, which prevents the pattern selection.
488 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
489 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
490 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
491 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
494 let Predicates = [HasAVX512] in {
495 def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
497 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
498 addr:$src)), sub_ymm)>;
500 //===----------------------------------------------------------------------===//
501 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
504 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
505 RegisterClass DstRC, RegisterClass KRC,
506 ValueType OpVT, ValueType SrcVT> {
507 def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
508 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
512 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
513 VK16, v16i32, v16i1>, EVEX_V512;
514 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
515 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
517 //===----------------------------------------------------------------------===//
520 // -- immediate form --
521 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
522 SDNode OpNode, PatFrag mem_frag,
523 X86MemOperand x86memop, ValueType OpVT> {
524 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
525 (ins RC:$src1, i8imm:$src2),
526 !strconcat(OpcodeStr,
527 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
529 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
531 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
532 (ins x86memop:$src1, i8imm:$src2),
533 !strconcat(OpcodeStr,
534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
536 (OpVT (OpNode (mem_frag addr:$src1),
537 (i8 imm:$src2))))]>, EVEX;
540 defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
541 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
542 let ExeDomain = SSEPackedDouble in
543 defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
544 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
546 // -- VPERM - register form --
547 multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
548 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
550 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
551 (ins RC:$src1, RC:$src2),
552 !strconcat(OpcodeStr,
553 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
555 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
557 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
558 (ins RC:$src1, x86memop:$src2),
559 !strconcat(OpcodeStr,
560 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
562 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
566 defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
567 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
568 defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
569 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
570 let ExeDomain = SSEPackedSingle in
571 defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
572 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
573 let ExeDomain = SSEPackedDouble in
574 defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
575 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
577 // -- VPERM2I - 3 source operands form --
578 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
579 PatFrag mem_frag, X86MemOperand x86memop,
581 let Constraints = "$src1 = $dst" in {
582 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
583 (ins RC:$src1, RC:$src2, RC:$src3),
584 !strconcat(OpcodeStr,
585 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
587 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
590 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
591 (ins RC:$src1, RC:$src2, x86memop:$src3),
592 !strconcat(OpcodeStr,
593 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
595 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
596 (mem_frag addr:$src3))))]>, EVEX_4V;
599 defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
600 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
601 defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
602 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
603 defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
604 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
605 defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
606 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
608 //===----------------------------------------------------------------------===//
609 // AVX-512 - BLEND using mask
611 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, Intrinsic Int,
612 RegisterClass KRC, RegisterClass RC,
613 X86MemOperand x86memop, PatFrag mem_frag,
614 SDNode OpNode, ValueType vt> {
615 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
616 (ins KRC:$mask, RC:$src1, RC:$src2),
617 !strconcat(OpcodeStr,
618 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
619 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
620 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
621 def rr_Int : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
622 (ins KRC:$mask, RC:$src1, RC:$src2),
623 !strconcat(OpcodeStr,
624 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
625 [(set RC:$dst, (Int KRC:$mask, (vt RC:$src2),
626 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
629 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
630 (ins KRC:$mask, RC:$src1, x86memop:$src2),
631 !strconcat(OpcodeStr,
632 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
636 def rm_Int : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
637 (ins KRC:$mask, RC:$src1, x86memop:$src2),
638 !strconcat(OpcodeStr,
639 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
640 [(set RC:$dst, (Int KRC:$mask, (vt RC:$src1),
641 (mem_frag addr:$src2)))]>,
646 let ExeDomain = SSEPackedSingle in
647 defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
648 int_x86_avx512_mask_blend_ps_512,
649 VK16WM, VR512, f512mem,
650 memopv16f32, vselect, v16f32>,
651 EVEX_CD8<32, CD8VF>, EVEX_V512;
652 let ExeDomain = SSEPackedDouble in
653 defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
654 int_x86_avx512_mask_blend_pd_512,
655 VK8WM, VR512, f512mem,
656 memopv8f64, vselect, v8f64>,
657 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
659 defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
660 int_x86_avx512_mask_blend_d_512,
661 VK16WM, VR512, f512mem,
662 memopv16i32, vselect, v16i32>,
663 EVEX_CD8<32, CD8VF>, EVEX_V512;
665 defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
666 int_x86_avx512_mask_blend_q_512,
667 VK8WM, VR512, f512mem,
668 memopv8i64, vselect, v8i64>,
669 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
671 let Predicates = [HasAVX512] in {
672 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
673 (v8f32 VR256X:$src2))),
675 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
676 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
677 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
679 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
680 (v8i32 VR256X:$src2))),
682 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
683 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
684 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
686 //===----------------------------------------------------------------------===//
687 // Compare Instructions
688 //===----------------------------------------------------------------------===//
690 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
691 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
692 Operand CC, SDNode OpNode, ValueType VT,
693 PatFrag ld_frag, string asm, string asm_alt> {
694 def rr : AVX512Ii8<0xC2, MRMSrcReg,
695 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
696 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
697 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
698 def rm : AVX512Ii8<0xC2, MRMSrcMem,
699 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
700 [(set VK1:$dst, (OpNode (VT RC:$src1),
701 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
702 let neverHasSideEffects = 1 in {
703 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
704 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
705 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
706 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
707 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
708 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
712 let Predicates = [HasAVX512] in {
713 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
714 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
715 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
717 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
718 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
719 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
723 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
724 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
725 SDNode OpNode, ValueType vt> {
726 def rr : AVX512BI<opc, MRMSrcReg,
727 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
728 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
729 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
730 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
731 def rm : AVX512BI<opc, MRMSrcMem,
732 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
733 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
734 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
735 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
738 defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
739 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
740 defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
741 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
743 defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
744 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
745 defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
746 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
748 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
749 (COPY_TO_REGCLASS (VPCMPGTDZrr
750 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
751 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
753 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
754 (COPY_TO_REGCLASS (VPCMPEQDZrr
755 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
756 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
758 multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
759 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
760 SDNode OpNode, ValueType vt, Operand CC, string asm,
762 def rri : AVX512AIi8<opc, MRMSrcReg,
763 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
764 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
765 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
766 def rmi : AVX512AIi8<opc, MRMSrcMem,
767 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
768 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
769 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
770 // Accept explicit immediate argument form instead of comparison code.
771 let neverHasSideEffects = 1 in {
772 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
773 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
774 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
775 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
776 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
777 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
781 defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
782 X86cmpm, v16i32, AVXCC,
783 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
784 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
785 EVEX_V512, EVEX_CD8<32, CD8VF>;
786 defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
787 X86cmpmu, v16i32, AVXCC,
788 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
789 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
790 EVEX_V512, EVEX_CD8<32, CD8VF>;
792 defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
793 X86cmpm, v8i64, AVXCC,
794 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
795 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
796 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
797 defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
798 X86cmpmu, v8i64, AVXCC,
799 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
800 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
801 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
803 // avx512_cmp_packed - sse 1 & 2 compare packed instructions
804 multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
805 X86MemOperand x86memop, Operand CC,
806 SDNode OpNode, ValueType vt, string asm,
807 string asm_alt, Domain d> {
808 def rri : AVX512PIi8<0xC2, MRMSrcReg,
809 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
810 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
811 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
812 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
814 (OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
816 // Accept explicit immediate argument form instead of comparison code.
817 let neverHasSideEffects = 1 in {
818 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
819 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
821 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
822 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
827 defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
828 "vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
829 "vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
830 SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
831 defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
832 "vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
833 "vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
834 SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
837 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
838 (COPY_TO_REGCLASS (VCMPPSZrri
839 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
840 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
842 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
843 (COPY_TO_REGCLASS (VPCMPDZrri
844 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
845 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
847 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
848 (COPY_TO_REGCLASS (VPCMPUDZrri
849 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
850 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
853 // Mask register copy, including
854 // - copy between mask registers
855 // - load/store mask registers
856 // - copy from GPR to mask register and vice versa
858 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
859 string OpcodeStr, RegisterClass KRC,
860 ValueType vt, X86MemOperand x86memop> {
861 let neverHasSideEffects = 1 in {
862 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
863 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
865 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
866 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
867 [(set KRC:$dst, (vt (load addr:$src)))]>;
869 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
870 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
874 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
876 RegisterClass KRC, RegisterClass GRC> {
877 let neverHasSideEffects = 1 in {
878 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
879 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
880 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
881 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
885 let Predicates = [HasAVX512] in {
886 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
888 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
892 let Predicates = [HasAVX512] in {
893 // GR16 from/to 16-bit mask
894 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
895 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
896 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
897 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
899 // Store kreg in memory
900 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
901 (KMOVWmk addr:$dst, VK16:$src)>;
903 def : Pat<(store VK8:$src, addr:$dst),
904 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
906 def : Pat<(i1 (load addr:$src)),
907 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
909 def : Pat<(v8i1 (load addr:$src)),
910 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
912 def : Pat<(i1 (X86trunc (i32 GR32:$src))),
913 (COPY_TO_REGCLASS (KMOVWkr $src), VK1)>;
915 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
916 let Predicates = [HasAVX512] in {
917 // GR from/to 8-bit mask without native support
918 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
920 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
922 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
924 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
927 def : Pat<(i1 (extractelt VK16:$src, (iPTR 0))),
928 (COPY_TO_REGCLASS VK16:$src, VK1)>;
929 def : Pat<(i1 (extractelt VK8:$src, (iPTR 0))),
930 (COPY_TO_REGCLASS VK8:$src, VK1)>;
934 // Mask unary operation
936 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
937 RegisterClass KRC, SDPatternOperator OpNode> {
938 let Predicates = [HasAVX512] in
939 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
940 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
941 [(set KRC:$dst, (OpNode KRC:$src))]>;
944 multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
945 SDPatternOperator OpNode> {
946 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
950 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
952 multiclass avx512_mask_unop_int<string IntName, string InstName> {
953 let Predicates = [HasAVX512] in
954 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
956 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
957 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
959 defm : avx512_mask_unop_int<"knot", "KNOT">;
961 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
962 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
963 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
965 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
966 def : Pat<(not VK8:$src),
968 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
970 // Mask binary operation
971 // - KAND, KANDN, KOR, KXNOR, KXOR
972 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
973 RegisterClass KRC, SDPatternOperator OpNode> {
974 let Predicates = [HasAVX512] in
975 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
976 !strconcat(OpcodeStr,
977 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
978 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
981 multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
982 SDPatternOperator OpNode> {
983 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
987 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
988 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
990 let isCommutable = 1 in {
991 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
992 let isCommutable = 0 in
993 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
994 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
995 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
996 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
999 def : Pat<(xor VK1:$src1, VK1:$src2),
1000 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1001 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1003 def : Pat<(or VK1:$src1, VK1:$src2),
1004 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1005 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1007 def : Pat<(not VK1:$src),
1008 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src, VK16),
1009 (COPY_TO_REGCLASS (VCMPSSZrr (f32 (IMPLICIT_DEF)),
1010 (f32 (IMPLICIT_DEF)), (i8 0)), VK16)), VK1)>;
1012 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1013 let Predicates = [HasAVX512] in
1014 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1015 (i16 GR16:$src1), (i16 GR16:$src2)),
1016 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1017 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1018 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1021 defm : avx512_mask_binop_int<"kand", "KAND">;
1022 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1023 defm : avx512_mask_binop_int<"kor", "KOR">;
1024 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1025 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1027 // With AVX-512, 8-bit mask is promoted to 16-bit mask.
1028 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1029 let Predicates = [HasAVX512] in
1030 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1032 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1033 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1036 defm : avx512_binop_pat<and, KANDWrr>;
1037 defm : avx512_binop_pat<andn, KANDNWrr>;
1038 defm : avx512_binop_pat<or, KORWrr>;
1039 defm : avx512_binop_pat<xnor, KXNORWrr>;
1040 defm : avx512_binop_pat<xor, KXORWrr>;
1043 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
1044 RegisterClass KRC> {
1045 let Predicates = [HasAVX512] in
1046 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1047 !strconcat(OpcodeStr,
1048 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1051 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
1052 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
1053 VEX_4V, VEX_L, OpSize, TB;
1056 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
1057 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1058 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1059 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1062 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1063 let Predicates = [HasAVX512] in
1064 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1065 (i16 GR16:$src1), (i16 GR16:$src2)),
1066 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1067 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1068 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1070 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
1073 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1075 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1076 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
1077 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1078 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1081 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1082 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1086 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
1088 def : Pat<(X86cmp VK1:$src1, VK1:$src2),
1089 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1090 (COPY_TO_REGCLASS VK1:$src2, VK16))>;
1093 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1095 let Predicates = [HasAVX512] in
1096 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1097 !strconcat(OpcodeStr,
1098 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
1099 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1102 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1104 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
1105 VEX, OpSize, TA, VEX_W;
1108 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1109 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
1111 // Mask setting all 0s or 1s
1112 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1113 let Predicates = [HasAVX512] in
1114 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1115 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1116 [(set KRC:$dst, (VT Val))]>;
1119 multiclass avx512_mask_setop_w<PatFrag Val> {
1120 defm B : avx512_mask_setop<VK8, v8i1, Val>;
1121 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1124 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1125 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1127 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1128 let Predicates = [HasAVX512] in {
1129 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1130 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
1132 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1133 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1135 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1136 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1138 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1139 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1141 //===----------------------------------------------------------------------===//
1142 // AVX-512 - Aligned and unaligned load and store
1145 multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1146 X86MemOperand x86memop, PatFrag ld_frag,
1147 string asm, Domain d> {
1148 let neverHasSideEffects = 1 in
1149 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1150 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1152 let canFoldAsLoad = 1 in
1153 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1154 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1155 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1156 let Constraints = "$src1 = $dst" in {
1157 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1158 (ins RC:$src1, KRC:$mask, RC:$src2),
1160 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1162 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1163 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1165 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1166 [], d>, EVEX, EVEX_K;
1170 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1171 "vmovaps", SSEPackedSingle>,
1172 EVEX_V512, EVEX_CD8<32, CD8VF>;
1173 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1174 "vmovapd", SSEPackedDouble>,
1175 OpSize, EVEX_V512, VEX_W,
1176 EVEX_CD8<64, CD8VF>;
1177 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1178 "vmovups", SSEPackedSingle>,
1179 EVEX_V512, EVEX_CD8<32, CD8VF>;
1180 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1181 "vmovupd", SSEPackedDouble>,
1182 OpSize, EVEX_V512, VEX_W,
1183 EVEX_CD8<64, CD8VF>;
1184 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1185 "vmovaps\t{$src, $dst|$dst, $src}",
1186 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1187 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1188 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1189 "vmovapd\t{$src, $dst|$dst, $src}",
1190 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1191 SSEPackedDouble>, EVEX, EVEX_V512,
1192 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1193 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1194 "vmovups\t{$src, $dst|$dst, $src}",
1195 [(store (v16f32 VR512:$src), addr:$dst)],
1196 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1197 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1198 "vmovupd\t{$src, $dst|$dst, $src}",
1199 [(store (v8f64 VR512:$src), addr:$dst)],
1200 SSEPackedDouble>, EVEX, EVEX_V512,
1201 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1203 let neverHasSideEffects = 1 in {
1204 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1206 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1208 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1210 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1211 EVEX, EVEX_V512, VEX_W;
1212 let mayStore = 1 in {
1213 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1214 (ins i512mem:$dst, VR512:$src),
1215 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1216 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1217 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1218 (ins i512mem:$dst, VR512:$src),
1219 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1220 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1222 let mayLoad = 1 in {
1223 def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1225 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1226 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1227 def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1229 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1230 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1234 // 512-bit aligned load/store
1235 def : Pat<(alignedloadv8i64 addr:$src), (VMOVDQA64rm addr:$src)>;
1236 def : Pat<(alignedloadv16i32 addr:$src), (VMOVDQA32rm addr:$src)>;
1238 def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1239 (VMOVDQA64mr addr:$dst, VR512:$src)>;
1240 def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1241 (VMOVDQA32mr addr:$dst, VR512:$src)>;
1243 multiclass avx512_mov_int<bits<8> load_opc, bits<8> store_opc, string asm,
1244 RegisterClass RC, RegisterClass KRC,
1245 PatFrag ld_frag, X86MemOperand x86memop> {
1246 let neverHasSideEffects = 1 in
1247 def rr : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1248 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1249 let canFoldAsLoad = 1 in
1250 def rm : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1251 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1252 [(set RC:$dst, (ld_frag addr:$src))]>, EVEX;
1254 def mr : AVX512XSI<store_opc, MRMDestMem, (outs),
1255 (ins x86memop:$dst, VR512:$src),
1256 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>, EVEX;
1257 let Constraints = "$src1 = $dst" in {
1258 def rrk : AVX512XSI<load_opc, MRMSrcReg, (outs RC:$dst),
1259 (ins RC:$src1, KRC:$mask, RC:$src2),
1261 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1263 def rmk : AVX512XSI<load_opc, MRMSrcMem, (outs RC:$dst),
1264 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1266 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1271 defm VMOVDQU32 : avx512_mov_int<0x6F, 0x7F, "vmovdqu32", VR512, VK16WM,
1272 memopv16i32, i512mem>,
1273 EVEX_V512, EVEX_CD8<32, CD8VF>;
1274 defm VMOVDQU64 : avx512_mov_int<0x6F, 0x7F, "vmovdqu64", VR512, VK8WM,
1275 memopv8i64, i512mem>,
1276 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1278 // 512-bit unaligned load/store
1279 def : Pat<(loadv8i64 addr:$src), (VMOVDQU64rm addr:$src)>;
1280 def : Pat<(loadv16i32 addr:$src), (VMOVDQU32rm addr:$src)>;
1282 def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1283 (VMOVDQU64mr addr:$dst, VR512:$src)>;
1284 def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1285 (VMOVDQU32mr addr:$dst, VR512:$src)>;
1287 let AddedComplexity = 20 in {
1288 def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1289 (v16f32 VR512:$src2))),
1290 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1291 def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1292 (v8f64 VR512:$src2))),
1293 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1294 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1295 (v16i32 VR512:$src2))),
1296 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1297 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1298 (v8i64 VR512:$src2))),
1299 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1301 // Move Int Doubleword to Packed Double Int
1303 def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1304 "vmovd\t{$src, $dst|$dst, $src}",
1306 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1308 def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1309 "vmovd\t{$src, $dst|$dst, $src}",
1311 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1312 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1313 def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1314 "vmovq\t{$src, $dst|$dst, $src}",
1316 (v2i64 (scalar_to_vector GR64:$src)))],
1317 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1318 let isCodeGenOnly = 1 in {
1319 def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1320 "vmovq\t{$src, $dst|$dst, $src}",
1321 [(set FR64:$dst, (bitconvert GR64:$src))],
1322 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1323 def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1324 "vmovq\t{$src, $dst|$dst, $src}",
1325 [(set GR64:$dst, (bitconvert FR64:$src))],
1326 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1328 def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1329 "vmovq\t{$src, $dst|$dst, $src}",
1330 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1331 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1332 EVEX_CD8<64, CD8VT1>;
1334 // Move Int Doubleword to Single Scalar
1336 let isCodeGenOnly = 1 in {
1337 def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1338 "vmovd\t{$src, $dst|$dst, $src}",
1339 [(set FR32X:$dst, (bitconvert GR32:$src))],
1340 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1342 def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1343 "vmovd\t{$src, $dst|$dst, $src}",
1344 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1345 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1348 // Move Packed Doubleword Int to Packed Double Int
1350 def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1351 "vmovd\t{$src, $dst|$dst, $src}",
1352 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1353 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1355 def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1356 (ins i32mem:$dst, VR128X:$src),
1357 "vmovd\t{$src, $dst|$dst, $src}",
1358 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1359 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1360 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1362 // Move Packed Doubleword Int first element to Doubleword Int
1364 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1365 "vmovq\t{$src, $dst|$dst, $src}",
1366 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1368 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1369 Requires<[HasAVX512, In64BitMode]>;
1371 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
1372 (ins i64mem:$dst, VR128X:$src),
1373 "vmovq\t{$src, $dst|$dst, $src}",
1374 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1375 addr:$dst)], IIC_SSE_MOVDQ>,
1376 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
1377 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1379 // Move Scalar Single to Double Int
1381 let isCodeGenOnly = 1 in {
1382 def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1384 "vmovd\t{$src, $dst|$dst, $src}",
1385 [(set GR32:$dst, (bitconvert FR32X:$src))],
1386 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1387 def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1388 (ins i32mem:$dst, FR32X:$src),
1389 "vmovd\t{$src, $dst|$dst, $src}",
1390 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1391 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1394 // Move Quadword Int to Packed Quadword Int
1396 def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1398 "vmovq\t{$src, $dst|$dst, $src}",
1400 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1401 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1403 //===----------------------------------------------------------------------===//
1404 // AVX-512 MOVSS, MOVSD
1405 //===----------------------------------------------------------------------===//
1407 multiclass avx512_move_scalar <string asm, RegisterClass RC,
1408 SDNode OpNode, ValueType vt,
1409 X86MemOperand x86memop, PatFrag mem_pat> {
1410 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1411 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1412 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1413 (scalar_to_vector RC:$src2))))],
1414 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1415 let Constraints = "$src1 = $dst" in
1416 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
1417 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
1419 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
1420 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
1421 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1422 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1423 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1425 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1426 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1427 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1431 let ExeDomain = SSEPackedSingle in
1432 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
1433 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1435 let ExeDomain = SSEPackedDouble in
1436 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
1437 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1439 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
1440 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
1441 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
1443 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
1444 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
1445 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
1447 // For the disassembler
1448 let isCodeGenOnly = 1 in {
1449 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1450 (ins VR128X:$src1, FR32X:$src2),
1451 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1453 XS, EVEX_4V, VEX_LIG;
1454 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1455 (ins VR128X:$src1, FR64X:$src2),
1456 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1458 XD, EVEX_4V, VEX_LIG, VEX_W;
1461 let Predicates = [HasAVX512] in {
1462 let AddedComplexity = 15 in {
1463 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1464 // MOVS{S,D} to the lower bits.
1465 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1466 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1467 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1468 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1469 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1470 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1471 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1472 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1474 // Move low f32 and clear high bits.
1475 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1476 (SUBREG_TO_REG (i32 0),
1477 (VMOVSSZrr (v4f32 (V_SET0)),
1478 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1479 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1480 (SUBREG_TO_REG (i32 0),
1481 (VMOVSSZrr (v4i32 (V_SET0)),
1482 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1485 let AddedComplexity = 20 in {
1486 // MOVSSrm zeros the high parts of the register; represent this
1487 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1488 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1489 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1490 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1491 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1492 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1493 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1495 // MOVSDrm zeros the high parts of the register; represent this
1496 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1497 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1498 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1499 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1500 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1501 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1502 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1503 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1504 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1505 def : Pat<(v2f64 (X86vzload addr:$src)),
1506 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1508 // Represent the same patterns above but in the form they appear for
1510 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1511 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
1512 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
1513 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1514 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1515 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1516 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1517 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1518 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1520 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1521 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1522 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1523 FR32X:$src)), sub_xmm)>;
1524 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1525 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1526 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1527 FR64X:$src)), sub_xmm)>;
1528 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1529 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
1530 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
1532 // Move low f64 and clear high bits.
1533 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1534 (SUBREG_TO_REG (i32 0),
1535 (VMOVSDZrr (v2f64 (V_SET0)),
1536 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1538 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1539 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1540 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1542 // Extract and store.
1543 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1545 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1546 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1548 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1550 // Shuffle with VMOVSS
1551 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1552 (VMOVSSZrr (v4i32 VR128X:$src1),
1553 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1554 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1555 (VMOVSSZrr (v4f32 VR128X:$src1),
1556 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1559 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1560 (SUBREG_TO_REG (i32 0),
1561 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1562 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1564 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1565 (SUBREG_TO_REG (i32 0),
1566 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1567 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1570 // Shuffle with VMOVSD
1571 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1572 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1573 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1574 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1575 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1576 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1577 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1578 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1581 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1582 (SUBREG_TO_REG (i32 0),
1583 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1584 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1586 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1587 (SUBREG_TO_REG (i32 0),
1588 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1589 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1592 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1593 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1594 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1595 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1596 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1597 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1598 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1599 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1602 let AddedComplexity = 15 in
1603 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1605 "vmovq\t{$src, $dst|$dst, $src}",
1606 [(set VR128X:$dst, (v2i64 (X86vzmovl
1607 (v2i64 VR128X:$src))))],
1608 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1610 let AddedComplexity = 20 in
1611 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1613 "vmovq\t{$src, $dst|$dst, $src}",
1614 [(set VR128X:$dst, (v2i64 (X86vzmovl
1615 (loadv2i64 addr:$src))))],
1616 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1617 EVEX_CD8<8, CD8VT8>;
1619 let Predicates = [HasAVX512] in {
1620 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1621 let AddedComplexity = 20 in {
1622 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1623 (VMOVDI2PDIZrm addr:$src)>;
1624 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1625 (VMOV64toPQIZrr GR64:$src)>;
1626 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1627 (VMOVDI2PDIZrr GR32:$src)>;
1629 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1630 (VMOVDI2PDIZrm addr:$src)>;
1631 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1632 (VMOVDI2PDIZrm addr:$src)>;
1633 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1634 (VMOVZPQILo2PQIZrm addr:$src)>;
1635 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1636 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1637 def : Pat<(v2i64 (X86vzload addr:$src)),
1638 (VMOVZPQILo2PQIZrm addr:$src)>;
1641 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1642 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1643 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1644 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1645 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1646 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1647 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1650 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1651 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1653 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1654 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1656 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1657 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1659 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1660 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1662 //===----------------------------------------------------------------------===//
1663 // AVX-512 - Integer arithmetic
1665 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1666 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1667 X86MemOperand x86memop, PatFrag scalar_mfrag,
1668 X86MemOperand x86scalar_mop, string BrdcstStr,
1669 OpndItins itins, bit IsCommutable = 0> {
1670 let isCommutable = IsCommutable in
1671 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1672 (ins RC:$src1, RC:$src2),
1673 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1674 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1676 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1677 (ins RC:$src1, x86memop:$src2),
1678 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1679 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1681 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1682 (ins RC:$src1, x86scalar_mop:$src2),
1683 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1684 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1685 [(set RC:$dst, (OpNode RC:$src1,
1686 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1687 itins.rm>, EVEX_4V, EVEX_B;
1689 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1690 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1691 PatFrag memop_frag, X86MemOperand x86memop,
1693 bit IsCommutable = 0> {
1694 let isCommutable = IsCommutable in
1695 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1696 (ins RC:$src1, RC:$src2),
1697 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1698 []>, EVEX_4V, VEX_W;
1699 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1700 (ins RC:$src1, x86memop:$src2),
1701 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1702 []>, EVEX_4V, VEX_W;
1705 defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1706 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1707 EVEX_V512, EVEX_CD8<32, CD8VF>;
1709 defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1710 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1711 EVEX_V512, EVEX_CD8<32, CD8VF>;
1713 defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1714 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1715 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1717 defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1718 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1719 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1721 defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1722 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1723 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1725 defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1726 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1727 EVEX_V512, EVEX_CD8<64, CD8VF>;
1729 defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1730 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1731 EVEX_CD8<64, CD8VF>;
1733 def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1734 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1736 defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
1737 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1738 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1739 defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
1740 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1741 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1743 defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
1744 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1745 EVEX_V512, EVEX_CD8<32, CD8VF>;
1746 defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
1747 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1748 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1750 defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
1751 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1752 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1753 defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
1754 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1755 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1757 defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
1758 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1759 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1760 defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
1761 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1762 T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1764 //===----------------------------------------------------------------------===//
1765 // AVX-512 - Unpack Instructions
1766 //===----------------------------------------------------------------------===//
1768 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1769 PatFrag mem_frag, RegisterClass RC,
1770 X86MemOperand x86memop, string asm,
1772 def rr : AVX512PI<opc, MRMSrcReg,
1773 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1775 (vt (OpNode RC:$src1, RC:$src2)))],
1777 def rm : AVX512PI<opc, MRMSrcMem,
1778 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1780 (vt (OpNode RC:$src1,
1781 (bitconvert (mem_frag addr:$src2)))))],
1785 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1786 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1787 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1788 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1789 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1790 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1791 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1792 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1793 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1794 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1795 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1796 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1798 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1799 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1800 X86MemOperand x86memop> {
1801 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1802 (ins RC:$src1, RC:$src2),
1803 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1804 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1805 IIC_SSE_UNPCK>, EVEX_4V;
1806 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1807 (ins RC:$src1, x86memop:$src2),
1808 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1809 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1810 (bitconvert (memop_frag addr:$src2)))))],
1811 IIC_SSE_UNPCK>, EVEX_4V;
1813 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1814 VR512, memopv16i32, i512mem>, EVEX_V512,
1815 EVEX_CD8<32, CD8VF>;
1816 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1817 VR512, memopv8i64, i512mem>, EVEX_V512,
1818 VEX_W, EVEX_CD8<64, CD8VF>;
1819 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1820 VR512, memopv16i32, i512mem>, EVEX_V512,
1821 EVEX_CD8<32, CD8VF>;
1822 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1823 VR512, memopv8i64, i512mem>, EVEX_V512,
1824 VEX_W, EVEX_CD8<64, CD8VF>;
1825 //===----------------------------------------------------------------------===//
1829 multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1830 SDNode OpNode, PatFrag mem_frag,
1831 X86MemOperand x86memop, ValueType OpVT> {
1832 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1833 (ins RC:$src1, i8imm:$src2),
1834 !strconcat(OpcodeStr,
1835 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1837 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1839 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1840 (ins x86memop:$src1, i8imm:$src2),
1841 !strconcat(OpcodeStr,
1842 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1844 (OpVT (OpNode (mem_frag addr:$src1),
1845 (i8 imm:$src2))))]>, EVEX;
1848 defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1849 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1851 let ExeDomain = SSEPackedSingle in
1852 defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1853 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1854 EVEX_CD8<32, CD8VF>;
1855 let ExeDomain = SSEPackedDouble in
1856 defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1857 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1858 VEX_W, EVEX_CD8<32, CD8VF>;
1860 def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1861 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1862 def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1863 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1865 //===----------------------------------------------------------------------===//
1866 // AVX-512 Logical Instructions
1867 //===----------------------------------------------------------------------===//
1869 defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1870 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1871 EVEX_V512, EVEX_CD8<32, CD8VF>;
1872 defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1873 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1874 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1875 defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1876 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1877 EVEX_V512, EVEX_CD8<32, CD8VF>;
1878 defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1879 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1880 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1881 defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1882 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1883 EVEX_V512, EVEX_CD8<32, CD8VF>;
1884 defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1885 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1886 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1887 defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1888 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1889 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1890 defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1891 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1892 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1894 //===----------------------------------------------------------------------===//
1895 // AVX-512 FP arithmetic
1896 //===----------------------------------------------------------------------===//
1898 multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1900 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
1901 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1902 EVEX_CD8<32, CD8VT1>;
1903 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
1904 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1905 EVEX_CD8<64, CD8VT1>;
1908 let isCommutable = 1 in {
1909 defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1910 defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1911 defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1912 defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1914 let isCommutable = 0 in {
1915 defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1916 defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1919 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1920 RegisterClass RC, ValueType vt,
1921 X86MemOperand x86memop, PatFrag mem_frag,
1922 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1924 Domain d, OpndItins itins, bit commutable> {
1925 let isCommutable = commutable in
1926 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1927 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1928 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
1930 let mayLoad = 1 in {
1931 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1932 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1933 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
1934 itins.rm, d>, EVEX_4V, TB;
1935 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1936 (ins RC:$src1, x86scalar_mop:$src2),
1937 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1938 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1939 [(set RC:$dst, (OpNode RC:$src1,
1940 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1941 itins.rm, d>, EVEX_4V, EVEX_B, TB;
1945 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1946 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1947 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1949 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1950 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1951 SSE_ALU_ITINS_P.d, 1>,
1952 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1954 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
1955 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1956 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1957 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
1958 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1959 SSE_ALU_ITINS_P.d, 1>,
1960 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1962 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
1963 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1964 SSE_ALU_ITINS_P.s, 1>,
1965 EVEX_V512, EVEX_CD8<32, CD8VF>;
1966 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
1967 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1968 SSE_ALU_ITINS_P.s, 1>,
1969 EVEX_V512, EVEX_CD8<32, CD8VF>;
1971 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
1972 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1973 SSE_ALU_ITINS_P.d, 1>,
1974 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1975 defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
1976 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1977 SSE_ALU_ITINS_P.d, 1>,
1978 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1980 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
1981 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1982 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1983 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
1984 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1985 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1987 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
1988 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1989 SSE_ALU_ITINS_P.d, 0>,
1990 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1991 defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
1992 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1993 SSE_ALU_ITINS_P.d, 0>,
1994 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1996 //===----------------------------------------------------------------------===//
1997 // AVX-512 VPTESTM instructions
1998 //===----------------------------------------------------------------------===//
2000 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2001 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2002 SDNode OpNode, ValueType vt> {
2003 def rr : AVX5128I<opc, MRMSrcReg,
2004 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
2005 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2006 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
2007 def rm : AVX5128I<opc, MRMSrcMem,
2008 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
2009 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2010 [(set KRC:$dst, (OpNode (vt RC:$src1),
2011 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
2014 defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
2015 memopv16i32, X86testm, v16i32>, EVEX_V512,
2016 EVEX_CD8<32, CD8VF>;
2017 defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
2018 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
2019 EVEX_CD8<64, CD8VF>;
2021 //===----------------------------------------------------------------------===//
2022 // AVX-512 Shift instructions
2023 //===----------------------------------------------------------------------===//
2024 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
2025 string OpcodeStr, SDNode OpNode, RegisterClass RC,
2026 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
2027 RegisterClass KRC> {
2028 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2029 (ins RC:$src1, i8imm:$src2),
2030 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2031 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
2032 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2033 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
2034 (ins KRC:$mask, RC:$src1, i8imm:$src2),
2035 !strconcat(OpcodeStr,
2036 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2037 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2038 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2039 (ins x86memop:$src1, i8imm:$src2),
2040 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2041 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
2042 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2043 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
2044 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
2045 !strconcat(OpcodeStr,
2046 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2047 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2050 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2051 RegisterClass RC, ValueType vt, ValueType SrcVT,
2052 PatFrag bc_frag, RegisterClass KRC> {
2053 // src2 is always 128-bit
2054 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2055 (ins RC:$src1, VR128X:$src2),
2056 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2057 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
2058 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
2059 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2060 (ins KRC:$mask, RC:$src1, VR128X:$src2),
2061 !strconcat(OpcodeStr,
2062 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2063 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
2064 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2065 (ins RC:$src1, i128mem:$src2),
2066 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2067 [(set RC:$dst, (vt (OpNode RC:$src1,
2068 (bc_frag (memopv2i64 addr:$src2)))))],
2069 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
2070 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2071 (ins KRC:$mask, RC:$src1, i128mem:$src2),
2072 !strconcat(OpcodeStr,
2073 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2074 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
2077 defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
2078 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2079 EVEX_V512, EVEX_CD8<32, CD8VF>;
2080 defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
2081 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2082 EVEX_CD8<32, CD8VQ>;
2084 defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
2085 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2086 EVEX_CD8<64, CD8VF>, VEX_W;
2087 defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
2088 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2089 EVEX_CD8<64, CD8VQ>, VEX_W;
2091 defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
2092 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
2093 EVEX_CD8<32, CD8VF>;
2094 defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
2095 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2096 EVEX_CD8<32, CD8VQ>;
2098 defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
2099 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2100 EVEX_CD8<64, CD8VF>, VEX_W;
2101 defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
2102 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2103 EVEX_CD8<64, CD8VQ>, VEX_W;
2105 defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
2106 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
2107 EVEX_V512, EVEX_CD8<32, CD8VF>;
2108 defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
2109 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
2110 EVEX_CD8<32, CD8VQ>;
2112 defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
2113 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
2114 EVEX_CD8<64, CD8VF>, VEX_W;
2115 defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
2116 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
2117 EVEX_CD8<64, CD8VQ>, VEX_W;
2119 //===-------------------------------------------------------------------===//
2120 // Variable Bit Shifts
2121 //===-------------------------------------------------------------------===//
2122 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
2123 RegisterClass RC, ValueType vt,
2124 X86MemOperand x86memop, PatFrag mem_frag> {
2125 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
2126 (ins RC:$src1, RC:$src2),
2127 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2129 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
2131 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
2132 (ins RC:$src1, x86memop:$src2),
2133 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2135 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
2139 defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
2140 i512mem, memopv16i32>, EVEX_V512,
2141 EVEX_CD8<32, CD8VF>;
2142 defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
2143 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2144 EVEX_CD8<64, CD8VF>;
2145 defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
2146 i512mem, memopv16i32>, EVEX_V512,
2147 EVEX_CD8<32, CD8VF>;
2148 defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
2149 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2150 EVEX_CD8<64, CD8VF>;
2151 defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
2152 i512mem, memopv16i32>, EVEX_V512,
2153 EVEX_CD8<32, CD8VF>;
2154 defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
2155 i512mem, memopv8i64>, EVEX_V512, VEX_W,
2156 EVEX_CD8<64, CD8VF>;
2158 //===----------------------------------------------------------------------===//
2159 // AVX-512 - MOVDDUP
2160 //===----------------------------------------------------------------------===//
2162 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
2163 X86MemOperand x86memop, PatFrag memop_frag> {
2164 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2165 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2166 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
2167 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2168 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2170 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
2173 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
2174 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
2175 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
2176 (VMOVDDUPZrm addr:$src)>;
2178 //===---------------------------------------------------------------------===//
2179 // Replicate Single FP - MOVSHDUP and MOVSLDUP
2180 //===---------------------------------------------------------------------===//
2181 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
2182 ValueType vt, RegisterClass RC, PatFrag mem_frag,
2183 X86MemOperand x86memop> {
2184 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
2185 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2186 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
2188 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2189 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2190 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
2193 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
2194 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2195 EVEX_CD8<32, CD8VF>;
2196 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
2197 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
2198 EVEX_CD8<32, CD8VF>;
2200 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
2201 def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
2202 (VMOVSHDUPZrm addr:$src)>;
2203 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
2204 def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
2205 (VMOVSLDUPZrm addr:$src)>;
2207 //===----------------------------------------------------------------------===//
2208 // Move Low to High and High to Low packed FP Instructions
2209 //===----------------------------------------------------------------------===//
2210 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
2211 (ins VR128X:$src1, VR128X:$src2),
2212 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2213 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
2214 IIC_SSE_MOV_LH>, EVEX_4V;
2215 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
2216 (ins VR128X:$src1, VR128X:$src2),
2217 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2218 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2219 IIC_SSE_MOV_LH>, EVEX_4V;
2221 let Predicates = [HasAVX512] in {
2223 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2224 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2225 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2226 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
2229 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2230 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2233 //===----------------------------------------------------------------------===//
2234 // FMA - Fused Multiply Operations
2236 let Constraints = "$src1 = $dst" in {
2237 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2238 RegisterClass RC, X86MemOperand x86memop,
2239 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2240 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2241 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2242 (ins RC:$src1, RC:$src2, RC:$src3),
2243 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2244 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2247 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2248 (ins RC:$src1, RC:$src2, x86memop:$src3),
2249 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2250 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2251 (mem_frag addr:$src3))))]>;
2252 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2253 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2254 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2255 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2256 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2257 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2259 } // Constraints = "$src1 = $dst"
2261 let ExeDomain = SSEPackedSingle in {
2262 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2263 memopv16f32, f32mem, loadf32, "{1to16}",
2264 X86Fmadd, v16f32>, EVEX_V512,
2265 EVEX_CD8<32, CD8VF>;
2266 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2267 memopv16f32, f32mem, loadf32, "{1to16}",
2268 X86Fmsub, v16f32>, EVEX_V512,
2269 EVEX_CD8<32, CD8VF>;
2270 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2271 memopv16f32, f32mem, loadf32, "{1to16}",
2272 X86Fmaddsub, v16f32>,
2273 EVEX_V512, EVEX_CD8<32, CD8VF>;
2274 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2275 memopv16f32, f32mem, loadf32, "{1to16}",
2276 X86Fmsubadd, v16f32>,
2277 EVEX_V512, EVEX_CD8<32, CD8VF>;
2278 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2279 memopv16f32, f32mem, loadf32, "{1to16}",
2280 X86Fnmadd, v16f32>, EVEX_V512,
2281 EVEX_CD8<32, CD8VF>;
2282 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2283 memopv16f32, f32mem, loadf32, "{1to16}",
2284 X86Fnmsub, v16f32>, EVEX_V512,
2285 EVEX_CD8<32, CD8VF>;
2287 let ExeDomain = SSEPackedDouble in {
2288 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2289 memopv8f64, f64mem, loadf64, "{1to8}",
2290 X86Fmadd, v8f64>, EVEX_V512,
2291 VEX_W, EVEX_CD8<64, CD8VF>;
2292 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2293 memopv8f64, f64mem, loadf64, "{1to8}",
2294 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2295 EVEX_CD8<64, CD8VF>;
2296 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2297 memopv8f64, f64mem, loadf64, "{1to8}",
2298 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2299 EVEX_CD8<64, CD8VF>;
2300 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2301 memopv8f64, f64mem, loadf64, "{1to8}",
2302 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2303 EVEX_CD8<64, CD8VF>;
2304 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2305 memopv8f64, f64mem, loadf64, "{1to8}",
2306 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2307 EVEX_CD8<64, CD8VF>;
2308 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2309 memopv8f64, f64mem, loadf64, "{1to8}",
2310 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2311 EVEX_CD8<64, CD8VF>;
2314 let Constraints = "$src1 = $dst" in {
2315 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2316 RegisterClass RC, X86MemOperand x86memop,
2317 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2318 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2320 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2321 (ins RC:$src1, RC:$src3, x86memop:$src2),
2322 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2323 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2324 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2325 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2326 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2327 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2328 [(set RC:$dst, (OpNode RC:$src1,
2329 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2331 } // Constraints = "$src1 = $dst"
2334 let ExeDomain = SSEPackedSingle in {
2335 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2336 memopv16f32, f32mem, loadf32, "{1to16}",
2337 X86Fmadd, v16f32>, EVEX_V512,
2338 EVEX_CD8<32, CD8VF>;
2339 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2340 memopv16f32, f32mem, loadf32, "{1to16}",
2341 X86Fmsub, v16f32>, EVEX_V512,
2342 EVEX_CD8<32, CD8VF>;
2343 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2344 memopv16f32, f32mem, loadf32, "{1to16}",
2345 X86Fmaddsub, v16f32>,
2346 EVEX_V512, EVEX_CD8<32, CD8VF>;
2347 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2348 memopv16f32, f32mem, loadf32, "{1to16}",
2349 X86Fmsubadd, v16f32>,
2350 EVEX_V512, EVEX_CD8<32, CD8VF>;
2351 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2352 memopv16f32, f32mem, loadf32, "{1to16}",
2353 X86Fnmadd, v16f32>, EVEX_V512,
2354 EVEX_CD8<32, CD8VF>;
2355 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2356 memopv16f32, f32mem, loadf32, "{1to16}",
2357 X86Fnmsub, v16f32>, EVEX_V512,
2358 EVEX_CD8<32, CD8VF>;
2360 let ExeDomain = SSEPackedDouble in {
2361 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2362 memopv8f64, f64mem, loadf64, "{1to8}",
2363 X86Fmadd, v8f64>, EVEX_V512,
2364 VEX_W, EVEX_CD8<64, CD8VF>;
2365 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2366 memopv8f64, f64mem, loadf64, "{1to8}",
2367 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2368 EVEX_CD8<64, CD8VF>;
2369 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2370 memopv8f64, f64mem, loadf64, "{1to8}",
2371 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2372 EVEX_CD8<64, CD8VF>;
2373 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2374 memopv8f64, f64mem, loadf64, "{1to8}",
2375 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2376 EVEX_CD8<64, CD8VF>;
2377 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2378 memopv8f64, f64mem, loadf64, "{1to8}",
2379 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2380 EVEX_CD8<64, CD8VF>;
2381 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2382 memopv8f64, f64mem, loadf64, "{1to8}",
2383 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2384 EVEX_CD8<64, CD8VF>;
2388 let Constraints = "$src1 = $dst" in {
2389 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2390 RegisterClass RC, ValueType OpVT,
2391 X86MemOperand x86memop, Operand memop,
2393 let isCommutable = 1 in
2394 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2395 (ins RC:$src1, RC:$src2, RC:$src3),
2396 !strconcat(OpcodeStr,
2397 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2399 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2401 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2402 (ins RC:$src1, RC:$src2, f128mem:$src3),
2403 !strconcat(OpcodeStr,
2404 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2406 (OpVT (OpNode RC:$src2, RC:$src1,
2407 (mem_frag addr:$src3))))]>;
2410 } // Constraints = "$src1 = $dst"
2412 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
2413 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2414 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
2415 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2416 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
2417 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2418 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
2419 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2420 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
2421 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2422 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
2423 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2424 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
2425 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2426 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
2427 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2429 //===----------------------------------------------------------------------===//
2430 // AVX-512 Scalar convert from sign integer to float/double
2431 //===----------------------------------------------------------------------===//
2433 multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2434 X86MemOperand x86memop, string asm> {
2435 let neverHasSideEffects = 1 in {
2436 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
2437 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2440 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2441 (ins DstRC:$src1, x86memop:$src),
2442 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2444 } // neverHasSideEffects = 1
2446 let Predicates = [HasAVX512] in {
2447 defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
2448 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2449 defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
2450 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2451 defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
2452 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2453 defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
2454 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2456 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2457 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2458 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
2459 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2460 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2461 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2462 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
2463 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2465 def : Pat<(f32 (sint_to_fp GR32:$src)),
2466 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2467 def : Pat<(f32 (sint_to_fp GR64:$src)),
2468 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2469 def : Pat<(f64 (sint_to_fp GR32:$src)),
2470 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2471 def : Pat<(f64 (sint_to_fp GR64:$src)),
2472 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2474 defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
2475 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2476 defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
2477 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2478 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
2479 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2480 defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
2481 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2483 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2484 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2485 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2486 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2487 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2488 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2489 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2490 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2492 def : Pat<(f32 (uint_to_fp GR32:$src)),
2493 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2494 def : Pat<(f32 (uint_to_fp GR64:$src)),
2495 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2496 def : Pat<(f64 (uint_to_fp GR32:$src)),
2497 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2498 def : Pat<(f64 (uint_to_fp GR64:$src)),
2499 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2502 //===----------------------------------------------------------------------===//
2503 // AVX-512 Scalar convert from float/double to integer
2504 //===----------------------------------------------------------------------===//
2505 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2506 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2508 let neverHasSideEffects = 1 in {
2509 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2510 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2511 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
2512 Requires<[HasAVX512]>;
2514 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2515 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
2516 Requires<[HasAVX512]>;
2517 } // neverHasSideEffects = 1
2519 let Predicates = [HasAVX512] in {
2520 // Convert float/double to signed/unsigned int 32/64
2521 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2522 ssmem, sse_load_f32, "cvtss2si">,
2523 XS, EVEX_CD8<32, CD8VT1>;
2524 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2525 ssmem, sse_load_f32, "cvtss2si">,
2526 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2527 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2528 ssmem, sse_load_f32, "cvtss2usi">,
2529 XS, EVEX_CD8<32, CD8VT1>;
2530 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2531 int_x86_avx512_cvtss2usi64, ssmem,
2532 sse_load_f32, "cvtss2usi">, XS, VEX_W,
2533 EVEX_CD8<32, CD8VT1>;
2534 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2535 sdmem, sse_load_f64, "cvtsd2si">,
2536 XD, EVEX_CD8<64, CD8VT1>;
2537 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2538 sdmem, sse_load_f64, "cvtsd2si">,
2539 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2540 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2541 sdmem, sse_load_f64, "cvtsd2usi">,
2542 XD, EVEX_CD8<64, CD8VT1>;
2543 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2544 int_x86_avx512_cvtsd2usi64, sdmem,
2545 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
2546 EVEX_CD8<64, CD8VT1>;
2548 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2549 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
2550 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2551 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2552 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
2553 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2554 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2555 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
2556 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2557 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2558 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
2559 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2561 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2562 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
2563 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2564 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2565 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
2566 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2567 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2568 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
2569 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2570 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2571 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
2572 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2574 // Convert float/double to signed/unsigned int 32/64 with truncation
2575 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2576 ssmem, sse_load_f32, "cvttss2si">,
2577 XS, EVEX_CD8<32, CD8VT1>;
2578 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2579 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2580 "cvttss2si">, XS, VEX_W,
2581 EVEX_CD8<32, CD8VT1>;
2582 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2583 sdmem, sse_load_f64, "cvttsd2si">, XD,
2584 EVEX_CD8<64, CD8VT1>;
2585 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2586 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2587 "cvttsd2si">, XD, VEX_W,
2588 EVEX_CD8<64, CD8VT1>;
2589 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2590 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2591 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
2592 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2593 int_x86_avx512_cvttss2usi64, ssmem,
2594 sse_load_f32, "cvttss2usi">, XS, VEX_W,
2595 EVEX_CD8<32, CD8VT1>;
2596 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2597 int_x86_avx512_cvttsd2usi,
2598 sdmem, sse_load_f64, "cvttsd2usi">, XD,
2599 EVEX_CD8<64, CD8VT1>;
2600 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2601 int_x86_avx512_cvttsd2usi64, sdmem,
2602 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
2603 EVEX_CD8<64, CD8VT1>;
2605 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2606 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2608 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2609 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2610 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2611 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2612 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2613 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2616 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2617 loadf32, "cvttss2si">, XS,
2618 EVEX_CD8<32, CD8VT1>;
2619 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2620 loadf32, "cvttss2usi">, XS,
2621 EVEX_CD8<32, CD8VT1>;
2622 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2623 loadf32, "cvttss2si">, XS, VEX_W,
2624 EVEX_CD8<32, CD8VT1>;
2625 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2626 loadf32, "cvttss2usi">, XS, VEX_W,
2627 EVEX_CD8<32, CD8VT1>;
2628 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2629 loadf64, "cvttsd2si">, XD,
2630 EVEX_CD8<64, CD8VT1>;
2631 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2632 loadf64, "cvttsd2usi">, XD,
2633 EVEX_CD8<64, CD8VT1>;
2634 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2635 loadf64, "cvttsd2si">, XD, VEX_W,
2636 EVEX_CD8<64, CD8VT1>;
2637 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2638 loadf64, "cvttsd2usi">, XD, VEX_W,
2639 EVEX_CD8<64, CD8VT1>;
2641 //===----------------------------------------------------------------------===//
2642 // AVX-512 Convert form float to double and back
2643 //===----------------------------------------------------------------------===//
2644 let neverHasSideEffects = 1 in {
2645 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2646 (ins FR32X:$src1, FR32X:$src2),
2647 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2648 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2650 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2651 (ins FR32X:$src1, f32mem:$src2),
2652 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2653 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2654 EVEX_CD8<32, CD8VT1>;
2656 // Convert scalar double to scalar single
2657 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2658 (ins FR64X:$src1, FR64X:$src2),
2659 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2660 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2662 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2663 (ins FR64X:$src1, f64mem:$src2),
2664 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2665 []>, EVEX_4V, VEX_LIG, VEX_W,
2666 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2669 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2670 Requires<[HasAVX512]>;
2671 def : Pat<(fextend (loadf32 addr:$src)),
2672 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2674 def : Pat<(extloadf32 addr:$src),
2675 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2676 Requires<[HasAVX512, OptForSize]>;
2678 def : Pat<(extloadf32 addr:$src),
2679 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2680 Requires<[HasAVX512, OptForSpeed]>;
2682 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2683 Requires<[HasAVX512]>;
2685 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2686 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2687 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2689 let neverHasSideEffects = 1 in {
2690 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2691 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2693 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2695 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2696 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2698 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2699 } // neverHasSideEffects = 1
2702 defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2703 memopv8f64, f512mem, v8f32, v8f64,
2704 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2705 EVEX_CD8<64, CD8VF>;
2707 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2708 memopv4f64, f256mem, v8f64, v8f32,
2709 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2710 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2711 (VCVTPS2PDZrm addr:$src)>;
2713 //===----------------------------------------------------------------------===//
2714 // AVX-512 Vector convert from sign integer to float/double
2715 //===----------------------------------------------------------------------===//
2717 defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2718 memopv8i64, i512mem, v16f32, v16i32,
2719 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2721 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2722 memopv4i64, i256mem, v8f64, v8i32,
2723 SSEPackedDouble>, EVEX_V512, XS,
2724 EVEX_CD8<32, CD8VH>;
2726 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2727 memopv16f32, f512mem, v16i32, v16f32,
2728 SSEPackedSingle>, EVEX_V512, XS,
2729 EVEX_CD8<32, CD8VF>;
2731 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2732 memopv8f64, f512mem, v8i32, v8f64,
2733 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2734 EVEX_CD8<64, CD8VF>;
2736 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2737 memopv16f32, f512mem, v16i32, v16f32,
2738 SSEPackedSingle>, EVEX_V512,
2739 EVEX_CD8<32, CD8VF>;
2741 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2742 memopv8f64, f512mem, v8i32, v8f64,
2743 SSEPackedDouble>, EVEX_V512, VEX_W,
2744 EVEX_CD8<64, CD8VF>;
2746 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2747 memopv4i64, f256mem, v8f64, v8i32,
2748 SSEPackedDouble>, EVEX_V512, XS,
2749 EVEX_CD8<32, CD8VH>;
2751 defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2752 memopv16i32, f512mem, v16f32, v16i32,
2753 SSEPackedSingle>, EVEX_V512, XD,
2754 EVEX_CD8<32, CD8VF>;
2756 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2757 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2758 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2761 def : Pat<(int_x86_avx512_cvtdq2_ps_512 VR512:$src),
2762 (VCVTDQ2PSZrr VR512:$src)>;
2763 def : Pat<(int_x86_avx512_cvtdq2_ps_512 (bitconvert (memopv8i64 addr:$src))),
2764 (VCVTDQ2PSZrm addr:$src)>;
2766 def VCVTPS2DQZrr : AVX512BI<0x5B, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2767 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2769 (int_x86_avx512_cvt_ps2dq_512 VR512:$src))],
2770 IIC_SSE_CVT_PS_RR>, EVEX, EVEX_V512;
2771 def VCVTPS2DQZrm : AVX512BI<0x5B, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2772 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2774 (int_x86_avx512_cvt_ps2dq_512 (memopv16f32 addr:$src)))],
2775 IIC_SSE_CVT_PS_RM>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2778 let Predicates = [HasAVX512] in {
2779 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2780 (VCVTPD2PSZrm addr:$src)>;
2781 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2782 (VCVTPS2PDZrm addr:$src)>;
2785 //===----------------------------------------------------------------------===//
2786 // Half precision conversion instructions
2787 //===----------------------------------------------------------------------===//
2788 multiclass avx512_f16c_ph2ps<RegisterClass destRC, RegisterClass srcRC,
2789 X86MemOperand x86memop, Intrinsic Int> {
2790 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
2791 "vcvtph2ps\t{$src, $dst|$dst, $src}",
2792 [(set destRC:$dst, (Int srcRC:$src))]>, EVEX;
2793 let neverHasSideEffects = 1, mayLoad = 1 in
2794 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
2795 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
2798 multiclass avx512_f16c_ps2ph<RegisterClass destRC, RegisterClass srcRC,
2799 X86MemOperand x86memop, Intrinsic Int> {
2800 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
2801 (ins srcRC:$src1, i32i8imm:$src2),
2802 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2803 [(set destRC:$dst, (Int srcRC:$src1, imm:$src2))]>, EVEX;
2804 let neverHasSideEffects = 1, mayStore = 1 in
2805 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
2806 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
2807 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
2810 defm VCVTPH2PSZ : avx512_f16c_ph2ps<VR512, VR256X, f256mem,
2811 int_x86_avx512_vcvtph2ps_512>, EVEX_V512,
2812 EVEX_CD8<32, CD8VH>;
2813 defm VCVTPS2PHZ : avx512_f16c_ps2ph<VR256X, VR512, f256mem,
2814 int_x86_avx512_vcvtps2ph_512>, EVEX_V512,
2815 EVEX_CD8<32, CD8VH>;
2817 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2818 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2819 "ucomiss">, TB, EVEX, VEX_LIG,
2820 EVEX_CD8<32, CD8VT1>;
2821 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
2822 "ucomisd">, TB, OpSize, EVEX,
2823 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2824 let Pattern = []<dag> in {
2825 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
2826 "comiss">, TB, EVEX, VEX_LIG,
2827 EVEX_CD8<32, CD8VT1>;
2828 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
2829 "comisd">, TB, OpSize, EVEX,
2830 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2832 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
2833 load, "ucomiss">, TB, EVEX, VEX_LIG,
2834 EVEX_CD8<32, CD8VT1>;
2835 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
2836 load, "ucomisd">, TB, OpSize, EVEX,
2837 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2839 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
2840 load, "comiss">, TB, EVEX, VEX_LIG,
2841 EVEX_CD8<32, CD8VT1>;
2842 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
2843 load, "comisd">, TB, OpSize, EVEX,
2844 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2847 /// avx512_unop_p - AVX-512 unops in packed form.
2848 multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2849 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2850 !strconcat(OpcodeStr,
2851 "ps\t{$src, $dst|$dst, $src}"),
2852 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
2854 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
2855 !strconcat(OpcodeStr,
2856 "ps\t{$src, $dst|$dst, $src}"),
2857 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2858 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2859 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2860 !strconcat(OpcodeStr,
2861 "pd\t{$src, $dst|$dst, $src}"),
2862 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
2863 EVEX, EVEX_V512, VEX_W;
2864 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2865 !strconcat(OpcodeStr,
2866 "pd\t{$src, $dst|$dst, $src}"),
2867 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2868 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2871 /// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
2872 multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2873 Intrinsic V16F32Int, Intrinsic V8F64Int> {
2874 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2875 !strconcat(OpcodeStr,
2876 "ps\t{$src, $dst|$dst, $src}"),
2877 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2879 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2880 !strconcat(OpcodeStr,
2881 "ps\t{$src, $dst|$dst, $src}"),
2883 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2884 EVEX_V512, EVEX_CD8<32, CD8VF>;
2885 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2886 !strconcat(OpcodeStr,
2887 "pd\t{$src, $dst|$dst, $src}"),
2888 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2889 EVEX, EVEX_V512, VEX_W;
2890 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2891 !strconcat(OpcodeStr,
2892 "pd\t{$src, $dst|$dst, $src}"),
2894 (V8F64Int (memopv8f64 addr:$src)))]>,
2895 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2898 /// avx512_fp_unop_s - AVX-512 unops in scalar form.
2899 multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr> {
2900 let hasSideEffects = 0 in {
2901 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
2902 (ins FR32X:$src1, FR32X:$src2),
2903 !strconcat(OpcodeStr,
2904 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2906 let mayLoad = 1 in {
2907 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
2908 (ins FR32X:$src1, f32mem:$src2),
2909 !strconcat(OpcodeStr,
2910 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2911 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2912 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2913 (ins VR128X:$src1, ssmem:$src2),
2914 !strconcat(OpcodeStr,
2915 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2916 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2918 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
2919 (ins FR64X:$src1, FR64X:$src2),
2920 !strconcat(OpcodeStr,
2921 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2923 let mayLoad = 1 in {
2924 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
2925 (ins FR64X:$src1, f64mem:$src2),
2926 !strconcat(OpcodeStr,
2927 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2928 EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2929 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2930 (ins VR128X:$src1, sdmem:$src2),
2931 !strconcat(OpcodeStr,
2932 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2933 []>, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2938 defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14">,
2939 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
2940 avx512_fp_unop_p_int<0x4C, "vrcp14",
2941 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
2943 defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14">,
2944 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
2945 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
2946 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
2948 def : Pat<(int_x86_avx512_rsqrt14_ss VR128X:$src),
2949 (COPY_TO_REGCLASS (VRSQRT14SSZr (f32 (IMPLICIT_DEF)),
2950 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2952 def : Pat<(int_x86_avx512_rsqrt14_ss sse_load_f32:$src),
2953 (VRSQRT14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2955 def : Pat<(int_x86_avx512_rcp14_ss VR128X:$src),
2956 (COPY_TO_REGCLASS (VRCP14SSZr (f32 (IMPLICIT_DEF)),
2957 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2959 def : Pat<(int_x86_avx512_rcp14_ss sse_load_f32:$src),
2960 (VRCP14SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2962 let AddedComplexity = 20, Predicates = [HasERI] in {
2963 defm VRCP28 : avx512_fp_unop_s<0xCB, "vrcp28">,
2964 avx512_fp_unop_p<0xCA, "vrcp28", X86frcp>,
2965 avx512_fp_unop_p_int<0xCA, "vrcp28",
2966 int_x86_avx512_rcp28_ps_512, int_x86_avx512_rcp28_pd_512>;
2968 defm VRSQRT28 : avx512_fp_unop_s<0xCD, "vrsqrt28">,
2969 avx512_fp_unop_p<0xCC, "vrsqrt28", X86frsqrt>,
2970 avx512_fp_unop_p_int<0xCC, "vrsqrt28",
2971 int_x86_avx512_rsqrt28_ps_512, int_x86_avx512_rsqrt28_pd_512>;
2974 let Predicates = [HasERI] in {
2975 def : Pat<(int_x86_avx512_rsqrt28_ss VR128X:$src),
2976 (COPY_TO_REGCLASS (VRSQRT28SSZr (f32 (IMPLICIT_DEF)),
2977 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2979 def : Pat<(int_x86_avx512_rsqrt28_ss sse_load_f32:$src),
2980 (VRSQRT28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2982 def : Pat<(int_x86_avx512_rcp28_ss VR128X:$src),
2983 (COPY_TO_REGCLASS (VRCP28SSZr (f32 (IMPLICIT_DEF)),
2984 (COPY_TO_REGCLASS VR128X:$src, FR32)),
2986 def : Pat<(int_x86_avx512_rcp28_ss sse_load_f32:$src),
2987 (VRCP28SSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2989 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2990 Intrinsic V16F32Int, Intrinsic V8F64Int,
2991 OpndItins itins_s, OpndItins itins_d> {
2992 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2993 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2994 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
2998 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2999 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3001 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
3002 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
3004 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3005 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3006 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
3010 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3011 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3012 [(set VR512:$dst, (OpNode
3013 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
3014 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
3016 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3017 !strconcat(OpcodeStr,
3018 "ps\t{$src, $dst|$dst, $src}"),
3019 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
3021 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3022 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3024 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
3025 EVEX_V512, EVEX_CD8<32, CD8VF>;
3026 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
3027 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3028 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
3029 EVEX, EVEX_V512, VEX_W;
3030 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
3031 !strconcat(OpcodeStr,
3032 "pd\t{$src, $dst|$dst, $src}"),
3033 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
3034 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3037 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
3038 Intrinsic F32Int, Intrinsic F64Int,
3039 OpndItins itins_s, OpndItins itins_d> {
3040 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
3041 (ins FR32X:$src1, FR32X:$src2),
3042 !strconcat(OpcodeStr,
3043 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3044 [], itins_s.rr>, XS, EVEX_4V;
3045 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3046 (ins VR128X:$src1, VR128X:$src2),
3047 !strconcat(OpcodeStr,
3048 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3050 (F32Int VR128X:$src1, VR128X:$src2))],
3051 itins_s.rr>, XS, EVEX_4V;
3052 let mayLoad = 1 in {
3053 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
3054 (ins FR32X:$src1, f32mem:$src2),
3055 !strconcat(OpcodeStr,
3056 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3057 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3058 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3059 (ins VR128X:$src1, ssmem:$src2),
3060 !strconcat(OpcodeStr,
3061 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3063 (F32Int VR128X:$src1, sse_load_f32:$src2))],
3064 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
3066 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
3067 (ins FR64X:$src1, FR64X:$src2),
3068 !strconcat(OpcodeStr,
3069 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3071 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
3072 (ins VR128X:$src1, VR128X:$src2),
3073 !strconcat(OpcodeStr,
3074 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3076 (F64Int VR128X:$src1, VR128X:$src2))],
3077 itins_s.rr>, XD, EVEX_4V, VEX_W;
3078 let mayLoad = 1 in {
3079 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
3080 (ins FR64X:$src1, f64mem:$src2),
3081 !strconcat(OpcodeStr,
3082 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
3083 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3084 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
3085 (ins VR128X:$src1, sdmem:$src2),
3086 !strconcat(OpcodeStr,
3087 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3089 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
3090 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
3095 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
3096 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
3097 SSE_SQRTSS, SSE_SQRTSD>,
3098 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
3099 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
3100 SSE_SQRTPS, SSE_SQRTPD>;
3102 let Predicates = [HasAVX512] in {
3103 def : Pat<(f32 (fsqrt FR32X:$src)),
3104 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3105 def : Pat<(f32 (fsqrt (load addr:$src))),
3106 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3107 Requires<[OptForSize]>;
3108 def : Pat<(f64 (fsqrt FR64X:$src)),
3109 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
3110 def : Pat<(f64 (fsqrt (load addr:$src))),
3111 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
3112 Requires<[OptForSize]>;
3114 def : Pat<(f32 (X86frsqrt FR32X:$src)),
3115 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3116 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3117 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3118 Requires<[OptForSize]>;
3120 def : Pat<(f32 (X86frcp FR32X:$src)),
3121 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
3122 def : Pat<(f32 (X86frcp (load addr:$src))),
3123 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
3124 Requires<[OptForSize]>;
3126 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
3127 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
3128 (COPY_TO_REGCLASS VR128X:$src, FR32)),
3130 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3131 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3133 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
3134 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
3135 (COPY_TO_REGCLASS VR128X:$src, FR64)),
3137 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3138 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3142 multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
3143 X86MemOperand x86memop, RegisterClass RC,
3144 PatFrag mem_frag32, PatFrag mem_frag64,
3145 Intrinsic V4F32Int, Intrinsic V2F64Int,
3147 let ExeDomain = SSEPackedSingle in {
3148 // Intrinsic operation, reg.
3149 // Vector intrinsic operation, reg
3150 def PSr : AVX512AIi8<opcps, MRMSrcReg,
3151 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3152 !strconcat(OpcodeStr,
3153 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3154 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
3156 // Vector intrinsic operation, mem
3157 def PSm : AVX512AIi8<opcps, MRMSrcMem,
3158 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3159 !strconcat(OpcodeStr,
3160 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3162 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
3163 EVEX_CD8<32, VForm>;
3164 } // ExeDomain = SSEPackedSingle
3166 let ExeDomain = SSEPackedDouble in {
3167 // Vector intrinsic operation, reg
3168 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
3169 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
3170 !strconcat(OpcodeStr,
3171 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3172 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
3174 // Vector intrinsic operation, mem
3175 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
3176 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
3177 !strconcat(OpcodeStr,
3178 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3180 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
3181 EVEX_CD8<64, VForm>;
3182 } // ExeDomain = SSEPackedDouble
3185 multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3189 let ExeDomain = GenericDomain in {
3191 let hasSideEffects = 0 in
3192 def SSr : AVX512AIi8<opcss, MRMSrcReg,
3193 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
3194 !strconcat(OpcodeStr,
3195 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3198 // Intrinsic operation, reg.
3199 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
3200 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3201 !strconcat(OpcodeStr,
3202 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3203 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
3205 // Intrinsic operation, mem.
3206 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
3207 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
3208 !strconcat(OpcodeStr,
3209 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3210 [(set VR128X:$dst, (F32Int VR128X:$src1,
3211 sse_load_f32:$src2, imm:$src3))]>,
3212 EVEX_CD8<32, CD8VT1>;
3215 let hasSideEffects = 0 in
3216 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
3217 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
3218 !strconcat(OpcodeStr,
3219 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3222 // Intrinsic operation, reg.
3223 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
3224 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
3225 !strconcat(OpcodeStr,
3226 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3227 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
3230 // Intrinsic operation, mem.
3231 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
3232 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
3233 !strconcat(OpcodeStr,
3234 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3236 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
3237 VEX_W, EVEX_CD8<64, CD8VT1>;
3238 } // ExeDomain = GenericDomain
3241 let Predicates = [HasAVX512] in {
3242 defm VRNDSCALE : avx512_fp_binop_rm<0x0A, 0x0B, "vrndscale",
3243 int_x86_avx512_rndscale_ss,
3244 int_x86_avx512_rndscale_sd>, EVEX_4V;
3246 defm VRNDSCALEZ : avx512_fp_unop_rm<0x08, 0x09, "vrndscale", f256mem, VR512,
3247 memopv16f32, memopv8f64,
3248 int_x86_avx512_rndscale_ps_512,
3249 int_x86_avx512_rndscale_pd_512, CD8VF>,
3253 def : Pat<(ffloor FR32X:$src),
3254 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
3255 def : Pat<(f64 (ffloor FR64X:$src)),
3256 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
3257 def : Pat<(f32 (fnearbyint FR32X:$src)),
3258 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
3259 def : Pat<(f64 (fnearbyint FR64X:$src)),
3260 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
3261 def : Pat<(f32 (fceil FR32X:$src)),
3262 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
3263 def : Pat<(f64 (fceil FR64X:$src)),
3264 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
3265 def : Pat<(f32 (frint FR32X:$src)),
3266 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
3267 def : Pat<(f64 (frint FR64X:$src)),
3268 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
3269 def : Pat<(f32 (ftrunc FR32X:$src)),
3270 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
3271 def : Pat<(f64 (ftrunc FR64X:$src)),
3272 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
3274 def : Pat<(v16f32 (ffloor VR512:$src)),
3275 (VRNDSCALEZPSr VR512:$src, (i32 0x1))>;
3276 def : Pat<(v16f32 (fnearbyint VR512:$src)),
3277 (VRNDSCALEZPSr VR512:$src, (i32 0xC))>;
3278 def : Pat<(v16f32 (fceil VR512:$src)),
3279 (VRNDSCALEZPSr VR512:$src, (i32 0x2))>;
3280 def : Pat<(v16f32 (frint VR512:$src)),
3281 (VRNDSCALEZPSr VR512:$src, (i32 0x4))>;
3282 def : Pat<(v16f32 (ftrunc VR512:$src)),
3283 (VRNDSCALEZPSr VR512:$src, (i32 0x3))>;
3285 def : Pat<(v8f64 (ffloor VR512:$src)),
3286 (VRNDSCALEZPDr VR512:$src, (i32 0x1))>;
3287 def : Pat<(v8f64 (fnearbyint VR512:$src)),
3288 (VRNDSCALEZPDr VR512:$src, (i32 0xC))>;
3289 def : Pat<(v8f64 (fceil VR512:$src)),
3290 (VRNDSCALEZPDr VR512:$src, (i32 0x2))>;
3291 def : Pat<(v8f64 (frint VR512:$src)),
3292 (VRNDSCALEZPDr VR512:$src, (i32 0x4))>;
3293 def : Pat<(v8f64 (ftrunc VR512:$src)),
3294 (VRNDSCALEZPDr VR512:$src, (i32 0x3))>;
3296 //-------------------------------------------------
3297 // Integer truncate and extend operations
3298 //-------------------------------------------------
3300 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
3301 RegisterClass dstRC, RegisterClass srcRC,
3302 RegisterClass KRC, X86MemOperand x86memop> {
3303 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3305 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3308 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3309 (ins KRC:$mask, srcRC:$src),
3310 !strconcat(OpcodeStr,
3311 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3314 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3315 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3318 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3319 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3320 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3321 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3322 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3323 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3324 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3325 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3326 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3327 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3328 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3329 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3330 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3331 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3332 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3333 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3334 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3335 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3336 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3337 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3338 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3339 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3340 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3341 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3342 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3343 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3344 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3345 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3346 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3347 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3349 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3350 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3351 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3352 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3353 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3355 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3356 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3357 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3358 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3359 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3360 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3361 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3362 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3365 multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3366 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3367 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3369 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3371 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3372 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3373 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3374 (ins x86memop:$src),
3375 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3377 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3381 defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3382 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3384 defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3385 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3387 defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3388 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3389 EVEX_CD8<16, CD8VH>;
3390 defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3391 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3392 EVEX_CD8<16, CD8VQ>;
3393 defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3394 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3395 EVEX_CD8<32, CD8VH>;
3397 defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3398 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3400 defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3401 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3403 defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3404 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3405 EVEX_CD8<16, CD8VH>;
3406 defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3407 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3408 EVEX_CD8<16, CD8VQ>;
3409 defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3410 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3411 EVEX_CD8<32, CD8VH>;
3413 //===----------------------------------------------------------------------===//
3414 // GATHER - SCATTER Operations
3416 multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3417 RegisterClass RC, X86MemOperand memop> {
3419 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3420 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3421 (ins RC:$src1, KRC:$mask, memop:$src2),
3422 !strconcat(OpcodeStr,
3423 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3426 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3427 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3428 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3429 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3431 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3432 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3433 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3434 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3436 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3437 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3438 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3439 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3441 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3442 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3443 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3444 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3446 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3447 RegisterClass RC, X86MemOperand memop> {
3448 let mayStore = 1, Constraints = "$mask = $mask_wb" in
3449 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3450 (ins memop:$dst, KRC:$mask, RC:$src2),
3451 !strconcat(OpcodeStr,
3452 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3456 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3457 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3458 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3459 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3461 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3462 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3463 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3464 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3466 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3467 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3468 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3469 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3471 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3472 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3473 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3474 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3476 //===----------------------------------------------------------------------===//
3477 // VSHUFPS - VSHUFPD Operations
3479 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3480 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3482 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3483 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3484 !strconcat(OpcodeStr,
3485 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3486 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3487 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3488 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
3489 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3490 (ins RC:$src1, RC:$src2, i8imm:$src3),
3491 !strconcat(OpcodeStr,
3492 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3493 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3494 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
3495 EVEX_4V, Sched<[WriteShuffle]>;
3498 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3499 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3500 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3501 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3503 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3504 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3505 def : Pat<(v16i32 (X86Shufp VR512:$src1,
3506 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3507 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3509 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3510 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3511 def : Pat<(v8i64 (X86Shufp VR512:$src1,
3512 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3513 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3515 multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3516 X86MemOperand x86memop> {
3517 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3518 (ins RC:$src1, RC:$src2, i8imm:$src3),
3519 !strconcat(OpcodeStr,
3520 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3523 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3524 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3525 !strconcat(OpcodeStr,
3526 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3529 defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3530 EVEX_V512, EVEX_CD8<32, CD8VF>;
3531 defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3532 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3534 def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3535 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3536 def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3537 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3538 def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3539 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3540 def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3541 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3543 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3544 X86MemOperand x86memop> {
3545 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3546 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3548 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3549 (ins x86memop:$src),
3550 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3554 defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3555 EVEX_CD8<32, CD8VF>;
3556 defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3557 EVEX_CD8<64, CD8VF>;
3559 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
3560 RegisterClass RC, RegisterClass KRC,
3561 X86MemOperand x86memop,
3562 X86MemOperand x86scalar_mop, string BrdcstStr> {
3563 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3565 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
3567 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3568 (ins x86memop:$src),
3569 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
3571 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3572 (ins x86scalar_mop:$src),
3573 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3574 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
3576 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3577 (ins KRC:$mask, RC:$src),
3578 !strconcat(OpcodeStr,
3579 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3581 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3582 (ins KRC:$mask, x86memop:$src),
3583 !strconcat(OpcodeStr,
3584 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3586 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3587 (ins KRC:$mask, x86scalar_mop:$src),
3588 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
3589 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
3591 []>, EVEX, EVEX_KZ, EVEX_B;
3593 let Constraints = "$src1 = $dst" in {
3594 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3595 (ins RC:$src1, KRC:$mask, RC:$src2),
3596 !strconcat(OpcodeStr,
3597 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3599 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3600 (ins RC:$src1, KRC:$mask, x86memop:$src2),
3601 !strconcat(OpcodeStr,
3602 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3604 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3605 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
3606 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
3607 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
3608 []>, EVEX, EVEX_K, EVEX_B;
3612 let Predicates = [HasCDI] in {
3613 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
3614 i512mem, i32mem, "{1to16}">,
3615 EVEX_V512, EVEX_CD8<32, CD8VF>;
3618 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
3619 i512mem, i64mem, "{1to8}">,
3620 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3624 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
3626 (VPCONFLICTDrrk VR512:$src1,
3627 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
3629 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
3631 (VPCONFLICTQrrk VR512:$src1,
3632 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;