1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def i32x_info : X86VectorVTInfo<1, i32, GR32, "si">;
149 def i64x_info : X86VectorVTInfo<1, i64, GR64, "sq">;
150 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
151 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
153 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
154 X86VectorVTInfo i128> {
155 X86VectorVTInfo info512 = i512;
156 X86VectorVTInfo info256 = i256;
157 X86VectorVTInfo info128 = i128;
160 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
162 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
164 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
166 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
168 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
170 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
173 // This multiclass generates the masking variants from the non-masking
174 // variant. It only provides the assembly pieces for the masking variants.
175 // It assumes custom ISel patterns for masking which can be provided as
176 // template arguments.
177 multiclass AVX512_maskable_custom<bits<8> O, Format F,
179 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
181 string AttSrcAsm, string IntelSrcAsm,
183 list<dag> MaskingPattern,
184 list<dag> ZeroMaskingPattern,
185 string MaskingConstraint = "",
186 InstrItinClass itin = NoItinerary,
187 bit IsCommutable = 0> {
188 let isCommutable = IsCommutable in
189 def NAME: AVX512<O, F, Outs, Ins,
190 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
191 "$dst , "#IntelSrcAsm#"}",
194 // Prefer over VMOV*rrk Pat<>
195 let AddedComplexity = 20 in
196 def NAME#k: AVX512<O, F, Outs, MaskingIns,
197 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
198 "$dst {${mask}}, "#IntelSrcAsm#"}",
199 MaskingPattern, itin>,
201 // In case of the 3src subclass this is overridden with a let.
202 string Constraints = MaskingConstraint;
204 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
205 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
206 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
207 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
214 // Common base class of AVX512_maskable and AVX512_maskable_3src.
215 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
217 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
219 string AttSrcAsm, string IntelSrcAsm,
220 dag RHS, dag MaskingRHS,
221 SDNode Select = vselect,
222 string MaskingConstraint = "",
223 InstrItinClass itin = NoItinerary,
224 bit IsCommutable = 0> :
225 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
226 AttSrcAsm, IntelSrcAsm,
227 [(set _.RC:$dst, RHS)],
228 [(set _.RC:$dst, MaskingRHS)],
230 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
231 MaskingConstraint, NoItinerary, IsCommutable>;
233 // This multiclass generates the unconditional/non-masking, the masking and
234 // the zero-masking variant of the vector instruction. In the masking case, the
235 // perserved vector elements come from a new dummy input operand tied to $dst.
236 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
237 dag Outs, dag Ins, string OpcodeStr,
238 string AttSrcAsm, string IntelSrcAsm,
240 InstrItinClass itin = NoItinerary,
241 bit IsCommutable = 0> :
242 AVX512_maskable_common<O, F, _, Outs, Ins,
243 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
244 !con((ins _.KRCWM:$mask), Ins),
245 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
246 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
247 "$src0 = $dst", itin, IsCommutable>;
249 // This multiclass generates the unconditional/non-masking, the masking and
250 // the zero-masking variant of the scalar instruction.
251 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
252 dag Outs, dag Ins, string OpcodeStr,
253 string AttSrcAsm, string IntelSrcAsm,
255 InstrItinClass itin = NoItinerary,
256 bit IsCommutable = 0> :
257 AVX512_maskable_common<O, F, _, Outs, Ins,
258 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
259 !con((ins _.KRCWM:$mask), Ins),
260 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
261 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
262 "$src0 = $dst", itin, IsCommutable>;
264 // Similar to AVX512_maskable but in this case one of the source operands
265 // ($src1) is already tied to $dst so we just use that for the preserved
266 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
268 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
269 dag Outs, dag NonTiedIns, string OpcodeStr,
270 string AttSrcAsm, string IntelSrcAsm,
272 AVX512_maskable_common<O, F, _, Outs,
273 !con((ins _.RC:$src1), NonTiedIns),
274 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
275 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
276 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
277 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
279 multiclass AVX512_maskable_3src_scalar<bits<8> O, Format F, X86VectorVTInfo _,
280 dag Outs, dag NonTiedIns, string OpcodeStr,
281 string AttSrcAsm, string IntelSrcAsm,
283 AVX512_maskable_common<O, F, _, Outs,
284 !con((ins _.RC:$src1), NonTiedIns),
285 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
286 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
287 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
288 (X86select _.KRCWM:$mask, RHS, _.RC:$src1)>;
290 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
293 string AttSrcAsm, string IntelSrcAsm,
295 AVX512_maskable_custom<O, F, Outs, Ins,
296 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
297 !con((ins _.KRCWM:$mask), Ins),
298 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
302 // Instruction with mask that puts result in mask register,
303 // like "compare" and "vptest"
304 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
306 dag Ins, dag MaskingIns,
308 string AttSrcAsm, string IntelSrcAsm,
310 list<dag> MaskingPattern,
312 InstrItinClass itin = NoItinerary> {
313 def NAME: AVX512<O, F, Outs, Ins,
314 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
315 "$dst "#Round#", "#IntelSrcAsm#"}",
318 def NAME#k: AVX512<O, F, Outs, MaskingIns,
319 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
320 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
321 MaskingPattern, itin>, EVEX_K;
324 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
326 dag Ins, dag MaskingIns,
328 string AttSrcAsm, string IntelSrcAsm,
329 dag RHS, dag MaskingRHS,
331 InstrItinClass itin = NoItinerary> :
332 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
333 AttSrcAsm, IntelSrcAsm,
334 [(set _.KRC:$dst, RHS)],
335 [(set _.KRC:$dst, MaskingRHS)],
338 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
339 dag Outs, dag Ins, string OpcodeStr,
340 string AttSrcAsm, string IntelSrcAsm,
341 dag RHS, string Round = "",
342 InstrItinClass itin = NoItinerary> :
343 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
344 !con((ins _.KRCWM:$mask), Ins),
345 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
346 (and _.KRCWM:$mask, RHS),
349 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
350 dag Outs, dag Ins, string OpcodeStr,
351 string AttSrcAsm, string IntelSrcAsm> :
352 AVX512_maskable_custom_cmp<O, F, Outs,
353 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
354 AttSrcAsm, IntelSrcAsm,
355 [],[],"", NoItinerary>;
357 // Bitcasts between 512-bit vector types. Return the original type since
358 // no instruction is needed for the conversion
359 let Predicates = [HasAVX512] in {
360 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
361 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
362 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
363 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
364 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
365 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
366 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
367 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
368 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
369 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
370 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
371 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
372 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
373 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
374 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
375 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
376 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
377 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
378 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
379 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
380 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
381 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
382 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
383 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
384 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
385 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
386 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
387 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
388 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
389 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
390 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
392 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
393 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
394 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
395 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
396 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
397 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
398 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
399 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
400 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
401 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
402 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
403 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
404 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
405 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
406 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
407 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
408 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
409 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
410 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
411 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
412 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
413 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
414 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
415 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
416 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
417 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
418 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
419 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
420 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
421 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
423 // Bitcasts between 256-bit vector types. Return the original type since
424 // no instruction is needed for the conversion
425 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
426 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
427 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
428 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
429 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
430 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
431 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
432 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
433 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
434 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
435 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
436 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
437 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
438 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
439 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
440 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
441 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
442 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
443 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
444 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
445 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
446 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
447 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
448 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
449 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
450 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
451 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
452 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
453 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
454 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
458 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
461 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
462 isPseudo = 1, Predicates = [HasAVX512] in {
463 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
464 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
467 let Predicates = [HasAVX512] in {
468 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
469 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
470 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
473 //===----------------------------------------------------------------------===//
474 // AVX-512 - VECTOR INSERT
476 multiclass vinsert_for_size<int Opcode, X86VectorVTInfo From, X86VectorVTInfo To,
477 PatFrag vinsert_insert> {
478 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
479 defm rr : AVX512_maskable<Opcode, MRMSrcReg, To, (outs To.RC:$dst),
480 (ins To.RC:$src1, From.RC:$src2, i32u8imm:$src3),
481 "vinsert" # From.EltTypeName # "x" # From.NumElts,
482 "$src3, $src2, $src1", "$src1, $src2, $src3",
483 (vinsert_insert:$src3 (To.VT To.RC:$src1),
484 (From.VT From.RC:$src2),
485 (iPTR imm))>, AVX512AIi8Base, EVEX_4V;
488 defm rm : AVX512_maskable<Opcode, MRMSrcMem, To, (outs To.RC:$dst),
489 (ins To.RC:$src1, From.MemOp:$src2, i32u8imm:$src3),
490 "vinsert" # From.EltTypeName # "x" # From.NumElts,
491 "$src3, $src2, $src1", "$src1, $src2, $src3",
492 (vinsert_insert:$src3 (To.VT To.RC:$src1),
493 (From.VT (bitconvert (From.LdFrag addr:$src2))),
494 (iPTR imm))>, AVX512AIi8Base, EVEX_4V,
495 EVEX_CD8<From.EltSize, From.CD8TupleForm>;
499 multiclass vinsert_for_size_lowering<string InstrStr, X86VectorVTInfo From,
500 X86VectorVTInfo To, PatFrag vinsert_insert,
501 SDNodeXForm INSERT_get_vinsert_imm , list<Predicate> p> {
502 let Predicates = p in {
503 def : Pat<(vinsert_insert:$ins
504 (To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
505 (To.VT (!cast<Instruction>(InstrStr#"rr")
506 To.RC:$src1, From.RC:$src2,
507 (INSERT_get_vinsert_imm To.RC:$ins)))>;
509 def : Pat<(vinsert_insert:$ins
511 (From.VT (bitconvert (From.LdFrag addr:$src2))),
513 (To.VT (!cast<Instruction>(InstrStr#"rm")
514 To.RC:$src1, addr:$src2,
515 (INSERT_get_vinsert_imm To.RC:$ins)))>;
519 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
520 ValueType EltVT64, int Opcode256> {
522 let Predicates = [HasVLX] in
523 defm NAME # "32x4Z256" : vinsert_for_size<Opcode128,
524 X86VectorVTInfo< 4, EltVT32, VR128X>,
525 X86VectorVTInfo< 8, EltVT32, VR256X>,
526 vinsert128_insert>, EVEX_V256;
528 defm NAME # "32x4Z" : vinsert_for_size<Opcode128,
529 X86VectorVTInfo< 4, EltVT32, VR128X>,
530 X86VectorVTInfo<16, EltVT32, VR512>,
531 vinsert128_insert>, EVEX_V512;
533 defm NAME # "64x4Z" : vinsert_for_size<Opcode256,
534 X86VectorVTInfo< 4, EltVT64, VR256X>,
535 X86VectorVTInfo< 8, EltVT64, VR512>,
536 vinsert256_insert>, VEX_W, EVEX_V512;
538 let Predicates = [HasVLX, HasDQI] in
539 defm NAME # "64x2Z256" : vinsert_for_size<Opcode128,
540 X86VectorVTInfo< 2, EltVT64, VR128X>,
541 X86VectorVTInfo< 4, EltVT64, VR256X>,
542 vinsert128_insert>, VEX_W, EVEX_V256;
544 let Predicates = [HasDQI] in {
545 defm NAME # "64x2Z" : vinsert_for_size<Opcode128,
546 X86VectorVTInfo< 2, EltVT64, VR128X>,
547 X86VectorVTInfo< 8, EltVT64, VR512>,
548 vinsert128_insert>, VEX_W, EVEX_V512;
550 defm NAME # "32x8Z" : vinsert_for_size<Opcode256,
551 X86VectorVTInfo< 8, EltVT32, VR256X>,
552 X86VectorVTInfo<16, EltVT32, VR512>,
553 vinsert256_insert>, EVEX_V512;
557 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
558 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
560 // Codegen pattern with the alternative types,
561 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
562 defm : vinsert_for_size_lowering<"VINSERTF32x4Z256", v2f64x_info, v4f64x_info,
563 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
564 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v2i64x_info, v4i64x_info,
565 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX, NoDQI]>;
567 defm : vinsert_for_size_lowering<"VINSERTF32x4Z", v2f64x_info, v8f64_info,
568 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
569 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v2i64x_info, v8i64_info,
570 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512, NoDQI]>;
572 defm : vinsert_for_size_lowering<"VINSERTF64x4Z", v8f32x_info, v16f32_info,
573 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
574 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v8i32x_info, v16i32_info,
575 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512, NoDQI]>;
577 // Codegen pattern with the alternative types insert VEC128 into VEC256
578 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v8i16x_info, v16i16x_info,
579 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
580 defm : vinsert_for_size_lowering<"VINSERTI32x4Z256", v16i8x_info, v32i8x_info,
581 vinsert128_insert, INSERT_get_vinsert128_imm, [HasVLX]>;
582 // Codegen pattern with the alternative types insert VEC128 into VEC512
583 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v8i16x_info, v32i16_info,
584 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
585 defm : vinsert_for_size_lowering<"VINSERTI32x4Z", v16i8x_info, v64i8_info,
586 vinsert128_insert, INSERT_get_vinsert128_imm, [HasAVX512]>;
587 // Codegen pattern with the alternative types insert VEC256 into VEC512
588 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v16i16x_info, v32i16_info,
589 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
590 defm : vinsert_for_size_lowering<"VINSERTI64x4Z", v32i8x_info, v64i8_info,
591 vinsert256_insert, INSERT_get_vinsert256_imm, [HasAVX512]>;
593 // vinsertps - insert f32 to XMM
594 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
595 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
596 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
597 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
599 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
600 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
601 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
602 [(set VR128X:$dst, (X86insertps VR128X:$src1,
603 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
604 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
606 //===----------------------------------------------------------------------===//
607 // AVX-512 VECTOR EXTRACT
610 multiclass vextract_for_size_first_position_lowering<X86VectorVTInfo From,
611 X86VectorVTInfo To> {
612 // A subvector extract from the first vector position is
613 // a subregister copy that needs no instruction.
614 def NAME # To.NumElts:
615 Pat<(To.VT (extract_subvector (From.VT From.RC:$src),(iPTR 0))),
616 (To.VT (EXTRACT_SUBREG (From.VT From.RC:$src), To.SubRegIdx))>;
619 multiclass vextract_for_size<int Opcode,
620 X86VectorVTInfo From, X86VectorVTInfo To,
621 PatFrag vextract_extract> :
622 vextract_for_size_first_position_lowering<From, To> {
624 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
625 // use AVX512_maskable_in_asm (AVX512_maskable can't be used due to
626 // vextract_extract), we interesting only in patterns without mask,
627 // intrinsics pattern match generated bellow.
628 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
629 (ins From.RC:$src1, i32u8imm:$idx),
630 "vextract" # To.EltTypeName # "x" # To.NumElts,
631 "$idx, $src1", "$src1, $idx",
632 [(set To.RC:$dst, (vextract_extract:$idx (From.VT From.RC:$src1),
634 AVX512AIi8Base, EVEX;
635 let mayStore = 1 in {
636 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
637 (ins To.MemOp:$dst, From.RC:$src1, i32u8imm:$src2),
638 "vextract" # To.EltTypeName # "x" # To.NumElts #
639 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
642 def rmk : AVX512AIi8<Opcode, MRMDestMem, (outs),
643 (ins To.MemOp:$dst, To.KRCWM:$mask,
644 From.RC:$src1, i32u8imm:$src2),
645 "vextract" # To.EltTypeName # "x" # To.NumElts #
646 "\t{$src2, $src1, $dst {${mask}}|"
647 "$dst {${mask}}, $src1, $src2}",
652 // Intrinsic call with masking.
653 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
654 "x" # To.NumElts # "_" # From.Size)
655 From.RC:$src1, (iPTR imm:$idx), To.RC:$src0, To.MRC:$mask),
656 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
657 From.ZSuffix # "rrk")
659 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
660 From.RC:$src1, imm:$idx)>;
662 // Intrinsic call with zero-masking.
663 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
664 "x" # To.NumElts # "_" # From.Size)
665 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, To.MRC:$mask),
666 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
667 From.ZSuffix # "rrkz")
668 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
669 From.RC:$src1, imm:$idx)>;
671 // Intrinsic call without masking.
672 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
673 "x" # To.NumElts # "_" # From.Size)
674 From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
675 (!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
677 From.RC:$src1, imm:$idx)>;
680 // Codegen pattern for the alternative types
681 multiclass vextract_for_size_lowering<string InstrStr, X86VectorVTInfo From,
682 X86VectorVTInfo To, PatFrag vextract_extract,
683 SDNodeXForm EXTRACT_get_vextract_imm, list<Predicate> p> :
684 vextract_for_size_first_position_lowering<From, To> {
686 let Predicates = p in
687 def : Pat<(vextract_extract:$ext (From.VT From.RC:$src1), (iPTR imm)),
688 (To.VT (!cast<Instruction>(InstrStr#"rr")
690 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
693 multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
694 ValueType EltVT64, int Opcode256> {
695 defm NAME # "32x4Z" : vextract_for_size<Opcode128,
696 X86VectorVTInfo<16, EltVT32, VR512>,
697 X86VectorVTInfo< 4, EltVT32, VR128X>,
698 vextract128_extract>,
699 EVEX_V512, EVEX_CD8<32, CD8VT4>;
700 defm NAME # "64x4Z" : vextract_for_size<Opcode256,
701 X86VectorVTInfo< 8, EltVT64, VR512>,
702 X86VectorVTInfo< 4, EltVT64, VR256X>,
703 vextract256_extract>,
704 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>;
705 let Predicates = [HasVLX] in
706 defm NAME # "32x4Z256" : vextract_for_size<Opcode128,
707 X86VectorVTInfo< 8, EltVT32, VR256X>,
708 X86VectorVTInfo< 4, EltVT32, VR128X>,
709 vextract128_extract>,
710 EVEX_V256, EVEX_CD8<32, CD8VT4>;
711 let Predicates = [HasVLX, HasDQI] in
712 defm NAME # "64x2Z256" : vextract_for_size<Opcode128,
713 X86VectorVTInfo< 4, EltVT64, VR256X>,
714 X86VectorVTInfo< 2, EltVT64, VR128X>,
715 vextract128_extract>,
716 VEX_W, EVEX_V256, EVEX_CD8<64, CD8VT2>;
717 let Predicates = [HasDQI] in {
718 defm NAME # "64x2Z" : vextract_for_size<Opcode128,
719 X86VectorVTInfo< 8, EltVT64, VR512>,
720 X86VectorVTInfo< 2, EltVT64, VR128X>,
721 vextract128_extract>,
722 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>;
723 defm NAME # "32x8Z" : vextract_for_size<Opcode256,
724 X86VectorVTInfo<16, EltVT32, VR512>,
725 X86VectorVTInfo< 8, EltVT32, VR256X>,
726 vextract256_extract>,
727 EVEX_V512, EVEX_CD8<32, CD8VT8>;
731 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
732 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
734 // extract_subvector codegen patterns with the alternative types.
735 // Only add this if 64x2 and its friends are not supported natively via AVX512DQ.
736 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z", v8f64_info, v2f64x_info,
737 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
738 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v8i64_info, v2i64x_info,
739 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512, NoDQI]>;
741 defm : vextract_for_size_lowering<"VEXTRACTF64x4Z", v16f32_info, v8f32x_info,
742 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
743 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v16i32_info, v8i32x_info,
744 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512, NoDQI]>;
746 defm : vextract_for_size_lowering<"VEXTRACTF32x4Z256", v4f64x_info, v2f64x_info,
747 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
748 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z256", v4i64x_info, v2i64x_info,
749 vextract128_extract, EXTRACT_get_vextract128_imm, [HasVLX, NoDQI]>;
751 // Codegen pattern with the alternative types extract VEC128 from VEC512
752 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v32i16_info, v8i16x_info,
753 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
754 defm : vextract_for_size_lowering<"VEXTRACTI32x4Z", v64i8_info, v16i8x_info,
755 vextract128_extract, EXTRACT_get_vextract128_imm, [HasAVX512]>;
756 // Codegen pattern with the alternative types extract VEC256 from VEC512
757 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v32i16_info, v16i16x_info,
758 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
759 defm : vextract_for_size_lowering<"VEXTRACTI64x4Z", v64i8_info, v32i8x_info,
760 vextract256_extract, EXTRACT_get_vextract256_imm, [HasAVX512]>;
762 // A 128-bit subvector insert to the first 512-bit vector position
763 // is a subregister copy that needs no instruction.
764 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
765 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
766 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
768 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
769 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
770 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
772 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
773 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
774 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
776 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
777 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
778 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
781 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
782 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
783 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
784 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
785 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
786 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
787 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
788 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
789 def : Pat<(insert_subvector undef, (v16i16 VR256X:$src), (iPTR 0)),
790 (INSERT_SUBREG (v32i16 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
791 def : Pat<(insert_subvector undef, (v32i8 VR256X:$src), (iPTR 0)),
792 (INSERT_SUBREG (v64i8 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
794 // vextractps - extract 32 bits from XMM
795 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
796 (ins VR128X:$src1, u8imm:$src2),
797 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
798 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
801 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
802 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
803 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
804 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
805 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
807 //===---------------------------------------------------------------------===//
811 multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr,
812 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo> {
814 defm r : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
815 (ins SrcInfo.RC:$src), OpcodeStr, "$src", "$src",
816 (DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src)))>,
819 defm m : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
820 (ins SrcInfo.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
821 (DestInfo.VT (X86VBroadcast
822 (SrcInfo.ScalarLdFrag addr:$src)))>,
823 T8PD, EVEX, EVEX_CD8<SrcInfo.EltSize, CD8VT1>;
826 multiclass avx512_fp_broadcast_vl<bits<8> opc, string OpcodeStr,
827 AVX512VLVectorVTInfo _> {
828 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
831 let Predicates = [HasVLX] in {
832 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
837 let ExeDomain = SSEPackedSingle in {
838 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, "vbroadcastss",
840 let Predicates = [HasVLX] in {
841 defm VBROADCASTSSZ128 : avx512_broadcast_rm<0x18, "vbroadcastss",
842 v4f32x_info, v4f32x_info>, EVEX_V128;
846 let ExeDomain = SSEPackedDouble in {
847 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, "vbroadcastsd",
848 avx512vl_f64_info>, VEX_W;
851 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
852 // Later, we can canonize broadcast instructions before ISel phase and
853 // eliminate additional patterns on ISel.
854 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
855 // representations of source
856 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
857 X86VectorVTInfo _, RegisterClass SrcRC_v,
858 RegisterClass SrcRC_s> {
859 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
860 (!cast<Instruction>(InstName##"r")
861 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
863 let AddedComplexity = 30 in {
864 def : Pat<(_.VT (vselect _.KRCWM:$mask,
865 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
866 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
867 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
869 def : Pat<(_.VT(vselect _.KRCWM:$mask,
870 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
871 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
872 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
876 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
878 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
881 let Predicates = [HasVLX] in {
882 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
883 v8f32x_info, VR128X, FR32X>;
884 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
885 v4f32x_info, VR128X, FR32X>;
886 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
887 v4f64x_info, VR128X, FR64X>;
890 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
891 (VBROADCASTSSZm addr:$src)>;
892 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
893 (VBROADCASTSDZm addr:$src)>;
895 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
896 (VBROADCASTSSZm addr:$src)>;
897 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
898 (VBROADCASTSDZm addr:$src)>;
900 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
901 RegisterClass SrcRC> {
902 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
903 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
904 "$src", "$src", []>, T8PD, EVEX;
907 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
908 RegisterClass SrcRC, Predicate prd> {
909 let Predicates = [prd] in
910 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
911 let Predicates = [prd, HasVLX] in {
912 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
913 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
917 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
919 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
921 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
923 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
926 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
927 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
929 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
930 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
932 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
933 (VPBROADCASTDrZr GR32:$src)>;
934 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
935 (VPBROADCASTQrZr GR64:$src)>;
937 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
938 (VPBROADCASTDrZr GR32:$src)>;
939 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
940 (VPBROADCASTQrZr GR64:$src)>;
942 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
943 (v16i32 immAllZerosV), (i16 GR16:$mask))),
944 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
945 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
946 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
947 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
949 // Provide aliases for broadcast from the same register class that
950 // automatically does the extract.
951 multiclass avx512_int_broadcast_rm_lowering<X86VectorVTInfo DestInfo,
952 X86VectorVTInfo SrcInfo> {
953 def : Pat<(DestInfo.VT (X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src))),
954 (!cast<Instruction>(NAME#DestInfo.ZSuffix#"r")
955 (EXTRACT_SUBREG (SrcInfo.VT SrcInfo.RC:$src), sub_xmm))>;
958 multiclass avx512_int_broadcast_rm_vl<bits<8> opc, string OpcodeStr,
959 AVX512VLVectorVTInfo _, Predicate prd> {
960 let Predicates = [prd] in {
961 defm Z : avx512_broadcast_rm<opc, OpcodeStr, _.info512, _.info128>,
962 avx512_int_broadcast_rm_lowering<_.info512, _.info256>,
964 // Defined separately to avoid redefinition.
965 defm Z_Alt : avx512_int_broadcast_rm_lowering<_.info512, _.info512>;
967 let Predicates = [prd, HasVLX] in {
968 defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, _.info256, _.info128>,
969 avx512_int_broadcast_rm_lowering<_.info256, _.info256>,
971 defm Z128 : avx512_broadcast_rm<opc, OpcodeStr, _.info128, _.info128>,
976 defm VPBROADCASTB : avx512_int_broadcast_rm_vl<0x78, "vpbroadcastb",
977 avx512vl_i8_info, HasBWI>;
978 defm VPBROADCASTW : avx512_int_broadcast_rm_vl<0x79, "vpbroadcastw",
979 avx512vl_i16_info, HasBWI>;
980 defm VPBROADCASTD : avx512_int_broadcast_rm_vl<0x58, "vpbroadcastd",
981 avx512vl_i32_info, HasAVX512>;
982 defm VPBROADCASTQ : avx512_int_broadcast_rm_vl<0x59, "vpbroadcastq",
983 avx512vl_i64_info, HasAVX512>, VEX_W;
985 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
986 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
988 def rm : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Src.MemOp:$src),
989 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
991 (_Dst.VT (X86SubVBroadcast
992 (_Src.VT (bitconvert (_Src.LdFrag addr:$src))))))]>, EVEX;
993 def rmk : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
995 !strconcat(OpcodeStr,
996 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
998 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
1000 !strconcat(OpcodeStr,
1001 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
1006 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1007 v16i32_info, v4i32x_info>,
1008 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1009 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1010 v16f32_info, v4f32x_info>,
1011 EVEX_V512, EVEX_CD8<32, CD8VT4>;
1012 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
1013 v8i64_info, v4i64x_info>, VEX_W,
1014 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1015 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
1016 v8f64_info, v4f64x_info>, VEX_W,
1017 EVEX_V512, EVEX_CD8<64, CD8VT4>;
1019 let Predicates = [HasVLX] in {
1020 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
1021 v8i32x_info, v4i32x_info>,
1022 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1023 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
1024 v8f32x_info, v4f32x_info>,
1025 EVEX_V256, EVEX_CD8<32, CD8VT4>;
1027 let Predicates = [HasVLX, HasDQI] in {
1028 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1029 v4i64x_info, v2i64x_info>, VEX_W,
1030 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1031 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1032 v4f64x_info, v2f64x_info>, VEX_W,
1033 EVEX_V256, EVEX_CD8<64, CD8VT2>;
1035 let Predicates = [HasDQI] in {
1036 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
1037 v8i64_info, v2i64x_info>, VEX_W,
1038 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1039 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
1040 v16i32_info, v8i32x_info>,
1041 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1042 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
1043 v8f64_info, v2f64x_info>, VEX_W,
1044 EVEX_V512, EVEX_CD8<64, CD8VT2>;
1045 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
1046 v16f32_info, v8f32x_info>,
1047 EVEX_V512, EVEX_CD8<32, CD8VT8>;
1050 multiclass avx512_broadcast_32x2<bits<8> opc, string OpcodeStr,
1051 X86VectorVTInfo _Dst, X86VectorVTInfo _Src,
1052 SDNode OpNode = X86SubVBroadcast> {
1054 defm r : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
1055 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
1056 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src)))>,
1059 defm m : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
1060 (ins _Src.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
1062 (_Src.VT (scalar_to_vector(loadi64 addr:$src)))))>,
1063 T8PD, EVEX, EVEX_CD8<_Src.EltSize, CD8VT2>;
1066 multiclass avx512_common_broadcast_32x2<bits<8> opc, string OpcodeStr,
1067 AVX512VLVectorVTInfo _> {
1068 let Predicates = [HasDQI] in
1069 defm Z : avx512_broadcast_32x2<opc, OpcodeStr, _.info512, _.info128>,
1071 let Predicates = [HasDQI, HasVLX] in
1072 defm Z256 : avx512_broadcast_32x2<opc, OpcodeStr, _.info256, _.info128>,
1076 multiclass avx512_common_broadcast_i32x2<bits<8> opc, string OpcodeStr,
1077 AVX512VLVectorVTInfo _> :
1078 avx512_common_broadcast_32x2<opc, OpcodeStr, _> {
1080 let Predicates = [HasDQI, HasVLX] in
1081 defm Z128 : avx512_broadcast_32x2<opc, OpcodeStr, _.info128, _.info128,
1082 X86SubV32x2Broadcast>, EVEX_V128;
1085 defm VPBROADCASTI32X2 : avx512_common_broadcast_i32x2<0x59, "vbroadcasti32x2",
1087 defm VPBROADCASTF32X2 : avx512_common_broadcast_32x2<0x19, "vbroadcastf32x2",
1090 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
1091 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
1092 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
1093 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
1095 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
1096 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
1097 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
1098 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
1100 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
1101 (VBROADCASTSSZr VR128X:$src)>;
1102 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
1103 (VBROADCASTSDZr VR128X:$src)>;
1105 // Provide fallback in case the load node that is used in the patterns above
1106 // is used by additional users, which prevents the pattern selection.
1107 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
1108 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
1109 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
1110 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
1113 //===----------------------------------------------------------------------===//
1114 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
1116 multiclass avx512_mask_broadcastm<bits<8> opc, string OpcodeStr,
1117 X86VectorVTInfo _, RegisterClass KRC> {
1118 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.RC:$dst), (ins KRC:$src),
1119 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1120 [(set _.RC:$dst, (_.VT (X86VBroadcastm KRC:$src)))]>, EVEX;
1123 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
1124 AVX512VLVectorVTInfo VTInfo, RegisterClass KRC> {
1125 let Predicates = [HasCDI] in
1126 defm Z : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info512, KRC>, EVEX_V512;
1127 let Predicates = [HasCDI, HasVLX] in {
1128 defm Z256 : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info256, KRC>, EVEX_V256;
1129 defm Z128 : avx512_mask_broadcastm<opc, OpcodeStr, VTInfo.info128, KRC>, EVEX_V128;
1133 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
1134 avx512vl_i32_info, VK16>;
1135 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1136 avx512vl_i64_info, VK8>, VEX_W;
1138 //===----------------------------------------------------------------------===//
1139 // -- VPERM2I - 3 source operands form --
1140 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr,
1141 SDNode OpNode, X86VectorVTInfo _> {
1142 let Constraints = "$src1 = $dst" in {
1143 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1144 (ins _.RC:$src2, _.RC:$src3),
1145 OpcodeStr, "$src3, $src2", "$src2, $src3",
1146 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>, EVEX_4V,
1150 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1151 (ins _.RC:$src2, _.MemOp:$src3),
1152 OpcodeStr, "$src3, $src2", "$src2, $src3",
1153 (_.VT (OpNode _.RC:$src1, _.RC:$src2,
1154 (_.VT (bitconvert (_.LdFrag addr:$src3)))))>,
1155 EVEX_4V, AVX5128IBase;
1158 multiclass avx512_perm_3src_mb<bits<8> opc, string OpcodeStr,
1159 SDNode OpNode, X86VectorVTInfo _> {
1160 let mayLoad = 1, Constraints = "$src1 = $dst" in
1161 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1162 (ins _.RC:$src2, _.ScalarMemOp:$src3),
1163 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1164 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1165 (_.VT (OpNode _.RC:$src1,
1166 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1167 AVX5128IBase, EVEX_4V, EVEX_B;
1170 multiclass avx512_perm_3src_sizes<bits<8> opc, string OpcodeStr,
1171 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1172 let Predicates = [HasAVX512] in
1173 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1174 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
1175 let Predicates = [HasVLX] in {
1176 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1177 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1179 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1180 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1184 multiclass avx512_perm_3src_sizes_w<bits<8> opc, string OpcodeStr,
1185 SDNode OpNode, AVX512VLVectorVTInfo VTInfo> {
1186 let Predicates = [HasBWI] in
1187 defm NAME: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info512>,
1188 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1190 let Predicates = [HasBWI, HasVLX] in {
1191 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info128>,
1192 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1194 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, OpNode, VTInfo.info256>,
1195 avx512_perm_3src_mb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1199 defm VPERMI2D : avx512_perm_3src_sizes<0x76, "vpermi2d", X86VPermiv3,
1200 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1201 defm VPERMI2Q : avx512_perm_3src_sizes<0x76, "vpermi2q", X86VPermiv3,
1202 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1203 defm VPERMI2PS : avx512_perm_3src_sizes<0x77, "vpermi2ps", X86VPermiv3,
1204 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1205 defm VPERMI2PD : avx512_perm_3src_sizes<0x77, "vpermi2pd", X86VPermiv3,
1206 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1208 defm VPERMT2D : avx512_perm_3src_sizes<0x7E, "vpermt2d", X86VPermv3,
1209 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
1210 defm VPERMT2Q : avx512_perm_3src_sizes<0x7E, "vpermt2q", X86VPermv3,
1211 avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1212 defm VPERMT2PS : avx512_perm_3src_sizes<0x7F, "vpermt2ps", X86VPermv3,
1213 avx512vl_f32_info>, EVEX_CD8<32, CD8VF>;
1214 defm VPERMT2PD : avx512_perm_3src_sizes<0x7F, "vpermt2pd", X86VPermv3,
1215 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VF>;
1217 defm VPERMT2W : avx512_perm_3src_sizes_w<0x7D, "vpermt2w", X86VPermv3,
1218 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1219 defm VPERMI2W : avx512_perm_3src_sizes_w<0x75, "vpermi2w", X86VPermiv3,
1220 avx512vl_i16_info>, VEX_W, EVEX_CD8<16, CD8VF>;
1222 //===----------------------------------------------------------------------===//
1223 // AVX-512 - BLEND using mask
1225 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1226 let ExeDomain = _.ExeDomain in {
1227 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1228 (ins _.RC:$src1, _.RC:$src2),
1229 !strconcat(OpcodeStr,
1230 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1232 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1233 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1234 !strconcat(OpcodeStr,
1235 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1236 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1237 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1238 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1239 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1240 !strconcat(OpcodeStr,
1241 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1242 []>, EVEX_4V, EVEX_KZ;
1243 let mayLoad = 1 in {
1244 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1245 (ins _.RC:$src1, _.MemOp:$src2),
1246 !strconcat(OpcodeStr,
1247 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1248 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1249 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1250 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1251 !strconcat(OpcodeStr,
1252 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1253 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1254 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1255 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1256 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1257 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1258 !strconcat(OpcodeStr,
1259 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1260 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1264 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1266 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1267 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1268 !strconcat(OpcodeStr,
1269 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1270 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1271 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1272 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1273 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1275 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1276 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1277 !strconcat(OpcodeStr,
1278 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1279 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1280 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1284 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1285 AVX512VLVectorVTInfo VTInfo> {
1286 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1287 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1289 let Predicates = [HasVLX] in {
1290 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1291 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1292 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1293 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1297 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1298 AVX512VLVectorVTInfo VTInfo> {
1299 let Predicates = [HasBWI] in
1300 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1302 let Predicates = [HasBWI, HasVLX] in {
1303 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1304 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1309 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1310 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1311 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1312 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1313 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1314 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1317 let Predicates = [HasAVX512] in {
1318 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1319 (v8f32 VR256X:$src2))),
1321 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1322 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1323 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1325 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1326 (v8i32 VR256X:$src2))),
1328 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1329 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1330 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1332 //===----------------------------------------------------------------------===//
1333 // Compare Instructions
1334 //===----------------------------------------------------------------------===//
1336 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1338 multiclass avx512_cmp_scalar<X86VectorVTInfo _, SDNode OpNode, SDNode OpNodeRnd>{
1340 defm rr_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1342 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1343 "vcmp${cc}"#_.Suffix,
1344 "$src2, $src1", "$src1, $src2",
1345 (OpNode (_.VT _.RC:$src1),
1349 defm rm_Int : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1351 (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1352 "vcmp${cc}"#_.Suffix,
1353 "$src2, $src1", "$src1, $src2",
1354 (OpNode (_.VT _.RC:$src1),
1355 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
1356 imm:$cc)>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1358 defm rrb_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1360 (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1361 "vcmp${cc}"#_.Suffix,
1362 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1363 (OpNodeRnd (_.VT _.RC:$src1),
1366 (i32 FROUND_NO_EXC))>, EVEX_4V, EVEX_B;
1367 // Accept explicit immediate argument form instead of comparison code.
1368 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1369 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1371 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1373 "$cc, $src2, $src1", "$src1, $src2, $cc">, EVEX_4V;
1374 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1376 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1378 "$cc, $src2, $src1", "$src1, $src2, $cc">,
1379 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1381 defm rrb_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1383 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1385 "$cc,{sae}, $src2, $src1","$src1, $src2,{sae}, $cc">,
1387 }// let isAsmParserOnly = 1, hasSideEffects = 0
1389 let isCodeGenOnly = 1 in {
1390 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1391 (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, AVXCC:$cc),
1392 !strconcat("vcmp${cc}", _.Suffix,
1393 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1394 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1397 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1399 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1401 (ins _.FRC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1402 !strconcat("vcmp${cc}", _.Suffix,
1403 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1404 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1405 (_.ScalarLdFrag addr:$src2),
1407 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
1411 let Predicates = [HasAVX512] in {
1412 defm VCMPSSZ : avx512_cmp_scalar<f32x_info, X86cmpms, X86cmpmsRnd>,
1414 defm VCMPSDZ : avx512_cmp_scalar<f64x_info, X86cmpms, X86cmpmsRnd>,
1415 AVX512XDIi8Base, VEX_W;
1418 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1419 X86VectorVTInfo _> {
1420 def rr : AVX512BI<opc, MRMSrcReg,
1421 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1422 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1423 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1424 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1426 def rm : AVX512BI<opc, MRMSrcMem,
1427 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1428 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1429 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1430 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1431 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1432 def rrk : AVX512BI<opc, MRMSrcReg,
1433 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1434 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1435 "$dst {${mask}}, $src1, $src2}"),
1436 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1437 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1438 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1440 def rmk : AVX512BI<opc, MRMSrcMem,
1441 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1442 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1443 "$dst {${mask}}, $src1, $src2}"),
1444 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1445 (OpNode (_.VT _.RC:$src1),
1447 (_.LdFrag addr:$src2))))))],
1448 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1451 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1452 X86VectorVTInfo _> :
1453 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1454 let mayLoad = 1 in {
1455 def rmb : AVX512BI<opc, MRMSrcMem,
1456 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1457 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1458 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1459 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1460 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1461 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1462 def rmbk : AVX512BI<opc, MRMSrcMem,
1463 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1464 _.ScalarMemOp:$src2),
1465 !strconcat(OpcodeStr,
1466 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1467 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1468 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1469 (OpNode (_.VT _.RC:$src1),
1471 (_.ScalarLdFrag addr:$src2)))))],
1472 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1476 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1477 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1478 let Predicates = [prd] in
1479 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1482 let Predicates = [prd, HasVLX] in {
1483 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1485 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1490 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1491 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1493 let Predicates = [prd] in
1494 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1497 let Predicates = [prd, HasVLX] in {
1498 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1500 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1505 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1506 avx512vl_i8_info, HasBWI>,
1509 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1510 avx512vl_i16_info, HasBWI>,
1511 EVEX_CD8<16, CD8VF>;
1513 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1514 avx512vl_i32_info, HasAVX512>,
1515 EVEX_CD8<32, CD8VF>;
1517 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1518 avx512vl_i64_info, HasAVX512>,
1519 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1521 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1522 avx512vl_i8_info, HasBWI>,
1525 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1526 avx512vl_i16_info, HasBWI>,
1527 EVEX_CD8<16, CD8VF>;
1529 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1530 avx512vl_i32_info, HasAVX512>,
1531 EVEX_CD8<32, CD8VF>;
1533 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1534 avx512vl_i64_info, HasAVX512>,
1535 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1537 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1538 (COPY_TO_REGCLASS (VPCMPGTDZrr
1539 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1540 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1542 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1543 (COPY_TO_REGCLASS (VPCMPEQDZrr
1544 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1545 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1547 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1548 X86VectorVTInfo _> {
1549 def rri : AVX512AIi8<opc, MRMSrcReg,
1550 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1551 !strconcat("vpcmp${cc}", Suffix,
1552 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1553 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1555 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1557 def rmi : AVX512AIi8<opc, MRMSrcMem,
1558 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1559 !strconcat("vpcmp${cc}", Suffix,
1560 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1561 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1562 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1564 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1565 def rrik : AVX512AIi8<opc, MRMSrcReg,
1566 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1568 !strconcat("vpcmp${cc}", Suffix,
1569 "\t{$src2, $src1, $dst {${mask}}|",
1570 "$dst {${mask}}, $src1, $src2}"),
1571 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1572 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1574 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1576 def rmik : AVX512AIi8<opc, MRMSrcMem,
1577 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1579 !strconcat("vpcmp${cc}", Suffix,
1580 "\t{$src2, $src1, $dst {${mask}}|",
1581 "$dst {${mask}}, $src1, $src2}"),
1582 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1583 (OpNode (_.VT _.RC:$src1),
1584 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1586 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1588 // Accept explicit immediate argument form instead of comparison code.
1589 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1590 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1591 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1592 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1593 "$dst, $src1, $src2, $cc}"),
1594 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1596 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1597 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1598 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1599 "$dst, $src1, $src2, $cc}"),
1600 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1601 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1602 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1604 !strconcat("vpcmp", Suffix,
1605 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1606 "$dst {${mask}}, $src1, $src2, $cc}"),
1607 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1609 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1610 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1612 !strconcat("vpcmp", Suffix,
1613 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1614 "$dst {${mask}}, $src1, $src2, $cc}"),
1615 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1619 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1620 X86VectorVTInfo _> :
1621 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1622 def rmib : AVX512AIi8<opc, MRMSrcMem,
1623 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1625 !strconcat("vpcmp${cc}", Suffix,
1626 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1627 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1628 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1629 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1631 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1632 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1633 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1634 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1635 !strconcat("vpcmp${cc}", Suffix,
1636 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1637 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1638 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1639 (OpNode (_.VT _.RC:$src1),
1640 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1642 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1644 // Accept explicit immediate argument form instead of comparison code.
1645 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1646 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1647 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1649 !strconcat("vpcmp", Suffix,
1650 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1651 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1652 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1653 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1654 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1655 _.ScalarMemOp:$src2, u8imm:$cc),
1656 !strconcat("vpcmp", Suffix,
1657 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1658 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1659 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1663 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1664 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1665 let Predicates = [prd] in
1666 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1668 let Predicates = [prd, HasVLX] in {
1669 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1670 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1674 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1675 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1676 let Predicates = [prd] in
1677 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1680 let Predicates = [prd, HasVLX] in {
1681 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1683 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1688 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1689 HasBWI>, EVEX_CD8<8, CD8VF>;
1690 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1691 HasBWI>, EVEX_CD8<8, CD8VF>;
1693 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1694 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1695 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1696 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1698 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1699 HasAVX512>, EVEX_CD8<32, CD8VF>;
1700 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1701 HasAVX512>, EVEX_CD8<32, CD8VF>;
1703 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1704 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1705 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1706 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1708 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1710 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1711 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1712 "vcmp${cc}"#_.Suffix,
1713 "$src2, $src1", "$src1, $src2",
1714 (X86cmpm (_.VT _.RC:$src1),
1718 let mayLoad = 1 in {
1719 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1720 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1721 "vcmp${cc}"#_.Suffix,
1722 "$src2, $src1", "$src1, $src2",
1723 (X86cmpm (_.VT _.RC:$src1),
1724 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1727 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1729 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1730 "vcmp${cc}"#_.Suffix,
1731 "${src2}"##_.BroadcastStr##", $src1",
1732 "$src1, ${src2}"##_.BroadcastStr,
1733 (X86cmpm (_.VT _.RC:$src1),
1734 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1737 // Accept explicit immediate argument form instead of comparison code.
1738 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1739 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1741 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1743 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1745 let mayLoad = 1 in {
1746 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1748 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1750 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1752 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1754 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1756 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1757 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1762 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1763 // comparison code form (VCMP[EQ/LT/LE/...]
1764 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1765 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1766 "vcmp${cc}"#_.Suffix,
1767 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1768 (X86cmpmRnd (_.VT _.RC:$src1),
1771 (i32 FROUND_NO_EXC))>, EVEX_B;
1773 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1774 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1776 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1778 "$cc,{sae}, $src2, $src1",
1779 "$src1, $src2,{sae}, $cc">, EVEX_B;
1783 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1784 let Predicates = [HasAVX512] in {
1785 defm Z : avx512_vcmp_common<_.info512>,
1786 avx512_vcmp_sae<_.info512>, EVEX_V512;
1789 let Predicates = [HasAVX512,HasVLX] in {
1790 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1791 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1795 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1796 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1797 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1798 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1800 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1801 (COPY_TO_REGCLASS (VCMPPSZrri
1802 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1803 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1805 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1806 (COPY_TO_REGCLASS (VPCMPDZrri
1807 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1808 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1810 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1811 (COPY_TO_REGCLASS (VPCMPUDZrri
1812 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1813 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1816 // ----------------------------------------------------------------
1818 //handle fpclass instruction mask = op(reg_scalar,imm)
1819 // op(mem_scalar,imm)
1820 multiclass avx512_scalar_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1821 X86VectorVTInfo _, Predicate prd> {
1822 let Predicates = [prd] in {
1823 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),//_.KRC:$dst),
1824 (ins _.RC:$src1, i32u8imm:$src2),
1825 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1826 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1827 (i32 imm:$src2)))], NoItinerary>;
1828 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1829 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1830 OpcodeStr##_.Suffix#
1831 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1832 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1833 (OpNode (_.VT _.RC:$src1),
1834 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1835 let mayLoad = 1, AddedComplexity = 20 in {
1836 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1837 (ins _.MemOp:$src1, i32u8imm:$src2),
1838 OpcodeStr##_.Suffix##
1839 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1841 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1842 (i32 imm:$src2)))], NoItinerary>;
1843 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1844 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1845 OpcodeStr##_.Suffix##
1846 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1847 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1848 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
1849 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1854 //handle fpclass instruction mask = fpclass(reg_vec, reg_vec, imm)
1855 // fpclass(reg_vec, mem_vec, imm)
1856 // fpclass(reg_vec, broadcast(eltVt), imm)
1857 multiclass avx512_vector_fpclass<bits<8> opc, string OpcodeStr, SDNode OpNode,
1858 X86VectorVTInfo _, string mem, string broadcast>{
1859 def rr : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1860 (ins _.RC:$src1, i32u8imm:$src2),
1861 OpcodeStr##_.Suffix#"\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1862 [(set _.KRC:$dst,(OpNode (_.VT _.RC:$src1),
1863 (i32 imm:$src2)))], NoItinerary>;
1864 def rrk : AVX512<opc, MRMSrcReg, (outs _.KRC:$dst),
1865 (ins _.KRCWM:$mask, _.RC:$src1, i32u8imm:$src2),
1866 OpcodeStr##_.Suffix#
1867 "\t{$src2, $src1, $dst {${mask}}| $dst {${mask}}, $src1, $src2}",
1868 [(set _.KRC:$dst,(or _.KRCWM:$mask,
1869 (OpNode (_.VT _.RC:$src1),
1870 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1871 let mayLoad = 1 in {
1872 def rm : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1873 (ins _.MemOp:$src1, i32u8imm:$src2),
1874 OpcodeStr##_.Suffix##mem#
1875 "\t{$src2, $src1, $dst | $dst, $src1, $src2}",
1876 [(set _.KRC:$dst,(OpNode
1877 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1878 (i32 imm:$src2)))], NoItinerary>;
1879 def rmk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1880 (ins _.KRCWM:$mask, _.MemOp:$src1, i32u8imm:$src2),
1881 OpcodeStr##_.Suffix##mem#
1882 "\t{$src2, $src1, $dst {${mask}} | $dst {${mask}}, $src1, $src2}",
1883 [(set _.KRC:$dst, (or _.KRCWM:$mask, (OpNode
1884 (_.VT (bitconvert (_.LdFrag addr:$src1))),
1885 (i32 imm:$src2))))], NoItinerary>, EVEX_K;
1886 def rmb : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1887 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
1888 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1889 _.BroadcastStr##", $dst | $dst, ${src1}"
1890 ##_.BroadcastStr##", $src2}",
1891 [(set _.KRC:$dst,(OpNode
1892 (_.VT (X86VBroadcast
1893 (_.ScalarLdFrag addr:$src1))),
1894 (i32 imm:$src2)))], NoItinerary>,EVEX_B;
1895 def rmbk : AVX512<opc, MRMSrcMem, (outs _.KRC:$dst),
1896 (ins _.KRCWM:$mask, _.ScalarMemOp:$src1, i32u8imm:$src2),
1897 OpcodeStr##_.Suffix##broadcast##"\t{$src2, ${src1}"##
1898 _.BroadcastStr##", $dst {${mask}} | $dst {${mask}}, ${src1}"##
1899 _.BroadcastStr##", $src2}",
1900 [(set _.KRC:$dst,(or _.KRCWM:$mask, (OpNode
1901 (_.VT (X86VBroadcast
1902 (_.ScalarLdFrag addr:$src1))),
1903 (i32 imm:$src2))))], NoItinerary>,
1908 multiclass avx512_vector_fpclass_all<string OpcodeStr,
1909 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd,
1911 let Predicates = [prd] in {
1912 defm Z : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info512, "{z}",
1913 broadcast>, EVEX_V512;
1915 let Predicates = [prd, HasVLX] in {
1916 defm Z128 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info128, "{x}",
1917 broadcast>, EVEX_V128;
1918 defm Z256 : avx512_vector_fpclass<opc, OpcodeStr, OpNode, _.info256, "{y}",
1919 broadcast>, EVEX_V256;
1923 multiclass avx512_fp_fpclass_all<string OpcodeStr, bits<8> opcVec,
1924 bits<8> opcScalar, SDNode VecOpNode, SDNode ScalarOpNode, Predicate prd>{
1925 defm PS : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f32_info, opcVec,
1926 VecOpNode, prd, "{l}">, EVEX_CD8<32, CD8VF>;
1927 defm PD : avx512_vector_fpclass_all<OpcodeStr, avx512vl_f64_info, opcVec,
1928 VecOpNode, prd, "{q}">,EVEX_CD8<64, CD8VF> , VEX_W;
1929 defm SS : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
1930 f32x_info, prd>, EVEX_CD8<32, CD8VT1>;
1931 defm SD : avx512_scalar_fpclass<opcScalar, OpcodeStr, ScalarOpNode,
1932 f64x_info, prd>, EVEX_CD8<64, CD8VT1>, VEX_W;
1935 defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, X86Vfpclass,
1936 X86Vfpclasss, HasDQI>, AVX512AIi8Base,EVEX;
1938 //-----------------------------------------------------------------
1939 // Mask register copy, including
1940 // - copy between mask registers
1941 // - load/store mask registers
1942 // - copy from GPR to mask register and vice versa
1944 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1945 string OpcodeStr, RegisterClass KRC,
1946 ValueType vvt, X86MemOperand x86memop> {
1947 let hasSideEffects = 0 in {
1948 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1949 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1951 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1952 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1953 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1955 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1956 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1957 [(store KRC:$src, addr:$dst)]>;
1961 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1963 RegisterClass KRC, RegisterClass GRC> {
1964 let hasSideEffects = 0 in {
1965 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1966 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1967 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1968 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1972 let Predicates = [HasDQI] in
1973 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1974 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1977 let Predicates = [HasAVX512] in
1978 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1979 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1982 let Predicates = [HasBWI] in {
1983 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1985 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1989 let Predicates = [HasBWI] in {
1990 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1992 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1996 // GR from/to mask register
1997 let Predicates = [HasDQI] in {
1998 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1999 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
2000 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2001 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
2003 let Predicates = [HasAVX512] in {
2004 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
2005 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
2006 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
2007 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
2009 let Predicates = [HasBWI] in {
2010 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
2011 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
2013 let Predicates = [HasBWI] in {
2014 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
2015 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
2019 let Predicates = [HasDQI] in {
2020 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2021 (KMOVBmk addr:$dst, VK8:$src)>;
2022 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2023 (KMOVBkm addr:$src)>;
2025 def : Pat<(store VK4:$src, addr:$dst),
2026 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK4:$src, VK8))>;
2027 def : Pat<(store VK2:$src, addr:$dst),
2028 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK2:$src, VK8))>;
2030 let Predicates = [HasAVX512, NoDQI] in {
2031 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
2032 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
2033 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
2034 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
2036 let Predicates = [HasAVX512] in {
2037 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
2038 (KMOVWmk addr:$dst, VK16:$src)>;
2039 def : Pat<(i1 (load addr:$src)),
2040 (COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
2041 (MOV8rm addr:$src), sub_8bit)),
2043 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
2044 (KMOVWkm addr:$src)>;
2046 let Predicates = [HasBWI] in {
2047 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
2048 (KMOVDmk addr:$dst, VK32:$src)>;
2049 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
2050 (KMOVDkm addr:$src)>;
2052 let Predicates = [HasBWI] in {
2053 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
2054 (KMOVQmk addr:$dst, VK64:$src)>;
2055 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
2056 (KMOVQkm addr:$src)>;
2059 let Predicates = [HasAVX512] in {
2060 def : Pat<(i1 (trunc (i64 GR64:$src))),
2061 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
2064 def : Pat<(i1 (trunc (i32 GR32:$src))),
2065 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
2067 def : Pat<(i1 (trunc (i8 GR8:$src))),
2069 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
2071 def : Pat<(i1 (trunc (i16 GR16:$src))),
2073 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
2076 def : Pat<(i32 (zext VK1:$src)),
2077 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
2078 def : Pat<(i32 (anyext VK1:$src)),
2079 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
2081 def : Pat<(i8 (zext VK1:$src)),
2084 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
2085 def : Pat<(i8 (anyext VK1:$src)),
2087 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_8bit)>;
2089 def : Pat<(i64 (zext VK1:$src)),
2090 (AND64ri8 (SUBREG_TO_REG (i64 0),
2091 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
2092 def : Pat<(i16 (zext VK1:$src)),
2094 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
2096 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
2097 (COPY_TO_REGCLASS VK1:$src, VK16)>;
2098 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
2099 (COPY_TO_REGCLASS VK1:$src, VK8)>;
2101 let Predicates = [HasBWI] in {
2102 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
2103 (COPY_TO_REGCLASS VK1:$src, VK32)>;
2104 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
2105 (COPY_TO_REGCLASS VK1:$src, VK64)>;
2109 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2110 let Predicates = [HasAVX512, NoDQI] in {
2111 // GR from/to 8-bit mask without native support
2112 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
2114 (KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
2115 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
2117 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
2121 let Predicates = [HasAVX512] in {
2122 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
2123 (COPY_TO_REGCLASS VK16:$src, VK1)>;
2124 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
2125 (COPY_TO_REGCLASS VK8:$src, VK1)>;
2127 let Predicates = [HasBWI] in {
2128 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
2129 (COPY_TO_REGCLASS VK32:$src, VK1)>;
2130 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
2131 (COPY_TO_REGCLASS VK64:$src, VK1)>;
2134 // Mask unary operation
2136 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
2137 RegisterClass KRC, SDPatternOperator OpNode,
2139 let Predicates = [prd] in
2140 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
2141 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2142 [(set KRC:$dst, (OpNode KRC:$src))]>;
2145 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
2146 SDPatternOperator OpNode> {
2147 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2149 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2150 HasAVX512>, VEX, PS;
2151 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2152 HasBWI>, VEX, PD, VEX_W;
2153 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2154 HasBWI>, VEX, PS, VEX_W;
2157 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
2159 multiclass avx512_mask_unop_int<string IntName, string InstName> {
2160 let Predicates = [HasAVX512] in
2161 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2163 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2164 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
2166 defm : avx512_mask_unop_int<"knot", "KNOT">;
2168 let Predicates = [HasDQI] in
2169 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
2170 let Predicates = [HasAVX512] in
2171 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
2172 let Predicates = [HasBWI] in
2173 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
2174 let Predicates = [HasBWI] in
2175 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
2177 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
2178 let Predicates = [HasAVX512, NoDQI] in {
2179 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
2180 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
2181 def : Pat<(not VK8:$src),
2183 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
2185 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
2186 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
2187 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
2188 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
2190 // Mask binary operation
2191 // - KAND, KANDN, KOR, KXNOR, KXOR
2192 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
2193 RegisterClass KRC, SDPatternOperator OpNode,
2194 Predicate prd, bit IsCommutable> {
2195 let Predicates = [prd], isCommutable = IsCommutable in
2196 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2197 !strconcat(OpcodeStr,
2198 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2199 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
2202 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
2203 SDPatternOperator OpNode, bit IsCommutable,
2204 Predicate prdW = HasAVX512> {
2205 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
2206 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
2207 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2208 prdW, IsCommutable>, VEX_4V, VEX_L, PS;
2209 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
2210 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
2211 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
2212 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
2215 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
2216 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
2218 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
2219 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
2220 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
2221 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
2222 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
2223 defm KADD : avx512_mask_binop_all<0x4A, "kadd", add, 1, HasDQI>;
2225 multiclass avx512_mask_binop_int<string IntName, string InstName> {
2226 let Predicates = [HasAVX512] in
2227 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
2228 (i16 GR16:$src1), (i16 GR16:$src2)),
2229 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
2230 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2231 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2234 defm : avx512_mask_binop_int<"kand", "KAND">;
2235 defm : avx512_mask_binop_int<"kandn", "KANDN">;
2236 defm : avx512_mask_binop_int<"kor", "KOR">;
2237 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
2238 defm : avx512_mask_binop_int<"kxor", "KXOR">;
2240 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
2241 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
2242 // for the DQI set, this type is legal and KxxxB instruction is used
2243 let Predicates = [NoDQI] in
2244 def : Pat<(OpNode VK8:$src1, VK8:$src2),
2246 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
2247 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2249 // All types smaller than 8 bits require conversion anyway
2250 def : Pat<(OpNode VK1:$src1, VK1:$src2),
2251 (COPY_TO_REGCLASS (Inst
2252 (COPY_TO_REGCLASS VK1:$src1, VK16),
2253 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2254 def : Pat<(OpNode VK2:$src1, VK2:$src2),
2255 (COPY_TO_REGCLASS (Inst
2256 (COPY_TO_REGCLASS VK2:$src1, VK16),
2257 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
2258 def : Pat<(OpNode VK4:$src1, VK4:$src2),
2259 (COPY_TO_REGCLASS (Inst
2260 (COPY_TO_REGCLASS VK4:$src1, VK16),
2261 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2264 defm : avx512_binop_pat<and, KANDWrr>;
2265 defm : avx512_binop_pat<andn, KANDNWrr>;
2266 defm : avx512_binop_pat<or, KORWrr>;
2267 defm : avx512_binop_pat<xnor, KXNORWrr>;
2268 defm : avx512_binop_pat<xor, KXORWrr>;
2270 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2271 (KXNORWrr VK16:$src1, VK16:$src2)>;
2272 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2273 (KXNORBrr VK8:$src1, VK8:$src2)>, Requires<[HasDQI]>;
2274 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2275 (KXNORDrr VK32:$src1, VK32:$src2)>, Requires<[HasBWI]>;
2276 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2277 (KXNORQrr VK64:$src1, VK64:$src2)>, Requires<[HasBWI]>;
2279 let Predicates = [NoDQI] in
2280 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2281 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2282 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2284 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2285 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2286 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2288 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2289 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2290 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2292 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2293 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2294 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2297 multiclass avx512_mask_unpck<string Suffix,RegisterClass KRC, ValueType VT,
2298 RegisterClass KRCSrc, Predicate prd> {
2299 let Predicates = [prd] in {
2300 def rr : I<0x4b, MRMSrcReg, (outs KRC:$dst),
2301 (ins KRC:$src1, KRC:$src2),
2302 "kunpck"#Suffix#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2305 def : Pat<(VT (concat_vectors KRCSrc:$src1, KRCSrc:$src2)),
2306 (!cast<Instruction>(NAME##rr)
2307 (COPY_TO_REGCLASS KRCSrc:$src2, KRC),
2308 (COPY_TO_REGCLASS KRCSrc:$src1, KRC))>;
2312 defm KUNPCKBW : avx512_mask_unpck<"bw", VK16, v16i1, VK8, HasAVX512>, PD;
2313 defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, HasBWI>, PS;
2314 defm KUNPCKDQ : avx512_mask_unpck<"dq", VK64, v64i1, VK32, HasBWI>, PS, VEX_W;
2316 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
2317 let Predicates = [HasAVX512] in
2318 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
2319 (i16 GR16:$src1), (i16 GR16:$src2)),
2320 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
2321 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2322 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2324 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
2327 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2328 SDNode OpNode, Predicate prd> {
2329 let Predicates = [prd], Defs = [EFLAGS] in
2330 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2331 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2332 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2335 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2336 Predicate prdW = HasAVX512> {
2337 defm B : avx512_mask_testop<opc, OpcodeStr#"b", VK8, OpNode, HasDQI>,
2339 defm W : avx512_mask_testop<opc, OpcodeStr#"w", VK16, OpNode, prdW>,
2341 defm Q : avx512_mask_testop<opc, OpcodeStr#"q", VK64, OpNode, HasBWI>,
2343 defm D : avx512_mask_testop<opc, OpcodeStr#"d", VK32, OpNode, HasBWI>,
2347 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2348 defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest, HasDQI>;
2351 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2353 let Predicates = [HasAVX512] in
2354 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2355 !strconcat(OpcodeStr,
2356 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2357 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2360 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2362 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2364 let Predicates = [HasDQI] in
2365 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2367 let Predicates = [HasBWI] in {
2368 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2370 let Predicates = [HasDQI] in
2371 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2376 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2377 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2379 // Mask setting all 0s or 1s
2380 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2381 let Predicates = [HasAVX512] in
2382 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2383 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2384 [(set KRC:$dst, (VT Val))]>;
2387 multiclass avx512_mask_setop_w<PatFrag Val> {
2388 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2389 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2390 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2391 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2394 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2395 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2397 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2398 let Predicates = [HasAVX512] in {
2399 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2400 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2401 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2402 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2403 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2404 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2405 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2407 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2408 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2410 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2411 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2413 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2414 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2416 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
2417 (v32i1 (COPY_TO_REGCLASS VK64:$src, VK32))>;
2419 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2420 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2422 let Predicates = [HasVLX] in {
2423 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2424 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2425 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2426 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2427 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2428 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2429 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2430 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2431 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2432 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2435 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2436 (v8i1 (COPY_TO_REGCLASS
2437 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2438 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2440 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2441 (v8i1 (COPY_TO_REGCLASS
2442 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2443 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2445 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2446 (v4i1 (COPY_TO_REGCLASS
2447 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2448 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2450 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2451 (v4i1 (COPY_TO_REGCLASS
2452 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2453 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2455 //===----------------------------------------------------------------------===//
2456 // AVX-512 - Aligned and unaligned load and store
2460 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2461 PatFrag ld_frag, PatFrag mload,
2462 bit IsReMaterializable = 1> {
2463 let hasSideEffects = 0 in {
2464 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2465 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2467 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2468 (ins _.KRCWM:$mask, _.RC:$src),
2469 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2470 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2473 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2474 SchedRW = [WriteLoad] in
2475 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2476 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2477 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2480 let Constraints = "$src0 = $dst" in {
2481 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2482 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2483 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2484 "${dst} {${mask}}, $src1}"),
2485 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2487 (_.VT _.RC:$src0))))], _.ExeDomain>,
2489 let mayLoad = 1, SchedRW = [WriteLoad] in
2490 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2491 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2492 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2493 "${dst} {${mask}}, $src1}"),
2494 [(set _.RC:$dst, (_.VT
2495 (vselect _.KRCWM:$mask,
2496 (_.VT (bitconvert (ld_frag addr:$src1))),
2497 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2499 let mayLoad = 1, SchedRW = [WriteLoad] in
2500 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2501 (ins _.KRCWM:$mask, _.MemOp:$src),
2502 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2503 "${dst} {${mask}} {z}, $src}",
2504 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2505 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2506 _.ExeDomain>, EVEX, EVEX_KZ;
2508 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2509 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2511 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2512 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2514 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2515 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2516 _.KRCWM:$mask, addr:$ptr)>;
2519 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2520 AVX512VLVectorVTInfo _,
2522 bit IsReMaterializable = 1> {
2523 let Predicates = [prd] in
2524 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2525 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2527 let Predicates = [prd, HasVLX] in {
2528 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2529 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2530 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2531 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2535 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2536 AVX512VLVectorVTInfo _,
2538 bit IsReMaterializable = 1> {
2539 let Predicates = [prd] in
2540 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2541 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2543 let Predicates = [prd, HasVLX] in {
2544 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2545 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2546 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2547 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2551 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2552 PatFrag st_frag, PatFrag mstore> {
2554 def rr_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2555 OpcodeStr # ".s\t{$src, $dst|$dst, $src}",
2556 [], _.ExeDomain>, EVEX;
2557 def rrk_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2558 (ins _.KRCWM:$mask, _.RC:$src),
2559 OpcodeStr # ".s\t{$src, ${dst} {${mask}}|"#
2560 "${dst} {${mask}}, $src}",
2561 [], _.ExeDomain>, EVEX, EVEX_K;
2562 def rrkz_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2563 (ins _.KRCWM:$mask, _.RC:$src),
2564 OpcodeStr # ".s\t{$src, ${dst} {${mask}} {z}|" #
2565 "${dst} {${mask}} {z}, $src}",
2566 [], _.ExeDomain>, EVEX, EVEX_KZ;
2568 let mayStore = 1 in {
2569 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2570 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2571 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2572 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2573 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2574 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2575 [], _.ExeDomain>, EVEX, EVEX_K;
2578 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2579 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2580 _.KRCWM:$mask, _.RC:$src)>;
2584 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2585 AVX512VLVectorVTInfo _, Predicate prd> {
2586 let Predicates = [prd] in
2587 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2588 masked_store_unaligned>, EVEX_V512;
2590 let Predicates = [prd, HasVLX] in {
2591 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2592 masked_store_unaligned>, EVEX_V256;
2593 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2594 masked_store_unaligned>, EVEX_V128;
2598 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2599 AVX512VLVectorVTInfo _, Predicate prd> {
2600 let Predicates = [prd] in
2601 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2602 masked_store_aligned512>, EVEX_V512;
2604 let Predicates = [prd, HasVLX] in {
2605 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2606 masked_store_aligned256>, EVEX_V256;
2607 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2608 masked_store_aligned128>, EVEX_V128;
2612 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2614 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2615 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2617 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2619 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2620 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2622 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2623 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2624 PS, EVEX_CD8<32, CD8VF>;
2626 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2627 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2628 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2630 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2631 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2632 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2634 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2635 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2636 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2638 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2639 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2640 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2642 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2643 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2644 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2646 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2647 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2648 (VMOVAPDZrm addr:$ptr)>;
2650 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2651 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2652 (VMOVAPSZrm addr:$ptr)>;
2654 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2656 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2658 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2660 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2663 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2665 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2667 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2669 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2672 let Predicates = [HasAVX512, NoVLX] in {
2673 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2674 (VMOVUPSZmrk addr:$ptr,
2675 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2676 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2678 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2679 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2680 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2682 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2683 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2684 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2685 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2688 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2690 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2691 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2693 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2695 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2696 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2698 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2699 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2700 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2702 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2703 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2704 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2706 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2707 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2708 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2710 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2711 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2712 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2714 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2715 (v16i32 immAllZerosV), GR16:$mask)),
2716 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2718 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2719 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2720 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2722 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2724 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2726 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2728 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2731 let AddedComplexity = 20 in {
2732 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2733 (bc_v8i64 (v16i32 immAllZerosV)))),
2734 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2736 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2737 (v8i64 VR512:$src))),
2738 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2741 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2742 (v16i32 immAllZerosV))),
2743 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2745 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2746 (v16i32 VR512:$src))),
2747 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2750 let Predicates = [HasAVX512, NoVLX] in {
2751 def: Pat<(X86mstore addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2752 (VMOVDQU32Zmrk addr:$ptr,
2753 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2754 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2756 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2757 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2758 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2761 // Move Int Doubleword to Packed Double Int
2763 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2764 "vmovd\t{$src, $dst|$dst, $src}",
2766 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2768 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2769 "vmovd\t{$src, $dst|$dst, $src}",
2771 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2772 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2773 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2774 "vmovq\t{$src, $dst|$dst, $src}",
2776 (v2i64 (scalar_to_vector GR64:$src)))],
2777 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2778 let isCodeGenOnly = 1 in {
2779 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2780 "vmovq\t{$src, $dst|$dst, $src}",
2781 [(set FR64:$dst, (bitconvert GR64:$src))],
2782 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2783 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2784 "vmovq\t{$src, $dst|$dst, $src}",
2785 [(set GR64:$dst, (bitconvert FR64:$src))],
2786 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2788 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2789 "vmovq\t{$src, $dst|$dst, $src}",
2790 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2791 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2792 EVEX_CD8<64, CD8VT1>;
2794 // Move Int Doubleword to Single Scalar
2796 let isCodeGenOnly = 1 in {
2797 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2798 "vmovd\t{$src, $dst|$dst, $src}",
2799 [(set FR32X:$dst, (bitconvert GR32:$src))],
2800 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2802 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2803 "vmovd\t{$src, $dst|$dst, $src}",
2804 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2805 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2808 // Move doubleword from xmm register to r/m32
2810 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2811 "vmovd\t{$src, $dst|$dst, $src}",
2812 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2813 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2815 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2816 (ins i32mem:$dst, VR128X:$src),
2817 "vmovd\t{$src, $dst|$dst, $src}",
2818 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2819 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2820 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2822 // Move quadword from xmm1 register to r/m64
2824 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2825 "vmovq\t{$src, $dst|$dst, $src}",
2826 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2828 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2829 Requires<[HasAVX512, In64BitMode]>;
2831 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2832 (ins i64mem:$dst, VR128X:$src),
2833 "vmovq\t{$src, $dst|$dst, $src}",
2834 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2835 addr:$dst)], IIC_SSE_MOVDQ>,
2836 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2837 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2839 // Move Scalar Single to Double Int
2841 let isCodeGenOnly = 1 in {
2842 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2844 "vmovd\t{$src, $dst|$dst, $src}",
2845 [(set GR32:$dst, (bitconvert FR32X:$src))],
2846 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2847 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2848 (ins i32mem:$dst, FR32X:$src),
2849 "vmovd\t{$src, $dst|$dst, $src}",
2850 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2851 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2854 // Move Quadword Int to Packed Quadword Int
2856 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2858 "vmovq\t{$src, $dst|$dst, $src}",
2860 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2861 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2863 //===----------------------------------------------------------------------===//
2864 // AVX-512 MOVSS, MOVSD
2865 //===----------------------------------------------------------------------===//
2867 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2868 SDNode OpNode, ValueType vt,
2869 X86MemOperand x86memop, PatFrag mem_pat> {
2870 let hasSideEffects = 0 in {
2871 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2872 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2873 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2874 (scalar_to_vector RC:$src2))))],
2875 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2876 let Constraints = "$src1 = $dst" in
2877 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2878 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2880 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2881 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2882 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2883 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2884 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2886 let mayStore = 1 in {
2887 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2888 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2889 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2891 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2892 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2893 [], IIC_SSE_MOV_S_MR>,
2894 EVEX, VEX_LIG, EVEX_K;
2896 } //hasSideEffects = 0
2899 let ExeDomain = SSEPackedSingle in
2900 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2901 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2903 let ExeDomain = SSEPackedDouble in
2904 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2905 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2907 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2908 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2909 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2911 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2912 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2913 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2915 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2916 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2917 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2919 defm VMOVSSZrr_REV : AVX512_maskable_in_asm<0x11, MRMDestReg, f32x_info,
2920 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2),
2921 "vmovss.s", "$src2, $src1", "$src1, $src2", []>,
2922 XS, EVEX_4V, VEX_LIG;
2924 defm VMOVSSDrr_REV : AVX512_maskable_in_asm<0x11, MRMDestReg, f64x_info,
2925 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2),
2926 "vmovsd.s", "$src2, $src1", "$src1, $src2", []>,
2927 XD, EVEX_4V, VEX_LIG, VEX_W;
2929 let Predicates = [HasAVX512] in {
2930 let AddedComplexity = 15 in {
2931 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2932 // MOVS{S,D} to the lower bits.
2933 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2934 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2935 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2936 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2937 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2938 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2939 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2940 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2942 // Move low f32 and clear high bits.
2943 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2944 (SUBREG_TO_REG (i32 0),
2945 (VMOVSSZrr (v4f32 (V_SET0)),
2946 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2947 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2948 (SUBREG_TO_REG (i32 0),
2949 (VMOVSSZrr (v4i32 (V_SET0)),
2950 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2953 let AddedComplexity = 20 in {
2954 // MOVSSrm zeros the high parts of the register; represent this
2955 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2956 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2957 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2958 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2959 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2960 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2961 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2963 // MOVSDrm zeros the high parts of the register; represent this
2964 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2965 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2966 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2967 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2968 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2969 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2970 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2971 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2972 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2973 def : Pat<(v2f64 (X86vzload addr:$src)),
2974 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2976 // Represent the same patterns above but in the form they appear for
2978 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2979 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2980 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2981 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2982 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2983 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2984 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2985 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2986 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2988 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2989 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2990 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2991 FR32X:$src)), sub_xmm)>;
2992 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2993 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2994 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2995 FR64X:$src)), sub_xmm)>;
2996 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2997 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2998 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
3000 // Move low f64 and clear high bits.
3001 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
3002 (SUBREG_TO_REG (i32 0),
3003 (VMOVSDZrr (v2f64 (V_SET0)),
3004 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
3006 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
3007 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
3008 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
3010 // Extract and store.
3011 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
3013 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
3014 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
3016 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
3018 // Shuffle with VMOVSS
3019 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
3020 (VMOVSSZrr (v4i32 VR128X:$src1),
3021 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
3022 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
3023 (VMOVSSZrr (v4f32 VR128X:$src1),
3024 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
3027 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
3028 (SUBREG_TO_REG (i32 0),
3029 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
3030 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
3032 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
3033 (SUBREG_TO_REG (i32 0),
3034 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
3035 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
3038 // Shuffle with VMOVSD
3039 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3040 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3041 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
3042 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3043 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3044 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3045 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
3046 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3049 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3050 (SUBREG_TO_REG (i32 0),
3051 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
3052 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
3054 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
3055 (SUBREG_TO_REG (i32 0),
3056 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
3057 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
3060 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3061 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3062 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
3063 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3064 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3065 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3066 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
3067 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
3070 let AddedComplexity = 15 in
3071 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
3073 "vmovq\t{$src, $dst|$dst, $src}",
3074 [(set VR128X:$dst, (v2i64 (X86vzmovl
3075 (v2i64 VR128X:$src))))],
3076 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
3078 let AddedComplexity = 20 , isCodeGenOnly = 1 in
3079 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
3081 "vmovq\t{$src, $dst|$dst, $src}",
3082 [(set VR128X:$dst, (v2i64 (X86vzmovl
3083 (loadv2i64 addr:$src))))],
3084 IIC_SSE_MOVDQ>, EVEX, VEX_W,
3085 EVEX_CD8<8, CD8VT8>;
3087 let Predicates = [HasAVX512] in {
3088 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3089 let AddedComplexity = 20 in {
3090 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
3091 (VMOVDI2PDIZrm addr:$src)>;
3092 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
3093 (VMOV64toPQIZrr GR64:$src)>;
3094 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
3095 (VMOVDI2PDIZrr GR32:$src)>;
3097 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3098 (VMOVDI2PDIZrm addr:$src)>;
3099 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3100 (VMOVDI2PDIZrm addr:$src)>;
3101 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3102 (VMOVZPQILo2PQIZrm addr:$src)>;
3103 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
3104 (VMOVZPQILo2PQIZrr VR128X:$src)>;
3105 def : Pat<(v2i64 (X86vzload addr:$src)),
3106 (VMOVZPQILo2PQIZrm addr:$src)>;
3109 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3110 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3111 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
3112 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
3113 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3114 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
3115 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
3118 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
3119 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3121 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
3122 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3124 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
3125 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
3127 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
3128 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
3130 //===----------------------------------------------------------------------===//
3131 // AVX-512 - Non-temporals
3132 //===----------------------------------------------------------------------===//
3133 let SchedRW = [WriteLoad] in {
3134 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
3135 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
3136 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
3137 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
3138 EVEX_CD8<64, CD8VF>;
3140 let Predicates = [HasAVX512, HasVLX] in {
3141 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
3143 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3144 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
3145 EVEX_CD8<64, CD8VF>;
3147 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
3149 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
3150 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
3151 EVEX_CD8<64, CD8VF>;
3155 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3156 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
3157 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
3158 let SchedRW = [WriteStore], mayStore = 1,
3159 AddedComplexity = 400 in
3160 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
3161 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3162 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
3165 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
3166 string elty, string elsz, string vsz512,
3167 string vsz256, string vsz128, Domain d,
3168 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
3169 let Predicates = [prd] in
3170 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
3171 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
3172 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
3175 let Predicates = [prd, HasVLX] in {
3176 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
3177 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
3178 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
3181 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
3182 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
3183 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
3188 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
3189 "i", "64", "8", "4", "2", SSEPackedInt,
3190 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
3192 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
3193 "f", "64", "8", "4", "2", SSEPackedDouble,
3194 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
3196 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
3197 "f", "32", "16", "8", "4", SSEPackedSingle,
3198 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
3200 //===----------------------------------------------------------------------===//
3201 // AVX-512 - Integer arithmetic
3203 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3204 X86VectorVTInfo _, OpndItins itins,
3205 bit IsCommutable = 0> {
3206 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3207 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3208 "$src2, $src1", "$src1, $src2",
3209 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
3210 itins.rr, IsCommutable>,
3211 AVX512BIBase, EVEX_4V;
3214 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3215 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3216 "$src2, $src1", "$src1, $src2",
3217 (_.VT (OpNode _.RC:$src1,
3218 (bitconvert (_.LdFrag addr:$src2)))),
3220 AVX512BIBase, EVEX_4V;
3223 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3224 X86VectorVTInfo _, OpndItins itins,
3225 bit IsCommutable = 0> :
3226 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
3228 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3229 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3230 "${src2}"##_.BroadcastStr##", $src1",
3231 "$src1, ${src2}"##_.BroadcastStr,
3232 (_.VT (OpNode _.RC:$src1,
3234 (_.ScalarLdFrag addr:$src2)))),
3236 AVX512BIBase, EVEX_4V, EVEX_B;
3239 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3240 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3241 Predicate prd, bit IsCommutable = 0> {
3242 let Predicates = [prd] in
3243 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3244 IsCommutable>, EVEX_V512;
3246 let Predicates = [prd, HasVLX] in {
3247 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3248 IsCommutable>, EVEX_V256;
3249 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3250 IsCommutable>, EVEX_V128;
3254 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3255 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3256 Predicate prd, bit IsCommutable = 0> {
3257 let Predicates = [prd] in
3258 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3259 IsCommutable>, EVEX_V512;
3261 let Predicates = [prd, HasVLX] in {
3262 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3263 IsCommutable>, EVEX_V256;
3264 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3265 IsCommutable>, EVEX_V128;
3269 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3270 OpndItins itins, Predicate prd,
3271 bit IsCommutable = 0> {
3272 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3273 itins, prd, IsCommutable>,
3274 VEX_W, EVEX_CD8<64, CD8VF>;
3277 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3278 OpndItins itins, Predicate prd,
3279 bit IsCommutable = 0> {
3280 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3281 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3284 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3285 OpndItins itins, Predicate prd,
3286 bit IsCommutable = 0> {
3287 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3288 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3291 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3292 OpndItins itins, Predicate prd,
3293 bit IsCommutable = 0> {
3294 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3295 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3298 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3299 SDNode OpNode, OpndItins itins, Predicate prd,
3300 bit IsCommutable = 0> {
3301 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr#"q", OpNode, itins, prd,
3304 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr#"d", OpNode, itins, prd,
3308 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3309 SDNode OpNode, OpndItins itins, Predicate prd,
3310 bit IsCommutable = 0> {
3311 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr#"w", OpNode, itins, prd,
3314 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr#"b", OpNode, itins, prd,
3318 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3319 bits<8> opc_d, bits<8> opc_q,
3320 string OpcodeStr, SDNode OpNode,
3321 OpndItins itins, bit IsCommutable = 0> {
3322 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3323 itins, HasAVX512, IsCommutable>,
3324 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3325 itins, HasBWI, IsCommutable>;
3328 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3329 SDNode OpNode,X86VectorVTInfo _Src,
3330 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3331 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3332 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3333 "$src2, $src1","$src1, $src2",
3335 (_Src.VT _Src.RC:$src1),
3336 (_Src.VT _Src.RC:$src2))),
3337 itins.rr, IsCommutable>,
3338 AVX512BIBase, EVEX_4V;
3339 let mayLoad = 1 in {
3340 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3341 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3342 "$src2, $src1", "$src1, $src2",
3343 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3344 (bitconvert (_Src.LdFrag addr:$src2)))),
3346 AVX512BIBase, EVEX_4V;
3348 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3349 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3351 "${src2}"##_Dst.BroadcastStr##", $src1",
3352 "$src1, ${src2}"##_Dst.BroadcastStr,
3353 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3354 (_Dst.VT (X86VBroadcast
3355 (_Dst.ScalarLdFrag addr:$src2)))))),
3357 AVX512BIBase, EVEX_4V, EVEX_B;
3361 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3362 SSE_INTALU_ITINS_P, 1>;
3363 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3364 SSE_INTALU_ITINS_P, 0>;
3365 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3366 SSE_INTALU_ITINS_P, HasBWI, 1>;
3367 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3368 SSE_INTALU_ITINS_P, HasBWI, 0>;
3369 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3370 SSE_INTALU_ITINS_P, HasBWI, 1>;
3371 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3372 SSE_INTALU_ITINS_P, HasBWI, 0>;
3373 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmulld", mul,
3374 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3375 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmullw", mul,
3376 SSE_INTALU_ITINS_P, HasBWI, 1>;
3377 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmullq", mul,
3378 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3379 defm VPMULHW : avx512_binop_rm_vl_w<0xE5, "vpmulhw", mulhs, SSE_INTALU_ITINS_P,
3381 defm VPMULHUW : avx512_binop_rm_vl_w<0xE4, "vpmulhuw", mulhu, SSE_INTMUL_ITINS_P,
3383 defm VPMULHRSW : avx512_binop_rm_vl_w<0x0B, "vpmulhrsw", X86mulhrs, SSE_INTMUL_ITINS_P,
3385 defm VPAVG : avx512_binop_rm_vl_bw<0xE0, 0xE3, "vpavg", X86avg,
3386 SSE_INTALU_ITINS_P, HasBWI, 1>;
3388 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3389 SDNode OpNode, bit IsCommutable = 0> {
3391 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3392 v16i32_info, v8i64_info, IsCommutable>,
3393 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3394 let Predicates = [HasVLX] in {
3395 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3396 v8i32x_info, v4i64x_info, IsCommutable>,
3397 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3398 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3399 v4i32x_info, v2i64x_info, IsCommutable>,
3400 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3404 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3406 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3409 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3410 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3411 let mayLoad = 1 in {
3412 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3413 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3415 "${src2}"##_Src.BroadcastStr##", $src1",
3416 "$src1, ${src2}"##_Src.BroadcastStr,
3417 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3418 (_Src.VT (X86VBroadcast
3419 (_Src.ScalarLdFrag addr:$src2))))))>,
3420 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3424 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3425 SDNode OpNode,X86VectorVTInfo _Src,
3426 X86VectorVTInfo _Dst> {
3427 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3428 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3429 "$src2, $src1","$src1, $src2",
3431 (_Src.VT _Src.RC:$src1),
3432 (_Src.VT _Src.RC:$src2)))>,
3433 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3434 let mayLoad = 1 in {
3435 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3436 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3437 "$src2, $src1", "$src1, $src2",
3438 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3439 (bitconvert (_Src.LdFrag addr:$src2))))>,
3440 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3444 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3446 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3448 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3449 v32i16_info>, EVEX_V512;
3450 let Predicates = [HasVLX] in {
3451 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3453 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3454 v16i16x_info>, EVEX_V256;
3455 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3457 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3458 v8i16x_info>, EVEX_V128;
3461 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3463 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3464 v64i8_info>, EVEX_V512;
3465 let Predicates = [HasVLX] in {
3466 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3467 v32i8x_info>, EVEX_V256;
3468 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3469 v16i8x_info>, EVEX_V128;
3473 multiclass avx512_vpmadd<bits<8> opc, string OpcodeStr,
3474 SDNode OpNode, AVX512VLVectorVTInfo _Src,
3475 AVX512VLVectorVTInfo _Dst> {
3476 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info512,
3477 _Dst.info512>, EVEX_V512;
3478 let Predicates = [HasVLX] in {
3479 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info256,
3480 _Dst.info256>, EVEX_V256;
3481 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, _Src.info128,
3482 _Dst.info128>, EVEX_V128;
3486 let Predicates = [HasBWI] in {
3487 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3488 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3489 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3490 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3492 defm VPMADDUBSW : avx512_vpmadd<0x04, "vpmaddubsw", X86vpmaddubsw,
3493 avx512vl_i8_info, avx512vl_i16_info>, AVX512BIBase, T8PD;
3494 defm VPMADDWD : avx512_vpmadd<0xF5, "vpmaddwd", X86vpmaddwd,
3495 avx512vl_i16_info, avx512vl_i32_info>, AVX512BIBase;
3498 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxsb", smax,
3499 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3500 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxsw", smax,
3501 SSE_INTALU_ITINS_P, HasBWI, 1>;
3502 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", smax,
3503 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3505 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxub", umax,
3506 SSE_INTALU_ITINS_P, HasBWI, 1>;
3507 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxuw", umax,
3508 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3509 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", umax,
3510 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3512 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpminsb", smin,
3513 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3514 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpminsw", smin,
3515 SSE_INTALU_ITINS_P, HasBWI, 1>;
3516 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", smin,
3517 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3519 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminub", umin,
3520 SSE_INTALU_ITINS_P, HasBWI, 1>;
3521 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminuw", umin,
3522 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3523 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", umin,
3524 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3525 //===----------------------------------------------------------------------===//
3526 // AVX-512 Logical Instructions
3527 //===----------------------------------------------------------------------===//
3529 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3530 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3531 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3532 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3533 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3534 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3535 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3536 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3538 //===----------------------------------------------------------------------===//
3539 // AVX-512 FP arithmetic
3540 //===----------------------------------------------------------------------===//
3541 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3542 SDNode OpNode, SDNode VecNode, OpndItins itins,
3545 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3546 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3547 "$src2, $src1", "$src1, $src2",
3548 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3549 (i32 FROUND_CURRENT)),
3550 itins.rr, IsCommutable>;
3552 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3553 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3554 "$src2, $src1", "$src1, $src2",
3555 (VecNode (_.VT _.RC:$src1),
3556 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3557 (i32 FROUND_CURRENT)),
3558 itins.rm, IsCommutable>;
3559 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3560 Predicates = [HasAVX512] in {
3561 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3562 (ins _.FRC:$src1, _.FRC:$src2),
3563 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3564 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3566 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3567 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3568 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3569 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3570 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3574 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3575 SDNode VecNode, OpndItins itins, bit IsCommutable = 0> {
3577 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3578 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3579 "$rc, $src2, $src1", "$src1, $src2, $rc",
3580 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3581 (i32 imm:$rc)), itins.rr, IsCommutable>,
3584 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3585 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3587 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3588 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3589 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3590 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3591 (i32 FROUND_NO_EXC))>, EVEX_B;
3594 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3596 SizeItins itins, bit IsCommutable> {
3597 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3598 itins.s, IsCommutable>,
3599 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3600 itins.s, IsCommutable>,
3601 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3602 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3603 itins.d, IsCommutable>,
3604 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3605 itins.d, IsCommutable>,
3606 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3609 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3611 SizeItins itins, bit IsCommutable> {
3612 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3613 itins.s, IsCommutable>,
3614 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3615 itins.s, IsCommutable>,
3616 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3617 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3618 itins.d, IsCommutable>,
3619 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3620 itins.d, IsCommutable>,
3621 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3623 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3624 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3625 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3626 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3627 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3628 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3630 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3631 X86VectorVTInfo _, bit IsCommutable> {
3632 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3633 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3634 "$src2, $src1", "$src1, $src2",
3635 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3636 let mayLoad = 1 in {
3637 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3638 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3639 "$src2, $src1", "$src1, $src2",
3640 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3641 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3642 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3643 "${src2}"##_.BroadcastStr##", $src1",
3644 "$src1, ${src2}"##_.BroadcastStr,
3645 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3646 (_.ScalarLdFrag addr:$src2))))>,
3651 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3652 X86VectorVTInfo _> {
3653 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3654 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3655 "$rc, $src2, $src1", "$src1, $src2, $rc",
3656 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3657 EVEX_4V, EVEX_B, EVEX_RC;
3661 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3662 X86VectorVTInfo _> {
3663 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3664 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3665 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3666 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3670 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3671 bit IsCommutable = 0> {
3672 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3673 IsCommutable>, EVEX_V512, PS,
3674 EVEX_CD8<32, CD8VF>;
3675 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3676 IsCommutable>, EVEX_V512, PD, VEX_W,
3677 EVEX_CD8<64, CD8VF>;
3679 // Define only if AVX512VL feature is present.
3680 let Predicates = [HasVLX] in {
3681 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3682 IsCommutable>, EVEX_V128, PS,
3683 EVEX_CD8<32, CD8VF>;
3684 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3685 IsCommutable>, EVEX_V256, PS,
3686 EVEX_CD8<32, CD8VF>;
3687 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3688 IsCommutable>, EVEX_V128, PD, VEX_W,
3689 EVEX_CD8<64, CD8VF>;
3690 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3691 IsCommutable>, EVEX_V256, PD, VEX_W,
3692 EVEX_CD8<64, CD8VF>;
3696 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3697 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3698 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3699 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3700 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3703 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3704 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
3705 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3706 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
3707 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3710 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3711 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3712 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3713 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3714 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3715 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3716 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3717 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3718 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3719 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3720 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3721 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3722 let Predicates = [HasDQI] in {
3723 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3724 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3725 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3726 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3729 multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3730 X86VectorVTInfo _> {
3731 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3732 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3733 "$src2, $src1", "$src1, $src2",
3734 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>, EVEX_4V;
3735 let mayLoad = 1 in {
3736 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3737 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3738 "$src2, $src1", "$src1, $src2",
3739 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>, EVEX_4V;
3740 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3741 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3742 "${src2}"##_.BroadcastStr##", $src1",
3743 "$src1, ${src2}"##_.BroadcastStr,
3744 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3745 (_.ScalarLdFrag addr:$src2))), (i32 FROUND_CURRENT))>,
3750 multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
3751 X86VectorVTInfo _> {
3752 defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3753 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3754 "$src2, $src1", "$src1, $src2",
3755 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>;
3756 let mayLoad = 1 in {
3757 defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3758 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3759 "$src2, $src1", "$src1, $src2",
3760 (OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>;
3764 multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode> {
3765 defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v16f32_info>,
3766 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
3767 EVEX_V512, EVEX_CD8<32, CD8VF>;
3768 defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f64_info>,
3769 avx512_fp_round_packed<opc, OpcodeStr, OpNode, v8f64_info>,
3770 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3771 defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f32x_info>,
3772 avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNode, SSE_ALU_ITINS_S.s>,
3773 EVEX_4V,EVEX_CD8<32, CD8VT1>;
3774 defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNode, f64x_info>,
3775 avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNode, SSE_ALU_ITINS_S.d>,
3776 EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
3778 // Define only if AVX512VL feature is present.
3779 let Predicates = [HasVLX] in {
3780 defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f32x_info>,
3781 EVEX_V128, EVEX_CD8<32, CD8VF>;
3782 defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f32x_info>,
3783 EVEX_V256, EVEX_CD8<32, CD8VF>;
3784 defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v2f64x_info>,
3785 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
3786 defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v4f64x_info>,
3787 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
3790 defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef>, T8PD;
3792 //===----------------------------------------------------------------------===//
3793 // AVX-512 VPTESTM instructions
3794 //===----------------------------------------------------------------------===//
3796 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3797 X86VectorVTInfo _> {
3798 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3799 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3800 "$src2, $src1", "$src1, $src2",
3801 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3804 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3805 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3806 "$src2, $src1", "$src1, $src2",
3807 (OpNode (_.VT _.RC:$src1),
3808 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3810 EVEX_CD8<_.EltSize, CD8VF>;
3813 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3814 X86VectorVTInfo _> {
3816 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3817 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3818 "${src2}"##_.BroadcastStr##", $src1",
3819 "$src1, ${src2}"##_.BroadcastStr,
3820 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3821 (_.ScalarLdFrag addr:$src2))))>,
3822 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3824 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3825 AVX512VLVectorVTInfo _> {
3826 let Predicates = [HasAVX512] in
3827 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3828 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3830 let Predicates = [HasAVX512, HasVLX] in {
3831 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3832 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3833 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3834 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3838 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3839 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3841 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3842 avx512vl_i64_info>, VEX_W;
3845 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3847 let Predicates = [HasBWI] in {
3848 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3850 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3853 let Predicates = [HasVLX, HasBWI] in {
3855 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3857 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3859 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3861 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3866 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3868 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3869 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3871 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3872 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3874 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3875 (v16i32 VR512:$src2), (i16 -1))),
3876 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3878 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3879 (v8i64 VR512:$src2), (i8 -1))),
3880 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3882 //===----------------------------------------------------------------------===//
3883 // AVX-512 Shift instructions
3884 //===----------------------------------------------------------------------===//
3885 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3886 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3887 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3888 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3889 "$src2, $src1", "$src1, $src2",
3890 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3891 SSE_INTSHIFT_ITINS_P.rr>;
3893 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3894 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3895 "$src2, $src1", "$src1, $src2",
3896 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3898 SSE_INTSHIFT_ITINS_P.rm>;
3901 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3902 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3904 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3905 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3906 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3907 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3908 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
3911 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3912 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3913 // src2 is always 128-bit
3914 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3915 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3916 "$src2, $src1", "$src1, $src2",
3917 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3918 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3919 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3920 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3921 "$src2, $src1", "$src1, $src2",
3922 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3923 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
3927 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3928 ValueType SrcVT, PatFrag bc_frag,
3929 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
3930 let Predicates = [prd] in
3931 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3932 VTInfo.info512>, EVEX_V512,
3933 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
3934 let Predicates = [prd, HasVLX] in {
3935 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3936 VTInfo.info256>, EVEX_V256,
3937 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
3938 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3939 VTInfo.info128>, EVEX_V128,
3940 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
3944 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
3945 string OpcodeStr, SDNode OpNode> {
3946 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3947 avx512vl_i32_info, HasAVX512>;
3948 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3949 avx512vl_i64_info, HasAVX512>, VEX_W;
3950 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
3951 avx512vl_i16_info, HasBWI>;
3954 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3955 string OpcodeStr, SDNode OpNode,
3956 AVX512VLVectorVTInfo VTInfo> {
3957 let Predicates = [HasAVX512] in
3958 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3960 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3961 VTInfo.info512>, EVEX_V512;
3962 let Predicates = [HasAVX512, HasVLX] in {
3963 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3965 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3966 VTInfo.info256>, EVEX_V256;
3967 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3969 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3970 VTInfo.info128>, EVEX_V128;
3974 multiclass avx512_shift_rmi_w<bits<8> opcw,
3975 Format ImmFormR, Format ImmFormM,
3976 string OpcodeStr, SDNode OpNode> {
3977 let Predicates = [HasBWI] in
3978 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3979 v32i16_info>, EVEX_V512;
3980 let Predicates = [HasVLX, HasBWI] in {
3981 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3982 v16i16x_info>, EVEX_V256;
3983 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3984 v8i16x_info>, EVEX_V128;
3988 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
3989 Format ImmFormR, Format ImmFormM,
3990 string OpcodeStr, SDNode OpNode> {
3991 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
3992 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
3993 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
3994 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
3997 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
3998 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
4000 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
4001 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
4003 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
4004 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
4006 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>, AVX512BIi8Base, EVEX_4V;
4007 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
4009 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
4010 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
4011 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
4013 //===-------------------------------------------------------------------===//
4014 // Variable Bit Shifts
4015 //===-------------------------------------------------------------------===//
4016 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
4017 X86VectorVTInfo _> {
4018 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4019 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4020 "$src2, $src1", "$src1, $src2",
4021 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
4022 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
4024 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4025 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4026 "$src2, $src1", "$src1, $src2",
4027 (_.VT (OpNode _.RC:$src1,
4028 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
4029 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
4030 EVEX_CD8<_.EltSize, CD8VF>;
4033 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
4034 X86VectorVTInfo _> {
4036 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4037 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4038 "${src2}"##_.BroadcastStr##", $src1",
4039 "$src1, ${src2}"##_.BroadcastStr,
4040 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4041 (_.ScalarLdFrag addr:$src2))))),
4042 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
4043 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4045 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4046 AVX512VLVectorVTInfo _> {
4047 let Predicates = [HasAVX512] in
4048 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4049 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4051 let Predicates = [HasAVX512, HasVLX] in {
4052 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4053 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4054 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
4055 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
4059 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
4061 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
4063 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
4064 avx512vl_i64_info>, VEX_W;
4067 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
4069 let Predicates = [HasBWI] in
4070 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
4072 let Predicates = [HasVLX, HasBWI] in {
4074 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
4076 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
4081 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
4082 avx512_var_shift_w<0x12, "vpsllvw", shl>;
4083 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
4084 avx512_var_shift_w<0x11, "vpsravw", sra>;
4085 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
4086 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
4087 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
4088 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
4090 //===-------------------------------------------------------------------===//
4091 // 1-src variable permutation VPERMW/D/Q
4092 //===-------------------------------------------------------------------===//
4093 multiclass avx512_vperm_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
4094 AVX512VLVectorVTInfo _> {
4095 let Predicates = [HasAVX512] in
4096 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
4097 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
4099 let Predicates = [HasAVX512, HasVLX] in
4100 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
4101 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
4104 multiclass avx512_vpermi_dq_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
4105 string OpcodeStr, SDNode OpNode,
4106 AVX512VLVectorVTInfo VTInfo> {
4107 let Predicates = [HasAVX512] in
4108 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4110 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4111 VTInfo.info512>, EVEX_V512;
4112 let Predicates = [HasAVX512, HasVLX] in
4113 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
4115 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
4116 VTInfo.info256>, EVEX_V256;
4120 defm VPERM : avx512_var_shift_w<0x8D, "vpermw", X86VPermv>;
4122 defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv,
4124 defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv,
4125 avx512vl_i64_info>, VEX_W;
4126 defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv,
4128 defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv,
4129 avx512vl_f64_info>, VEX_W;
4131 defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq",
4132 X86VPermi, avx512vl_i64_info>,
4133 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4134 defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
4135 X86VPermi, avx512vl_f64_info>,
4136 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
4137 //===----------------------------------------------------------------------===//
4138 // AVX-512 - VPERMIL
4139 //===----------------------------------------------------------------------===//
4141 multiclass avx512_permil_vec<bits<8> OpcVar, string OpcodeStr, SDNode OpNode,
4142 X86VectorVTInfo _, X86VectorVTInfo Ctrl> {
4143 defm rr: AVX512_maskable<OpcVar, MRMSrcReg, _, (outs _.RC:$dst),
4144 (ins _.RC:$src1, Ctrl.RC:$src2), OpcodeStr,
4145 "$src2, $src1", "$src1, $src2",
4146 (_.VT (OpNode _.RC:$src1,
4147 (Ctrl.VT Ctrl.RC:$src2)))>,
4149 let mayLoad = 1 in {
4150 defm rm: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4151 (ins _.RC:$src1, Ctrl.MemOp:$src2), OpcodeStr,
4152 "$src2, $src1", "$src1, $src2",
4155 (Ctrl.VT (bitconvert(Ctrl.LdFrag addr:$src2)))))>,
4156 T8PD, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
4157 defm rmb: AVX512_maskable<OpcVar, MRMSrcMem, _, (outs _.RC:$dst),
4158 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
4159 "${src2}"##_.BroadcastStr##", $src1",
4160 "$src1, ${src2}"##_.BroadcastStr,
4163 (Ctrl.VT (X86VBroadcast
4164 (Ctrl.ScalarLdFrag addr:$src2)))))>,
4165 T8PD, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
4169 multiclass avx512_permil_vec_common<string OpcodeStr, bits<8> OpcVar,
4170 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4171 let Predicates = [HasAVX512] in {
4172 defm Z : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info512,
4173 Ctrl.info512>, EVEX_V512;
4175 let Predicates = [HasAVX512, HasVLX] in {
4176 defm Z128 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info128,
4177 Ctrl.info128>, EVEX_V128;
4178 defm Z256 : avx512_permil_vec<OpcVar, OpcodeStr, X86VPermilpv, _.info256,
4179 Ctrl.info256>, EVEX_V256;
4183 multiclass avx512_permil<string OpcodeStr, bits<8> OpcImm, bits<8> OpcVar,
4184 AVX512VLVectorVTInfo _, AVX512VLVectorVTInfo Ctrl>{
4186 defm NAME: avx512_permil_vec_common<OpcodeStr, OpcVar, _, Ctrl>;
4187 defm NAME: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem, OpcodeStr,
4189 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4191 let isCodeGenOnly = 1 in {
4192 // lowering implementation with the alternative types
4193 defm NAME#_I: avx512_permil_vec_common<OpcodeStr, OpcVar, Ctrl, Ctrl>;
4194 defm NAME#_I: avx512_shift_rmi_sizes<OpcImm, MRMSrcReg, MRMSrcMem,
4195 OpcodeStr, X86VPermilpi, Ctrl>,
4196 EVEX, AVX512AIi8Base, EVEX_CD8<_.info128.EltSize, CD8VF>;
4200 defm VPERMILPS : avx512_permil<"vpermilps", 0x04, 0x0C, avx512vl_f32_info,
4202 defm VPERMILPD : avx512_permil<"vpermilpd", 0x05, 0x0D, avx512vl_f64_info,
4203 avx512vl_i64_info>, VEX_W;
4204 //===----------------------------------------------------------------------===//
4205 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
4206 //===----------------------------------------------------------------------===//
4208 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
4209 X86PShufd, avx512vl_i32_info>,
4210 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
4211 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
4212 X86PShufhw>, EVEX, AVX512XSIi8Base;
4213 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
4214 X86PShuflw>, EVEX, AVX512XDIi8Base;
4216 multiclass avx512_pshufb_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4217 let Predicates = [HasBWI] in
4218 defm Z: avx512_var_shift<opc, OpcodeStr, OpNode, v64i8_info>, EVEX_V512;
4220 let Predicates = [HasVLX, HasBWI] in {
4221 defm Z256: avx512_var_shift<opc, OpcodeStr, OpNode, v32i8x_info>, EVEX_V256;
4222 defm Z128: avx512_var_shift<opc, OpcodeStr, OpNode, v16i8x_info>, EVEX_V128;
4226 defm VPSHUFB: avx512_pshufb_sizes<0x00, "vpshufb", X86pshufb>;
4228 //===----------------------------------------------------------------------===//
4229 // Move Low to High and High to Low packed FP Instructions
4230 //===----------------------------------------------------------------------===//
4231 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
4232 (ins VR128X:$src1, VR128X:$src2),
4233 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4234 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
4235 IIC_SSE_MOV_LH>, EVEX_4V;
4236 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
4237 (ins VR128X:$src1, VR128X:$src2),
4238 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4239 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
4240 IIC_SSE_MOV_LH>, EVEX_4V;
4242 let Predicates = [HasAVX512] in {
4244 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4245 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
4246 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
4247 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
4250 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
4251 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
4254 //===----------------------------------------------------------------------===//
4255 // VMOVHPS/PD VMOVLPS Instructions
4256 // All patterns was taken from SSS implementation.
4257 //===----------------------------------------------------------------------===//
4258 multiclass avx512_mov_hilo_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
4259 X86VectorVTInfo _> {
4261 def rm : AVX512<opc, MRMSrcMem, (outs _.RC:$dst),
4262 (ins _.RC:$src1, f64mem:$src2),
4263 !strconcat(OpcodeStr,
4264 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4268 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))))))],
4269 IIC_SSE_MOV_LH>, EVEX_4V;
4272 defm VMOVHPSZ128 : avx512_mov_hilo_packed<0x16, "vmovhps", X86Movlhps,
4273 v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS;
4274 defm VMOVHPDZ128 : avx512_mov_hilo_packed<0x16, "vmovhpd", X86Movlhpd,
4275 v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W;
4276 defm VMOVLPSZ128 : avx512_mov_hilo_packed<0x12, "vmovlps", X86Movlps,
4277 v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS;
4278 defm VMOVLPDZ128 : avx512_mov_hilo_packed<0x12, "vmovlpd", X86Movlpd,
4279 v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W;
4281 let Predicates = [HasAVX512] in {
4283 def : Pat<(X86Movlhps VR128X:$src1,
4284 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
4285 (VMOVHPSZ128rm VR128X:$src1, addr:$src2)>;
4286 def : Pat<(X86Movlhps VR128X:$src1,
4287 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
4288 (VMOVHPSZ128rm VR128X:$src1, addr:$src2)>;
4290 def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
4291 (scalar_to_vector (loadf64 addr:$src2)))),
4292 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
4293 def : Pat<(v2f64 (X86Unpckl VR128X:$src1,
4294 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
4295 (VMOVHPDZ128rm VR128X:$src1, addr:$src2)>;
4297 def : Pat<(v4f32 (X86Movlps VR128X:$src1, (load addr:$src2))),
4298 (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
4299 def : Pat<(v4i32 (X86Movlps VR128X:$src1, (load addr:$src2))),
4300 (VMOVLPSZ128rm VR128X:$src1, addr:$src2)>;
4302 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, (load addr:$src2))),
4303 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4304 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, (load addr:$src2))),
4305 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4306 def : Pat<(v2f64 (X86Movsd VR128X:$src1,
4307 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
4308 (VMOVLPDZ128rm VR128X:$src1, addr:$src2)>;
4311 let mayStore = 1 in {
4312 def VMOVHPSZ128mr : AVX512PSI<0x17, MRMDestMem, (outs),
4313 (ins f64mem:$dst, VR128X:$src),
4314 "vmovhps\t{$src, $dst|$dst, $src}",
4315 [(store (f64 (vector_extract
4316 (X86Unpckh (bc_v2f64 (v4f32 VR128X:$src)),
4317 (bc_v2f64 (v4f32 VR128X:$src))),
4318 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>,
4319 EVEX, EVEX_CD8<32, CD8VT2>;
4320 def VMOVHPDZ128mr : AVX512PDI<0x17, MRMDestMem, (outs),
4321 (ins f64mem:$dst, VR128X:$src),
4322 "vmovhpd\t{$src, $dst|$dst, $src}",
4323 [(store (f64 (vector_extract
4324 (v2f64 (X86Unpckh VR128X:$src, VR128X:$src)),
4325 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>,
4326 EVEX, EVEX_CD8<64, CD8VT1>, VEX_W;
4327 def VMOVLPSZ128mr : AVX512PSI<0x13, MRMDestMem, (outs),
4328 (ins f64mem:$dst, VR128X:$src),
4329 "vmovlps\t{$src, $dst|$dst, $src}",
4330 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128X:$src)),
4331 (iPTR 0))), addr:$dst)],
4333 EVEX, EVEX_CD8<32, CD8VT2>;
4334 def VMOVLPDZ128mr : AVX512PDI<0x13, MRMDestMem, (outs),
4335 (ins f64mem:$dst, VR128X:$src),
4336 "vmovlpd\t{$src, $dst|$dst, $src}",
4337 [(store (f64 (vector_extract (v2f64 VR128X:$src),
4338 (iPTR 0))), addr:$dst)],
4340 EVEX, EVEX_CD8<64, CD8VT1>, VEX_W;
4342 let Predicates = [HasAVX512] in {
4344 def : Pat<(store (f64 (vector_extract
4345 (v2f64 (X86VPermilpi VR128X:$src, (i8 1))),
4346 (iPTR 0))), addr:$dst),
4347 (VMOVHPDZ128mr addr:$dst, VR128X:$src)>;
4349 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128X:$src2)),
4351 (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
4352 def : Pat<(store (v4i32 (X86Movlps
4353 (bc_v4i32 (loadv2i64 addr:$src1)), VR128X:$src2)), addr:$src1),
4354 (VMOVLPSZ128mr addr:$src1, VR128X:$src2)>;
4356 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128X:$src2)),
4358 (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
4359 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128X:$src2)),
4361 (VMOVLPDZ128mr addr:$src1, VR128X:$src2)>;
4363 //===----------------------------------------------------------------------===//
4364 // FMA - Fused Multiply Operations
4367 let Constraints = "$src1 = $dst" in {
4368 multiclass avx512_fma3p_213_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4369 X86VectorVTInfo _> {
4370 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4371 (ins _.RC:$src2, _.RC:$src3),
4372 OpcodeStr, "$src3, $src2", "$src2, $src3",
4373 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4376 let mayLoad = 1 in {
4377 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4378 (ins _.RC:$src2, _.MemOp:$src3),
4379 OpcodeStr, "$src3, $src2", "$src2, $src3",
4380 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
4383 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4384 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4385 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
4386 !strconcat("$src2, ${src3}", _.BroadcastStr ),
4388 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
4389 AVX512FMA3Base, EVEX_B;
4393 multiclass avx512_fma3_213_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4394 X86VectorVTInfo _> {
4395 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4396 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4397 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4398 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4399 AVX512FMA3Base, EVEX_B, EVEX_RC;
4401 } // Constraints = "$src1 = $dst"
4403 multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4404 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4405 let Predicates = [HasAVX512] in {
4406 defm Z : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info512>,
4407 avx512_fma3_213_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4408 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4410 let Predicates = [HasVLX, HasAVX512] in {
4411 defm Z256 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info256>,
4412 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4413 defm Z128 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info128>,
4414 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4418 multiclass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4419 SDNode OpNodeRnd > {
4420 defm PS : avx512_fma3p_213_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4422 defm PD : avx512_fma3p_213_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4423 avx512vl_f64_info>, VEX_W;
4426 defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", X86Fmadd, X86FmaddRnd>;
4427 defm VFMSUB213 : avx512_fma3p_213_f<0xAA, "vfmsub213", X86Fmsub, X86FmsubRnd>;
4428 defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub, X86FmaddsubRnd>;
4429 defm VFMSUBADD213 : avx512_fma3p_213_f<0xA7, "vfmsubadd213", X86Fmsubadd, X86FmsubaddRnd>;
4430 defm VFNMADD213 : avx512_fma3p_213_f<0xAC, "vfnmadd213", X86Fnmadd, X86FnmaddRnd>;
4431 defm VFNMSUB213 : avx512_fma3p_213_f<0xAE, "vfnmsub213", X86Fnmsub, X86FnmsubRnd>;
4434 let Constraints = "$src1 = $dst" in {
4435 multiclass avx512_fma3p_231_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4436 X86VectorVTInfo _> {
4437 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4438 (ins _.RC:$src2, _.RC:$src3),
4439 OpcodeStr, "$src3, $src2", "$src2, $src3",
4440 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1))>,
4443 let mayLoad = 1 in {
4444 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4445 (ins _.RC:$src2, _.MemOp:$src3),
4446 OpcodeStr, "$src3, $src2", "$src2, $src3",
4447 (_.VT (OpNode _.RC:$src2, (_.LdFrag addr:$src3), _.RC:$src1))>,
4450 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4451 (ins _.RC:$src2, _.ScalarMemOp:$src3),
4452 OpcodeStr, "${src3}"##_.BroadcastStr##", $src2",
4453 "$src2, ${src3}"##_.BroadcastStr,
4454 (_.VT (OpNode _.RC:$src2,
4455 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
4456 _.RC:$src1))>, AVX512FMA3Base, EVEX_B;
4460 multiclass avx512_fma3_231_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4461 X86VectorVTInfo _> {
4462 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4463 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4464 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
4465 (_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc)))>,
4466 AVX512FMA3Base, EVEX_B, EVEX_RC;
4468 } // Constraints = "$src1 = $dst"
4470 multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4471 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4472 let Predicates = [HasAVX512] in {
4473 defm Z : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info512>,
4474 avx512_fma3_231_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4475 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4477 let Predicates = [HasVLX, HasAVX512] in {
4478 defm Z256 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info256>,
4479 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4480 defm Z128 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info128>,
4481 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4485 multiclass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4486 SDNode OpNodeRnd > {
4487 defm PS : avx512_fma3p_231_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4489 defm PD : avx512_fma3p_231_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4490 avx512vl_f64_info>, VEX_W;
4493 defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86Fmadd, X86FmaddRnd>;
4494 defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86Fmsub, X86FmsubRnd>;
4495 defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub, X86FmaddsubRnd>;
4496 defm VFMSUBADD231 : avx512_fma3p_231_f<0xB7, "vfmsubadd231", X86Fmsubadd, X86FmsubaddRnd>;
4497 defm VFNMADD231 : avx512_fma3p_231_f<0xBC, "vfnmadd231", X86Fnmadd, X86FnmaddRnd>;
4498 defm VFNMSUB231 : avx512_fma3p_231_f<0xBE, "vfnmsub231", X86Fnmsub, X86FnmsubRnd>;
4500 let Constraints = "$src1 = $dst" in {
4501 multiclass avx512_fma3p_132_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4502 X86VectorVTInfo _> {
4503 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4504 (ins _.RC:$src3, _.RC:$src2),
4505 OpcodeStr, "$src2, $src3", "$src3, $src2",
4506 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
4509 let mayLoad = 1 in {
4510 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4511 (ins _.RC:$src3, _.MemOp:$src2),
4512 OpcodeStr, "$src2, $src3", "$src3, $src2",
4513 (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2), _.RC:$src3))>,
4516 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
4517 (ins _.RC:$src3, _.ScalarMemOp:$src2),
4518 OpcodeStr, "${src2}"##_.BroadcastStr##", $src3",
4519 "$src3, ${src2}"##_.BroadcastStr,
4520 (_.VT (OpNode _.RC:$src1,
4521 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
4522 _.RC:$src3))>, AVX512FMA3Base, EVEX_B;
4526 multiclass avx512_fma3_132_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
4527 X86VectorVTInfo _> {
4528 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
4529 (ins _.RC:$src3, _.RC:$src2, AVX512RC:$rc),
4530 OpcodeStr, "$rc, $src2, $src3", "$src3, $src2, $rc",
4531 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
4532 AVX512FMA3Base, EVEX_B, EVEX_RC;
4534 } // Constraints = "$src1 = $dst"
4536 multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
4537 SDNode OpNodeRnd, AVX512VLVectorVTInfo _> {
4538 let Predicates = [HasAVX512] in {
4539 defm Z : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info512>,
4540 avx512_fma3_132_round<opc, OpcodeStr, OpNodeRnd, _.info512>,
4541 EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
4543 let Predicates = [HasVLX, HasAVX512] in {
4544 defm Z256 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info256>,
4545 EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
4546 defm Z128 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info128>,
4547 EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
4551 multiclass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
4552 SDNode OpNodeRnd > {
4553 defm PS : avx512_fma3p_132_common<opc, OpcodeStr#"ps", OpNode, OpNodeRnd,
4555 defm PD : avx512_fma3p_132_common<opc, OpcodeStr#"pd", OpNode, OpNodeRnd,
4556 avx512vl_f64_info>, VEX_W;
4559 defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86Fmadd, X86FmaddRnd>;
4560 defm VFMSUB132 : avx512_fma3p_132_f<0x9A, "vfmsub132", X86Fmsub, X86FmsubRnd>;
4561 defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub, X86FmaddsubRnd>;
4562 defm VFMSUBADD132 : avx512_fma3p_132_f<0x97, "vfmsubadd132", X86Fmsubadd, X86FmsubaddRnd>;
4563 defm VFNMADD132 : avx512_fma3p_132_f<0x9C, "vfnmadd132", X86Fnmadd, X86FnmaddRnd>;
4564 defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubRnd>;
4567 let Constraints = "$src1 = $dst" in {
4568 multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4569 dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
4570 dag RHS_r, dag RHS_m > {
4571 defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4572 (ins _.RC:$src2, _.RC:$src3), OpcodeStr,
4573 "$src3, $src2", "$src2, $src3", RHS_VEC_r>, AVX512FMA3Base;
4576 defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4577 (ins _.RC:$src2, _.MemOp:$src3), OpcodeStr,
4578 "$src3, $src2", "$src2, $src3", RHS_VEC_m>, AVX512FMA3Base;
4580 defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4581 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
4582 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb>,
4583 AVX512FMA3Base, EVEX_B, EVEX_RC;
4585 let isCodeGenOnly = 1 in {
4586 def r : AVX512FMA3<opc, MRMSrcReg, (outs _.FRC:$dst),
4587 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
4588 !strconcat(OpcodeStr,
4589 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4592 def m : AVX512FMA3<opc, MRMSrcMem, (outs _.FRC:$dst),
4593 (ins _.FRC:$src1, _.FRC:$src2, _.ScalarMemOp:$src3),
4594 !strconcat(OpcodeStr,
4595 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4597 }// isCodeGenOnly = 1
4599 }// Constraints = "$src1 = $dst"
4601 multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4602 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd, X86VectorVTInfo _ ,
4605 defm NAME#213#SUFF: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix , _ ,
4606 (_.VT (OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3)),
4607 (_.VT (OpNode _.RC:$src2, _.RC:$src1,
4608 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))))),
4609 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src1, _.RC:$src3,
4611 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4613 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
4614 (_.ScalarLdFrag addr:$src3))))>;
4616 defm NAME#231#SUFF: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix , _ ,
4617 (_.VT (OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1)),
4618 (_.VT (OpNode _.RC:$src2,
4619 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4621 (_.VT ( OpNodeRnd _.RC:$src2, _.RC:$src3, _.RC:$src1,
4623 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
4625 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
4626 (_.ScalarLdFrag addr:$src3), _.FRC:$src1)))>;
4628 defm NAME#132#SUFF: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix , _ ,
4629 (_.VT (OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2)),
4630 (_.VT (OpNode _.RC:$src1,
4631 (_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
4633 (_.VT ( OpNodeRnd _.RC:$src1, _.RC:$src3, _.RC:$src2,
4635 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
4637 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1,
4638 (_.ScalarLdFrag addr:$src3), _.FRC:$src2)))>;
4641 multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
4642 string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd>{
4643 let Predicates = [HasAVX512] in {
4644 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4645 OpNodeRnd, f32x_info, "SS">,
4646 EVEX_CD8<32, CD8VT1>, VEX_LIG;
4647 defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
4648 OpNodeRnd, f64x_info, "SD">,
4649 EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
4653 defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>;
4654 defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>;
4655 defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4656 defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4658 //===----------------------------------------------------------------------===//
4659 // AVX-512 Scalar convert from sign integer to float/double
4660 //===----------------------------------------------------------------------===//
4662 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4663 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4664 PatFrag ld_frag, string asm> {
4665 let hasSideEffects = 0 in {
4666 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
4667 (ins DstVT.FRC:$src1, SrcRC:$src),
4668 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4671 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
4672 (ins DstVT.FRC:$src1, x86memop:$src),
4673 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4675 } // hasSideEffects = 0
4676 let isCodeGenOnly = 1 in {
4677 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4678 (ins DstVT.RC:$src1, SrcRC:$src2),
4679 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4680 [(set DstVT.RC:$dst,
4681 (OpNode (DstVT.VT DstVT.RC:$src1),
4683 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4685 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
4686 (ins DstVT.RC:$src1, x86memop:$src2),
4687 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4688 [(set DstVT.RC:$dst,
4689 (OpNode (DstVT.VT DstVT.RC:$src1),
4690 (ld_frag addr:$src2),
4691 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4692 }//isCodeGenOnly = 1
4695 multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4696 X86VectorVTInfo DstVT, string asm> {
4697 def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4698 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
4700 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
4701 [(set DstVT.RC:$dst,
4702 (OpNode (DstVT.VT DstVT.RC:$src1),
4704 (i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
4707 multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4708 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4709 PatFrag ld_frag, string asm> {
4710 defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
4711 avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
4715 let Predicates = [HasAVX512] in {
4716 defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4717 v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
4718 XS, EVEX_CD8<32, CD8VT1>;
4719 defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4720 v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
4721 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4722 defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4723 v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
4724 XD, EVEX_CD8<32, CD8VT1>;
4725 defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4726 v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
4727 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4729 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4730 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4731 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4732 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4733 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4734 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4735 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4736 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4738 def : Pat<(f32 (sint_to_fp GR32:$src)),
4739 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4740 def : Pat<(f32 (sint_to_fp GR64:$src)),
4741 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4742 def : Pat<(f64 (sint_to_fp GR32:$src)),
4743 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4744 def : Pat<(f64 (sint_to_fp GR64:$src)),
4745 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4747 defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR32,
4748 v4f32x_info, i32mem, loadi32,
4749 "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
4750 defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4751 v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
4752 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4753 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86UintToFpRnd, GR32, v2f64x_info,
4754 i32mem, loadi32, "cvtusi2sd{l}">,
4755 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4756 defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFpRnd, GR64,
4757 v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
4758 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4760 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4761 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4762 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4763 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4764 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4765 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4766 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4767 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4769 def : Pat<(f32 (uint_to_fp GR32:$src)),
4770 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4771 def : Pat<(f32 (uint_to_fp GR64:$src)),
4772 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4773 def : Pat<(f64 (uint_to_fp GR32:$src)),
4774 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4775 def : Pat<(f64 (uint_to_fp GR64:$src)),
4776 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4779 //===----------------------------------------------------------------------===//
4780 // AVX-512 Scalar convert from float/double to integer
4781 //===----------------------------------------------------------------------===//
4782 multiclass avx512_cvt_s_int_round<bits<8> opc, RegisterClass SrcRC,
4783 RegisterClass DstRC, Intrinsic Int,
4784 Operand memop, ComplexPattern mem_cpat, string asm> {
4785 let hasSideEffects = 0, Predicates = [HasAVX512] in {
4786 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4787 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4788 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
4789 def rb : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4790 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"), []>,
4791 EVEX, VEX_LIG, EVEX_B, EVEX_RC;
4793 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4794 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
4795 } // hasSideEffects = 0, Predicates = [HasAVX512]
4798 // Convert float/double to signed/unsigned int 32/64
4799 defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4800 ssmem, sse_load_f32, "cvtss2si">,
4801 XS, EVEX_CD8<32, CD8VT1>;
4802 defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4803 int_x86_sse_cvtss2si64,
4804 ssmem, sse_load_f32, "cvtss2si">,
4805 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4806 defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4807 int_x86_avx512_cvtss2usi,
4808 ssmem, sse_load_f32, "cvtss2usi">,
4809 XS, EVEX_CD8<32, CD8VT1>;
4810 defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4811 int_x86_avx512_cvtss2usi64, ssmem,
4812 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4813 EVEX_CD8<32, CD8VT1>;
4814 defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4815 sdmem, sse_load_f64, "cvtsd2si">,
4816 XD, EVEX_CD8<64, CD8VT1>;
4817 defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, VR128X, GR64,
4818 int_x86_sse2_cvtsd2si64,
4819 sdmem, sse_load_f64, "cvtsd2si">,
4820 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4821 defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, VR128X, GR32,
4822 int_x86_avx512_cvtsd2usi,
4823 sdmem, sse_load_f64, "cvtsd2usi">,
4824 XD, EVEX_CD8<64, CD8VT1>;
4825 defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, VR128X, GR64,
4826 int_x86_avx512_cvtsd2usi64, sdmem,
4827 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4828 EVEX_CD8<64, CD8VT1>;
4830 let isCodeGenOnly = 1 , Predicates = [HasAVX512] in {
4831 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4832 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4833 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4834 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4835 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4836 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4837 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4838 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4839 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4840 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4841 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4842 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4844 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4845 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4846 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4847 } // isCodeGenOnly = 1, Predicates = [HasAVX512]
4849 // Convert float/double to signed/unsigned int 32/64 with truncation
4850 multiclass avx512_cvt_s_all<bits<8> opc, string asm, X86VectorVTInfo _SrcRC,
4851 X86VectorVTInfo _DstRC, SDNode OpNode,
4853 let Predicates = [HasAVX512] in {
4854 def rr : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4855 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4856 [(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))]>, EVEX;
4857 def rb : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
4858 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4860 def rm : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.MemOp:$src),
4861 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4862 [(set _DstRC.RC:$dst, (OpNode (_SrcRC.ScalarLdFrag addr:$src)))]>,
4865 let isCodeGenOnly = 1,hasSideEffects = 0 in {
4866 def rr_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4867 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4868 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4869 (i32 FROUND_CURRENT)))]>, EVEX, VEX_LIG;
4870 def rb_Int : SI<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
4871 !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
4872 [(set _DstRC.RC:$dst, (OpNodeRnd _SrcRC.RC:$src,
4873 (i32 FROUND_NO_EXC)))]>,
4874 EVEX,VEX_LIG , EVEX_B;
4876 def rm_Int : SI<opc, MRMSrcMem, (outs _DstRC.RC:$dst),
4877 (ins _SrcRC.MemOp:$src),
4878 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4881 } // isCodeGenOnly = 1, hasSideEffects = 0
4886 defm VCVTTSS2SIZ: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i32x_info,
4887 fp_to_sint,X86cvttss2IntRnd>,
4888 XS, EVEX_CD8<32, CD8VT1>;
4889 defm VCVTTSS2SI64Z: avx512_cvt_s_all<0x2C, "cvttss2si", f32x_info, i64x_info,
4890 fp_to_sint,X86cvttss2IntRnd>,
4891 VEX_W, XS, EVEX_CD8<32, CD8VT1>;
4892 defm VCVTTSD2SIZ: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i32x_info,
4893 fp_to_sint,X86cvttsd2IntRnd>,
4894 XD, EVEX_CD8<64, CD8VT1>;
4895 defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "cvttsd2si", f64x_info, i64x_info,
4896 fp_to_sint,X86cvttsd2IntRnd>,
4897 VEX_W, XD, EVEX_CD8<64, CD8VT1>;
4899 defm VCVTTSS2USIZ: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i32x_info,
4900 fp_to_uint,X86cvttss2UIntRnd>,
4901 XS, EVEX_CD8<32, CD8VT1>;
4902 defm VCVTTSS2USI64Z: avx512_cvt_s_all<0x78, "cvttss2usi", f32x_info, i64x_info,
4903 fp_to_uint,X86cvttss2UIntRnd>,
4904 XS,VEX_W, EVEX_CD8<32, CD8VT1>;
4905 defm VCVTTSD2USIZ: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i32x_info,
4906 fp_to_uint,X86cvttsd2UIntRnd>,
4907 XD, EVEX_CD8<64, CD8VT1>;
4908 defm VCVTTSD2USI64Z: avx512_cvt_s_all<0x78, "cvttsd2usi", f64x_info, i64x_info,
4909 fp_to_uint,X86cvttsd2UIntRnd>,
4910 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4911 let Predicates = [HasAVX512] in {
4912 def : Pat<(i32 (int_x86_sse_cvttss2si (v4f32 VR128X:$src))),
4913 (VCVTTSS2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
4914 def : Pat<(i64 (int_x86_sse_cvttss2si64 (v4f32 VR128X:$src))),
4915 (VCVTTSS2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
4916 def : Pat<(i32 (int_x86_sse2_cvttsd2si (v2f64 VR128X:$src))),
4917 (VCVTTSD2SIZrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
4918 def : Pat<(i64 (int_x86_sse2_cvttsd2si64 (v2f64 VR128X:$src))),
4919 (VCVTTSD2SI64Zrr_Int (COPY_TO_REGCLASS VR128X:$src, FR64X))>;
4922 //===----------------------------------------------------------------------===//
4923 // AVX-512 Convert form float to double and back
4924 //===----------------------------------------------------------------------===//
4925 multiclass avx512_cvt_fp_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4926 X86VectorVTInfo _Src, SDNode OpNode> {
4927 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4928 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
4929 "$src2, $src1", "$src1, $src2",
4930 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
4931 (_Src.VT _Src.RC:$src2)))>,
4932 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
4933 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4934 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
4935 "$src2, $src1", "$src1, $src2",
4936 (_.VT (OpNode (_Src.VT _Src.RC:$src1),
4937 (_Src.VT (scalar_to_vector
4938 (_Src.ScalarLdFrag addr:$src2)))))>,
4939 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>;
4942 // Scalar Coversion with SAE - suppress all exceptions
4943 multiclass avx512_cvt_fp_sae_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4944 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4945 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4946 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
4947 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
4948 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
4949 (_Src.VT _Src.RC:$src2),
4950 (i32 FROUND_NO_EXC)))>,
4951 EVEX_4V, VEX_LIG, EVEX_B;
4954 // Scalar Conversion with rounding control (RC)
4955 multiclass avx512_cvt_fp_rc_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4956 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
4957 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4958 (ins _Src.RC:$src1, _Src.RC:$src2, AVX512RC:$rc), OpcodeStr,
4959 "$rc, $src2, $src1", "$src1, $src2, $rc",
4960 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src1),
4961 (_Src.VT _Src.RC:$src2), (i32 imm:$rc)))>,
4962 EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
4965 multiclass avx512_cvt_fp_scalar_sd2ss<bits<8> opc, string OpcodeStr, SDNode OpNode,
4966 SDNode OpNodeRnd, X86VectorVTInfo _src,
4967 X86VectorVTInfo _dst> {
4968 let Predicates = [HasAVX512] in {
4969 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
4970 avx512_cvt_fp_rc_scalar<opc, OpcodeStr, _dst, _src,
4971 OpNodeRnd>, VEX_W, EVEX_CD8<64, CD8VT1>,
4976 multiclass avx512_cvt_fp_scalar_ss2sd<bits<8> opc, string OpcodeStr, SDNode OpNode,
4977 SDNode OpNodeRnd, X86VectorVTInfo _src,
4978 X86VectorVTInfo _dst> {
4979 let Predicates = [HasAVX512] in {
4980 defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNode>,
4981 avx512_cvt_fp_sae_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>,
4982 EVEX_CD8<32, CD8VT1>, XS, EVEX_V512;
4985 defm VCVTSD2SS : avx512_cvt_fp_scalar_sd2ss<0x5A, "vcvtsd2ss", X86fround,
4986 X86froundRnd, f64x_info, f32x_info>;
4987 defm VCVTSS2SD : avx512_cvt_fp_scalar_ss2sd<0x5A, "vcvtss2sd", X86fpext,
4988 X86fpextRnd,f32x_info, f64x_info >;
4990 def : Pat<(f64 (fextend FR32X:$src)),
4991 (COPY_TO_REGCLASS (VCVTSS2SDZrr (COPY_TO_REGCLASS FR32X:$src, VR128X),
4992 (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>,
4993 Requires<[HasAVX512]>;
4994 def : Pat<(f64 (fextend (loadf32 addr:$src))),
4995 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
4996 Requires<[HasAVX512]>;
4998 def : Pat<(f64 (extloadf32 addr:$src)),
4999 (COPY_TO_REGCLASS (VCVTSS2SDZrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5000 Requires<[HasAVX512, OptForSize]>;
5002 def : Pat<(f64 (extloadf32 addr:$src)),
5003 (COPY_TO_REGCLASS (VCVTSS2SDZrr (v4f32 (IMPLICIT_DEF)),
5004 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)), VR128X)>,
5005 Requires<[HasAVX512, OptForSpeed]>;
5007 def : Pat<(f32 (fround FR64X:$src)),
5008 (COPY_TO_REGCLASS (VCVTSD2SSZrr (COPY_TO_REGCLASS FR64X:$src, VR128X),
5009 (COPY_TO_REGCLASS FR64X:$src, VR128X)), VR128X)>,
5010 Requires<[HasAVX512]>;
5011 //===----------------------------------------------------------------------===//
5012 // AVX-512 Vector convert from signed/unsigned integer to float/double
5013 // and from float/double to signed/unsigned integer
5014 //===----------------------------------------------------------------------===//
5016 multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5017 X86VectorVTInfo _Src, SDNode OpNode,
5018 string Broadcast = _.BroadcastStr,
5019 string Alias = ""> {
5021 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5022 (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
5023 (_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
5025 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5026 (ins _Src.MemOp:$src), OpcodeStr#Alias, "$src", "$src",
5027 (_.VT (OpNode (_Src.VT
5028 (bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
5030 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5031 (ins _Src.MemOp:$src), OpcodeStr,
5032 "${src}"##Broadcast, "${src}"##Broadcast,
5033 (_.VT (OpNode (_Src.VT
5034 (X86VBroadcast (_Src.ScalarLdFrag addr:$src)))
5037 // Coversion with SAE - suppress all exceptions
5038 multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5039 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5040 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5041 (ins _Src.RC:$src), OpcodeStr,
5042 "{sae}, $src", "$src, {sae}",
5043 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src),
5044 (i32 FROUND_NO_EXC)))>,
5048 // Conversion with rounding control (RC)
5049 multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5050 X86VectorVTInfo _Src, SDNode OpNodeRnd> {
5051 defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5052 (ins _Src.RC:$src, AVX512RC:$rc), OpcodeStr,
5053 "$rc, $src", "$src, $rc",
5054 (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc)))>,
5055 EVEX, EVEX_B, EVEX_RC;
5058 // Extend Float to Double
5059 multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
5060 let Predicates = [HasAVX512] in {
5061 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fextend>,
5062 avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
5063 X86vfpextRnd>, EVEX_V512;
5065 let Predicates = [HasVLX] in {
5066 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
5067 X86vfpext, "{1to2}">, EVEX_V128;
5068 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fextend>,
5073 // Truncate Double to Float
5074 multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
5075 let Predicates = [HasAVX512] in {
5076 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fround>,
5077 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
5078 X86vfproundRnd>, EVEX_V512;
5080 let Predicates = [HasVLX] in {
5081 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
5082 X86vfpround, "{1to2}", "{x}">, EVEX_V128;
5083 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fround,
5084 "{1to4}", "{y}">, EVEX_V256;
5088 defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps">,
5089 VEX_W, PD, EVEX_CD8<64, CD8VF>;
5090 defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd">,
5091 PS, EVEX_CD8<32, CD8VH>;
5093 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5094 (VCVTPS2PDZrm addr:$src)>;
5096 let Predicates = [HasVLX] in {
5097 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
5098 (VCVTPS2PDZ256rm addr:$src)>;
5101 // Convert Signed/Unsigned Doubleword to Double
5102 multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
5104 // No rounding in this op
5105 let Predicates = [HasAVX512] in
5106 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode>,
5109 let Predicates = [HasVLX] in {
5110 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
5111 OpNode128, "{1to2}">, EVEX_V128;
5112 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
5117 // Convert Signed/Unsigned Doubleword to Float
5118 multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
5120 let Predicates = [HasAVX512] in
5121 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode>,
5122 avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
5123 OpNodeRnd>, EVEX_V512;
5125 let Predicates = [HasVLX] in {
5126 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode>,
5128 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode>,
5133 // Convert Float to Signed/Unsigned Doubleword with truncation
5134 multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr,
5135 SDNode OpNode, SDNode OpNodeRnd> {
5136 let Predicates = [HasAVX512] in {
5137 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5138 avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
5139 OpNodeRnd>, EVEX_V512;
5141 let Predicates = [HasVLX] in {
5142 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5144 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5149 // Convert Float to Signed/Unsigned Doubleword
5150 multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr,
5151 SDNode OpNode, SDNode OpNodeRnd> {
5152 let Predicates = [HasAVX512] in {
5153 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
5154 avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
5155 OpNodeRnd>, EVEX_V512;
5157 let Predicates = [HasVLX] in {
5158 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
5160 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
5165 // Convert Double to Signed/Unsigned Doubleword with truncation
5166 multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr,
5167 SDNode OpNode, SDNode OpNodeRnd> {
5168 let Predicates = [HasAVX512] in {
5169 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5170 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
5171 OpNodeRnd>, EVEX_V512;
5173 let Predicates = [HasVLX] in {
5174 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5175 // memory forms of these instructions in Asm Parcer. They have the same
5176 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5177 // due to the same reason.
5178 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5179 "{1to2}", "{x}">, EVEX_V128;
5180 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5181 "{1to4}", "{y}">, EVEX_V256;
5185 // Convert Double to Signed/Unsigned Doubleword
5186 multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr,
5187 SDNode OpNode, SDNode OpNodeRnd> {
5188 let Predicates = [HasAVX512] in {
5189 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
5190 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
5191 OpNodeRnd>, EVEX_V512;
5193 let Predicates = [HasVLX] in {
5194 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5195 // memory forms of these instructions in Asm Parcer. They have the same
5196 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5197 // due to the same reason.
5198 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
5199 "{1to2}", "{x}">, EVEX_V128;
5200 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
5201 "{1to4}", "{y}">, EVEX_V256;
5205 // Convert Double to Signed/Unsigned Quardword
5206 multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr,
5207 SDNode OpNode, SDNode OpNodeRnd> {
5208 let Predicates = [HasDQI] in {
5209 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5210 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
5211 OpNodeRnd>, EVEX_V512;
5213 let Predicates = [HasDQI, HasVLX] in {
5214 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5216 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5221 // Convert Double to Signed/Unsigned Quardword with truncation
5222 multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr,
5223 SDNode OpNode, SDNode OpNodeRnd> {
5224 let Predicates = [HasDQI] in {
5225 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
5226 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
5227 OpNodeRnd>, EVEX_V512;
5229 let Predicates = [HasDQI, HasVLX] in {
5230 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
5232 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
5237 // Convert Signed/Unsigned Quardword to Double
5238 multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr,
5239 SDNode OpNode, SDNode OpNodeRnd> {
5240 let Predicates = [HasDQI] in {
5241 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode>,
5242 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
5243 OpNodeRnd>, EVEX_V512;
5245 let Predicates = [HasDQI, HasVLX] in {
5246 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode>,
5248 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode>,
5253 // Convert Float to Signed/Unsigned Quardword
5254 multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr,
5255 SDNode OpNode, SDNode OpNodeRnd> {
5256 let Predicates = [HasDQI] in {
5257 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5258 avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
5259 OpNodeRnd>, EVEX_V512;
5261 let Predicates = [HasDQI, HasVLX] in {
5262 // Explicitly specified broadcast string, since we take only 2 elements
5263 // from v4f32x_info source
5264 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5265 "{1to2}">, EVEX_V128;
5266 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5271 // Convert Float to Signed/Unsigned Quardword with truncation
5272 multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr,
5273 SDNode OpNode, SDNode OpNodeRnd> {
5274 let Predicates = [HasDQI] in {
5275 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
5276 avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
5277 OpNodeRnd>, EVEX_V512;
5279 let Predicates = [HasDQI, HasVLX] in {
5280 // Explicitly specified broadcast string, since we take only 2 elements
5281 // from v4f32x_info source
5282 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
5283 "{1to2}">, EVEX_V128;
5284 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
5289 // Convert Signed/Unsigned Quardword to Float
5290 multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
5291 SDNode OpNode, SDNode OpNodeRnd> {
5292 let Predicates = [HasDQI] in {
5293 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
5294 avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
5295 OpNodeRnd>, EVEX_V512;
5297 let Predicates = [HasDQI, HasVLX] in {
5298 // we need "x"/"y" suffixes in order to distinguish between 128 and 256
5299 // memory forms of these instructions in Asm Parcer. They have the same
5300 // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
5301 // due to the same reason.
5302 defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode,
5303 "{1to2}", "{x}">, EVEX_V128;
5304 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i64x_info, OpNode,
5305 "{1to4}", "{y}">, EVEX_V256;
5309 defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>, XS,
5310 EVEX_CD8<32, CD8VH>;
5312 defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
5314 PS, EVEX_CD8<32, CD8VF>;
5316 defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
5318 XS, EVEX_CD8<32, CD8VF>;
5320 defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", fp_to_sint,
5322 PD, VEX_W, EVEX_CD8<64, CD8VF>;
5324 defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", fp_to_uint,
5325 X86VFpToUintRnd>, PS,
5326 EVEX_CD8<32, CD8VF>;
5328 defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", fp_to_uint,
5329 X86VFpToUintRnd>, PS, VEX_W,
5330 EVEX_CD8<64, CD8VF>;
5332 defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86cvtudq2pd>,
5333 XS, EVEX_CD8<32, CD8VH>;
5335 defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp,
5336 X86VUintToFpRnd>, XD,
5337 EVEX_CD8<32, CD8VF>;
5339 defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtps2Int,
5340 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VF>;
5342 defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtpd2Int,
5343 X86cvtpd2IntRnd>, XD, VEX_W,
5344 EVEX_CD8<64, CD8VF>;
5346 defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtps2UInt,
5348 PS, EVEX_CD8<32, CD8VF>;
5349 defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtpd2UInt,
5350 X86cvtpd2UIntRnd>, VEX_W,
5351 PS, EVEX_CD8<64, CD8VF>;
5353 defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtpd2Int,
5354 X86cvtpd2IntRnd>, VEX_W,
5355 PD, EVEX_CD8<64, CD8VF>;
5357 defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtps2Int,
5358 X86cvtps2IntRnd>, PD, EVEX_CD8<32, CD8VH>;
5360 defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtpd2UInt,
5361 X86cvtpd2UIntRnd>, VEX_W,
5362 PD, EVEX_CD8<64, CD8VF>;
5364 defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtps2UInt,
5365 X86cvtps2UIntRnd>, PD, EVEX_CD8<32, CD8VH>;
5367 defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", fp_to_sint,
5368 X86VFpToSlongRnd>, VEX_W,
5369 PD, EVEX_CD8<64, CD8VF>;
5371 defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", fp_to_sint,
5372 X86VFpToSlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5374 defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", fp_to_uint,
5375 X86VFpToUlongRnd>, VEX_W,
5376 PD, EVEX_CD8<64, CD8VF>;
5378 defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", fp_to_uint,
5379 X86VFpToUlongRnd>, PD, EVEX_CD8<32, CD8VH>;
5381 defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp,
5382 X86VSlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5384 defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp,
5385 X86VUlongToFpRnd>, VEX_W, XS, EVEX_CD8<64, CD8VF>;
5387 defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp,
5388 X86VSlongToFpRnd>, VEX_W, PS, EVEX_CD8<64, CD8VF>;
5390 defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp,
5391 X86VUlongToFpRnd>, VEX_W, XD, EVEX_CD8<64, CD8VF>;
5393 let Predicates = [NoVLX] in {
5394 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
5395 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5396 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5398 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
5399 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
5400 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5402 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
5403 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5404 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
5406 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
5407 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
5408 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
5410 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
5411 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
5412 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
5415 let Predicates = [HasAVX512] in {
5416 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
5417 (VCVTPD2PSZrm addr:$src)>;
5418 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
5419 (VCVTPS2PDZrm addr:$src)>;
5422 //===----------------------------------------------------------------------===//
5423 // Half precision conversion instructions
5424 //===----------------------------------------------------------------------===//
5425 multiclass avx512_cvtph2ps<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5426 X86MemOperand x86memop, PatFrag ld_frag> {
5427 defm rr : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5428 "vcvtph2ps", "$src", "$src",
5429 (X86cvtph2ps (_src.VT _src.RC:$src),
5430 (i32 FROUND_CURRENT))>, T8PD;
5431 let hasSideEffects = 0, mayLoad = 1 in {
5432 defm rm : AVX512_maskable<0x13, MRMSrcMem, _dest, (outs _dest.RC:$dst), (ins x86memop:$src),
5433 "vcvtph2ps", "$src", "$src",
5434 (X86cvtph2ps (_src.VT (bitconvert (ld_frag addr:$src))),
5435 (i32 FROUND_CURRENT))>, T8PD;
5439 multiclass avx512_cvtph2ps_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
5440 defm rb : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
5441 "vcvtph2ps", "{sae}, $src", "$src, {sae}",
5442 (X86cvtph2ps (_src.VT _src.RC:$src),
5443 (i32 FROUND_NO_EXC))>, T8PD, EVEX_B;
5447 let Predicates = [HasAVX512] in {
5448 defm VCVTPH2PSZ : avx512_cvtph2ps<v16f32_info, v16i16x_info, f256mem, loadv4i64>,
5449 avx512_cvtph2ps_sae<v16f32_info, v16i16x_info>,
5450 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5451 let Predicates = [HasVLX] in {
5452 defm VCVTPH2PSZ256 : avx512_cvtph2ps<v8f32x_info, v8i16x_info, f128mem,
5453 loadv2i64>,EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5454 defm VCVTPH2PSZ128 : avx512_cvtph2ps<v4f32x_info, v8i16x_info, f64mem,
5455 loadv2i64>, EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5459 multiclass avx512_cvtps2ph<X86VectorVTInfo _dest, X86VectorVTInfo _src,
5460 X86MemOperand x86memop> {
5461 defm rr : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
5462 (ins _src.RC:$src1, i32u8imm:$src2),
5463 "vcvtps2ph", "$src2, $src1", "$src1, $src2",
5464 (X86cvtps2ph (_src.VT _src.RC:$src1),
5466 (i32 FROUND_CURRENT))>, AVX512AIi8Base;
5467 let hasSideEffects = 0, mayStore = 1 in {
5468 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
5469 (ins x86memop:$dst, _src.RC:$src1, i32u8imm:$src2),
5470 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5471 [(store (_dest.VT (X86cvtps2ph (_src.VT _src.RC:$src1),
5472 (i32 imm:$src2), (i32 FROUND_CURRENT) )),
5474 def mrk : AVX512AIi8<0x1D, MRMDestMem, (outs),
5475 (ins x86memop:$dst, _dest.KRCWM:$mask, _src.RC:$src1, i32u8imm:$src2),
5476 "vcvtps2ph\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}",
5480 multiclass avx512_cvtps2ph_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
5481 defm rb : AVX512_maskable<0x1D, MRMDestReg, _dest ,(outs _dest.RC:$dst),
5482 (ins _src.RC:$src1, i32u8imm:$src2),
5483 "vcvtps2ph", "$src2, {sae}, $src1", "$src1, $src2, {sae}",
5484 (X86cvtps2ph (_src.VT _src.RC:$src1),
5486 (i32 FROUND_NO_EXC))>, EVEX_B, AVX512AIi8Base;
5488 let Predicates = [HasAVX512] in {
5489 defm VCVTPS2PHZ : avx512_cvtps2ph<v16i16x_info, v16f32_info, f256mem>,
5490 avx512_cvtps2ph_sae<v16i16x_info, v16f32_info>,
5491 EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
5492 let Predicates = [HasVLX] in {
5493 defm VCVTPS2PHZ256 : avx512_cvtps2ph<v8i16x_info, v8f32x_info, f128mem>,
5494 EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
5495 defm VCVTPS2PHZ128 : avx512_cvtps2ph<v8i16x_info, v4f32x_info, f128mem>,
5496 EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
5499 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
5500 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
5501 "ucomiss">, PS, EVEX, VEX_LIG,
5502 EVEX_CD8<32, CD8VT1>;
5503 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
5504 "ucomisd">, PD, EVEX,
5505 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5506 let Pattern = []<dag> in {
5507 defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, undef, f32, f32mem, loadf32,
5508 "comiss">, PS, EVEX, VEX_LIG,
5509 EVEX_CD8<32, CD8VT1>;
5510 defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, undef, f64, f64mem, loadf64,
5511 "comisd">, PD, EVEX,
5512 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5514 let isCodeGenOnly = 1 in {
5515 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
5516 load, "ucomiss">, PS, EVEX, VEX_LIG,
5517 EVEX_CD8<32, CD8VT1>;
5518 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
5519 load, "ucomisd">, PD, EVEX,
5520 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5522 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
5523 load, "comiss">, PS, EVEX, VEX_LIG,
5524 EVEX_CD8<32, CD8VT1>;
5525 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
5526 load, "comisd">, PD, EVEX,
5527 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
5531 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
5532 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
5533 X86VectorVTInfo _> {
5534 let hasSideEffects = 0, AddedComplexity = 20 , Predicates = [HasAVX512] in {
5535 defm rr : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5536 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5537 "$src2, $src1", "$src1, $src2",
5538 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>, EVEX_4V;
5539 let mayLoad = 1 in {
5540 defm rm : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5541 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5542 "$src2, $src1", "$src1, $src2",
5543 (OpNode (_.VT _.RC:$src1),
5544 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))))>, EVEX_4V;
5549 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", X86frcp14s, f32x_info>,
5550 EVEX_CD8<32, CD8VT1>, T8PD;
5551 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", X86frcp14s, f64x_info>,
5552 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5553 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", X86frsqrt14s, f32x_info>,
5554 EVEX_CD8<32, CD8VT1>, T8PD;
5555 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", X86frsqrt14s, f64x_info>,
5556 VEX_W, EVEX_CD8<64, CD8VT1>, T8PD;
5558 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
5559 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
5560 X86VectorVTInfo _> {
5561 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5562 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5563 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
5564 let mayLoad = 1 in {
5565 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5566 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5568 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
5569 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5570 (ins _.ScalarMemOp:$src), OpcodeStr,
5571 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5573 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5578 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5579 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
5580 EVEX_V512, EVEX_CD8<32, CD8VF>;
5581 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
5582 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5584 // Define only if AVX512VL feature is present.
5585 let Predicates = [HasVLX] in {
5586 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5587 OpNode, v4f32x_info>,
5588 EVEX_V128, EVEX_CD8<32, CD8VF>;
5589 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
5590 OpNode, v8f32x_info>,
5591 EVEX_V256, EVEX_CD8<32, CD8VF>;
5592 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5593 OpNode, v2f64x_info>,
5594 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
5595 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
5596 OpNode, v4f64x_info>,
5597 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
5601 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
5602 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
5604 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
5605 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5606 (VRSQRT14PSZr VR512:$src)>;
5607 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
5608 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5609 (VRSQRT14PDZr VR512:$src)>;
5611 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
5612 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
5613 (VRCP14PSZr VR512:$src)>;
5614 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
5615 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
5616 (VRCP14PDZr VR512:$src)>;
5618 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
5619 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5622 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5623 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5624 "$src2, $src1", "$src1, $src2",
5625 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5626 (i32 FROUND_CURRENT))>;
5628 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5629 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5630 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
5631 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5632 (i32 FROUND_NO_EXC))>, EVEX_B;
5634 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5635 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5636 "$src2, $src1", "$src1, $src2",
5637 (OpNode (_.VT _.RC:$src1),
5638 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5639 (i32 FROUND_CURRENT))>;
5642 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5643 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
5644 EVEX_CD8<32, CD8VT1>;
5645 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
5646 EVEX_CD8<64, CD8VT1>, VEX_W;
5649 let hasSideEffects = 0, Predicates = [HasERI] in {
5650 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
5651 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
5654 defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexpRnds>, T8PD, EVEX_4V;
5655 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
5657 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5660 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5661 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5662 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
5664 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5665 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5667 (bitconvert (_.LdFrag addr:$src))),
5668 (i32 FROUND_CURRENT))>;
5670 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5671 (ins _.MemOp:$src), OpcodeStr,
5672 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5674 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
5675 (i32 FROUND_CURRENT))>, EVEX_B;
5677 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5679 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5680 (ins _.RC:$src), OpcodeStr,
5681 "{sae}, $src", "$src, {sae}",
5682 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
5685 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
5686 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5687 avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
5688 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
5689 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5690 avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
5691 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5694 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
5696 // Define only if AVX512VL feature is present.
5697 let Predicates = [HasVLX] in {
5698 defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
5699 EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;
5700 defm PSZ256 : avx512_fp28_p<opc, OpcodeStr#"ps", v8f32x_info, OpNode>,
5701 EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>;
5702 defm PDZ128 : avx512_fp28_p<opc, OpcodeStr#"pd", v2f64x_info, OpNode>,
5703 EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5704 defm PDZ256 : avx512_fp28_p<opc, OpcodeStr#"pd", v4f64x_info, OpNode>,
5705 EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
5708 let Predicates = [HasERI], hasSideEffects = 0 in {
5710 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX;
5711 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX;
5712 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX;
5714 defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
5715 avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
5717 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
5718 SDNode OpNodeRnd, X86VectorVTInfo _>{
5719 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5720 (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
5721 (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
5722 EVEX, EVEX_B, EVEX_RC;
5725 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
5726 SDNode OpNode, X86VectorVTInfo _>{
5727 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5728 (ins _.RC:$src), OpcodeStr, "$src", "$src",
5729 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
5730 let mayLoad = 1 in {
5731 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5732 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
5734 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
5736 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5737 (ins _.ScalarMemOp:$src), OpcodeStr,
5738 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
5740 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
5745 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
5747 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
5749 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5750 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
5752 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5753 // Define only if AVX512VL feature is present.
5754 let Predicates = [HasVLX] in {
5755 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5756 OpNode, v4f32x_info>,
5757 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
5758 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5759 OpNode, v8f32x_info>,
5760 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
5761 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5762 OpNode, v2f64x_info>,
5763 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5764 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5765 OpNode, v4f64x_info>,
5766 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5770 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
5772 defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
5773 v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5774 defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
5775 v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5778 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
5779 string SUFF, SDNode OpNode, SDNode OpNodeRnd> {
5781 defm r_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5782 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
5783 "$src2, $src1", "$src1, $src2",
5784 (OpNodeRnd (_.VT _.RC:$src1),
5786 (i32 FROUND_CURRENT))>;
5788 defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5789 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
5790 "$src2, $src1", "$src1, $src2",
5791 (OpNodeRnd (_.VT _.RC:$src1),
5792 (_.VT (scalar_to_vector
5793 (_.ScalarLdFrag addr:$src2))),
5794 (i32 FROUND_CURRENT))>;
5796 defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5797 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
5798 "$rc, $src2, $src1", "$src1, $src2, $rc",
5799 (OpNodeRnd (_.VT _.RC:$src1),
5804 let isCodeGenOnly = 1 in {
5805 def r : SI<opc, MRMSrcReg, (outs _.FRC:$dst),
5806 (ins _.FRC:$src1, _.FRC:$src2),
5807 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5810 def m : SI<opc, MRMSrcMem, (outs _.FRC:$dst),
5811 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
5812 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
5815 def : Pat<(_.EltVT (OpNode _.FRC:$src)),
5816 (!cast<Instruction>(NAME#SUFF#Zr)
5817 (_.EltVT (IMPLICIT_DEF)), _.FRC:$src)>;
5819 def : Pat<(_.EltVT (OpNode (load addr:$src))),
5820 (!cast<Instruction>(NAME#SUFF#Zm)
5821 (_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[OptForSize]>;
5824 multiclass avx512_sqrt_scalar_all<bits<8> opc, string OpcodeStr> {
5825 defm SSZ : avx512_sqrt_scalar<opc, OpcodeStr#"ss", f32x_info, "SS", fsqrt,
5826 X86fsqrtRnds>, EVEX_CD8<32, CD8VT1>, EVEX_4V, XS;
5827 defm SDZ : avx512_sqrt_scalar<opc, OpcodeStr#"sd", f64x_info, "SD", fsqrt,
5828 X86fsqrtRnds>, EVEX_CD8<64, CD8VT1>, EVEX_4V, XD, VEX_W;
5831 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>,
5832 avx512_sqrt_packed_all_round<0x51, "vsqrt", X86fsqrtRnd>;
5834 defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt">, VEX_LIG;
5836 let Predicates = [HasAVX512] in {
5837 def : Pat<(f32 (X86frsqrt FR32X:$src)),
5838 (COPY_TO_REGCLASS (VRSQRT14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X)>;
5839 def : Pat<(f32 (X86frsqrt (load addr:$src))),
5840 (COPY_TO_REGCLASS (VRSQRT14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5841 Requires<[OptForSize]>;
5842 def : Pat<(f32 (X86frcp FR32X:$src)),
5843 (COPY_TO_REGCLASS (VRCP14SSrr (v4f32 (IMPLICIT_DEF)), (COPY_TO_REGCLASS FR32X:$src, VR128X)), VR128X )>;
5844 def : Pat<(f32 (X86frcp (load addr:$src))),
5845 (COPY_TO_REGCLASS (VRCP14SSrm (v4f32 (IMPLICIT_DEF)), addr:$src), VR128X)>,
5846 Requires<[OptForSize]>;
5850 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5852 let ExeDomain = _.ExeDomain in {
5853 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5854 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5855 "$src3, $src2, $src1", "$src1, $src2, $src3",
5856 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5857 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5859 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5860 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5861 "$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
5862 (_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5863 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5866 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5867 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5868 "$src3, $src2, $src1", "$src1, $src2, $src3",
5869 (_.VT (X86RndScales (_.VT _.RC:$src1),
5870 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5871 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5873 let Predicates = [HasAVX512] in {
5874 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5875 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5876 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5877 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5878 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5879 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5880 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5881 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5882 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5883 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5884 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5885 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5886 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5887 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5888 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
5890 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5891 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5892 addr:$src, (i32 0x1))), _.FRC)>;
5893 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5894 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5895 addr:$src, (i32 0x2))), _.FRC)>;
5896 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5897 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5898 addr:$src, (i32 0x3))), _.FRC)>;
5899 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5900 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5901 addr:$src, (i32 0x4))), _.FRC)>;
5902 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5903 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5904 addr:$src, (i32 0xc))), _.FRC)>;
5908 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
5909 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5911 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
5912 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
5914 //-------------------------------------------------
5915 // Integer truncate and extend operations
5916 //-------------------------------------------------
5918 multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
5919 X86VectorVTInfo SrcInfo, X86VectorVTInfo DestInfo,
5920 X86MemOperand x86memop> {
5922 defm rr : AVX512_maskable<opc, MRMDestReg, DestInfo, (outs DestInfo.RC:$dst),
5923 (ins SrcInfo.RC:$src1), OpcodeStr ,"$src1", "$src1",
5924 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1)))>,
5927 // for intrinsic patter match
5928 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5929 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5931 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
5934 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5935 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5936 DestInfo.ImmAllZerosV)),
5937 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,
5940 def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,
5941 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),
5942 DestInfo.RC:$src0)),
5943 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrk) DestInfo.RC:$src0,
5944 DestInfo.KRCWM:$mask ,
5947 let mayStore = 1 in {
5948 def mr : AVX512XS8I<opc, MRMDestMem, (outs),
5949 (ins x86memop:$dst, SrcInfo.RC:$src),
5950 OpcodeStr # "\t{$src, $dst |$dst, $src}",
5953 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
5954 (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),
5955 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5960 multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,
5961 X86VectorVTInfo DestInfo,
5962 PatFrag truncFrag, PatFrag mtruncFrag > {
5964 def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),
5965 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr)
5966 addr:$dst, SrcInfo.RC:$src)>;
5968 def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask,
5969 (SrcInfo.VT SrcInfo.RC:$src)),
5970 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk)
5971 addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;
5974 multiclass avx512_trunc_sat_mr_lowering<X86VectorVTInfo SrcInfo,
5975 X86VectorVTInfo DestInfo, string sat > {
5977 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
5978 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
5979 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), SrcInfo.MRC:$mask),
5980 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk) addr:$ptr,
5981 (COPY_TO_REGCLASS SrcInfo.MRC:$mask, SrcInfo.KRCWM),
5982 (SrcInfo.VT SrcInfo.RC:$src))>;
5984 def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#
5985 DestInfo.Suffix#"_mem_"#SrcInfo.Size)
5986 addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), -1),
5987 (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr) addr:$ptr,
5988 (SrcInfo.VT SrcInfo.RC:$src))>;
5991 multiclass avx512_trunc<bits<8> opc, string OpcodeStr, SDNode OpNode,
5992 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
5993 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
5994 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
5995 X86MemOperand x86memopZ, PatFrag truncFrag, PatFrag mtruncFrag,
5996 Predicate prd = HasAVX512>{
5998 let Predicates = [HasVLX, prd] in {
5999 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
6000 DestInfoZ128, x86memopZ128>,
6001 avx512_trunc_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
6002 truncFrag, mtruncFrag>, EVEX_V128;
6004 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
6005 DestInfoZ256, x86memopZ256>,
6006 avx512_trunc_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
6007 truncFrag, mtruncFrag>, EVEX_V256;
6009 let Predicates = [prd] in
6010 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
6011 DestInfoZ, x86memopZ>,
6012 avx512_trunc_mr_lowering<VTSrcInfo.info512, DestInfoZ,
6013 truncFrag, mtruncFrag>, EVEX_V512;
6016 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr, SDNode OpNode,
6017 AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,
6018 X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,
6019 X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,
6020 X86MemOperand x86memopZ, string sat, Predicate prd = HasAVX512>{
6022 let Predicates = [HasVLX, prd] in {
6023 defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,
6024 DestInfoZ128, x86memopZ128>,
6025 avx512_trunc_sat_mr_lowering<VTSrcInfo.info128, DestInfoZ128,
6028 defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,
6029 DestInfoZ256, x86memopZ256>,
6030 avx512_trunc_sat_mr_lowering<VTSrcInfo.info256, DestInfoZ256,
6033 let Predicates = [prd] in
6034 defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,
6035 DestInfoZ, x86memopZ>,
6036 avx512_trunc_sat_mr_lowering<VTSrcInfo.info512, DestInfoZ,
6040 multiclass avx512_trunc_qb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6041 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6042 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
6043 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VO>;
6045 multiclass avx512_trunc_sat_qb<bits<8> opc, string sat, SDNode OpNode> {
6046 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qb", OpNode, avx512vl_i64_info,
6047 v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,
6048 sat>, EVEX_CD8<8, CD8VO>;
6051 multiclass avx512_trunc_qw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6052 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6053 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
6054 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VQ>;
6056 multiclass avx512_trunc_sat_qw<bits<8> opc, string sat, SDNode OpNode> {
6057 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qw", OpNode, avx512vl_i64_info,
6058 v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,
6059 sat>, EVEX_CD8<16, CD8VQ>;
6062 multiclass avx512_trunc_qd<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6063 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,
6064 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
6065 truncstorevi32, masked_truncstorevi32>, EVEX_CD8<32, CD8VH>;
6067 multiclass avx512_trunc_sat_qd<bits<8> opc, string sat, SDNode OpNode> {
6068 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qd", OpNode, avx512vl_i64_info,
6069 v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,
6070 sat>, EVEX_CD8<32, CD8VH>;
6073 multiclass avx512_trunc_db<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6074 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
6075 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
6076 truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VQ>;
6078 multiclass avx512_trunc_sat_db<bits<8> opc, string sat, SDNode OpNode> {
6079 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"db", OpNode, avx512vl_i32_info,
6080 v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,
6081 sat>, EVEX_CD8<8, CD8VQ>;
6084 multiclass avx512_trunc_dw<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6085 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,
6086 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
6087 truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VH>;
6089 multiclass avx512_trunc_sat_dw<bits<8> opc, string sat, SDNode OpNode> {
6090 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"dw", OpNode, avx512vl_i32_info,
6091 v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,
6092 sat>, EVEX_CD8<16, CD8VH>;
6095 multiclass avx512_trunc_wb<bits<8> opc, string OpcodeStr, SDNode OpNode> {
6096 defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i16_info,
6097 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
6098 truncstorevi8, masked_truncstorevi8,HasBWI>, EVEX_CD8<16, CD8VH>;
6100 multiclass avx512_trunc_sat_wb<bits<8> opc, string sat, SDNode OpNode> {
6101 defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"wb", OpNode, avx512vl_i16_info,
6102 v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,
6103 sat, HasBWI>, EVEX_CD8<16, CD8VH>;
6106 defm VPMOVQB : avx512_trunc_qb<0x32, "vpmovqb", X86vtrunc>;
6107 defm VPMOVSQB : avx512_trunc_sat_qb<0x22, "s", X86vtruncs>;
6108 defm VPMOVUSQB : avx512_trunc_sat_qb<0x12, "us", X86vtruncus>;
6110 defm VPMOVQW : avx512_trunc_qw<0x34, "vpmovqw", X86vtrunc>;
6111 defm VPMOVSQW : avx512_trunc_sat_qw<0x24, "s", X86vtruncs>;
6112 defm VPMOVUSQW : avx512_trunc_sat_qw<0x14, "us", X86vtruncus>;
6114 defm VPMOVQD : avx512_trunc_qd<0x35, "vpmovqd", X86vtrunc>;
6115 defm VPMOVSQD : avx512_trunc_sat_qd<0x25, "s", X86vtruncs>;
6116 defm VPMOVUSQD : avx512_trunc_sat_qd<0x15, "us", X86vtruncus>;
6118 defm VPMOVDB : avx512_trunc_db<0x31, "vpmovdb", X86vtrunc>;
6119 defm VPMOVSDB : avx512_trunc_sat_db<0x21, "s", X86vtruncs>;
6120 defm VPMOVUSDB : avx512_trunc_sat_db<0x11, "us", X86vtruncus>;
6122 defm VPMOVDW : avx512_trunc_dw<0x33, "vpmovdw", X86vtrunc>;
6123 defm VPMOVSDW : avx512_trunc_sat_dw<0x23, "s", X86vtruncs>;
6124 defm VPMOVUSDW : avx512_trunc_sat_dw<0x13, "us", X86vtruncus>;
6126 defm VPMOVWB : avx512_trunc_wb<0x30, "vpmovwb", X86vtrunc>;
6127 defm VPMOVSWB : avx512_trunc_sat_wb<0x20, "s", X86vtruncs>;
6128 defm VPMOVUSWB : avx512_trunc_sat_wb<0x10, "us", X86vtruncus>;
6130 let Predicates = [HasAVX512, NoVLX] in {
6131 def: Pat<(v8i16 (X86vtrunc (v8i32 VR256X:$src))),
6132 (v8i16 (EXTRACT_SUBREG
6133 (v16i16 (VPMOVDWZrr (v16i32 (SUBREG_TO_REG (i32 0),
6134 VR256X:$src, sub_ymm)))), sub_xmm))>;
6135 def: Pat<(v4i32 (X86vtrunc (v4i64 VR256X:$src))),
6136 (v4i32 (EXTRACT_SUBREG
6137 (v8i32 (VPMOVQDZrr (v8i64 (SUBREG_TO_REG (i32 0),
6138 VR256X:$src, sub_ymm)))), sub_xmm))>;
6141 let Predicates = [HasBWI, NoVLX] in {
6142 def: Pat<(v16i8 (X86vtrunc (v16i16 VR256X:$src))),
6143 (v16i8 (EXTRACT_SUBREG (VPMOVWBZrr (v32i16 (SUBREG_TO_REG (i32 0),
6144 VR256X:$src, sub_ymm))), sub_xmm))>;
6147 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
6148 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
6149 X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{
6151 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6152 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
6153 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
6156 let mayLoad = 1 in {
6157 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6158 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
6159 (DestInfo.VT (LdFrag addr:$src))>,
6164 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode,
6165 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6166 let Predicates = [HasVLX, HasBWI] in {
6167 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
6168 v16i8x_info, i64mem, LdFrag, OpNode>,
6169 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
6171 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
6172 v16i8x_info, i128mem, LdFrag, OpNode>,
6173 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
6175 let Predicates = [HasBWI] in {
6176 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
6177 v32i8x_info, i256mem, LdFrag, OpNode>,
6178 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
6182 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6183 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6184 let Predicates = [HasVLX, HasAVX512] in {
6185 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6186 v16i8x_info, i32mem, LdFrag, OpNode>,
6187 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
6189 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6190 v16i8x_info, i64mem, LdFrag, OpNode>,
6191 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
6193 let Predicates = [HasAVX512] in {
6194 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6195 v16i8x_info, i128mem, LdFrag, OpNode>,
6196 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
6200 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6201 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
6202 let Predicates = [HasVLX, HasAVX512] in {
6203 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6204 v16i8x_info, i16mem, LdFrag, OpNode>,
6205 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
6207 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6208 v16i8x_info, i32mem, LdFrag, OpNode>,
6209 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
6211 let Predicates = [HasAVX512] in {
6212 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6213 v16i8x_info, i64mem, LdFrag, OpNode>,
6214 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
6218 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, SDNode OpNode,
6219 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6220 let Predicates = [HasVLX, HasAVX512] in {
6221 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
6222 v8i16x_info, i64mem, LdFrag, OpNode>,
6223 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
6225 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
6226 v8i16x_info, i128mem, LdFrag, OpNode>,
6227 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
6229 let Predicates = [HasAVX512] in {
6230 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
6231 v16i16x_info, i256mem, LdFrag, OpNode>,
6232 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
6236 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6237 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
6238 let Predicates = [HasVLX, HasAVX512] in {
6239 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6240 v8i16x_info, i32mem, LdFrag, OpNode>,
6241 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
6243 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6244 v8i16x_info, i64mem, LdFrag, OpNode>,
6245 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
6247 let Predicates = [HasAVX512] in {
6248 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6249 v8i16x_info, i128mem, LdFrag, OpNode>,
6250 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
6254 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
6255 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
6257 let Predicates = [HasVLX, HasAVX512] in {
6258 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
6259 v4i32x_info, i64mem, LdFrag, OpNode>,
6260 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
6262 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
6263 v4i32x_info, i128mem, LdFrag, OpNode>,
6264 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
6266 let Predicates = [HasAVX512] in {
6267 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
6268 v8i32x_info, i256mem, LdFrag, OpNode>,
6269 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
6273 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, "z">;
6274 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, "z">;
6275 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, "z">;
6276 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, "z">;
6277 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, "z">;
6278 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, "z">;
6281 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, "s">;
6282 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, "s">;
6283 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, "s">;
6284 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, "s">;
6285 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, "s">;
6286 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, "s">;
6288 //===----------------------------------------------------------------------===//
6289 // GATHER - SCATTER Operations
6291 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6292 X86MemOperand memop, PatFrag GatherNode> {
6293 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb",
6294 ExeDomain = _.ExeDomain in
6295 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
6296 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
6297 !strconcat(OpcodeStr#_.Suffix,
6298 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
6299 [(set _.RC:$dst, _.KRCWM:$mask_wb,
6300 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
6301 vectoraddr:$src2))]>, EVEX, EVEX_K,
6302 EVEX_CD8<_.EltSize, CD8VT1>;
6305 multiclass avx512_gather_q_pd<bits<8> dopc, bits<8> qopc,
6306 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6307 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512,
6308 vy32xmem, mgatherv8i32>, EVEX_V512, VEX_W;
6309 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info512,
6310 vz64mem, mgatherv8i64>, EVEX_V512, VEX_W;
6311 let Predicates = [HasVLX] in {
6312 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6313 vx32xmem, mgatherv4i32>, EVEX_V256, VEX_W;
6314 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info256,
6315 vy64xmem, mgatherv4i64>, EVEX_V256, VEX_W;
6316 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6317 vx32xmem, mgatherv4i32>, EVEX_V128, VEX_W;
6318 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6319 vx64xmem, mgatherv2i64>, EVEX_V128, VEX_W;
6323 multiclass avx512_gather_d_ps<bits<8> dopc, bits<8> qopc,
6324 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6325 defm NAME##D##SUFF##Z: avx512_gather<dopc, OpcodeStr##"d", _.info512, vz32mem,
6326 mgatherv16i32>, EVEX_V512;
6327 defm NAME##Q##SUFF##Z: avx512_gather<qopc, OpcodeStr##"q", _.info256, vz64mem,
6328 mgatherv8i64>, EVEX_V512;
6329 let Predicates = [HasVLX] in {
6330 defm NAME##D##SUFF##Z256: avx512_gather<dopc, OpcodeStr##"d", _.info256,
6331 vy32xmem, mgatherv8i32>, EVEX_V256;
6332 defm NAME##Q##SUFF##Z256: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6333 vy64xmem, mgatherv4i64>, EVEX_V256;
6334 defm NAME##D##SUFF##Z128: avx512_gather<dopc, OpcodeStr##"d", _.info128,
6335 vx32xmem, mgatherv4i32>, EVEX_V128;
6336 defm NAME##Q##SUFF##Z128: avx512_gather<qopc, OpcodeStr##"q", _.info128,
6337 vx64xmem, mgatherv2i64>, EVEX_V128;
6342 defm VGATHER : avx512_gather_q_pd<0x92, 0x93, avx512vl_f64_info, "vgather", "PD">,
6343 avx512_gather_d_ps<0x92, 0x93, avx512vl_f32_info, "vgather", "PS">;
6345 defm VPGATHER : avx512_gather_q_pd<0x90, 0x91, avx512vl_i64_info, "vpgather", "Q">,
6346 avx512_gather_d_ps<0x90, 0x91, avx512vl_i32_info, "vpgather", "D">;
6348 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
6349 X86MemOperand memop, PatFrag ScatterNode> {
6351 let mayStore = 1, Constraints = "$mask = $mask_wb", ExeDomain = _.ExeDomain in
6353 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
6354 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
6355 !strconcat(OpcodeStr#_.Suffix,
6356 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
6357 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
6358 _.KRCWM:$mask, vectoraddr:$dst))]>,
6359 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6362 multiclass avx512_scatter_q_pd<bits<8> dopc, bits<8> qopc,
6363 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6364 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512,
6365 vy32xmem, mscatterv8i32>, EVEX_V512, VEX_W;
6366 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info512,
6367 vz64mem, mscatterv8i64>, EVEX_V512, VEX_W;
6368 let Predicates = [HasVLX] in {
6369 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6370 vx32xmem, mscatterv4i32>, EVEX_V256, VEX_W;
6371 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info256,
6372 vy64xmem, mscatterv4i64>, EVEX_V256, VEX_W;
6373 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6374 vx32xmem, mscatterv4i32>, EVEX_V128, VEX_W;
6375 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6376 vx64xmem, mscatterv2i64>, EVEX_V128, VEX_W;
6380 multiclass avx512_scatter_d_ps<bits<8> dopc, bits<8> qopc,
6381 AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> {
6382 defm NAME##D##SUFF##Z: avx512_scatter<dopc, OpcodeStr##"d", _.info512, vz32mem,
6383 mscatterv16i32>, EVEX_V512;
6384 defm NAME##Q##SUFF##Z: avx512_scatter<qopc, OpcodeStr##"q", _.info256, vz64mem,
6385 mscatterv8i64>, EVEX_V512;
6386 let Predicates = [HasVLX] in {
6387 defm NAME##D##SUFF##Z256: avx512_scatter<dopc, OpcodeStr##"d", _.info256,
6388 vy32xmem, mscatterv8i32>, EVEX_V256;
6389 defm NAME##Q##SUFF##Z256: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6390 vy64xmem, mscatterv4i64>, EVEX_V256;
6391 defm NAME##D##SUFF##Z128: avx512_scatter<dopc, OpcodeStr##"d", _.info128,
6392 vx32xmem, mscatterv4i32>, EVEX_V128;
6393 defm NAME##Q##SUFF##Z128: avx512_scatter<qopc, OpcodeStr##"q", _.info128,
6394 vx64xmem, mscatterv2i64>, EVEX_V128;
6398 defm VSCATTER : avx512_scatter_q_pd<0xA2, 0xA3, avx512vl_f64_info, "vscatter", "PD">,
6399 avx512_scatter_d_ps<0xA2, 0xA3, avx512vl_f32_info, "vscatter", "PS">;
6401 defm VPSCATTER : avx512_scatter_q_pd<0xA0, 0xA1, avx512vl_i64_info, "vpscatter", "Q">,
6402 avx512_scatter_d_ps<0xA0, 0xA1, avx512vl_i32_info, "vpscatter", "D">;
6405 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
6406 RegisterClass KRC, X86MemOperand memop> {
6407 let Predicates = [HasPFI], hasSideEffects = 1 in
6408 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
6409 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
6413 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
6414 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6416 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
6417 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6419 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
6420 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6422 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
6423 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6425 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
6426 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6428 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
6429 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6431 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
6432 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6434 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
6435 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6437 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
6438 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6440 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
6441 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6443 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
6444 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6446 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
6447 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6449 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
6450 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
6452 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
6453 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
6455 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
6456 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
6458 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
6459 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
6461 // Helper fragments to match sext vXi1 to vXiY.
6462 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
6463 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
6465 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6466 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
6467 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
6469 def : Pat<(store VK1:$src, addr:$dst),
6471 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
6472 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6474 def : Pat<(store VK8:$src, addr:$dst),
6476 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
6477 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
6479 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
6480 (truncstore node:$val, node:$ptr), [{
6481 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
6484 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
6485 (MOV8mr addr:$dst, GR8:$src)>;
6487 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
6488 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
6489 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
6490 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
6493 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
6494 string OpcodeStr, Predicate prd> {
6495 let Predicates = [prd] in
6496 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6498 let Predicates = [prd, HasVLX] in {
6499 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6500 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6504 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
6505 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
6507 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
6509 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
6511 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
6515 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
6517 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
6518 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
6519 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6520 [(set _.KRC:$dst, (trunc (_.VT _.RC:$src)))]>, EVEX;
6523 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
6524 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
6525 let Predicates = [prd] in
6526 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
6529 let Predicates = [prd, HasVLX] in {
6530 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
6532 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
6537 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
6538 avx512vl_i8_info, HasBWI>;
6539 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
6540 avx512vl_i16_info, HasBWI>, VEX_W;
6541 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
6542 avx512vl_i32_info, HasDQI>;
6543 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
6544 avx512vl_i64_info, HasDQI>, VEX_W;
6546 //===----------------------------------------------------------------------===//
6547 // AVX-512 - COMPRESS and EXPAND
6550 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6552 defm rr : AVX512_maskable<opc, MRMDestReg, _, (outs _.RC:$dst),
6553 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6554 (_.VT (X86compress _.RC:$src1))>, AVX5128IBase;
6556 let mayStore = 1 in {
6557 def mr : AVX5128I<opc, MRMDestMem, (outs),
6558 (ins _.MemOp:$dst, _.RC:$src),
6559 OpcodeStr # "\t{$src, $dst |$dst, $src}",
6560 []>, EVEX_CD8<_.EltSize, CD8VT1>;
6562 def mrk : AVX5128I<opc, MRMDestMem, (outs),
6563 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
6564 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
6565 [(store (_.VT (vselect _.KRCWM:$mask,
6566 (_.VT (X86compress _.RC:$src)), _.ImmAllZerosV)),
6568 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
6572 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
6573 AVX512VLVectorVTInfo VTInfo> {
6574 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6576 let Predicates = [HasVLX] in {
6577 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6578 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6582 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
6584 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
6586 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
6588 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
6592 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
6594 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6595 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
6596 (_.VT (X86expand _.RC:$src1))>, AVX5128IBase;
6599 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6600 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
6601 (_.VT (X86expand (_.VT (bitconvert
6602 (_.LdFrag addr:$src1)))))>,
6603 AVX5128IBase, EVEX_CD8<_.EltSize, CD8VT1>;
6606 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
6607 AVX512VLVectorVTInfo VTInfo> {
6608 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
6610 let Predicates = [HasVLX] in {
6611 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
6612 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
6616 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
6618 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
6620 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
6622 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
6625 //handle instruction reg_vec1 = op(reg_vec,imm)
6627 // op(broadcast(eltVt),imm)
6628 //all instruction created with FROUND_CURRENT
6629 multiclass avx512_unary_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6631 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6632 (ins _.RC:$src1, i32u8imm:$src2),
6633 OpcodeStr##_.Suffix, "$src2, $src1", "$src2, $src2",
6634 (OpNode (_.VT _.RC:$src1),
6636 (i32 FROUND_CURRENT))>;
6637 let mayLoad = 1 in {
6638 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6639 (ins _.MemOp:$src1, i32u8imm:$src2),
6640 OpcodeStr##_.Suffix, "$src2, $src1", "$src1, $src2",
6641 (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
6643 (i32 FROUND_CURRENT))>;
6644 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6645 (ins _.ScalarMemOp:$src1, i32u8imm:$src2),
6646 OpcodeStr##_.Suffix, "$src2, ${src1}"##_.BroadcastStr,
6647 "${src1}"##_.BroadcastStr##", $src2",
6648 (OpNode (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src1))),
6650 (i32 FROUND_CURRENT))>, EVEX_B;
6654 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6655 multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6656 SDNode OpNode, X86VectorVTInfo _>{
6657 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6658 (ins _.RC:$src1, i32u8imm:$src2),
6659 OpcodeStr##_.Suffix, "$src2,{sae}, $src1",
6660 "$src1, {sae}, $src2",
6661 (OpNode (_.VT _.RC:$src1),
6663 (i32 FROUND_NO_EXC))>, EVEX_B;
6666 multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
6667 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6668 let Predicates = [prd] in {
6669 defm Z : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6670 avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6673 let Predicates = [prd, HasVLX] in {
6674 defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6676 defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6681 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6682 // op(reg_vec2,mem_vec,imm)
6683 // op(reg_vec2,broadcast(eltVt),imm)
6684 //all instruction created with FROUND_CURRENT
6685 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6687 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6688 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6689 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6690 (OpNode (_.VT _.RC:$src1),
6693 (i32 FROUND_CURRENT))>;
6694 let mayLoad = 1 in {
6695 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6696 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6697 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6698 (OpNode (_.VT _.RC:$src1),
6699 (_.VT (bitconvert (_.LdFrag addr:$src2))),
6701 (i32 FROUND_CURRENT))>;
6702 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6703 (ins _.RC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
6704 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6705 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6706 (OpNode (_.VT _.RC:$src1),
6707 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6709 (i32 FROUND_CURRENT))>, EVEX_B;
6713 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6714 // op(reg_vec2,mem_vec,imm)
6715 multiclass avx512_3Op_rm_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6716 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo>{
6718 defm rri : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
6719 (ins SrcInfo.RC:$src1, SrcInfo.RC:$src2, u8imm:$src3),
6720 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6721 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6722 (SrcInfo.VT SrcInfo.RC:$src2),
6725 defm rmi : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
6726 (ins SrcInfo.RC:$src1, SrcInfo.MemOp:$src2, u8imm:$src3),
6727 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6728 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1),
6729 (SrcInfo.VT (bitconvert
6730 (SrcInfo.LdFrag addr:$src2))),
6734 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6735 // op(reg_vec2,mem_vec,imm)
6736 // op(reg_vec2,broadcast(eltVt),imm)
6737 multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6739 avx512_3Op_rm_imm8<opc, OpcodeStr, OpNode, _, _>{
6742 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6743 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6744 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6745 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6746 (OpNode (_.VT _.RC:$src1),
6747 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6748 (i8 imm:$src3))>, EVEX_B;
6751 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6752 // op(reg_vec2,mem_scalar,imm)
6753 //all instruction created with FROUND_CURRENT
6754 multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6755 X86VectorVTInfo _> {
6757 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6758 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6759 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6760 (OpNode (_.VT _.RC:$src1),
6763 (i32 FROUND_CURRENT))>;
6764 let mayLoad = 1 in {
6765 defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6766 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3),
6767 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6768 (OpNode (_.VT _.RC:$src1),
6769 (_.VT (scalar_to_vector
6770 (_.ScalarLdFrag addr:$src2))),
6772 (i32 FROUND_CURRENT))>;
6774 let isAsmParserOnly = 1 in {
6775 defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
6776 (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6777 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6783 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6784 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6785 SDNode OpNode, X86VectorVTInfo _>{
6786 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6787 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6788 OpcodeStr, "$src3,{sae}, $src2, $src1",
6789 "$src1, $src2,{sae}, $src3",
6790 (OpNode (_.VT _.RC:$src1),
6793 (i32 FROUND_NO_EXC))>, EVEX_B;
6795 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6796 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
6797 SDNode OpNode, X86VectorVTInfo _> {
6798 defm NAME#rrib : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6799 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
6800 OpcodeStr, "$src3,{sae}, $src2, $src1",
6801 "$src1, $src2,{sae}, $src3",
6802 (OpNode (_.VT _.RC:$src1),
6805 (i32 FROUND_NO_EXC))>, EVEX_B;
6808 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
6809 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6810 let Predicates = [prd] in {
6811 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6812 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6816 let Predicates = [prd, HasVLX] in {
6817 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6819 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6824 multiclass avx512_common_3Op_rm_imm8<bits<8> opc, SDNode OpNode, string OpStr,
6825 AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo>{
6826 let Predicates = [HasBWI] in {
6827 defm Z : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info512,
6828 SrcInfo.info512>, EVEX_V512, AVX512AIi8Base, EVEX_4V;
6830 let Predicates = [HasBWI, HasVLX] in {
6831 defm Z128 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info128,
6832 SrcInfo.info128>, EVEX_V128, AVX512AIi8Base, EVEX_4V;
6833 defm Z256 : avx512_3Op_rm_imm8<opc, OpStr, OpNode, DestInfo.info256,
6834 SrcInfo.info256>, EVEX_V256, AVX512AIi8Base, EVEX_4V;
6838 multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
6839 bits<8> opc, SDNode OpNode>{
6840 let Predicates = [HasAVX512] in {
6841 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6843 let Predicates = [HasAVX512, HasVLX] in {
6844 defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
6845 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6849 multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
6850 X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6851 let Predicates = [prd] in {
6852 defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
6853 avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
6857 multiclass avx512_common_unary_fp_sae_packed_imm_all<string OpcodeStr,
6858 bits<8> opcPs, bits<8> opcPd, SDNode OpNode, Predicate prd>{
6859 defm PS : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f32_info,
6860 opcPs, OpNode, prd>, EVEX_CD8<32, CD8VF>;
6861 defm PD : avx512_common_unary_fp_sae_packed_imm<OpcodeStr, avx512vl_f64_info,
6862 opcPd, OpNode, prd>, EVEX_CD8<64, CD8VF>, VEX_W;
6865 defm VFIXUPIMMPD : avx512_common_fp_sae_packed_imm<"vfixupimmpd",
6866 avx512vl_f64_info, 0x54, X86VFixupimm, HasAVX512>,
6867 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6868 defm VFIXUPIMMPS : avx512_common_fp_sae_packed_imm<"vfixupimmps",
6869 avx512vl_f32_info, 0x54, X86VFixupimm, HasAVX512>,
6870 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6872 defm VFIXUPIMMSD: avx512_common_fp_sae_scalar_imm<"vfixupimmsd", f64x_info,
6873 0x55, X86VFixupimm, HasAVX512>,
6874 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6875 defm VFIXUPIMMSS: avx512_common_fp_sae_scalar_imm<"vfixupimmss", f32x_info,
6876 0x55, X86VFixupimm, HasAVX512>,
6877 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6879 defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56,
6880 X86VReduce, HasDQI>, AVX512AIi8Base, EVEX;
6881 defm VRNDSCALE : avx512_common_unary_fp_sae_packed_imm_all<"vrndscale", 0x08, 0x09,
6882 X86VRndScale, HasAVX512>, AVX512AIi8Base, EVEX;
6883 defm VGETMANT : avx512_common_unary_fp_sae_packed_imm_all<"vgetmant", 0x26, 0x26,
6884 X86VGetMant, HasAVX512>, AVX512AIi8Base, EVEX;
6887 defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
6888 0x50, X86VRange, HasDQI>,
6889 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6890 defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
6891 0x50, X86VRange, HasDQI>,
6892 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6894 defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
6895 0x51, X86VRange, HasDQI>,
6896 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6897 defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
6898 0x51, X86VRange, HasDQI>,
6899 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6901 defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info,
6902 0x57, X86Reduces, HasDQI>,
6903 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6904 defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info,
6905 0x57, X86Reduces, HasDQI>,
6906 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6908 defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info,
6909 0x27, X86GetMants, HasAVX512>,
6910 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6911 defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info,
6912 0x27, X86GetMants, HasAVX512>,
6913 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6915 multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
6916 bits<8> opc, SDNode OpNode = X86Shuf128>{
6917 let Predicates = [HasAVX512] in {
6918 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6921 let Predicates = [HasAVX512, HasVLX] in {
6922 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6925 let Predicates = [HasAVX512] in {
6926 def : Pat<(v16f32 (ffloor VR512:$src)),
6927 (VRNDSCALEPSZrri VR512:$src, (i32 0x1))>;
6928 def : Pat<(v16f32 (fnearbyint VR512:$src)),
6929 (VRNDSCALEPSZrri VR512:$src, (i32 0xC))>;
6930 def : Pat<(v16f32 (fceil VR512:$src)),
6931 (VRNDSCALEPSZrri VR512:$src, (i32 0x2))>;
6932 def : Pat<(v16f32 (frint VR512:$src)),
6933 (VRNDSCALEPSZrri VR512:$src, (i32 0x4))>;
6934 def : Pat<(v16f32 (ftrunc VR512:$src)),
6935 (VRNDSCALEPSZrri VR512:$src, (i32 0x3))>;
6937 def : Pat<(v8f64 (ffloor VR512:$src)),
6938 (VRNDSCALEPDZrri VR512:$src, (i32 0x1))>;
6939 def : Pat<(v8f64 (fnearbyint VR512:$src)),
6940 (VRNDSCALEPDZrri VR512:$src, (i32 0xC))>;
6941 def : Pat<(v8f64 (fceil VR512:$src)),
6942 (VRNDSCALEPDZrri VR512:$src, (i32 0x2))>;
6943 def : Pat<(v8f64 (frint VR512:$src)),
6944 (VRNDSCALEPDZrri VR512:$src, (i32 0x4))>;
6945 def : Pat<(v8f64 (ftrunc VR512:$src)),
6946 (VRNDSCALEPDZrri VR512:$src, (i32 0x3))>;
6949 defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
6950 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6951 defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
6952 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6953 defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
6954 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6955 defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
6956 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6958 multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
6959 AVX512VLVectorVTInfo VTInfo_FP>{
6960 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
6961 AVX512AIi8Base, EVEX_4V;
6962 let isCodeGenOnly = 1 in {
6963 defm NAME#_FP: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0x03, X86VAlign>,
6964 AVX512AIi8Base, EVEX_4V;
6968 defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info, avx512vl_f32_info>,
6969 EVEX_CD8<32, CD8VF>;
6970 defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info, avx512vl_f64_info>,
6971 EVEX_CD8<64, CD8VF>, VEX_W;
6973 multiclass avx512_vpalign_lowering<X86VectorVTInfo _ , list<Predicate> p>{
6974 let Predicates = p in
6975 def NAME#_.VTName#rri:
6976 Pat<(_.VT (X86PAlignr _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
6977 (!cast<Instruction>(NAME#_.ZSuffix#rri)
6978 _.RC:$src1, _.RC:$src2, imm:$imm)>;
6981 multiclass avx512_vpalign_lowering_common<AVX512VLVectorVTInfo _>:
6982 avx512_vpalign_lowering<_.info512, [HasBWI]>,
6983 avx512_vpalign_lowering<_.info128, [HasBWI, HasVLX]>,
6984 avx512_vpalign_lowering<_.info256, [HasBWI, HasVLX]>;
6986 defm VPALIGN: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr" ,
6987 avx512vl_i8_info, avx512vl_i8_info>,
6988 avx512_vpalign_lowering_common<avx512vl_i16_info>,
6989 avx512_vpalign_lowering_common<avx512vl_i32_info>,
6990 avx512_vpalign_lowering_common<avx512vl_f32_info>,
6991 avx512_vpalign_lowering_common<avx512vl_i64_info>,
6992 avx512_vpalign_lowering_common<avx512vl_f64_info>,
6995 defm VDBPSADBW: avx512_common_3Op_rm_imm8<0x42, X86dbpsadbw, "vdbpsadbw" ,
6996 avx512vl_i16_info, avx512vl_i8_info>, EVEX_CD8<8, CD8VF>;
6998 multiclass avx512_unary_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6999 X86VectorVTInfo _> {
7000 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7001 (ins _.RC:$src1), OpcodeStr,
7003 (_.VT (OpNode _.RC:$src1))>, EVEX, AVX5128IBase;
7006 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7007 (ins _.MemOp:$src1), OpcodeStr,
7009 (_.VT (OpNode (bitconvert (_.LdFrag addr:$src1))))>,
7010 EVEX, AVX5128IBase, EVEX_CD8<_.EltSize, CD8VF>;
7013 multiclass avx512_unary_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
7014 X86VectorVTInfo _> :
7015 avx512_unary_rm<opc, OpcodeStr, OpNode, _> {
7017 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7018 (ins _.ScalarMemOp:$src1), OpcodeStr,
7019 "${src1}"##_.BroadcastStr,
7020 "${src1}"##_.BroadcastStr,
7021 (_.VT (OpNode (X86VBroadcast
7022 (_.ScalarLdFrag addr:$src1))))>,
7023 EVEX, AVX5128IBase, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
7026 multiclass avx512_unary_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
7027 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
7028 let Predicates = [prd] in
7029 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
7031 let Predicates = [prd, HasVLX] in {
7032 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
7034 defm Z128 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info128>,
7039 multiclass avx512_unary_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
7040 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
7041 let Predicates = [prd] in
7042 defm Z : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
7045 let Predicates = [prd, HasVLX] in {
7046 defm Z256 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
7048 defm Z128 : avx512_unary_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
7053 multiclass avx512_unary_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
7054 SDNode OpNode, Predicate prd> {
7055 defm Q : avx512_unary_rmb_vl<opc_q, OpcodeStr#"q", OpNode, avx512vl_i64_info,
7057 defm D : avx512_unary_rmb_vl<opc_d, OpcodeStr#"d", OpNode, avx512vl_i32_info,
7061 multiclass avx512_unary_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
7062 SDNode OpNode, Predicate prd> {
7063 defm W : avx512_unary_rm_vl<opc_w, OpcodeStr#"w", OpNode, avx512vl_i16_info, prd>;
7064 defm B : avx512_unary_rm_vl<opc_b, OpcodeStr#"b", OpNode, avx512vl_i8_info, prd>;
7067 multiclass avx512_unary_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
7068 bits<8> opc_d, bits<8> opc_q,
7069 string OpcodeStr, SDNode OpNode> {
7070 defm NAME : avx512_unary_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
7072 avx512_unary_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
7076 defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", X86Abs>;
7079 (bc_v16i32 (v16i1sextv16i32)),
7080 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
7081 (VPABSDZrr VR512:$src)>;
7083 (bc_v8i64 (v8i1sextv8i64)),
7084 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
7085 (VPABSQZrr VR512:$src)>;
7087 multiclass avx512_ctlz<bits<8> opc, string OpcodeStr, Predicate prd>{
7089 defm NAME : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr, ctlz, prd>;
7090 let isCodeGenOnly = 1 in
7091 defm NAME#_UNDEF : avx512_unary_rm_vl_dq<opc, opc, OpcodeStr,
7092 ctlz_zero_undef, prd>;
7095 defm VPLZCNT : avx512_ctlz<0x44, "vplzcnt", HasCDI>;
7096 defm VPCONFLICT : avx512_unary_rm_vl_dq<0xC4, 0xC4, "vpconflict", X86Conflict, HasCDI>;
7098 //===---------------------------------------------------------------------===//
7099 // Replicate Single FP - MOVSHDUP and MOVSLDUP
7100 //===---------------------------------------------------------------------===//
7101 multiclass avx512_replicate<bits<8> opc, string OpcodeStr, SDNode OpNode>{
7102 defm NAME: avx512_unary_rm_vl<opc, OpcodeStr, OpNode, avx512vl_f32_info,
7104 let isCodeGenOnly = 1 in
7105 defm NAME#_I: avx512_unary_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
7109 defm VMOVSHDUP : avx512_replicate<0x16, "vmovshdup", X86Movshdup>;
7110 defm VMOVSLDUP : avx512_replicate<0x12, "vmovsldup", X86Movsldup>;
7112 //===----------------------------------------------------------------------===//
7113 // AVX-512 - MOVDDUP
7114 //===----------------------------------------------------------------------===//
7116 multiclass avx512_movddup_128<bits<8> opc, string OpcodeStr, SDNode OpNode,
7117 X86VectorVTInfo _> {
7118 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
7119 (ins _.RC:$src), OpcodeStr, "$src", "$src",
7120 (_.VT (OpNode (_.VT _.RC:$src)))>, EVEX;
7122 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
7123 (ins _.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
7124 (_.VT (OpNode (_.VT (scalar_to_vector
7125 (_.ScalarLdFrag addr:$src)))))>,
7126 EVEX, EVEX_CD8<_.EltSize, CD8VH>;
7129 multiclass avx512_movddup_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
7130 AVX512VLVectorVTInfo VTInfo> {
7132 defm Z : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info512>, EVEX_V512;
7134 let Predicates = [HasAVX512, HasVLX] in {
7135 defm Z256 : avx512_unary_rm<opc, OpcodeStr, OpNode, VTInfo.info256>,
7137 defm Z128 : avx512_movddup_128<opc, OpcodeStr, OpNode, VTInfo.info128>,
7142 multiclass avx512_movddup<bits<8> opc, string OpcodeStr, SDNode OpNode>{
7143 defm NAME: avx512_movddup_common<opc, OpcodeStr, OpNode,
7144 avx512vl_f64_info>, XD, VEX_W;
7145 let isCodeGenOnly = 1 in
7146 defm NAME#_I: avx512_movddup_common<opc, OpcodeStr, OpNode,
7150 defm VMOVDDUP : avx512_movddup<0x12, "vmovddup", X86Movddup>;
7152 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
7153 (VMOVDDUPZ128rm addr:$src)>, Requires<[HasAVX512, HasVLX]>;
7154 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
7155 (VMOVDDUPZ128rm addr:$src)>, Requires<[HasAVX512, HasVLX]>;
7157 //===----------------------------------------------------------------------===//
7158 // AVX-512 - Unpack Instructions
7159 //===----------------------------------------------------------------------===//
7160 defm VUNPCKH : avx512_fp_binop_p<0x15, "vunpckh", X86Unpckh>;
7161 defm VUNPCKL : avx512_fp_binop_p<0x14, "vunpckl", X86Unpckl>;
7163 defm VPUNPCKLBW : avx512_binop_rm_vl_b<0x60, "vpunpcklbw", X86Unpckl,
7164 SSE_INTALU_ITINS_P, HasBWI>;
7165 defm VPUNPCKHBW : avx512_binop_rm_vl_b<0x68, "vpunpckhbw", X86Unpckh,
7166 SSE_INTALU_ITINS_P, HasBWI>;
7167 defm VPUNPCKLWD : avx512_binop_rm_vl_w<0x61, "vpunpcklwd", X86Unpckl,
7168 SSE_INTALU_ITINS_P, HasBWI>;
7169 defm VPUNPCKHWD : avx512_binop_rm_vl_w<0x69, "vpunpckhwd", X86Unpckh,
7170 SSE_INTALU_ITINS_P, HasBWI>;
7172 defm VPUNPCKLDQ : avx512_binop_rm_vl_d<0x62, "vpunpckldq", X86Unpckl,
7173 SSE_INTALU_ITINS_P, HasAVX512>;
7174 defm VPUNPCKHDQ : avx512_binop_rm_vl_d<0x6A, "vpunpckhdq", X86Unpckh,
7175 SSE_INTALU_ITINS_P, HasAVX512>;
7176 defm VPUNPCKLQDQ : avx512_binop_rm_vl_q<0x6C, "vpunpcklqdq", X86Unpckl,
7177 SSE_INTALU_ITINS_P, HasAVX512>;
7178 defm VPUNPCKHQDQ : avx512_binop_rm_vl_q<0x6D, "vpunpckhqdq", X86Unpckh,
7179 SSE_INTALU_ITINS_P, HasAVX512>;
7181 //===----------------------------------------------------------------------===//
7182 // AVX-512 - Extract & Insert Integer Instructions
7183 //===----------------------------------------------------------------------===//
7185 multiclass avx512_extract_elt_bw_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7186 X86VectorVTInfo _> {
7188 def mr : AVX512Ii8<opc, MRMDestMem, (outs),
7189 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7190 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7191 [(store (_.EltVT (trunc (assertzext (OpNode (_.VT _.RC:$src1),
7194 EVEX, EVEX_CD8<_.EltSize, CD8VT1>;
7197 multiclass avx512_extract_elt_b<string OpcodeStr, X86VectorVTInfo _> {
7198 let Predicates = [HasBWI] in {
7199 def rr : AVX512Ii8<0x14, MRMDestReg, (outs GR32orGR64:$dst),
7200 (ins _.RC:$src1, u8imm:$src2),
7201 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7202 [(set GR32orGR64:$dst,
7203 (X86pextrb (_.VT _.RC:$src1), imm:$src2))]>,
7206 defm NAME : avx512_extract_elt_bw_m<0x14, OpcodeStr, X86pextrb, _>, TAPD;
7210 multiclass avx512_extract_elt_w<string OpcodeStr, X86VectorVTInfo _> {
7211 let Predicates = [HasBWI] in {
7212 def rr : AVX512Ii8<0xC5, MRMSrcReg, (outs GR32orGR64:$dst),
7213 (ins _.RC:$src1, u8imm:$src2),
7214 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7215 [(set GR32orGR64:$dst,
7216 (X86pextrw (_.VT _.RC:$src1), imm:$src2))]>,
7219 def rr_REV : AVX512Ii8<0x15, MRMDestReg, (outs GR32orGR64:$dst),
7220 (ins _.RC:$src1, u8imm:$src2),
7221 OpcodeStr#".s\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7224 defm NAME : avx512_extract_elt_bw_m<0x15, OpcodeStr, X86pextrw, _>, TAPD;
7228 multiclass avx512_extract_elt_dq<string OpcodeStr, X86VectorVTInfo _,
7229 RegisterClass GRC> {
7230 let Predicates = [HasDQI] in {
7231 def rr : AVX512Ii8<0x16, MRMDestReg, (outs GRC:$dst),
7232 (ins _.RC:$src1, u8imm:$src2),
7233 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7235 (extractelt (_.VT _.RC:$src1), imm:$src2))]>,
7239 def mr : AVX512Ii8<0x16, MRMDestMem, (outs),
7240 (ins _.ScalarMemOp:$dst, _.RC:$src1, u8imm:$src2),
7241 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7242 [(store (extractelt (_.VT _.RC:$src1),
7243 imm:$src2),addr:$dst)]>,
7244 EVEX, EVEX_CD8<_.EltSize, CD8VT1>, TAPD;
7248 defm VPEXTRBZ : avx512_extract_elt_b<"vpextrb", v16i8x_info>;
7249 defm VPEXTRWZ : avx512_extract_elt_w<"vpextrw", v8i16x_info>;
7250 defm VPEXTRDZ : avx512_extract_elt_dq<"vpextrd", v4i32x_info, GR32>;
7251 defm VPEXTRQZ : avx512_extract_elt_dq<"vpextrq", v2i64x_info, GR64>, VEX_W;
7253 multiclass avx512_insert_elt_m<bits<8> opc, string OpcodeStr, SDNode OpNode,
7254 X86VectorVTInfo _, PatFrag LdFrag> {
7255 def rm : AVX512Ii8<opc, MRMSrcMem, (outs _.RC:$dst),
7256 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
7257 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7259 (_.VT (OpNode _.RC:$src1, (LdFrag addr:$src2), imm:$src3)))]>,
7260 EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
7263 multiclass avx512_insert_elt_bw<bits<8> opc, string OpcodeStr, SDNode OpNode,
7264 X86VectorVTInfo _, PatFrag LdFrag> {
7265 let Predicates = [HasBWI] in {
7266 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7267 (ins _.RC:$src1, GR32orGR64:$src2, u8imm:$src3),
7268 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7270 (OpNode _.RC:$src1, GR32orGR64:$src2, imm:$src3))]>, EVEX_4V;
7272 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, OpNode, _, LdFrag>;
7276 multiclass avx512_insert_elt_dq<bits<8> opc, string OpcodeStr,
7277 X86VectorVTInfo _, RegisterClass GRC> {
7278 let Predicates = [HasDQI] in {
7279 def rr : AVX512Ii8<opc, MRMSrcReg, (outs _.RC:$dst),
7280 (ins _.RC:$src1, GRC:$src2, u8imm:$src3),
7281 OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7283 (_.VT (insertelt _.RC:$src1, GRC:$src2, imm:$src3)))]>,
7286 defm NAME : avx512_insert_elt_m<opc, OpcodeStr, insertelt, _,
7287 _.ScalarLdFrag>, TAPD;
7291 defm VPINSRBZ : avx512_insert_elt_bw<0x20, "vpinsrb", X86pinsrb, v16i8x_info,
7293 defm VPINSRWZ : avx512_insert_elt_bw<0xC4, "vpinsrw", X86pinsrw, v8i16x_info,
7295 defm VPINSRDZ : avx512_insert_elt_dq<0x22, "vpinsrd", v4i32x_info, GR32>;
7296 defm VPINSRQZ : avx512_insert_elt_dq<0x22, "vpinsrq", v2i64x_info, GR64>, VEX_W;
7297 //===----------------------------------------------------------------------===//
7298 // VSHUFPS - VSHUFPD Operations
7299 //===----------------------------------------------------------------------===//
7300 multiclass avx512_shufp<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
7301 AVX512VLVectorVTInfo VTInfo_FP>{
7302 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0xC6, X86Shufp>,
7303 EVEX_CD8<VTInfo_FP.info512.EltSize, CD8VF>,
7304 AVX512AIi8Base, EVEX_4V;
7305 let isCodeGenOnly = 1 in {
7306 defm NAME#_I: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0xC6, X86Shufp>,
7307 EVEX_CD8<VTInfo_I.info512.EltSize, CD8VF>,
7308 AVX512AIi8Base, EVEX_4V;
7312 defm VSHUFPS: avx512_shufp<"vshufps", avx512vl_i32_info, avx512vl_f32_info>, PS;
7313 defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_i64_info, avx512vl_f64_info>, PD, VEX_W;
7314 //===----------------------------------------------------------------------===//
7315 // AVX-512 - Byte shift Left/Right
7316 //===----------------------------------------------------------------------===//
7318 multiclass avx512_shift_packed<bits<8> opc, SDNode OpNode, Format MRMr,
7319 Format MRMm, string OpcodeStr, X86VectorVTInfo _>{
7320 def rr : AVX512<opc, MRMr,
7321 (outs _.RC:$dst), (ins _.RC:$src1, u8imm:$src2),
7322 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7323 [(set _.RC:$dst,(_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>;
7325 def rm : AVX512<opc, MRMm,
7326 (outs _.RC:$dst), (ins _.MemOp:$src1, u8imm:$src2),
7327 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7328 [(set _.RC:$dst,(_.VT (OpNode
7329 (_.LdFrag addr:$src1), (i8 imm:$src2))))]>;
7332 multiclass avx512_shift_packed_all<bits<8> opc, SDNode OpNode, Format MRMr,
7333 Format MRMm, string OpcodeStr, Predicate prd>{
7334 let Predicates = [prd] in
7335 defm Z512 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7336 OpcodeStr, v8i64_info>, EVEX_V512;
7337 let Predicates = [prd, HasVLX] in {
7338 defm Z256 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7339 OpcodeStr, v4i64x_info>, EVEX_V256;
7340 defm Z128 : avx512_shift_packed<opc, OpNode, MRMr, MRMm,
7341 OpcodeStr, v2i64x_info>, EVEX_V128;
7344 defm VPSLLDQ : avx512_shift_packed_all<0x73, X86vshldq, MRM7r, MRM7m, "vpslldq",
7345 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7346 defm VPSRLDQ : avx512_shift_packed_all<0x73, X86vshrdq, MRM3r, MRM3m, "vpsrldq",
7347 HasBWI>, AVX512PDIi8Base, EVEX_4V;
7350 multiclass avx512_psadbw_packed<bits<8> opc, SDNode OpNode,
7351 string OpcodeStr, X86VectorVTInfo _src>{
7352 def rr : AVX512BI<opc, MRMSrcReg,
7353 (outs _src.RC:$dst), (ins _src.RC:$src1, _src.RC:$src2),
7354 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7355 [(set _src.RC:$dst,(_src.VT
7356 (OpNode _src.RC:$src1, _src.RC:$src2)))]>;
7358 def rm : AVX512BI<opc, MRMSrcMem,
7359 (outs _src.RC:$dst), (ins _src.RC:$src1, _src.MemOp:$src2),
7360 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7361 [(set _src.RC:$dst,(_src.VT
7362 (OpNode _src.RC:$src1,
7363 (_src.VT (bitconvert
7364 (_src.LdFrag addr:$src2))))))]>;
7367 multiclass avx512_psadbw_packed_all<bits<8> opc, SDNode OpNode,
7368 string OpcodeStr, Predicate prd> {
7369 let Predicates = [prd] in
7370 defm Z512 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v64i8_info>,
7372 let Predicates = [prd, HasVLX] in {
7373 defm Z256 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v32i8x_info>,
7375 defm Z128 : avx512_psadbw_packed<opc, OpNode, OpcodeStr, v16i8x_info>,
7380 defm VPSADBW : avx512_psadbw_packed_all<0xf6, X86psadbw, "vpsadbw",
7383 multiclass avx512_ternlog<bits<8> opc, string OpcodeStr, SDNode OpNode,
7385 let Constraints = "$src1 = $dst" in {
7386 defm rri : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
7387 (ins _.RC:$src2, _.RC:$src3, u8imm:$src4),
7388 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src3",
7389 (OpNode (_.VT _.RC:$src1),
7392 (i8 imm:$src4))>, AVX512AIi8Base, EVEX_4V;
7393 let mayLoad = 1 in {
7394 defm rmi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7395 (ins _.RC:$src2, _.MemOp:$src3, u8imm:$src4),
7396 OpcodeStr, "$src4, $src3, $src2", "$src2, $src3, $src3",
7397 (OpNode (_.VT _.RC:$src1),
7399 (_.VT (bitconvert (_.LdFrag addr:$src3))),
7401 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7402 defm rmbi : AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
7403 (ins _.RC:$src2, _.ScalarMemOp:$src3, u8imm:$src4),
7404 OpcodeStr, "$src4, ${src3}"##_.BroadcastStr##", $src2",
7405 "$src2, ${src3}"##_.BroadcastStr##", $src4",
7406 (OpNode (_.VT _.RC:$src1),
7408 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src3))),
7409 (i8 imm:$src4))>, EVEX_B,
7410 AVX512AIi8Base, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
7412 }// Constraints = "$src1 = $dst"
7415 multiclass avx512_common_ternlog<string OpcodeStr, AVX512VLVectorVTInfo _>{
7416 let Predicates = [HasAVX512] in
7417 defm Z : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info512>, EVEX_V512;
7418 let Predicates = [HasAVX512, HasVLX] in {
7419 defm Z128 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info128>, EVEX_V128;
7420 defm Z256 : avx512_ternlog<0x25, OpcodeStr, X86vpternlog, _.info256>, EVEX_V256;
7424 defm VPTERNLOGD : avx512_common_ternlog<"vpternlogd", avx512vl_i32_info>;
7425 defm VPTERNLOGQ : avx512_common_ternlog<"vpternlogq", avx512vl_i64_info>, VEX_W;