1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 AVX512 instruction set, defining the
11 // instructions, and properties of the instructions which are needed for code
12 // generation, machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Group template arguments that can be derived from the vector type (EltNum x
17 // EltVT). These are things like the register class for the writemask, etc.
18 // The idea is to pass one of these as the template argument rather than the
19 // individual arguments.
20 // The template is also used for scalar types, in this case numelts is 1.
21 class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
23 RegisterClass RC = rc;
24 ValueType EltVT = eltvt;
25 int NumElts = numelts;
27 // Corresponding mask register class.
28 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
30 // Corresponding write-mask register class.
31 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
33 // The GPR register class that can hold the write mask. Use GR8 for fewer
34 // than 8 elements. Use shift-right and equal to work around the lack of
37 !cast<RegisterClass>("GR" #
38 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
40 // Suffix used in the instruction mnemonic.
41 string Suffix = suffix;
43 // VTName is a string name for vector VT. For vector types it will be
44 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
45 // It is a little bit complex for scalar types, where NumElts = 1.
46 // In this case we build v4f32 or v2f64
47 string VTName = "v" # !if (!eq (NumElts, 1),
48 !if (!eq (EltVT.Size, 32), 4,
49 !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts) # EltVT;
52 ValueType VT = !cast<ValueType>(VTName);
54 string EltTypeName = !cast<string>(EltVT);
55 // Size of the element type in bits, e.g. 32 for v16i32.
56 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
57 int EltSize = EltVT.Size;
59 // "i" for integer types and "f" for floating-point types
60 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
62 // Size of RC in bits, e.g. 512 for VR512.
65 // The corresponding memory operand, e.g. i512mem for VR512.
66 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
67 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
70 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
71 // due to load promotion during legalization
72 PatFrag LdFrag = !cast<PatFrag>("load" #
73 !if (!eq (TypeVariantName, "i"),
74 !if (!eq (Size, 128), "v2i64",
75 !if (!eq (Size, 256), "v4i64",
78 PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
79 !if (!eq (TypeVariantName, "i"),
80 !if (!eq (Size, 128), "v2i64",
81 !if (!eq (Size, 256), "v4i64",
83 !if (!eq (EltSize, 64), "v8i64", "v16i32"),
86 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
88 // The corresponding float type, e.g. v16f32 for v16i32
89 // Note: For EltSize < 32, FloatVT is illegal and TableGen
90 // fails to compile, so we choose FloatVT = VT
91 ValueType FloatVT = !cast<ValueType>(
92 !if (!eq (!srl(EltSize,5),0),
94 !if (!eq(TypeVariantName, "i"),
95 "v" # NumElts # "f" # EltSize,
98 // The string to specify embedded broadcast in assembly.
99 string BroadcastStr = "{1to" # NumElts # "}";
101 // 8-bit compressed displacement tuple/subvector format. This is only
102 // defined for NumElts <= 8.
103 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
104 !cast<CD8VForm>("CD8VT" # NumElts), ?);
106 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
107 !if (!eq (Size, 256), sub_ymm, ?));
109 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
110 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
113 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
115 // A vector type of the same width with element type i32. This is used to
116 // create the canonical constant zero node ImmAllZerosV.
117 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
118 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
120 string ZSuffix = !if (!eq (Size, 128), "Z128",
121 !if (!eq (Size, 256), "Z256", "Z"));
124 def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
125 def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
126 def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
127 def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
128 def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
129 def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
131 // "x" in v32i8x_info means RC = VR256X
132 def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
133 def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
134 def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
135 def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
136 def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
137 def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
139 def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
140 def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
141 def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
142 def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
143 def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
144 def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
146 // We map scalar types to the smallest (128-bit) vector type
147 // with the appropriate element type. This allows to use the same masking logic.
148 def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
149 def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
151 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
152 X86VectorVTInfo i128> {
153 X86VectorVTInfo info512 = i512;
154 X86VectorVTInfo info256 = i256;
155 X86VectorVTInfo info128 = i128;
158 def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
160 def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
162 def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
164 def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
166 def avx512vl_f32_info : AVX512VLVectorVTInfo<v16f32_info, v8f32x_info,
168 def avx512vl_f64_info : AVX512VLVectorVTInfo<v8f64_info, v4f64x_info,
171 // This multiclass generates the masking variants from the non-masking
172 // variant. It only provides the assembly pieces for the masking variants.
173 // It assumes custom ISel patterns for masking which can be provided as
174 // template arguments.
175 multiclass AVX512_maskable_custom<bits<8> O, Format F,
177 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
179 string AttSrcAsm, string IntelSrcAsm,
181 list<dag> MaskingPattern,
182 list<dag> ZeroMaskingPattern,
183 string MaskingConstraint = "",
184 InstrItinClass itin = NoItinerary,
185 bit IsCommutable = 0> {
186 let isCommutable = IsCommutable in
187 def NAME: AVX512<O, F, Outs, Ins,
188 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
189 "$dst , "#IntelSrcAsm#"}",
192 // Prefer over VMOV*rrk Pat<>
193 let AddedComplexity = 20 in
194 def NAME#k: AVX512<O, F, Outs, MaskingIns,
195 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
196 "$dst {${mask}}, "#IntelSrcAsm#"}",
197 MaskingPattern, itin>,
199 // In case of the 3src subclass this is overridden with a let.
200 string Constraints = MaskingConstraint;
202 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
203 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
204 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
205 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
212 // Common base class of AVX512_maskable and AVX512_maskable_3src.
213 multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
215 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
217 string AttSrcAsm, string IntelSrcAsm,
218 dag RHS, dag MaskingRHS,
219 SDNode Select = vselect,
220 string MaskingConstraint = "",
221 InstrItinClass itin = NoItinerary,
222 bit IsCommutable = 0> :
223 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
224 AttSrcAsm, IntelSrcAsm,
225 [(set _.RC:$dst, RHS)],
226 [(set _.RC:$dst, MaskingRHS)],
228 (Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
229 MaskingConstraint, NoItinerary, IsCommutable>;
231 // This multiclass generates the unconditional/non-masking, the masking and
232 // the zero-masking variant of the vector instruction. In the masking case, the
233 // perserved vector elements come from a new dummy input operand tied to $dst.
234 multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
235 dag Outs, dag Ins, string OpcodeStr,
236 string AttSrcAsm, string IntelSrcAsm,
238 InstrItinClass itin = NoItinerary,
239 bit IsCommutable = 0> :
240 AVX512_maskable_common<O, F, _, Outs, Ins,
241 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
242 !con((ins _.KRCWM:$mask), Ins),
243 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
244 (vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
245 "$src0 = $dst", itin, IsCommutable>;
247 // This multiclass generates the unconditional/non-masking, the masking and
248 // the zero-masking variant of the scalar instruction.
249 multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
250 dag Outs, dag Ins, string OpcodeStr,
251 string AttSrcAsm, string IntelSrcAsm,
253 InstrItinClass itin = NoItinerary,
254 bit IsCommutable = 0> :
255 AVX512_maskable_common<O, F, _, Outs, Ins,
256 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
257 !con((ins _.KRCWM:$mask), Ins),
258 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
259 (X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
260 "$src0 = $dst", itin, IsCommutable>;
262 // Similar to AVX512_maskable but in this case one of the source operands
263 // ($src1) is already tied to $dst so we just use that for the preserved
264 // vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
266 multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
267 dag Outs, dag NonTiedIns, string OpcodeStr,
268 string AttSrcAsm, string IntelSrcAsm,
270 AVX512_maskable_common<O, F, _, Outs,
271 !con((ins _.RC:$src1), NonTiedIns),
272 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
273 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
274 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
275 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
278 multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
281 string AttSrcAsm, string IntelSrcAsm,
283 AVX512_maskable_custom<O, F, Outs, Ins,
284 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
285 !con((ins _.KRCWM:$mask), Ins),
286 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
290 // Instruction with mask that puts result in mask register,
291 // like "compare" and "vptest"
292 multiclass AVX512_maskable_custom_cmp<bits<8> O, Format F,
294 dag Ins, dag MaskingIns,
296 string AttSrcAsm, string IntelSrcAsm,
298 list<dag> MaskingPattern,
300 InstrItinClass itin = NoItinerary> {
301 def NAME: AVX512<O, F, Outs, Ins,
302 OpcodeStr#"\t{"#AttSrcAsm#", $dst "#Round#"|"#
303 "$dst "#Round#", "#IntelSrcAsm#"}",
306 def NAME#k: AVX512<O, F, Outs, MaskingIns,
307 OpcodeStr#"\t{"#Round#AttSrcAsm#", $dst {${mask}}|"#
308 "$dst {${mask}}, "#IntelSrcAsm#Round#"}",
309 MaskingPattern, itin>, EVEX_K;
312 multiclass AVX512_maskable_common_cmp<bits<8> O, Format F, X86VectorVTInfo _,
314 dag Ins, dag MaskingIns,
316 string AttSrcAsm, string IntelSrcAsm,
317 dag RHS, dag MaskingRHS,
319 InstrItinClass itin = NoItinerary> :
320 AVX512_maskable_custom_cmp<O, F, Outs, Ins, MaskingIns, OpcodeStr,
321 AttSrcAsm, IntelSrcAsm,
322 [(set _.KRC:$dst, RHS)],
323 [(set _.KRC:$dst, MaskingRHS)],
326 multiclass AVX512_maskable_cmp<bits<8> O, Format F, X86VectorVTInfo _,
327 dag Outs, dag Ins, string OpcodeStr,
328 string AttSrcAsm, string IntelSrcAsm,
329 dag RHS, string Round = "",
330 InstrItinClass itin = NoItinerary> :
331 AVX512_maskable_common_cmp<O, F, _, Outs, Ins,
332 !con((ins _.KRCWM:$mask), Ins),
333 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
334 (and _.KRCWM:$mask, RHS),
337 multiclass AVX512_maskable_cmp_alt<bits<8> O, Format F, X86VectorVTInfo _,
338 dag Outs, dag Ins, string OpcodeStr,
339 string AttSrcAsm, string IntelSrcAsm> :
340 AVX512_maskable_custom_cmp<O, F, Outs,
341 Ins, !con((ins _.KRCWM:$mask),Ins), OpcodeStr,
342 AttSrcAsm, IntelSrcAsm,
343 [],[],"", NoItinerary>;
345 // Bitcasts between 512-bit vector types. Return the original type since
346 // no instruction is needed for the conversion
347 let Predicates = [HasAVX512] in {
348 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
349 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
350 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
351 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
352 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
353 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
354 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
355 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
356 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
357 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
358 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
359 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
360 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
361 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
362 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
363 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
364 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
365 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
366 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
367 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
368 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
369 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
370 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
371 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
372 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
373 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
374 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
375 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
376 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
377 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
378 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
380 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
381 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
382 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
383 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
384 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
385 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
386 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
387 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
388 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
389 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
390 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
391 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
392 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
393 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
394 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
395 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
396 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
397 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
398 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
399 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
400 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
401 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
402 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
403 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
404 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
405 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
406 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
407 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
408 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
409 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
411 // Bitcasts between 256-bit vector types. Return the original type since
412 // no instruction is needed for the conversion
413 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
414 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
415 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
416 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
417 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
418 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
419 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
420 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
421 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
422 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
423 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
424 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
425 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
426 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
427 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
428 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
429 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
430 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
431 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
432 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
433 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
434 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
435 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
436 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
437 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
438 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
439 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
440 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
441 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
442 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
446 // AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
449 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
450 isPseudo = 1, Predicates = [HasAVX512] in {
451 def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
452 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
455 let Predicates = [HasAVX512] in {
456 def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
457 def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
458 def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
461 //===----------------------------------------------------------------------===//
462 // AVX-512 - VECTOR INSERT
465 multiclass vinsert_for_size_no_alt<int Opcode,
466 X86VectorVTInfo From, X86VectorVTInfo To,
467 PatFrag vinsert_insert,
468 SDNodeXForm INSERT_get_vinsert_imm> {
469 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
470 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
471 (ins VR512:$src1, From.RC:$src2, u8imm:$src3),
472 "vinsert" # From.EltTypeName # "x" # From.NumElts #
473 "\t{$src3, $src2, $src1, $dst|"
474 "$dst, $src1, $src2, $src3}",
475 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
476 (From.VT From.RC:$src2),
481 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
482 (ins VR512:$src1, From.MemOp:$src2, u8imm:$src3),
483 "vinsert" # From.EltTypeName # "x" # From.NumElts #
484 "\t{$src3, $src2, $src1, $dst|"
485 "$dst, $src1, $src2, $src3}",
487 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
491 multiclass vinsert_for_size<int Opcode,
492 X86VectorVTInfo From, X86VectorVTInfo To,
493 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
494 PatFrag vinsert_insert,
495 SDNodeXForm INSERT_get_vinsert_imm> :
496 vinsert_for_size_no_alt<Opcode, From, To,
497 vinsert_insert, INSERT_get_vinsert_imm> {
498 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
499 // vinserti32x4. Only add this if 64x2 and friends are not supported
500 // natively via AVX512DQ.
501 let Predicates = [NoDQI] in
502 def : Pat<(vinsert_insert:$ins
503 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
504 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
505 VR512:$src1, From.RC:$src2,
506 (INSERT_get_vinsert_imm VR512:$ins)))>;
509 multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
510 ValueType EltVT64, int Opcode256> {
511 defm NAME # "32x4" : vinsert_for_size<Opcode128,
512 X86VectorVTInfo< 4, EltVT32, VR128X>,
513 X86VectorVTInfo<16, EltVT32, VR512>,
514 X86VectorVTInfo< 2, EltVT64, VR128X>,
515 X86VectorVTInfo< 8, EltVT64, VR512>,
517 INSERT_get_vinsert128_imm>;
518 let Predicates = [HasDQI] in
519 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
520 X86VectorVTInfo< 2, EltVT64, VR128X>,
521 X86VectorVTInfo< 8, EltVT64, VR512>,
523 INSERT_get_vinsert128_imm>, VEX_W;
524 defm NAME # "64x4" : vinsert_for_size<Opcode256,
525 X86VectorVTInfo< 4, EltVT64, VR256X>,
526 X86VectorVTInfo< 8, EltVT64, VR512>,
527 X86VectorVTInfo< 8, EltVT32, VR256>,
528 X86VectorVTInfo<16, EltVT32, VR512>,
530 INSERT_get_vinsert256_imm>, VEX_W;
531 let Predicates = [HasDQI] in
532 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
533 X86VectorVTInfo< 8, EltVT32, VR256X>,
534 X86VectorVTInfo<16, EltVT32, VR512>,
536 INSERT_get_vinsert256_imm>;
539 defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
540 defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
542 // vinsertps - insert f32 to XMM
543 def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
544 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
545 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
546 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
548 def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
549 (ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
550 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
551 [(set VR128X:$dst, (X86insertps VR128X:$src1,
552 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
553 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
555 //===----------------------------------------------------------------------===//
556 // AVX-512 VECTOR EXTRACT
559 multiclass vextract_for_size<int Opcode,
560 X86VectorVTInfo From, X86VectorVTInfo To,
561 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
562 PatFrag vextract_extract,
563 SDNodeXForm EXTRACT_get_vextract_imm> {
564 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
565 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
566 (ins VR512:$src1, u8imm:$idx),
567 "vextract" # To.EltTypeName # "x4",
568 "$idx, $src1", "$src1, $idx",
569 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
571 AVX512AIi8Base, EVEX, EVEX_V512;
573 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
574 (ins To.MemOp:$dst, VR512:$src1, u8imm:$src2),
575 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
576 "$dst, $src1, $src2}",
577 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
580 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
582 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
583 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
585 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
587 // A 128/256-bit subvector extract from the first 512-bit vector position is
588 // a subregister copy that needs no instruction.
589 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
591 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
593 // And for the alternative types.
594 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
596 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
598 // Intrinsic call with masking.
599 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
601 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
602 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
603 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
604 VR512:$src1, imm:$idx)>;
606 // Intrinsic call with zero-masking.
607 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
609 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
610 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
611 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
612 VR512:$src1, imm:$idx)>;
614 // Intrinsic call without masking.
615 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
617 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
618 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
619 VR512:$src1, imm:$idx)>;
622 multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
623 ValueType EltVT64, int Opcode64> {
624 defm NAME # "32x4" : vextract_for_size<Opcode32,
625 X86VectorVTInfo<16, EltVT32, VR512>,
626 X86VectorVTInfo< 4, EltVT32, VR128X>,
627 X86VectorVTInfo< 8, EltVT64, VR512>,
628 X86VectorVTInfo< 2, EltVT64, VR128X>,
630 EXTRACT_get_vextract128_imm>;
631 defm NAME # "64x4" : vextract_for_size<Opcode64,
632 X86VectorVTInfo< 8, EltVT64, VR512>,
633 X86VectorVTInfo< 4, EltVT64, VR256X>,
634 X86VectorVTInfo<16, EltVT32, VR512>,
635 X86VectorVTInfo< 8, EltVT32, VR256>,
637 EXTRACT_get_vextract256_imm>, VEX_W;
640 defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
641 defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
643 // A 128-bit subvector insert to the first 512-bit vector position
644 // is a subregister copy that needs no instruction.
645 def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
646 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
647 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
649 def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
650 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
651 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
653 def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
654 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
655 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
657 def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
658 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
659 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
662 def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
663 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
664 def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
665 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
666 def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
667 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
668 def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
669 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
671 // vextractps - extract 32 bits from XMM
672 def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
673 (ins VR128X:$src1, u8imm:$src2),
674 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
675 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
678 def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
679 (ins f32mem:$dst, VR128X:$src1, u8imm:$src2),
680 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
681 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
682 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
684 //===---------------------------------------------------------------------===//
687 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
688 ValueType svt, X86VectorVTInfo _> {
689 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
690 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
691 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
695 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
696 (ins _.ScalarMemOp:$src),
697 "vbroadcast"##!subst("p", "s", _.Suffix), "$src", "$src",
698 (_.VT (OpNode (_.ScalarLdFrag addr:$src)))>,
703 multiclass avx512_fp_broadcast_vl<bits<8> opc, SDNode OpNode,
704 AVX512VLVectorVTInfo _> {
705 defm Z : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info512>,
708 let Predicates = [HasVLX] in {
709 defm Z256 : avx512_fp_broadcast<opc, OpNode, VR128X, _.info128.VT, _.info256>,
714 let ExeDomain = SSEPackedSingle in {
715 defm VBROADCASTSS : avx512_fp_broadcast_vl<0x18, X86VBroadcast,
716 avx512vl_f32_info>, EVEX_CD8<32, CD8VT1>;
717 let Predicates = [HasVLX] in {
718 defm VBROADCASTSSZ128 : avx512_fp_broadcast<0x18, X86VBroadcast, VR128X,
719 v4f32, v4f32x_info>, EVEX_V128,
720 EVEX_CD8<32, CD8VT1>;
724 let ExeDomain = SSEPackedDouble in {
725 defm VBROADCASTSD : avx512_fp_broadcast_vl<0x19, X86VBroadcast,
726 avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;
729 // avx512_broadcast_pat introduces patterns for broadcast with a scalar argument.
730 // Later, we can canonize broadcast instructions before ISel phase and
731 // eliminate additional patterns on ISel.
732 // SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar
733 // representations of source
734 multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,
735 X86VectorVTInfo _, RegisterClass SrcRC_v,
736 RegisterClass SrcRC_s> {
737 def : Pat<(_.VT (OpNode (_.EltVT SrcRC_s:$src))),
738 (!cast<Instruction>(InstName##"r")
739 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
741 let AddedComplexity = 30 in {
742 def : Pat<(_.VT (vselect _.KRCWM:$mask,
743 (OpNode (_.EltVT SrcRC_s:$src)), _.RC:$src0)),
744 (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,
745 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
747 def : Pat<(_.VT(vselect _.KRCWM:$mask,
748 (OpNode (_.EltVT SrcRC_s:$src)), _.ImmAllZerosV)),
749 (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,
750 (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;
754 defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,
756 defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,
759 let Predicates = [HasVLX] in {
760 defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,
761 v8f32x_info, VR128X, FR32X>;
762 defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,
763 v4f32x_info, VR128X, FR32X>;
764 defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,
765 v4f64x_info, VR128X, FR64X>;
768 def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
769 (VBROADCASTSSZm addr:$src)>;
770 def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
771 (VBROADCASTSDZm addr:$src)>;
773 def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
774 (VBROADCASTSSZm addr:$src)>;
775 def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
776 (VBROADCASTSDZm addr:$src)>;
778 multiclass avx512_int_broadcast_reg<bits<8> opc, X86VectorVTInfo _,
779 RegisterClass SrcRC> {
780 defm r : AVX512_maskable_in_asm<opc, MRMSrcReg, _, (outs _.RC:$dst),
781 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
782 "$src", "$src", []>, T8PD, EVEX;
785 multiclass avx512_int_broadcast_reg_vl<bits<8> opc, AVX512VLVectorVTInfo _,
786 RegisterClass SrcRC, Predicate prd> {
787 let Predicates = [prd] in
788 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
789 let Predicates = [prd, HasVLX] in {
790 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
791 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
795 defm VPBROADCASTBr : avx512_int_broadcast_reg_vl<0x7A, avx512vl_i8_info, GR32,
797 defm VPBROADCASTWr : avx512_int_broadcast_reg_vl<0x7B, avx512vl_i16_info, GR32,
799 defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, GR32,
801 defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, GR64,
804 def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
805 (VPBROADCASTDrZrkz VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
807 def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
808 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
810 def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
811 (VPBROADCASTDrZr GR32:$src)>;
812 def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
813 (VPBROADCASTQrZr GR64:$src)>;
815 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
816 (VPBROADCASTDrZr GR32:$src)>;
817 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
818 (VPBROADCASTQrZr GR64:$src)>;
820 def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
821 (v16i32 immAllZerosV), (i16 GR16:$mask))),
822 (VPBROADCASTDrZrkz (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
823 def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
824 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
825 (VPBROADCASTQrZrkz (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
827 multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
828 X86MemOperand x86memop, PatFrag ld_frag,
829 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
831 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
832 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
834 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
835 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
837 !strconcat(OpcodeStr,
838 "\t{$src, ${dst} {${mask}} |${dst} {${mask}}, $src}"),
840 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
842 !strconcat(OpcodeStr,
843 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
846 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
847 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
849 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
850 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
852 !strconcat(OpcodeStr,
853 "\t{$src, ${dst} {${mask}}|${dst} {${mask}} , $src}"),
855 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
857 !strconcat(OpcodeStr,
858 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
859 [(set DstRC:$dst, (OpVT (vselect KRC:$mask,
860 (X86VBroadcast (ld_frag addr:$src)),
861 (OpVT (bitconvert (v16i32 immAllZerosV))))))]>, EVEX, EVEX_KZ;
865 defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
866 loadi32, VR512, v16i32, v4i32, VK16WM>,
867 EVEX_V512, EVEX_CD8<32, CD8VT1>;
868 defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
869 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
870 EVEX_CD8<64, CD8VT1>;
872 multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
873 X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
875 def rm : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Src.MemOp:$src),
876 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
878 (_Dst.VT (X86SubVBroadcast
879 (_Src.VT (bitconvert (_Src.LdFrag addr:$src))))))]>, EVEX;
880 def rmk : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
882 !strconcat(OpcodeStr,
883 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
885 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _Dst.RC:$dst), (ins _Dst.KRCWM:$mask,
887 !strconcat(OpcodeStr,
888 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
893 defm VBROADCASTI32X4 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
894 v16i32_info, v4i32x_info>,
895 EVEX_V512, EVEX_CD8<32, CD8VT4>;
896 defm VBROADCASTF32X4 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
897 v16f32_info, v4f32x_info>,
898 EVEX_V512, EVEX_CD8<32, CD8VT4>;
899 defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
900 v8i64_info, v4i64x_info>, VEX_W,
901 EVEX_V512, EVEX_CD8<64, CD8VT4>;
902 defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4",
903 v8f64_info, v4f64x_info>, VEX_W,
904 EVEX_V512, EVEX_CD8<64, CD8VT4>;
906 let Predicates = [HasVLX] in {
907 defm VBROADCASTI32X4Z256 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
908 v8i32x_info, v4i32x_info>,
909 EVEX_V256, EVEX_CD8<32, CD8VT4>;
910 defm VBROADCASTF32X4Z256 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf32x4",
911 v8f32x_info, v4f32x_info>,
912 EVEX_V256, EVEX_CD8<32, CD8VT4>;
914 let Predicates = [HasVLX, HasDQI] in {
915 defm VBROADCASTI64X2Z128 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
916 v4i64x_info, v2i64x_info>, VEX_W,
917 EVEX_V256, EVEX_CD8<64, CD8VT2>;
918 defm VBROADCASTF64X2Z128 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
919 v4f64x_info, v2f64x_info>, VEX_W,
920 EVEX_V256, EVEX_CD8<64, CD8VT2>;
922 let Predicates = [HasDQI] in {
923 defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm<0x5a, "vbroadcasti64x2",
924 v8i64_info, v2i64x_info>, VEX_W,
925 EVEX_V512, EVEX_CD8<64, CD8VT2>;
926 defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti32x8",
927 v16i32_info, v8i32x_info>,
928 EVEX_V512, EVEX_CD8<32, CD8VT8>;
929 defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm<0x1a, "vbroadcastf64x2",
930 v8f64_info, v2f64x_info>, VEX_W,
931 EVEX_V512, EVEX_CD8<64, CD8VT2>;
932 defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf32x8",
933 v16f32_info, v8f32x_info>,
934 EVEX_V512, EVEX_CD8<32, CD8VT8>;
937 def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
938 (VPBROADCASTDZrr VR128X:$src)>;
939 def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
940 (VPBROADCASTQZrr VR128X:$src)>;
942 def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
943 (VBROADCASTSSZr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
944 def : Pat<(v16f32 (X86VBroadcast (v8f32 VR256X:$src))),
945 (VBROADCASTSSZr (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm))>;
947 def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
948 (VBROADCASTSDZr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
949 def : Pat<(v8f64 (X86VBroadcast (v4f64 VR256X:$src))),
950 (VBROADCASTSDZr (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm))>;
952 def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
953 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
954 def : Pat<(v16i32 (X86VBroadcast (v8i32 VR256X:$src))),
955 (VPBROADCASTDZrr (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm))>;
957 def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
958 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
959 def : Pat<(v8i64 (X86VBroadcast (v4i64 VR256X:$src))),
960 (VPBROADCASTQZrr (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm))>;
962 def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
963 (VBROADCASTSSZr VR128X:$src)>;
964 def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
965 (VBROADCASTSDZr VR128X:$src)>;
967 // Provide fallback in case the load node that is used in the patterns above
968 // is used by additional users, which prevents the pattern selection.
969 def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
970 (VBROADCASTSSZr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
971 def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
972 (VBROADCASTSDZr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
975 //===----------------------------------------------------------------------===//
976 // AVX-512 BROADCAST MASK TO VECTOR REGISTER
979 multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
981 let Predicates = [HasCDI] in
982 def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
983 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
984 []>, EVEX, EVEX_V512;
986 let Predicates = [HasCDI, HasVLX] in {
987 def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
988 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
989 []>, EVEX, EVEX_V128;
990 def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
991 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
992 []>, EVEX, EVEX_V256;
996 let Predicates = [HasCDI] in {
997 defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
999 defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
1003 //===----------------------------------------------------------------------===//
1006 // -- immediate form --
1007 multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1008 X86VectorVTInfo _> {
1009 let ExeDomain = _.ExeDomain in {
1010 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
1011 (ins _.RC:$src1, u8imm:$src2),
1012 !strconcat(OpcodeStr,
1013 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1015 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
1017 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
1018 (ins _.MemOp:$src1, u8imm:$src2),
1019 !strconcat(OpcodeStr,
1020 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1022 (_.VT (OpNode (_.LdFrag addr:$src1),
1023 (i8 imm:$src2))))]>,
1024 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
1028 multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
1029 X86VectorVTInfo Ctrl> :
1030 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
1031 let ExeDomain = _.ExeDomain in {
1032 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
1033 (ins _.RC:$src1, _.RC:$src2),
1034 !strconcat("vpermil" # _.Suffix,
1035 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1037 (_.VT (X86VPermilpv _.RC:$src1,
1038 (Ctrl.VT Ctrl.RC:$src2))))]>,
1040 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
1041 (ins _.RC:$src1, Ctrl.MemOp:$src2),
1042 !strconcat("vpermil" # _.Suffix,
1043 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1045 (_.VT (X86VPermilpv _.RC:$src1,
1046 (Ctrl.VT (Ctrl.LdFrag addr:$src2)))))]>,
1050 defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
1052 defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
1055 def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
1056 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1057 def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
1058 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1060 // -- VPERM2I - 3 source operands form --
1061 multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr,
1062 X86VectorVTInfo _> {
1063 let Constraints = "$src1 = $dst" in {
1064 defm rr: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
1065 (ins _.RC:$src2, _.RC:$src3),
1066 OpcodeStr, "$src3, $src2", "$src2, $src3",
1067 (_.VT (X86VPermiv3 _.RC:$src1, _.RC:$src2, _.RC:$src3))>, EVEX_4V,
1071 defm rm: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1072 (ins _.RC:$src2, _.MemOp:$src3),
1073 OpcodeStr, "$src3, $src2", "$src2, $src3",
1074 (_.VT (X86VPermiv3 _.RC:$src1, _.RC:$src2,
1075 (_.VT (bitconvert (_.LdFrag addr:$src3)))))>,
1076 EVEX_4V, AVX5128IBase;
1079 multiclass avx512_perm_3src_mb<bits<8> opc, string OpcodeStr,
1080 X86VectorVTInfo _> {
1081 let mayLoad = 1, Constraints = "$src1 = $dst" in
1082 defm rmb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
1083 (ins _.RC:$src2, _.ScalarMemOp:$src3),
1084 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
1085 !strconcat("$src2, ${src3}", _.BroadcastStr ),
1086 (_.VT (X86VPermiv3 _.RC:$src1,
1087 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))>,
1088 AVX5128IBase, EVEX_4V, EVEX_B;
1091 multiclass avx512_perm_3src_sizes<bits<8> opc, string OpcodeStr,
1092 AVX512VLVectorVTInfo VTInfo> {
1093 let Predicates = [HasAVX512] in
1094 defm NAME: avx512_perm_3src<opc, OpcodeStr, VTInfo.info512>,
1095 avx512_perm_3src_mb<opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1096 let Predicates = [HasVLX] in {
1097 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, VTInfo.info128>,
1098 avx512_perm_3src_mb<opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1099 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, VTInfo.info256>,
1100 avx512_perm_3src_mb<opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1103 multiclass avx512_perm_3src_sizes_w<bits<8> opc, string OpcodeStr,
1104 AVX512VLVectorVTInfo VTInfo> {
1105 let Predicates = [HasBWI] in
1106 defm NAME: avx512_perm_3src<opc, OpcodeStr, VTInfo.info512>,
1107 avx512_perm_3src_mb<opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1108 let Predicates = [HasBWI, HasVLX] in {
1109 defm NAME#128: avx512_perm_3src<opc, OpcodeStr, VTInfo.info128>,
1110 avx512_perm_3src_mb<opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1111 defm NAME#256: avx512_perm_3src<opc, OpcodeStr, VTInfo.info256>,
1112 avx512_perm_3src_mb<opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1115 defm VPERMI2D : avx512_perm_3src_sizes<0x76, "vpermi2d", avx512vl_i32_info>,
1116 EVEX_CD8<32, CD8VF>;
1117 defm VPERMI2Q : avx512_perm_3src_sizes<0x76, "vpermi2q", avx512vl_i64_info>,
1118 VEX_W, EVEX_CD8<64, CD8VF>;
1119 defm VPERMI2PS : avx512_perm_3src_sizes<0x77, "vpermi2ps", avx512vl_f32_info>,
1120 EVEX_CD8<32, CD8VF>;
1121 defm VPERMI2PD : avx512_perm_3src_sizes<0x77, "vpermi2pd", avx512vl_f64_info>,
1122 VEX_W, EVEX_CD8<64, CD8VF>;
1124 defm VPERMT2D : avx512_perm_3src_sizes<0x7E, "vpermt2d", avx512vl_i32_info>,
1125 EVEX_CD8<32, CD8VF>;
1126 defm VPERMT2Q : avx512_perm_3src_sizes<0x7E, "vpermt2q", avx512vl_i64_info>,
1127 VEX_W, EVEX_CD8<64, CD8VF>;
1128 defm VPERMT2PS : avx512_perm_3src_sizes<0x7F, "vpermt2ps", avx512vl_f32_info>,
1129 EVEX_CD8<32, CD8VF>;
1130 defm VPERMT2PD : avx512_perm_3src_sizes<0x7F, "vpermt2pd", avx512vl_f64_info>,
1131 VEX_W, EVEX_CD8<64, CD8VF>;
1133 defm VPERMT2W : avx512_perm_3src_sizes_w<0x7D, "vpermt2w", avx512vl_i16_info>,
1134 VEX_W, EVEX_CD8<16, CD8VF>;
1135 defm VPERMI2W : avx512_perm_3src_sizes_w<0x75, "vpermi2w", avx512vl_i16_info>,
1136 VEX_W, EVEX_CD8<16, CD8VF>;
1138 //===----------------------------------------------------------------------===//
1139 // AVX-512 - BLEND using mask
1141 multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1142 let ExeDomain = _.ExeDomain in {
1143 def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1144 (ins _.RC:$src1, _.RC:$src2),
1145 !strconcat(OpcodeStr,
1146 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1148 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1149 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1150 !strconcat(OpcodeStr,
1151 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1152 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1153 (_.VT _.RC:$src2)))]>, EVEX_4V, EVEX_K;
1154 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
1155 (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1156 !strconcat(OpcodeStr,
1157 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1158 []>, EVEX_4V, EVEX_KZ;
1159 let mayLoad = 1 in {
1160 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1161 (ins _.RC:$src1, _.MemOp:$src2),
1162 !strconcat(OpcodeStr,
1163 "\t{$src2, $src1, ${dst} |${dst}, $src1, $src2}"),
1164 []>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
1165 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1166 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1167 !strconcat(OpcodeStr,
1168 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
1169 [(set _.RC:$dst, (X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1170 (_.VT (bitconvert (_.LdFrag addr:$src2)))))]>,
1171 EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
1172 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1173 (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1174 !strconcat(OpcodeStr,
1175 "\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
1176 []>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
1180 multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
1182 def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1183 (ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
1184 !strconcat(OpcodeStr,
1185 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1186 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1187 [(set _.RC:$dst,(X86select _.KRCWM:$mask, (_.VT _.RC:$src1),
1188 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))]>,
1189 EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1191 def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
1192 (ins _.RC:$src1, _.ScalarMemOp:$src2),
1193 !strconcat(OpcodeStr,
1194 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1195 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1196 []>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
1200 multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
1201 AVX512VLVectorVTInfo VTInfo> {
1202 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
1203 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1205 let Predicates = [HasVLX] in {
1206 defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
1207 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1208 defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
1209 avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1213 multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
1214 AVX512VLVectorVTInfo VTInfo> {
1215 let Predicates = [HasBWI] in
1216 defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
1218 let Predicates = [HasBWI, HasVLX] in {
1219 defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
1220 defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
1225 defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
1226 defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
1227 defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
1228 defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
1229 defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
1230 defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
1233 let Predicates = [HasAVX512] in {
1234 def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1235 (v8f32 VR256X:$src2))),
1237 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1238 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1239 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1241 def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1242 (v8i32 VR256X:$src2))),
1244 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1245 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1246 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1248 //===----------------------------------------------------------------------===//
1249 // Compare Instructions
1250 //===----------------------------------------------------------------------===//
1252 // avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1253 multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1254 SDNode OpNode, ValueType VT,
1255 PatFrag ld_frag, string Suffix> {
1256 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1257 (outs VK1:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1258 !strconcat("vcmp${cc}", Suffix,
1259 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1260 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1261 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1262 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1263 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
1264 !strconcat("vcmp${cc}", Suffix,
1265 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1266 [(set VK1:$dst, (OpNode (VT RC:$src1),
1267 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1268 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1269 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1270 (outs VK1:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
1271 !strconcat("vcmp", Suffix,
1272 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1273 [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1275 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1276 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
1277 !strconcat("vcmp", Suffix,
1278 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
1279 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1283 let Predicates = [HasAVX512] in {
1284 defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, X86cmpms, f32, loadf32, "ss">,
1286 defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, X86cmpms, f64, loadf64, "sd">,
1290 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1291 X86VectorVTInfo _> {
1292 def rr : AVX512BI<opc, MRMSrcReg,
1293 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1294 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1295 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1296 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1298 def rm : AVX512BI<opc, MRMSrcMem,
1299 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1300 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1301 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1302 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
1303 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1304 def rrk : AVX512BI<opc, MRMSrcReg,
1305 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1306 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1307 "$dst {${mask}}, $src1, $src2}"),
1308 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1309 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1310 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1312 def rmk : AVX512BI<opc, MRMSrcMem,
1313 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1314 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1315 "$dst {${mask}}, $src1, $src2}"),
1316 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1317 (OpNode (_.VT _.RC:$src1),
1319 (_.LdFrag addr:$src2))))))],
1320 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1323 multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
1324 X86VectorVTInfo _> :
1325 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
1326 let mayLoad = 1 in {
1327 def rmb : AVX512BI<opc, MRMSrcMem,
1328 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1329 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1330 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1331 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1332 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1333 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1334 def rmbk : AVX512BI<opc, MRMSrcMem,
1335 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1336 _.ScalarMemOp:$src2),
1337 !strconcat(OpcodeStr,
1338 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1339 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1340 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1341 (OpNode (_.VT _.RC:$src1),
1343 (_.ScalarLdFrag addr:$src2)))))],
1344 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1348 multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1349 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1350 let Predicates = [prd] in
1351 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1354 let Predicates = [prd, HasVLX] in {
1355 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1357 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1362 multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1363 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1365 let Predicates = [prd] in
1366 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1369 let Predicates = [prd, HasVLX] in {
1370 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1372 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1377 defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1378 avx512vl_i8_info, HasBWI>,
1381 defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1382 avx512vl_i16_info, HasBWI>,
1383 EVEX_CD8<16, CD8VF>;
1385 defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
1386 avx512vl_i32_info, HasAVX512>,
1387 EVEX_CD8<32, CD8VF>;
1389 defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
1390 avx512vl_i64_info, HasAVX512>,
1391 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1393 defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1394 avx512vl_i8_info, HasBWI>,
1397 defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1398 avx512vl_i16_info, HasBWI>,
1399 EVEX_CD8<16, CD8VF>;
1401 defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
1402 avx512vl_i32_info, HasAVX512>,
1403 EVEX_CD8<32, CD8VF>;
1405 defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
1406 avx512vl_i64_info, HasAVX512>,
1407 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1409 def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1410 (COPY_TO_REGCLASS (VPCMPGTDZrr
1411 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1412 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1414 def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
1415 (COPY_TO_REGCLASS (VPCMPEQDZrr
1416 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1417 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1419 multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1420 X86VectorVTInfo _> {
1421 def rri : AVX512AIi8<opc, MRMSrcReg,
1422 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVX512ICC:$cc),
1423 !strconcat("vpcmp${cc}", Suffix,
1424 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1425 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1427 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1429 def rmi : AVX512AIi8<opc, MRMSrcMem,
1430 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVX512ICC:$cc),
1431 !strconcat("vpcmp${cc}", Suffix,
1432 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1433 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1434 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1436 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1437 def rrik : AVX512AIi8<opc, MRMSrcReg,
1438 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1440 !strconcat("vpcmp${cc}", Suffix,
1441 "\t{$src2, $src1, $dst {${mask}}|",
1442 "$dst {${mask}}, $src1, $src2}"),
1443 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1444 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1446 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1448 def rmik : AVX512AIi8<opc, MRMSrcMem,
1449 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1451 !strconcat("vpcmp${cc}", Suffix,
1452 "\t{$src2, $src1, $dst {${mask}}|",
1453 "$dst {${mask}}, $src1, $src2}"),
1454 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1455 (OpNode (_.VT _.RC:$src1),
1456 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1458 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1460 // Accept explicit immediate argument form instead of comparison code.
1461 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1462 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
1463 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1464 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1465 "$dst, $src1, $src2, $cc}"),
1466 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
1468 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
1469 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1470 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1471 "$dst, $src1, $src2, $cc}"),
1472 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1473 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1474 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1476 !strconcat("vpcmp", Suffix,
1477 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1478 "$dst {${mask}}, $src1, $src2, $cc}"),
1479 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1481 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1482 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1484 !strconcat("vpcmp", Suffix,
1485 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1486 "$dst {${mask}}, $src1, $src2, $cc}"),
1487 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1491 multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
1492 X86VectorVTInfo _> :
1493 avx512_icmp_cc<opc, Suffix, OpNode, _> {
1494 def rmib : AVX512AIi8<opc, MRMSrcMem,
1495 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1497 !strconcat("vpcmp${cc}", Suffix,
1498 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1499 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1500 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1501 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1503 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1504 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1505 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1506 _.ScalarMemOp:$src2, AVX512ICC:$cc),
1507 !strconcat("vpcmp${cc}", Suffix,
1508 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1509 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1510 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1511 (OpNode (_.VT _.RC:$src1),
1512 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1514 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1516 // Accept explicit immediate argument form instead of comparison code.
1517 let isAsmParserOnly = 1, hasSideEffects = 0, mayLoad = 1 in {
1518 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1519 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1521 !strconcat("vpcmp", Suffix,
1522 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1523 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1524 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1525 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1526 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1527 _.ScalarMemOp:$src2, u8imm:$cc),
1528 !strconcat("vpcmp", Suffix,
1529 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1530 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1531 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1535 multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1536 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1537 let Predicates = [prd] in
1538 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1540 let Predicates = [prd, HasVLX] in {
1541 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1542 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1546 multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1547 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1548 let Predicates = [prd] in
1549 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1552 let Predicates = [prd, HasVLX] in {
1553 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1555 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1560 defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1561 HasBWI>, EVEX_CD8<8, CD8VF>;
1562 defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1563 HasBWI>, EVEX_CD8<8, CD8VF>;
1565 defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1566 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1567 defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1568 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1570 defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
1571 HasAVX512>, EVEX_CD8<32, CD8VF>;
1572 defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
1573 HasAVX512>, EVEX_CD8<32, CD8VF>;
1575 defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
1576 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1577 defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
1578 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
1580 multiclass avx512_vcmp_common<X86VectorVTInfo _> {
1582 defm rri : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1583 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2,AVXCC:$cc),
1584 "vcmp${cc}"#_.Suffix,
1585 "$src2, $src1", "$src1, $src2",
1586 (X86cmpm (_.VT _.RC:$src1),
1590 let mayLoad = 1 in {
1591 defm rmi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1592 (outs _.KRC:$dst),(ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
1593 "vcmp${cc}"#_.Suffix,
1594 "$src2, $src1", "$src1, $src2",
1595 (X86cmpm (_.VT _.RC:$src1),
1596 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1599 defm rmbi : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
1601 (ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
1602 "vcmp${cc}"#_.Suffix,
1603 "${src2}"##_.BroadcastStr##", $src1",
1604 "$src1, ${src2}"##_.BroadcastStr,
1605 (X86cmpm (_.VT _.RC:$src1),
1606 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
1609 // Accept explicit immediate argument form instead of comparison code.
1610 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1611 defm rri_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1613 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1615 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1617 let mayLoad = 1 in {
1618 defm rmi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1620 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$cc),
1622 "$cc, $src2, $src1", "$src1, $src2, $cc">;
1624 defm rmbi_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcMem, _,
1626 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$cc),
1628 "$cc, ${src2}"##_.BroadcastStr##", $src1",
1629 "$src1, ${src2}"##_.BroadcastStr##", $cc">,EVEX_B;
1634 multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
1635 // comparison code form (VCMP[EQ/LT/LE/...]
1636 defm rrib : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
1637 (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
1638 "vcmp${cc}"#_.Suffix,
1639 "{sae}, $src2, $src1", "$src1, $src2,{sae}",
1640 (X86cmpmRnd (_.VT _.RC:$src1),
1643 (i32 FROUND_NO_EXC))>, EVEX_B;
1645 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1646 defm rrib_alt : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
1648 (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
1650 "$cc,{sae}, $src2, $src1",
1651 "$src1, $src2,{sae}, $cc">, EVEX_B;
1655 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
1656 let Predicates = [HasAVX512] in {
1657 defm Z : avx512_vcmp_common<_.info512>,
1658 avx512_vcmp_sae<_.info512>, EVEX_V512;
1661 let Predicates = [HasAVX512,HasVLX] in {
1662 defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
1663 defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
1667 defm VCMPPD : avx512_vcmp<avx512vl_f64_info>,
1668 AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
1669 defm VCMPPS : avx512_vcmp<avx512vl_f32_info>,
1670 AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
1672 def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1673 (COPY_TO_REGCLASS (VCMPPSZrri
1674 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1675 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1677 def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1678 (COPY_TO_REGCLASS (VPCMPDZrri
1679 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1680 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1682 def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1683 (COPY_TO_REGCLASS (VPCMPUDZrri
1684 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1685 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1688 //-----------------------------------------------------------------
1689 // Mask register copy, including
1690 // - copy between mask registers
1691 // - load/store mask registers
1692 // - copy from GPR to mask register and vice versa
1694 multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1695 string OpcodeStr, RegisterClass KRC,
1696 ValueType vvt, X86MemOperand x86memop> {
1697 let hasSideEffects = 0 in {
1698 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1699 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1701 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
1702 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1703 [(set KRC:$dst, (vvt (load addr:$src)))]>;
1705 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
1706 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1707 [(store KRC:$src, addr:$dst)]>;
1711 multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1713 RegisterClass KRC, RegisterClass GRC> {
1714 let hasSideEffects = 0 in {
1715 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
1716 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1717 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
1718 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
1722 let Predicates = [HasDQI] in
1723 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8mem>,
1724 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1727 let Predicates = [HasAVX512] in
1728 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
1729 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
1732 let Predicates = [HasBWI] in {
1733 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
1735 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1739 let Predicates = [HasBWI] in {
1740 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>,
1742 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1746 // GR from/to mask register
1747 let Predicates = [HasDQI] in {
1748 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1749 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1750 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1751 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1753 let Predicates = [HasAVX512] in {
1754 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1755 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1756 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1757 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
1759 let Predicates = [HasBWI] in {
1760 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1761 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1763 let Predicates = [HasBWI] in {
1764 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1765 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1769 let Predicates = [HasDQI] in {
1770 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1771 (KMOVBmk addr:$dst, VK8:$src)>;
1772 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1773 (KMOVBkm addr:$src)>;
1775 let Predicates = [HasAVX512, NoDQI] in {
1776 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1777 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
1778 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
1779 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
1781 let Predicates = [HasAVX512] in {
1782 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
1783 (KMOVWmk addr:$dst, VK16:$src)>;
1784 def : Pat<(i1 (load addr:$src)),
1785 (COPY_TO_REGCLASS (AND16ri (i16 (SUBREG_TO_REG (i32 0),
1786 (MOV8rm addr:$src), sub_8bit)),
1788 def : Pat<(v16i1 (bitconvert (i16 (load addr:$src)))),
1789 (KMOVWkm addr:$src)>;
1791 let Predicates = [HasBWI] in {
1792 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1793 (KMOVDmk addr:$dst, VK32:$src)>;
1794 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
1795 (KMOVDkm addr:$src)>;
1797 let Predicates = [HasBWI] in {
1798 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1799 (KMOVQmk addr:$dst, VK64:$src)>;
1800 def : Pat<(v64i1 (bitconvert (i64 (load addr:$src)))),
1801 (KMOVQkm addr:$src)>;
1804 let Predicates = [HasAVX512] in {
1805 def : Pat<(i1 (trunc (i64 GR64:$src))),
1806 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1809 def : Pat<(i1 (trunc (i32 GR32:$src))),
1810 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
1812 def : Pat<(i1 (trunc (i8 GR8:$src))),
1814 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1816 def : Pat<(i1 (trunc (i16 GR16:$src))),
1818 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1821 def : Pat<(i32 (zext VK1:$src)),
1822 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
1823 def : Pat<(i32 (anyext VK1:$src)),
1824 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16))>;
1825 def : Pat<(i8 (zext VK1:$src)),
1828 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
1829 def : Pat<(i64 (zext VK1:$src)),
1830 (AND64ri8 (SUBREG_TO_REG (i64 0),
1831 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
1832 def : Pat<(i16 (zext VK1:$src)),
1834 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1836 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1837 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1838 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1839 (COPY_TO_REGCLASS VK1:$src, VK8)>;
1841 let Predicates = [HasBWI] in {
1842 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1843 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1844 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1845 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1849 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1850 let Predicates = [HasAVX512, NoDQI] in {
1851 // GR from/to 8-bit mask without native support
1852 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1854 (KMOVWkr (MOVZX32rr8 GR8 :$src)), VK8)>;
1855 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1857 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1861 let Predicates = [HasAVX512] in {
1862 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
1863 (COPY_TO_REGCLASS VK16:$src, VK1)>;
1864 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
1865 (COPY_TO_REGCLASS VK8:$src, VK1)>;
1867 let Predicates = [HasBWI] in {
1868 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1869 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1870 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1871 (COPY_TO_REGCLASS VK64:$src, VK1)>;
1874 // Mask unary operation
1876 multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
1877 RegisterClass KRC, SDPatternOperator OpNode,
1879 let Predicates = [prd] in
1880 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
1881 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1882 [(set KRC:$dst, (OpNode KRC:$src))]>;
1885 multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1886 SDPatternOperator OpNode> {
1887 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1889 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1890 HasAVX512>, VEX, PS;
1891 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1892 HasBWI>, VEX, PD, VEX_W;
1893 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1894 HasBWI>, VEX, PS, VEX_W;
1897 defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
1899 multiclass avx512_mask_unop_int<string IntName, string InstName> {
1900 let Predicates = [HasAVX512] in
1901 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1903 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1904 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1906 defm : avx512_mask_unop_int<"knot", "KNOT">;
1908 let Predicates = [HasDQI] in
1909 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1910 let Predicates = [HasAVX512] in
1911 def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
1912 let Predicates = [HasBWI] in
1913 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1914 let Predicates = [HasBWI] in
1915 def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1917 // KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1918 let Predicates = [HasAVX512, NoDQI] in {
1919 def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1920 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1921 def : Pat<(not VK8:$src),
1923 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
1925 def : Pat<(xor VK4:$src1, (v4i1 immAllOnesV)),
1926 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK4:$src1, VK16)), VK4)>;
1927 def : Pat<(xor VK2:$src1, (v2i1 immAllOnesV)),
1928 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK2:$src1, VK16)), VK2)>;
1930 // Mask binary operation
1931 // - KAND, KANDN, KOR, KXNOR, KXOR
1932 multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
1933 RegisterClass KRC, SDPatternOperator OpNode,
1934 Predicate prd, bit IsCommutable> {
1935 let Predicates = [prd], isCommutable = IsCommutable in
1936 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1937 !strconcat(OpcodeStr,
1938 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1939 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1942 multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1943 SDPatternOperator OpNode, bit IsCommutable> {
1944 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1945 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
1946 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1947 HasAVX512, IsCommutable>, VEX_4V, VEX_L, PS;
1948 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1949 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
1950 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1951 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
1954 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1955 def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1957 defm KAND : avx512_mask_binop_all<0x41, "kand", and, 1>;
1958 defm KOR : avx512_mask_binop_all<0x45, "kor", or, 1>;
1959 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor, 1>;
1960 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor, 1>;
1961 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn, 0>;
1963 multiclass avx512_mask_binop_int<string IntName, string InstName> {
1964 let Predicates = [HasAVX512] in
1965 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1966 (i16 GR16:$src1), (i16 GR16:$src2)),
1967 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1968 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1969 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
1972 defm : avx512_mask_binop_int<"kand", "KAND">;
1973 defm : avx512_mask_binop_int<"kandn", "KANDN">;
1974 defm : avx512_mask_binop_int<"kor", "KOR">;
1975 defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1976 defm : avx512_mask_binop_int<"kxor", "KXOR">;
1978 multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1979 // With AVX512F, 8-bit mask is promoted to 16-bit mask,
1980 // for the DQI set, this type is legal and KxxxB instruction is used
1981 let Predicates = [NoDQI] in
1982 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1984 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1985 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1987 // All types smaller than 8 bits require conversion anyway
1988 def : Pat<(OpNode VK1:$src1, VK1:$src2),
1989 (COPY_TO_REGCLASS (Inst
1990 (COPY_TO_REGCLASS VK1:$src1, VK16),
1991 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1992 def : Pat<(OpNode VK2:$src1, VK2:$src2),
1993 (COPY_TO_REGCLASS (Inst
1994 (COPY_TO_REGCLASS VK2:$src1, VK16),
1995 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK1)>;
1996 def : Pat<(OpNode VK4:$src1, VK4:$src2),
1997 (COPY_TO_REGCLASS (Inst
1998 (COPY_TO_REGCLASS VK4:$src1, VK16),
1999 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK1)>;
2002 defm : avx512_binop_pat<and, KANDWrr>;
2003 defm : avx512_binop_pat<andn, KANDNWrr>;
2004 defm : avx512_binop_pat<or, KORWrr>;
2005 defm : avx512_binop_pat<xnor, KXNORWrr>;
2006 defm : avx512_binop_pat<xor, KXORWrr>;
2008 def : Pat<(xor (xor VK16:$src1, VK16:$src2), (v16i1 immAllOnesV)),
2009 (KXNORWrr VK16:$src1, VK16:$src2)>;
2010 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2011 (KXNORBrr VK8:$src1, VK8:$src2)>, Requires<[HasDQI]>;
2012 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2013 (KXNORDrr VK32:$src1, VK32:$src2)>, Requires<[HasBWI]>;
2014 def : Pat<(xor (xor VK64:$src1, VK64:$src2), (v64i1 immAllOnesV)),
2015 (KXNORQrr VK64:$src1, VK64:$src2)>, Requires<[HasBWI]>;
2017 let Predicates = [NoDQI] in
2018 def : Pat<(xor (xor VK8:$src1, VK8:$src2), (v8i1 immAllOnesV)),
2019 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK8:$src1, VK16),
2020 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
2022 def : Pat<(xor (xor VK4:$src1, VK4:$src2), (v4i1 immAllOnesV)),
2023 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK4:$src1, VK16),
2024 (COPY_TO_REGCLASS VK4:$src2, VK16)), VK4)>;
2026 def : Pat<(xor (xor VK2:$src1, VK2:$src2), (v2i1 immAllOnesV)),
2027 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK2:$src1, VK16),
2028 (COPY_TO_REGCLASS VK2:$src2, VK16)), VK2)>;
2030 def : Pat<(xor (xor VK1:$src1, VK1:$src2), (i1 1)),
2031 (COPY_TO_REGCLASS (KXNORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
2032 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
2035 multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
2036 RegisterClass KRC> {
2037 let Predicates = [HasAVX512] in
2038 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
2039 !strconcat(OpcodeStr,
2040 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2043 multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
2044 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
2048 defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
2049 def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
2050 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
2051 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
2054 multiclass avx512_mask_unpck_int<string IntName, string InstName> {
2055 let Predicates = [HasAVX512] in
2056 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
2057 (i16 GR16:$src1), (i16 GR16:$src2)),
2058 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
2059 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
2060 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
2062 defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
2065 multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2067 let Predicates = [HasAVX512], Defs = [EFLAGS] in
2068 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
2069 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2070 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
2073 multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2074 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2076 let Predicates = [HasDQI] in
2077 defm B : avx512_mask_testop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2079 let Predicates = [HasBWI] in {
2080 defm Q : avx512_mask_testop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2082 defm D : avx512_mask_testop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2087 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
2090 multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2092 let Predicates = [HasAVX512] in
2093 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, u8imm:$imm),
2094 !strconcat(OpcodeStr,
2095 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
2096 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
2099 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2101 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2103 let Predicates = [HasDQI] in
2104 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
2106 let Predicates = [HasBWI] in {
2107 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2109 let Predicates = [HasDQI] in
2110 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
2115 defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
2116 defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
2118 // Mask setting all 0s or 1s
2119 multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
2120 let Predicates = [HasAVX512] in
2121 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
2122 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
2123 [(set KRC:$dst, (VT Val))]>;
2126 multiclass avx512_mask_setop_w<PatFrag Val> {
2127 defm B : avx512_mask_setop<VK8, v8i1, Val>;
2128 defm W : avx512_mask_setop<VK16, v16i1, Val>;
2129 defm D : avx512_mask_setop<VK32, v32i1, Val>;
2130 defm Q : avx512_mask_setop<VK64, v64i1, Val>;
2133 defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
2134 defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
2136 // With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
2137 let Predicates = [HasAVX512] in {
2138 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
2139 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
2140 def : Pat<(v4i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK4)>;
2141 def : Pat<(v2i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK2)>;
2142 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
2143 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2144 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSHIFTRWri (KSET1W), (i8 15)), VK1)>;
2146 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
2147 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
2149 def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
2150 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
2152 def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
2153 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
2155 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 0))),
2156 (v32i1 (COPY_TO_REGCLASS VK64:$src, VK32))>;
2158 def : Pat<(v32i1 (extract_subvector (v64i1 VK64:$src), (iPTR 32))),
2159 (v32i1 (COPY_TO_REGCLASS (KSHIFTRQri VK64:$src, (i8 32)), VK32))>;
2161 let Predicates = [HasVLX] in {
2162 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
2163 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
2164 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2165 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
2166 def : Pat<(v4i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
2167 (v4i1 (COPY_TO_REGCLASS VK2:$src, VK4))>;
2168 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2169 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
2170 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
2171 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
2174 def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
2175 (v8i1 (COPY_TO_REGCLASS
2176 (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
2177 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2179 def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
2180 (v8i1 (COPY_TO_REGCLASS
2181 (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
2182 (I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
2184 def : Pat<(v4i1 (X86vshli VK4:$src, (i8 imm:$imm))),
2185 (v4i1 (COPY_TO_REGCLASS
2186 (KSHIFTLWri (COPY_TO_REGCLASS VK4:$src, VK16),
2187 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2189 def : Pat<(v4i1 (X86vsrli VK4:$src, (i8 imm:$imm))),
2190 (v4i1 (COPY_TO_REGCLASS
2191 (KSHIFTRWri (COPY_TO_REGCLASS VK4:$src, VK16),
2192 (I8Imm $imm)), VK4))>, Requires<[HasAVX512]>;
2194 //===----------------------------------------------------------------------===//
2195 // AVX-512 - Aligned and unaligned load and store
2199 multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2200 PatFrag ld_frag, PatFrag mload,
2201 bit IsReMaterializable = 1> {
2202 let hasSideEffects = 0 in {
2203 def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
2204 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
2206 def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2207 (ins _.KRCWM:$mask, _.RC:$src),
2208 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
2209 "${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
2212 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
2213 SchedRW = [WriteLoad] in
2214 def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
2215 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2216 [(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
2219 let Constraints = "$src0 = $dst" in {
2220 def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
2221 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
2222 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2223 "${dst} {${mask}}, $src1}"),
2224 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2226 (_.VT _.RC:$src0))))], _.ExeDomain>,
2228 let mayLoad = 1, SchedRW = [WriteLoad] in
2229 def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2230 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
2231 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
2232 "${dst} {${mask}}, $src1}"),
2233 [(set _.RC:$dst, (_.VT
2234 (vselect _.KRCWM:$mask,
2235 (_.VT (bitconvert (ld_frag addr:$src1))),
2236 (_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
2238 let mayLoad = 1, SchedRW = [WriteLoad] in
2239 def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
2240 (ins _.KRCWM:$mask, _.MemOp:$src),
2241 OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
2242 "${dst} {${mask}} {z}, $src}",
2243 [(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
2244 (_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
2245 _.ExeDomain>, EVEX, EVEX_KZ;
2247 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, undef)),
2248 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2250 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, _.ImmAllZerosV)),
2251 (!cast<Instruction>(NAME#_.ZSuffix##rmkz) _.KRCWM:$mask, addr:$ptr)>;
2253 def : Pat<(_.VT (mload addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src0))),
2254 (!cast<Instruction>(NAME#_.ZSuffix##rmk) _.RC:$src0,
2255 _.KRCWM:$mask, addr:$ptr)>;
2258 multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
2259 AVX512VLVectorVTInfo _,
2261 bit IsReMaterializable = 1> {
2262 let Predicates = [prd] in
2263 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
2264 masked_load_aligned512, IsReMaterializable>, EVEX_V512;
2266 let Predicates = [prd, HasVLX] in {
2267 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
2268 masked_load_aligned256, IsReMaterializable>, EVEX_V256;
2269 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
2270 masked_load_aligned128, IsReMaterializable>, EVEX_V128;
2274 multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
2275 AVX512VLVectorVTInfo _,
2277 bit IsReMaterializable = 1> {
2278 let Predicates = [prd] in
2279 defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
2280 masked_load_unaligned, IsReMaterializable>, EVEX_V512;
2282 let Predicates = [prd, HasVLX] in {
2283 defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
2284 masked_load_unaligned, IsReMaterializable>, EVEX_V256;
2285 defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
2286 masked_load_unaligned, IsReMaterializable>, EVEX_V128;
2290 multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
2291 PatFrag st_frag, PatFrag mstore> {
2292 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2293 def rr_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2294 OpcodeStr # "\t{$src, $dst|$dst, $src}", [],
2296 let Constraints = "$src1 = $dst" in
2297 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2298 (ins _.RC:$src1, _.KRCWM:$mask, _.RC:$src2),
2300 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}",
2301 [], _.ExeDomain>, EVEX, EVEX_K;
2302 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2303 (ins _.KRCWM:$mask, _.RC:$src),
2305 "\t{$src, ${dst} {${mask}} {z}|" #
2306 "${dst} {${mask}} {z}, $src}",
2307 [], _.ExeDomain>, EVEX, EVEX_KZ;
2309 let mayStore = 1 in {
2310 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
2311 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2312 [(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
2313 def mrk : AVX512PI<opc, MRMDestMem, (outs),
2314 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
2315 OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
2316 [], _.ExeDomain>, EVEX, EVEX_K;
2319 def: Pat<(mstore addr:$ptr, _.KRCWM:$mask, (_.VT _.RC:$src)),
2320 (!cast<Instruction>(NAME#_.ZSuffix##mrk) addr:$ptr,
2321 _.KRCWM:$mask, _.RC:$src)>;
2325 multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
2326 AVX512VLVectorVTInfo _, Predicate prd> {
2327 let Predicates = [prd] in
2328 defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
2329 masked_store_unaligned>, EVEX_V512;
2331 let Predicates = [prd, HasVLX] in {
2332 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
2333 masked_store_unaligned>, EVEX_V256;
2334 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
2335 masked_store_unaligned>, EVEX_V128;
2339 multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
2340 AVX512VLVectorVTInfo _, Predicate prd> {
2341 let Predicates = [prd] in
2342 defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512,
2343 masked_store_aligned512>, EVEX_V512;
2345 let Predicates = [prd, HasVLX] in {
2346 defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256,
2347 masked_store_aligned256>, EVEX_V256;
2348 defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
2349 masked_store_aligned128>, EVEX_V128;
2353 defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
2355 avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
2356 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2358 defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
2360 avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
2361 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2363 defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
2364 avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
2365 PS, EVEX_CD8<32, CD8VF>;
2367 defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
2368 avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
2369 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2371 def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
2372 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2373 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2375 def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2376 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2377 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2379 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2380 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
2381 (VMOVAPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2383 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2384 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2385 (VMOVAPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2387 def: Pat<(v8f64 (int_x86_avx512_mask_load_pd_512 addr:$ptr,
2388 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
2389 (VMOVAPDZrm addr:$ptr)>;
2391 def: Pat<(v16f32 (int_x86_avx512_mask_load_ps_512 addr:$ptr,
2392 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
2393 (VMOVAPSZrm addr:$ptr)>;
2395 def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2397 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2399 def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2401 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2404 def: Pat<(int_x86_avx512_mask_store_ps_512 addr:$ptr, (v16f32 VR512:$src),
2406 (VMOVAPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2408 def: Pat<(int_x86_avx512_mask_store_pd_512 addr:$ptr, (v8f64 VR512:$src),
2410 (VMOVAPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2413 let Predicates = [HasAVX512, NoVLX] in {
2414 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src)),
2415 (VMOVUPSZmrk addr:$ptr,
2416 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2417 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2419 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2420 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmkz
2421 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2423 def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
2424 (v8f32 (EXTRACT_SUBREG (v16f32 (VMOVUPSZrmk
2425 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
2426 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2429 defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
2431 avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
2432 HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
2434 defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
2436 avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
2437 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2439 defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
2440 avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
2441 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2443 defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
2444 avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
2445 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2447 defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
2448 avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
2449 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2451 defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
2452 avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
2453 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
2455 def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2456 (v16i32 immAllZerosV), GR16:$mask)),
2457 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
2459 def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
2460 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2461 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
2463 def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
2465 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2467 def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
2469 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2472 let AddedComplexity = 20 in {
2473 def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
2474 (bc_v8i64 (v16i32 immAllZerosV)))),
2475 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
2477 def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
2478 (v8i64 VR512:$src))),
2479 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
2482 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2483 (v16i32 immAllZerosV))),
2484 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
2486 def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
2487 (v16i32 VR512:$src))),
2488 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
2491 let Predicates = [HasAVX512, NoVLX] in {
2492 def: Pat<(masked_store addr:$ptr, VK8WM:$mask, (v8i32 VR256:$src)),
2493 (VMOVDQU32Zmrk addr:$ptr,
2494 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)),
2495 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256:$src, sub_ymm))>;
2497 def: Pat<(v8i32 (masked_load addr:$ptr, VK8WM:$mask, undef)),
2498 (v8i32 (EXTRACT_SUBREG (v16i32 (VMOVDQU32Zrmkz
2499 (v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
2502 // Move Int Doubleword to Packed Double Int
2504 def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
2505 "vmovd\t{$src, $dst|$dst, $src}",
2507 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2509 def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
2510 "vmovd\t{$src, $dst|$dst, $src}",
2512 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2513 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2514 def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
2515 "vmovq\t{$src, $dst|$dst, $src}",
2517 (v2i64 (scalar_to_vector GR64:$src)))],
2518 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
2519 let isCodeGenOnly = 1 in {
2520 def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2521 "vmovq\t{$src, $dst|$dst, $src}",
2522 [(set FR64:$dst, (bitconvert GR64:$src))],
2523 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2524 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2525 "vmovq\t{$src, $dst|$dst, $src}",
2526 [(set GR64:$dst, (bitconvert FR64:$src))],
2527 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
2529 def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2530 "vmovq\t{$src, $dst|$dst, $src}",
2531 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2532 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2533 EVEX_CD8<64, CD8VT1>;
2535 // Move Int Doubleword to Single Scalar
2537 let isCodeGenOnly = 1 in {
2538 def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
2539 "vmovd\t{$src, $dst|$dst, $src}",
2540 [(set FR32X:$dst, (bitconvert GR32:$src))],
2541 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2543 def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
2544 "vmovd\t{$src, $dst|$dst, $src}",
2545 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2546 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2549 // Move doubleword from xmm register to r/m32
2551 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2552 "vmovd\t{$src, $dst|$dst, $src}",
2553 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2554 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2556 def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2557 (ins i32mem:$dst, VR128X:$src),
2558 "vmovd\t{$src, $dst|$dst, $src}",
2559 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2560 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2561 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2563 // Move quadword from xmm1 register to r/m64
2565 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2566 "vmovq\t{$src, $dst|$dst, $src}",
2567 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2569 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
2570 Requires<[HasAVX512, In64BitMode]>;
2572 def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
2573 (ins i64mem:$dst, VR128X:$src),
2574 "vmovq\t{$src, $dst|$dst, $src}",
2575 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2576 addr:$dst)], IIC_SSE_MOVDQ>,
2577 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
2578 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2580 // Move Scalar Single to Double Int
2582 let isCodeGenOnly = 1 in {
2583 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
2585 "vmovd\t{$src, $dst|$dst, $src}",
2586 [(set GR32:$dst, (bitconvert FR32X:$src))],
2587 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
2588 def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
2589 (ins i32mem:$dst, FR32X:$src),
2590 "vmovd\t{$src, $dst|$dst, $src}",
2591 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2592 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2595 // Move Quadword Int to Packed Quadword Int
2597 def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
2599 "vmovq\t{$src, $dst|$dst, $src}",
2601 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2602 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2604 //===----------------------------------------------------------------------===//
2605 // AVX-512 MOVSS, MOVSD
2606 //===----------------------------------------------------------------------===//
2608 multiclass avx512_move_scalar <string asm, RegisterClass RC,
2609 SDNode OpNode, ValueType vt,
2610 X86MemOperand x86memop, PatFrag mem_pat> {
2611 let hasSideEffects = 0 in {
2612 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
2613 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2614 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2615 (scalar_to_vector RC:$src2))))],
2616 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
2617 let Constraints = "$src1 = $dst" in
2618 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2619 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2621 "\t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
2622 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
2623 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
2624 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2625 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2627 let mayStore = 1 in {
2628 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
2629 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2630 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2632 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2633 !strconcat(asm, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2634 [], IIC_SSE_MOV_S_MR>,
2635 EVEX, VEX_LIG, EVEX_K;
2637 } //hasSideEffects = 0
2640 let ExeDomain = SSEPackedSingle in
2641 defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
2642 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2644 let ExeDomain = SSEPackedDouble in
2645 defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
2646 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2648 def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2649 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2650 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2652 def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2653 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2654 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
2656 def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2657 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2658 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2660 // For the disassembler
2661 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
2662 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2663 (ins VR128X:$src1, FR32X:$src2),
2664 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2666 XS, EVEX_4V, VEX_LIG;
2667 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2668 (ins VR128X:$src1, FR64X:$src2),
2669 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
2671 XD, EVEX_4V, VEX_LIG, VEX_W;
2674 let Predicates = [HasAVX512] in {
2675 let AddedComplexity = 15 in {
2676 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2677 // MOVS{S,D} to the lower bits.
2678 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2679 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2680 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2681 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2682 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2683 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2684 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2685 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2687 // Move low f32 and clear high bits.
2688 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2689 (SUBREG_TO_REG (i32 0),
2690 (VMOVSSZrr (v4f32 (V_SET0)),
2691 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2692 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2693 (SUBREG_TO_REG (i32 0),
2694 (VMOVSSZrr (v4i32 (V_SET0)),
2695 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2698 let AddedComplexity = 20 in {
2699 // MOVSSrm zeros the high parts of the register; represent this
2700 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2701 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2702 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2703 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2704 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2705 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2706 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2708 // MOVSDrm zeros the high parts of the register; represent this
2709 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2710 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2711 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2712 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2713 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2714 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2715 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2716 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2717 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2718 def : Pat<(v2f64 (X86vzload addr:$src)),
2719 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2721 // Represent the same patterns above but in the form they appear for
2723 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2724 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
2725 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
2726 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2727 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2728 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2729 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2730 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2731 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2733 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2734 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2735 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2736 FR32X:$src)), sub_xmm)>;
2737 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2738 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2739 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2740 FR64X:$src)), sub_xmm)>;
2741 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2742 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
2743 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
2745 // Move low f64 and clear high bits.
2746 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2747 (SUBREG_TO_REG (i32 0),
2748 (VMOVSDZrr (v2f64 (V_SET0)),
2749 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2751 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2752 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2753 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2755 // Extract and store.
2756 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2758 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2759 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2761 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2763 // Shuffle with VMOVSS
2764 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2765 (VMOVSSZrr (v4i32 VR128X:$src1),
2766 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2767 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2768 (VMOVSSZrr (v4f32 VR128X:$src1),
2769 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2772 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2773 (SUBREG_TO_REG (i32 0),
2774 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2775 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2777 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2778 (SUBREG_TO_REG (i32 0),
2779 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2780 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2783 // Shuffle with VMOVSD
2784 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2785 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2786 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2787 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2788 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2789 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2790 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2791 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2794 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2795 (SUBREG_TO_REG (i32 0),
2796 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2797 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2799 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2800 (SUBREG_TO_REG (i32 0),
2801 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2802 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2805 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2806 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2807 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2808 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2809 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2810 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2811 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2812 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2815 let AddedComplexity = 15 in
2816 def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2818 "vmovq\t{$src, $dst|$dst, $src}",
2819 [(set VR128X:$dst, (v2i64 (X86vzmovl
2820 (v2i64 VR128X:$src))))],
2821 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2823 let AddedComplexity = 20 in
2824 def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2826 "vmovq\t{$src, $dst|$dst, $src}",
2827 [(set VR128X:$dst, (v2i64 (X86vzmovl
2828 (loadv2i64 addr:$src))))],
2829 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2830 EVEX_CD8<8, CD8VT8>;
2832 let Predicates = [HasAVX512] in {
2833 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2834 let AddedComplexity = 20 in {
2835 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2836 (VMOVDI2PDIZrm addr:$src)>;
2837 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2838 (VMOV64toPQIZrr GR64:$src)>;
2839 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2840 (VMOVDI2PDIZrr GR32:$src)>;
2842 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2843 (VMOVDI2PDIZrm addr:$src)>;
2844 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2845 (VMOVDI2PDIZrm addr:$src)>;
2846 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2847 (VMOVZPQILo2PQIZrm addr:$src)>;
2848 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2849 (VMOVZPQILo2PQIZrr VR128X:$src)>;
2850 def : Pat<(v2i64 (X86vzload addr:$src)),
2851 (VMOVZPQILo2PQIZrm addr:$src)>;
2854 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2855 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2856 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2857 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2858 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2859 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2860 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2863 def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2864 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2866 def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2867 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2869 def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2870 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2872 def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2873 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2875 //===----------------------------------------------------------------------===//
2876 // AVX-512 - Non-temporals
2877 //===----------------------------------------------------------------------===//
2878 let SchedRW = [WriteLoad] in {
2879 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2880 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2881 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2882 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2883 EVEX_CD8<64, CD8VF>;
2885 let Predicates = [HasAVX512, HasVLX] in {
2886 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2888 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2889 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2890 EVEX_CD8<64, CD8VF>;
2892 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2894 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2895 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2896 EVEX_CD8<64, CD8VF>;
2900 multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2901 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2902 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2903 let SchedRW = [WriteStore], mayStore = 1,
2904 AddedComplexity = 400 in
2905 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2906 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2907 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2910 multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2911 string elty, string elsz, string vsz512,
2912 string vsz256, string vsz128, Domain d,
2913 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2914 let Predicates = [prd] in
2915 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2916 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2917 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2920 let Predicates = [prd, HasVLX] in {
2921 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2922 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2923 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2926 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2927 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2928 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2933 defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2934 "i", "64", "8", "4", "2", SSEPackedInt,
2935 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2937 defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2938 "f", "64", "8", "4", "2", SSEPackedDouble,
2939 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2941 defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2942 "f", "32", "16", "8", "4", SSEPackedSingle,
2943 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2945 //===----------------------------------------------------------------------===//
2946 // AVX-512 - Integer arithmetic
2948 multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2949 X86VectorVTInfo _, OpndItins itins,
2950 bit IsCommutable = 0> {
2951 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2952 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2953 "$src2, $src1", "$src1, $src2",
2954 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2955 itins.rr, IsCommutable>,
2956 AVX512BIBase, EVEX_4V;
2959 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2960 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2961 "$src2, $src1", "$src1, $src2",
2962 (_.VT (OpNode _.RC:$src1,
2963 (bitconvert (_.LdFrag addr:$src2)))),
2965 AVX512BIBase, EVEX_4V;
2968 multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2969 X86VectorVTInfo _, OpndItins itins,
2970 bit IsCommutable = 0> :
2971 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2973 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2974 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2975 "${src2}"##_.BroadcastStr##", $src1",
2976 "$src1, ${src2}"##_.BroadcastStr,
2977 (_.VT (OpNode _.RC:$src1,
2979 (_.ScalarLdFrag addr:$src2)))),
2981 AVX512BIBase, EVEX_4V, EVEX_B;
2984 multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2985 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2986 Predicate prd, bit IsCommutable = 0> {
2987 let Predicates = [prd] in
2988 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2989 IsCommutable>, EVEX_V512;
2991 let Predicates = [prd, HasVLX] in {
2992 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2993 IsCommutable>, EVEX_V256;
2994 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2995 IsCommutable>, EVEX_V128;
2999 multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
3000 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
3001 Predicate prd, bit IsCommutable = 0> {
3002 let Predicates = [prd] in
3003 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
3004 IsCommutable>, EVEX_V512;
3006 let Predicates = [prd, HasVLX] in {
3007 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
3008 IsCommutable>, EVEX_V256;
3009 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
3010 IsCommutable>, EVEX_V128;
3014 multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
3015 OpndItins itins, Predicate prd,
3016 bit IsCommutable = 0> {
3017 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
3018 itins, prd, IsCommutable>,
3019 VEX_W, EVEX_CD8<64, CD8VF>;
3022 multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
3023 OpndItins itins, Predicate prd,
3024 bit IsCommutable = 0> {
3025 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
3026 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
3029 multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
3030 OpndItins itins, Predicate prd,
3031 bit IsCommutable = 0> {
3032 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
3033 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
3036 multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
3037 OpndItins itins, Predicate prd,
3038 bit IsCommutable = 0> {
3039 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
3040 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
3043 multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
3044 SDNode OpNode, OpndItins itins, Predicate prd,
3045 bit IsCommutable = 0> {
3046 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
3049 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
3053 multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
3054 SDNode OpNode, OpndItins itins, Predicate prd,
3055 bit IsCommutable = 0> {
3056 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
3059 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
3063 multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
3064 bits<8> opc_d, bits<8> opc_q,
3065 string OpcodeStr, SDNode OpNode,
3066 OpndItins itins, bit IsCommutable = 0> {
3067 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
3068 itins, HasAVX512, IsCommutable>,
3069 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
3070 itins, HasBWI, IsCommutable>;
3073 multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, OpndItins itins,
3074 SDNode OpNode,X86VectorVTInfo _Src,
3075 X86VectorVTInfo _Dst, bit IsCommutable = 0> {
3076 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3077 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3078 "$src2, $src1","$src1, $src2",
3080 (_Src.VT _Src.RC:$src1),
3081 (_Src.VT _Src.RC:$src2))),
3082 itins.rr, IsCommutable>,
3083 AVX512BIBase, EVEX_4V;
3084 let mayLoad = 1 in {
3085 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3086 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3087 "$src2, $src1", "$src1, $src2",
3088 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3089 (bitconvert (_Src.LdFrag addr:$src2)))),
3091 AVX512BIBase, EVEX_4V;
3093 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3094 (ins _Src.RC:$src1, _Dst.ScalarMemOp:$src2),
3096 "${src2}"##_Dst.BroadcastStr##", $src1",
3097 "$src1, ${src2}"##_Dst.BroadcastStr,
3098 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3099 (_Dst.VT (X86VBroadcast
3100 (_Dst.ScalarLdFrag addr:$src2)))))),
3102 AVX512BIBase, EVEX_4V, EVEX_B;
3106 defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
3107 SSE_INTALU_ITINS_P, 1>;
3108 defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
3109 SSE_INTALU_ITINS_P, 0>;
3110 defm VPADDS : avx512_binop_rm_vl_bw<0xEC, 0xED, "vpadds", X86adds,
3111 SSE_INTALU_ITINS_P, HasBWI, 1>;
3112 defm VPSUBS : avx512_binop_rm_vl_bw<0xE8, 0xE9, "vpsubs", X86subs,
3113 SSE_INTALU_ITINS_P, HasBWI, 0>;
3114 defm VPADDUS : avx512_binop_rm_vl_bw<0xDC, 0xDD, "vpaddus", X86addus,
3115 SSE_INTALU_ITINS_P, HasBWI, 1>;
3116 defm VPSUBUS : avx512_binop_rm_vl_bw<0xD8, 0xD9, "vpsubus", X86subus,
3117 SSE_INTALU_ITINS_P, HasBWI, 0>;
3118 defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
3119 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3120 defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
3121 SSE_INTALU_ITINS_P, HasBWI, 1>;
3122 defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
3123 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
3126 multiclass avx512_binop_all<bits<8> opc, string OpcodeStr, OpndItins itins,
3127 SDNode OpNode, bit IsCommutable = 0> {
3129 defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3130 v16i32_info, v8i64_info, IsCommutable>,
3131 EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
3132 let Predicates = [HasVLX] in {
3133 defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3134 v8i32x_info, v4i64x_info, IsCommutable>,
3135 EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W;
3136 defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, itins, OpNode,
3137 v4i32x_info, v2i64x_info, IsCommutable>,
3138 EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W;
3142 defm VPMULDQ : avx512_binop_all<0x28, "vpmuldq", SSE_INTALU_ITINS_P,
3144 defm VPMULUDQ : avx512_binop_all<0xF4, "vpmuludq", SSE_INTMUL_ITINS_P,
3147 multiclass avx512_packs_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3148 X86VectorVTInfo _Src, X86VectorVTInfo _Dst> {
3149 let mayLoad = 1 in {
3150 defm rmb : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3151 (ins _Src.RC:$src1, _Src.ScalarMemOp:$src2),
3153 "${src2}"##_Src.BroadcastStr##", $src1",
3154 "$src1, ${src2}"##_Src.BroadcastStr,
3155 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1), (bitconvert
3156 (_Src.VT (X86VBroadcast
3157 (_Src.ScalarLdFrag addr:$src2))))))>,
3158 EVEX_4V, EVEX_B, EVEX_CD8<_Src.EltSize, CD8VF>;
3162 multiclass avx512_packs_rm<bits<8> opc, string OpcodeStr,
3163 SDNode OpNode,X86VectorVTInfo _Src,
3164 X86VectorVTInfo _Dst> {
3165 defm rr : AVX512_maskable<opc, MRMSrcReg, _Dst, (outs _Dst.RC:$dst),
3166 (ins _Src.RC:$src1, _Src.RC:$src2), OpcodeStr,
3167 "$src2, $src1","$src1, $src2",
3169 (_Src.VT _Src.RC:$src1),
3170 (_Src.VT _Src.RC:$src2)))>,
3171 EVEX_CD8<_Src.EltSize, CD8VF>, EVEX_4V;
3172 let mayLoad = 1 in {
3173 defm rm : AVX512_maskable<opc, MRMSrcMem, _Dst, (outs _Dst.RC:$dst),
3174 (ins _Src.RC:$src1, _Src.MemOp:$src2), OpcodeStr,
3175 "$src2, $src1", "$src1, $src2",
3176 (_Dst.VT (OpNode (_Src.VT _Src.RC:$src1),
3177 (bitconvert (_Src.LdFrag addr:$src2))))>,
3178 EVEX_4V, EVEX_CD8<_Src.EltSize, CD8VF>;
3182 multiclass avx512_packs_all_i32_i16<bits<8> opc, string OpcodeStr,
3184 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i32_info,
3186 avx512_packs_rmb<opc, OpcodeStr, OpNode, v16i32_info,
3187 v32i16_info>, EVEX_V512;
3188 let Predicates = [HasVLX] in {
3189 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i32x_info,
3191 avx512_packs_rmb<opc, OpcodeStr, OpNode, v8i32x_info,
3192 v16i16x_info>, EVEX_V256;
3193 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v4i32x_info,
3195 avx512_packs_rmb<opc, OpcodeStr, OpNode, v4i32x_info,
3196 v8i16x_info>, EVEX_V128;
3199 multiclass avx512_packs_all_i16_i8<bits<8> opc, string OpcodeStr,
3201 defm NAME#Z : avx512_packs_rm<opc, OpcodeStr, OpNode, v32i16_info,
3202 v64i8_info>, EVEX_V512;
3203 let Predicates = [HasVLX] in {
3204 defm NAME#Z256 : avx512_packs_rm<opc, OpcodeStr, OpNode, v16i16x_info,
3205 v32i8x_info>, EVEX_V256;
3206 defm NAME#Z128 : avx512_packs_rm<opc, OpcodeStr, OpNode, v8i16x_info,
3207 v16i8x_info>, EVEX_V128;
3210 let Predicates = [HasBWI] in {
3211 defm VPACKSSDW : avx512_packs_all_i32_i16<0x6B, "vpackssdw", X86Packss>, PD;
3212 defm VPACKUSDW : avx512_packs_all_i32_i16<0x2b, "vpackusdw", X86Packus>, T8PD;
3213 defm VPACKSSWB : avx512_packs_all_i16_i8 <0x63, "vpacksswb", X86Packss>, AVX512BIBase, VEX_W;
3214 defm VPACKUSWB : avx512_packs_all_i16_i8 <0x67, "vpackuswb", X86Packus>, AVX512BIBase, VEX_W;
3217 defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
3218 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3219 defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
3220 SSE_INTALU_ITINS_P, HasBWI, 1>;
3221 defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
3222 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3224 defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
3225 SSE_INTALU_ITINS_P, HasBWI, 1>;
3226 defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
3227 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3228 defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
3229 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3231 defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
3232 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3233 defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
3234 SSE_INTALU_ITINS_P, HasBWI, 1>;
3235 defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
3236 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3238 defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
3239 SSE_INTALU_ITINS_P, HasBWI, 1>;
3240 defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
3241 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
3242 defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
3243 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
3245 //===----------------------------------------------------------------------===//
3246 // AVX-512 - Unpack Instructions
3247 //===----------------------------------------------------------------------===//
3249 multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
3250 PatFrag mem_frag, RegisterClass RC,
3251 X86MemOperand x86memop, string asm,
3253 def rr : AVX512PI<opc, MRMSrcReg,
3254 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3256 (vt (OpNode RC:$src1, RC:$src2)))],
3258 def rm : AVX512PI<opc, MRMSrcMem,
3259 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3261 (vt (OpNode RC:$src1,
3262 (bitconvert (mem_frag addr:$src2)))))],
3266 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, loadv8f64,
3267 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3268 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3269 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, loadv8f64,
3270 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3271 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3272 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, loadv8f64,
3273 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3274 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
3275 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, loadv8f64,
3276 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3277 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3279 multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
3280 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3281 X86MemOperand x86memop> {
3282 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3283 (ins RC:$src1, RC:$src2),
3284 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3285 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
3286 IIC_SSE_UNPCK>, EVEX_4V;
3287 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3288 (ins RC:$src1, x86memop:$src2),
3289 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3290 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
3291 (bitconvert (memop_frag addr:$src2)))))],
3292 IIC_SSE_UNPCK>, EVEX_4V;
3294 defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
3295 VR512, loadv16i32, i512mem>, EVEX_V512,
3296 EVEX_CD8<32, CD8VF>;
3297 defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
3298 VR512, loadv8i64, i512mem>, EVEX_V512,
3299 VEX_W, EVEX_CD8<64, CD8VF>;
3300 defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
3301 VR512, loadv16i32, i512mem>, EVEX_V512,
3302 EVEX_CD8<32, CD8VF>;
3303 defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
3304 VR512, loadv8i64, i512mem>, EVEX_V512,
3305 VEX_W, EVEX_CD8<64, CD8VF>;
3306 //===----------------------------------------------------------------------===//
3307 // AVX-512 Logical Instructions
3308 //===----------------------------------------------------------------------===//
3310 defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
3311 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3312 defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
3313 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3314 defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
3315 SSE_INTALU_ITINS_P, HasAVX512, 1>;
3316 defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
3317 SSE_INTALU_ITINS_P, HasAVX512, 0>;
3319 //===----------------------------------------------------------------------===//
3320 // AVX-512 FP arithmetic
3321 //===----------------------------------------------------------------------===//
3322 multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3323 SDNode OpNode, SDNode VecNode, OpndItins itins,
3326 defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3327 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3328 "$src2, $src1", "$src1, $src2",
3329 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3330 (i32 FROUND_CURRENT)),
3331 itins.rr, IsCommutable>;
3333 defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
3334 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3335 "$src2, $src1", "$src1, $src2",
3336 (VecNode (_.VT _.RC:$src1),
3337 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
3338 (i32 FROUND_CURRENT)),
3339 itins.rm, IsCommutable>;
3340 let isCodeGenOnly = 1, isCommutable = IsCommutable,
3341 Predicates = [HasAVX512] in {
3342 def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
3343 (ins _.FRC:$src1, _.FRC:$src2),
3344 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3345 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))],
3347 def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
3348 (ins _.FRC:$src1, _.ScalarMemOp:$src2),
3349 OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3350 [(set _.FRC:$dst, (OpNode _.FRC:$src1,
3351 (_.ScalarLdFrag addr:$src2)))], itins.rr>;
3355 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3356 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3358 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3359 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
3360 "$rc, $src2, $src1", "$src1, $src2, $rc",
3361 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3362 (i32 imm:$rc)), itins.rr, IsCommutable>,
3365 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
3366 SDNode VecNode, OpndItins itins, bit IsCommutable> {
3368 defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
3369 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3370 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3371 (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
3372 (i32 FROUND_NO_EXC))>, EVEX_B;
3375 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
3377 SizeItins itins, bit IsCommutable> {
3378 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3379 itins.s, IsCommutable>,
3380 avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
3381 itins.s, IsCommutable>,
3382 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3383 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3384 itins.d, IsCommutable>,
3385 avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
3386 itins.d, IsCommutable>,
3387 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3390 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
3392 SizeItins itins, bit IsCommutable> {
3393 defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
3394 itins.s, IsCommutable>,
3395 avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
3396 itins.s, IsCommutable>,
3397 XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
3398 defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
3399 itins.d, IsCommutable>,
3400 avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
3401 itins.d, IsCommutable>,
3402 XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3404 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
3405 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_ALU_ITINS_S, 1>;
3406 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
3407 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_ALU_ITINS_S, 0>;
3408 defm VMIN : avx512_binop_s_sae <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 1>;
3409 defm VMAX : avx512_binop_s_sae <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 1>;
3411 multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
3412 X86VectorVTInfo _, bit IsCommutable> {
3413 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3414 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3415 "$src2, $src1", "$src1, $src2",
3416 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
3417 let mayLoad = 1 in {
3418 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3419 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
3420 "$src2, $src1", "$src1, $src2",
3421 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
3422 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3423 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
3424 "${src2}"##_.BroadcastStr##", $src1",
3425 "$src1, ${src2}"##_.BroadcastStr,
3426 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3427 (_.ScalarLdFrag addr:$src2))))>,
3432 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3433 X86VectorVTInfo _, bit IsCommutable> {
3434 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3435 (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
3436 "$rc, $src2, $src1", "$src1, $src2, $rc",
3437 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
3438 EVEX_4V, EVEX_B, EVEX_RC;
3442 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
3443 X86VectorVTInfo _, bit IsCommutable> {
3444 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3445 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
3446 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
3447 (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
3451 multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3452 bit IsCommutable = 0> {
3453 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3454 IsCommutable>, EVEX_V512, PS,
3455 EVEX_CD8<32, CD8VF>;
3456 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3457 IsCommutable>, EVEX_V512, PD, VEX_W,
3458 EVEX_CD8<64, CD8VF>;
3460 // Define only if AVX512VL feature is present.
3461 let Predicates = [HasVLX] in {
3462 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3463 IsCommutable>, EVEX_V128, PS,
3464 EVEX_CD8<32, CD8VF>;
3465 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3466 IsCommutable>, EVEX_V256, PS,
3467 EVEX_CD8<32, CD8VF>;
3468 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3469 IsCommutable>, EVEX_V128, PD, VEX_W,
3470 EVEX_CD8<64, CD8VF>;
3471 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3472 IsCommutable>, EVEX_V256, PD, VEX_W,
3473 EVEX_CD8<64, CD8VF>;
3477 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3478 defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info, 0>,
3479 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3480 defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info, 0>,
3481 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3484 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
3485 defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info, 0>,
3486 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
3487 defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info, 0>,
3488 EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
3491 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>,
3492 avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
3493 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>,
3494 avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
3495 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>,
3496 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd>;
3497 defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>,
3498 avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd>;
3499 defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>,
3500 avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd>;
3501 defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>,
3502 avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd>;
3503 let Predicates = [HasDQI] in {
3504 defm VAND : avx512_fp_binop_p<0x54, "vand", X86fand, 1>;
3505 defm VANDN : avx512_fp_binop_p<0x55, "vandn", X86fandn, 0>;
3506 defm VOR : avx512_fp_binop_p<0x56, "vor", X86for, 1>;
3507 defm VXOR : avx512_fp_binop_p<0x57, "vxor", X86fxor, 1>;
3510 //===----------------------------------------------------------------------===//
3511 // AVX-512 VPTESTM instructions
3512 //===----------------------------------------------------------------------===//
3514 multiclass avx512_vptest<bits<8> opc, string OpcodeStr, SDNode OpNode,
3515 X86VectorVTInfo _> {
3516 defm rr : AVX512_maskable_cmp<opc, MRMSrcReg, _, (outs _.KRC:$dst),
3517 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3518 "$src2, $src1", "$src1, $src2",
3519 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
3522 defm rm : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3523 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3524 "$src2, $src1", "$src1, $src2",
3525 (OpNode (_.VT _.RC:$src1),
3526 (_.VT (bitconvert (_.LdFrag addr:$src2))))>,
3528 EVEX_CD8<_.EltSize, CD8VF>;
3531 multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3532 X86VectorVTInfo _> {
3534 defm rmb : AVX512_maskable_cmp<opc, MRMSrcMem, _, (outs _.KRC:$dst),
3535 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3536 "${src2}"##_.BroadcastStr##", $src1",
3537 "$src1, ${src2}"##_.BroadcastStr,
3538 (OpNode (_.VT _.RC:$src1), (_.VT (X86VBroadcast
3539 (_.ScalarLdFrag addr:$src2))))>,
3540 EVEX_B, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3542 multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3543 AVX512VLVectorVTInfo _> {
3544 let Predicates = [HasAVX512] in
3545 defm Z : avx512_vptest<opc, OpcodeStr, OpNode, _.info512>,
3546 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3548 let Predicates = [HasAVX512, HasVLX] in {
3549 defm Z256 : avx512_vptest<opc, OpcodeStr, OpNode, _.info256>,
3550 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3551 defm Z128 : avx512_vptest<opc, OpcodeStr, OpNode, _.info128>,
3552 avx512_vptest_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3556 multiclass avx512_vptest_dq<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3557 defm D : avx512_vptest_dq_sizes<opc, OpcodeStr#"d", OpNode,
3559 defm Q : avx512_vptest_dq_sizes<opc, OpcodeStr#"q", OpNode,
3560 avx512vl_i64_info>, VEX_W;
3563 multiclass avx512_vptest_wb<bits<8> opc, string OpcodeStr,
3565 let Predicates = [HasBWI] in {
3566 defm WZ: avx512_vptest<opc, OpcodeStr#"w", OpNode, v32i16_info>,
3568 defm BZ: avx512_vptest<opc, OpcodeStr#"b", OpNode, v64i8_info>,
3571 let Predicates = [HasVLX, HasBWI] in {
3573 defm WZ256: avx512_vptest<opc, OpcodeStr#"w", OpNode, v16i16x_info>,
3575 defm WZ128: avx512_vptest<opc, OpcodeStr#"w", OpNode, v8i16x_info>,
3577 defm BZ256: avx512_vptest<opc, OpcodeStr#"b", OpNode, v32i8x_info>,
3579 defm BZ128: avx512_vptest<opc, OpcodeStr#"b", OpNode, v16i8x_info>,
3584 multiclass avx512_vptest_all_forms<bits<8> opc_wb, bits<8> opc_dq, string OpcodeStr,
3586 avx512_vptest_wb <opc_wb, OpcodeStr, OpNode>,
3587 avx512_vptest_dq<opc_dq, OpcodeStr, OpNode>;
3589 defm VPTESTM : avx512_vptest_all_forms<0x26, 0x27, "vptestm", X86testm>, T8PD;
3590 defm VPTESTNM : avx512_vptest_all_forms<0x26, 0x27, "vptestnm", X86testnm>, T8XS;
3592 def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3593 (v16i32 VR512:$src2), (i16 -1))),
3594 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3596 def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3597 (v8i64 VR512:$src2), (i8 -1))),
3598 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
3600 //===----------------------------------------------------------------------===//
3601 // AVX-512 Shift instructions
3602 //===----------------------------------------------------------------------===//
3603 multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3604 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3605 defm ri : AVX512_maskable<opc, ImmFormR, _, (outs _.RC:$dst),
3606 (ins _.RC:$src1, u8imm:$src2), OpcodeStr,
3607 "$src2, $src1", "$src1, $src2",
3608 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))),
3609 SSE_INTSHIFT_ITINS_P.rr>;
3611 defm mi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3612 (ins _.MemOp:$src1, u8imm:$src2), OpcodeStr,
3613 "$src2, $src1", "$src1, $src2",
3614 (_.VT (OpNode (_.VT (bitconvert (_.LdFrag addr:$src1))),
3616 SSE_INTSHIFT_ITINS_P.rm>;
3619 multiclass avx512_shift_rmbi<bits<8> opc, Format ImmFormM,
3620 string OpcodeStr, SDNode OpNode, X86VectorVTInfo _> {
3622 defm mbi : AVX512_maskable<opc, ImmFormM, _, (outs _.RC:$dst),
3623 (ins _.ScalarMemOp:$src1, u8imm:$src2), OpcodeStr,
3624 "$src2, ${src1}"##_.BroadcastStr, "${src1}"##_.BroadcastStr##", $src2",
3625 (_.VT (OpNode (X86VBroadcast (_.ScalarLdFrag addr:$src1)), (i8 imm:$src2))),
3626 SSE_INTSHIFT_ITINS_P.rm>, EVEX_B;
3629 multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3630 ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {
3631 // src2 is always 128-bit
3632 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3633 (ins _.RC:$src1, VR128X:$src2), OpcodeStr,
3634 "$src2, $src1", "$src1, $src2",
3635 (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),
3636 SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;
3637 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3638 (ins _.RC:$src1, i128mem:$src2), OpcodeStr,
3639 "$src2, $src1", "$src1, $src2",
3640 (_.VT (OpNode _.RC:$src1, (bc_frag (loadv2i64 addr:$src2)))),
3641 SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase,
3645 multiclass avx512_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3646 ValueType SrcVT, PatFrag bc_frag,
3647 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
3648 let Predicates = [prd] in
3649 defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3650 VTInfo.info512>, EVEX_V512,
3651 EVEX_CD8<VTInfo.info512.EltSize, CD8VQ> ;
3652 let Predicates = [prd, HasVLX] in {
3653 defm Z256 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3654 VTInfo.info256>, EVEX_V256,
3655 EVEX_CD8<VTInfo.info256.EltSize, CD8VH>;
3656 defm Z128 : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag,
3657 VTInfo.info128>, EVEX_V128,
3658 EVEX_CD8<VTInfo.info128.EltSize, CD8VF>;
3662 multiclass avx512_shift_types<bits<8> opcd, bits<8> opcq, bits<8> opcw,
3663 string OpcodeStr, SDNode OpNode> {
3664 defm D : avx512_shift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,
3665 avx512vl_i32_info, HasAVX512>;
3666 defm Q : avx512_shift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,
3667 avx512vl_i64_info, HasAVX512>, VEX_W;
3668 defm W : avx512_shift_sizes<opcw, OpcodeStr#"w", OpNode, v8i16, bc_v8i16,
3669 avx512vl_i16_info, HasBWI>;
3672 multiclass avx512_shift_rmi_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3673 string OpcodeStr, SDNode OpNode,
3674 AVX512VLVectorVTInfo VTInfo> {
3675 let Predicates = [HasAVX512] in
3676 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3678 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3679 VTInfo.info512>, EVEX_V512;
3680 let Predicates = [HasAVX512, HasVLX] in {
3681 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3683 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3684 VTInfo.info256>, EVEX_V256;
3685 defm Z128: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3687 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3688 VTInfo.info128>, EVEX_V128;
3692 multiclass avx512_shift_rmi_w<bits<8> opcw,
3693 Format ImmFormR, Format ImmFormM,
3694 string OpcodeStr, SDNode OpNode> {
3695 let Predicates = [HasBWI] in
3696 defm WZ: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3697 v32i16_info>, EVEX_V512;
3698 let Predicates = [HasVLX, HasBWI] in {
3699 defm WZ256: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3700 v16i16x_info>, EVEX_V256;
3701 defm WZ128: avx512_shift_rmi<opcw, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3702 v8i16x_info>, EVEX_V128;
3706 multiclass avx512_shift_rmi_dq<bits<8> opcd, bits<8> opcq,
3707 Format ImmFormR, Format ImmFormM,
3708 string OpcodeStr, SDNode OpNode> {
3709 defm D: avx512_shift_rmi_sizes<opcd, ImmFormR, ImmFormM, OpcodeStr#"d", OpNode,
3710 avx512vl_i32_info>, EVEX_CD8<32, CD8VF>;
3711 defm Q: avx512_shift_rmi_sizes<opcq, ImmFormR, ImmFormM, OpcodeStr#"q", OpNode,
3712 avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, VEX_W;
3715 defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli>,
3716 avx512_shift_rmi_w<0x71, MRM2r, MRM2m, "vpsrlw", X86vsrli>, AVX512BIi8Base, EVEX_4V;
3718 defm VPSLL : avx512_shift_rmi_dq<0x72, 0x73, MRM6r, MRM6m, "vpsll", X86vshli>,
3719 avx512_shift_rmi_w<0x71, MRM6r, MRM6m, "vpsllw", X86vshli>, AVX512BIi8Base, EVEX_4V;
3721 defm VPSRA : avx512_shift_rmi_dq<0x72, 0x72, MRM4r, MRM4m, "vpsra", X86vsrai>,
3722 avx512_shift_rmi_w<0x71, MRM4r, MRM4m, "vpsraw", X86vsrai>, AVX512BIi8Base, EVEX_4V;
3724 defm VPROR : avx512_shift_rmi_dq<0x72, 0x72, MRM0r, MRM0m, "vpror", rotr>, AVX512BIi8Base, EVEX_4V;
3725 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", rotl>, AVX512BIi8Base, EVEX_4V;
3727 defm VPSLL : avx512_shift_types<0xF2, 0xF3, 0xF1, "vpsll", X86vshl>;
3728 defm VPSRA : avx512_shift_types<0xE2, 0xE2, 0xE1, "vpsra", X86vsra>;
3729 defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl>;
3731 //===-------------------------------------------------------------------===//
3732 // Variable Bit Shifts
3733 //===-------------------------------------------------------------------===//
3734 multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3735 X86VectorVTInfo _> {
3736 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
3737 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
3738 "$src2, $src1", "$src1, $src2",
3739 (_.VT (OpNode _.RC:$src1, (_.VT _.RC:$src2))),
3740 SSE_INTSHIFT_ITINS_P.rr>, AVX5128IBase, EVEX_4V;
3742 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3743 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
3744 "$src2, $src1", "$src1, $src2",
3745 (_.VT (OpNode _.RC:$src1,
3746 (_.VT (bitconvert (_.LdFrag addr:$src2))))),
3747 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_4V,
3748 EVEX_CD8<_.EltSize, CD8VF>;
3751 multiclass avx512_var_shift_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
3752 X86VectorVTInfo _> {
3754 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
3755 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
3756 "${src2}"##_.BroadcastStr##", $src1",
3757 "$src1, ${src2}"##_.BroadcastStr,
3758 (_.VT (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3759 (_.ScalarLdFrag addr:$src2))))),
3760 SSE_INTSHIFT_ITINS_P.rm>, AVX5128IBase, EVEX_B,
3761 EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
3763 multiclass avx512_var_shift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3764 AVX512VLVectorVTInfo _> {
3765 let Predicates = [HasAVX512] in
3766 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
3767 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3769 let Predicates = [HasAVX512, HasVLX] in {
3770 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
3771 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3772 defm Z128 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info128>,
3773 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
3777 multiclass avx512_var_shift_types<bits<8> opc, string OpcodeStr,
3779 defm D : avx512_var_shift_sizes<opc, OpcodeStr#"d", OpNode,
3781 defm Q : avx512_var_shift_sizes<opc, OpcodeStr#"q", OpNode,
3782 avx512vl_i64_info>, VEX_W;
3785 multiclass avx512_var_shift_w<bits<8> opc, string OpcodeStr,
3787 let Predicates = [HasBWI] in
3788 defm WZ: avx512_var_shift<opc, OpcodeStr, OpNode, v32i16_info>,
3790 let Predicates = [HasVLX, HasBWI] in {
3792 defm WZ256: avx512_var_shift<opc, OpcodeStr, OpNode, v16i16x_info>,
3794 defm WZ128: avx512_var_shift<opc, OpcodeStr, OpNode, v8i16x_info>,
3799 defm VPSLLV : avx512_var_shift_types<0x47, "vpsllv", shl>,
3800 avx512_var_shift_w<0x12, "vpsllvw", shl>;
3801 defm VPSRAV : avx512_var_shift_types<0x46, "vpsrav", sra>,
3802 avx512_var_shift_w<0x11, "vpsravw", sra>;
3803 defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", srl>,
3804 avx512_var_shift_w<0x10, "vpsrlvw", srl>;
3805 defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr>;
3806 defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl>;
3808 //===-------------------------------------------------------------------===//
3809 // 1-src variable permutation VPERMW/D/Q
3810 //===-------------------------------------------------------------------===//
3811 multiclass avx512_vperm_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
3812 AVX512VLVectorVTInfo _> {
3813 let Predicates = [HasAVX512] in
3814 defm Z : avx512_var_shift<opc, OpcodeStr, OpNode, _.info512>,
3815 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
3817 let Predicates = [HasAVX512, HasVLX] in
3818 defm Z256 : avx512_var_shift<opc, OpcodeStr, OpNode, _.info256>,
3819 avx512_var_shift_mb<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
3822 multiclass avx512_vpermi_dq_sizes<bits<8> opc, Format ImmFormR, Format ImmFormM,
3823 string OpcodeStr, SDNode OpNode,
3824 AVX512VLVectorVTInfo VTInfo> {
3825 let Predicates = [HasAVX512] in
3826 defm Z: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3828 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3829 VTInfo.info512>, EVEX_V512;
3830 let Predicates = [HasAVX512, HasVLX] in
3831 defm Z256: avx512_shift_rmi<opc, ImmFormR, ImmFormM, OpcodeStr, OpNode,
3833 avx512_shift_rmbi<opc, ImmFormM, OpcodeStr, OpNode,
3834 VTInfo.info256>, EVEX_V256;
3838 defm VPERM : avx512_var_shift_w<0x8D, "vpermw", X86VPermv>;
3840 defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv,
3842 defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv,
3843 avx512vl_i64_info>, VEX_W;
3844 defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv,
3846 defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv,
3847 avx512vl_f64_info>, VEX_W;
3849 defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq",
3850 X86VPermi, avx512vl_i64_info>,
3851 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
3852 defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd",
3853 X86VPermi, avx512vl_f64_info>,
3854 EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W;
3856 //===----------------------------------------------------------------------===//
3857 // AVX-512 - VPSHUFD, VPSHUFLW, VPSHUFHW
3858 //===----------------------------------------------------------------------===//
3860 defm VPSHUFD : avx512_shift_rmi_sizes<0x70, MRMSrcReg, MRMSrcMem, "vpshufd",
3861 X86PShufd, avx512vl_i32_info>,
3862 EVEX, AVX512BIi8Base, EVEX_CD8<32, CD8VF>;
3863 defm VPSHUFH : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshufhw",
3864 X86PShufhw>, EVEX, AVX512XSIi8Base, VEX_W;
3865 defm VPSHUFL : avx512_shift_rmi_w<0x70, MRMSrcReg, MRMSrcMem, "vpshuflw",
3866 X86PShuflw>, EVEX, AVX512XDIi8Base, VEX_W;
3867 //===----------------------------------------------------------------------===//
3868 // AVX-512 - MOVDDUP
3869 //===----------------------------------------------------------------------===//
3871 multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3872 X86MemOperand x86memop, PatFrag memop_frag> {
3873 def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3874 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3875 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3876 def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3877 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3879 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3882 defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, loadv8f64>,
3883 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3884 def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3885 (VMOVDDUPZrm addr:$src)>;
3887 //===---------------------------------------------------------------------===//
3888 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3889 //===---------------------------------------------------------------------===//
3890 multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3891 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3892 X86MemOperand x86memop> {
3893 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3894 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3895 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3897 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3898 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3899 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3902 defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3903 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3904 EVEX_CD8<32, CD8VF>;
3905 defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3906 v16f32, VR512, loadv16f32, f512mem>, EVEX_V512,
3907 EVEX_CD8<32, CD8VF>;
3909 def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3910 def : Pat<(v16i32 (X86Movshdup (loadv16i32 addr:$src))),
3911 (VMOVSHDUPZrm addr:$src)>;
3912 def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3913 def : Pat<(v16i32 (X86Movsldup (loadv16i32 addr:$src))),
3914 (VMOVSLDUPZrm addr:$src)>;
3916 //===----------------------------------------------------------------------===//
3917 // Move Low to High and High to Low packed FP Instructions
3918 //===----------------------------------------------------------------------===//
3919 def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3920 (ins VR128X:$src1, VR128X:$src2),
3921 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3922 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3923 IIC_SSE_MOV_LH>, EVEX_4V;
3924 def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3925 (ins VR128X:$src1, VR128X:$src2),
3926 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3927 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3928 IIC_SSE_MOV_LH>, EVEX_4V;
3930 let Predicates = [HasAVX512] in {
3932 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3933 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3934 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3935 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
3938 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3939 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3942 //===----------------------------------------------------------------------===//
3943 // FMA - Fused Multiply Operations
3946 let Constraints = "$src1 = $dst" in {
3947 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3948 multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3949 SDPatternOperator OpNode = null_frag> {
3950 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3951 (ins _.RC:$src2, _.RC:$src3),
3952 OpcodeStr, "$src3, $src2", "$src2, $src3",
3953 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
3957 defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3958 (ins _.RC:$src2, _.MemOp:$src3),
3959 OpcodeStr, "$src3, $src2", "$src2, $src3",
3960 (_.VT (OpNode _.RC:$src1, _.RC:$src2, (_.LdFrag addr:$src3)))>,
3963 defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
3964 (ins _.RC:$src2, _.ScalarMemOp:$src3),
3965 OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
3966 !strconcat("$src2, ${src3}", _.BroadcastStr ),
3968 _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
3969 AVX512FMA3Base, EVEX_B;
3971 } // Constraints = "$src1 = $dst"
3973 let Constraints = "$src1 = $dst" in {
3974 // Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3975 multiclass avx512_fma3_round_rrb<bits<8> opc, string OpcodeStr,
3977 SDPatternOperator OpNode> {
3978 defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3979 (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
3980 OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
3981 (_.VT ( OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 imm:$rc)))>,
3982 AVX512FMA3Base, EVEX_B, EVEX_RC;
3984 } // Constraints = "$src1 = $dst"
3986 multiclass avx512_fma3_round_forms<bits<8> opc213, string OpcodeStr,
3987 X86VectorVTInfo VTI, SDPatternOperator OpNode> {
3988 defm v213r : avx512_fma3_round_rrb<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3989 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
3992 multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
3993 string OpcodeStr, X86VectorVTInfo VTI,
3994 SDPatternOperator OpNode> {
3995 defm v213r : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3996 VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
3997 defm v231r : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3998 VTI>, EVEX_CD8<VTI.EltSize, CD8VF>;
4001 multiclass avx512_fma3p<bits<8> opc213, bits<8> opc231,
4003 SDPatternOperator OpNode,
4004 SDPatternOperator OpNodeRnd> {
4005 let ExeDomain = SSEPackedSingle in {
4006 defm NAME##PSZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4007 v16f32_info, OpNode>,
4008 avx512_fma3_round_forms<opc213, OpcodeStr,
4009 v16f32_info, OpNodeRnd>, EVEX_V512;
4010 defm NAME##PSZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4011 v8f32x_info, OpNode>, EVEX_V256;
4012 defm NAME##PSZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4013 v4f32x_info, OpNode>, EVEX_V128;
4015 let ExeDomain = SSEPackedDouble in {
4016 defm NAME##PDZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4017 v8f64_info, OpNode>,
4018 avx512_fma3_round_forms<opc213, OpcodeStr, v8f64_info,
4019 OpNodeRnd>, EVEX_V512, VEX_W;
4020 defm NAME##PDZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4021 v4f64x_info, OpNode>,
4023 defm NAME##PDZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
4024 v2f64x_info, OpNode>,
4029 defm VFMADD : avx512_fma3p<0xA8, 0xB8, "vfmadd", X86Fmadd, X86FmaddRnd>;
4030 defm VFMSUB : avx512_fma3p<0xAA, 0xBA, "vfmsub", X86Fmsub, X86FmsubRnd>;
4031 defm VFMADDSUB : avx512_fma3p<0xA6, 0xB6, "vfmaddsub", X86Fmaddsub, X86FmaddsubRnd>;
4032 defm VFMSUBADD : avx512_fma3p<0xA7, 0xB7, "vfmsubadd", X86Fmsubadd, X86FmsubaddRnd>;
4033 defm VFNMADD : avx512_fma3p<0xAC, 0xBC, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
4034 defm VFNMSUB : avx512_fma3p<0xAE, 0xBE, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
4036 let Constraints = "$src1 = $dst" in {
4037 multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
4038 X86VectorVTInfo _> {
4040 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
4041 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
4042 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
4043 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.LdFrag addr:$src2),
4045 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
4046 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
4047 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr,
4048 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
4050 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
4051 (_.ScalarLdFrag addr:$src2))),
4052 _.RC:$src3))]>, EVEX_B;
4054 } // Constraints = "$src1 = $dst"
4056 multiclass avx512_fma3p_m132_f<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4058 let ExeDomain = SSEPackedSingle in {
4059 defm NAME##PSZ : avx512_fma3p_m132<opc, OpcodeStr##ps,
4060 OpNode,v16f32_info>, EVEX_V512,
4061 EVEX_CD8<32, CD8VF>;
4062 defm NAME##PSZ256 : avx512_fma3p_m132<opc, OpcodeStr##ps,
4063 OpNode, v8f32x_info>, EVEX_V256,
4064 EVEX_CD8<32, CD8VF>;
4065 defm NAME##PSZ128 : avx512_fma3p_m132<opc, OpcodeStr##ps,
4066 OpNode, v4f32x_info>, EVEX_V128,
4067 EVEX_CD8<32, CD8VF>;
4069 let ExeDomain = SSEPackedDouble in {
4070 defm NAME##PDZ : avx512_fma3p_m132<opc, OpcodeStr##pd,
4071 OpNode, v8f64_info>, EVEX_V512,
4072 VEX_W, EVEX_CD8<32, CD8VF>;
4073 defm NAME##PDZ256 : avx512_fma3p_m132<opc, OpcodeStr##pd,
4074 OpNode, v4f64x_info>, EVEX_V256,
4075 VEX_W, EVEX_CD8<32, CD8VF>;
4076 defm NAME##PDZ128 : avx512_fma3p_m132<opc, OpcodeStr##pd,
4077 OpNode, v2f64x_info>, EVEX_V128,
4078 VEX_W, EVEX_CD8<32, CD8VF>;
4082 defm VFMADD132 : avx512_fma3p_m132_f<0x98, "vfmadd132", X86Fmadd>;
4083 defm VFMSUB132 : avx512_fma3p_m132_f<0x9A, "vfmsub132", X86Fmsub>;
4084 defm VFMADDSUB132 : avx512_fma3p_m132_f<0x96, "vfmaddsub132", X86Fmaddsub>;
4085 defm VFMSUBADD132 : avx512_fma3p_m132_f<0x97, "vfmsubadd132", X86Fmsubadd>;
4086 defm VFNMADD132 : avx512_fma3p_m132_f<0x9C, "vfnmadd132", X86Fnmadd>;
4087 defm VFNMSUB132 : avx512_fma3p_m132_f<0x9E, "vfnmsub132", X86Fnmsub>;
4090 let Constraints = "$src1 = $dst" in {
4091 multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4092 RegisterClass RC, ValueType OpVT,
4093 X86MemOperand x86memop, Operand memop,
4095 let isCommutable = 1 in
4096 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
4097 (ins RC:$src1, RC:$src2, RC:$src3),
4098 !strconcat(OpcodeStr,
4099 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4101 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
4103 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
4104 (ins RC:$src1, RC:$src2, f128mem:$src3),
4105 !strconcat(OpcodeStr,
4106 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4108 (OpVT (OpNode RC:$src2, RC:$src1,
4109 (mem_frag addr:$src3))))]>;
4111 } // Constraints = "$src1 = $dst"
4113 defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
4114 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4115 defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
4116 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4117 defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
4118 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4119 defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
4120 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4121 defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
4122 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4123 defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
4124 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4125 defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
4126 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
4127 defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
4128 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
4130 //===----------------------------------------------------------------------===//
4131 // AVX-512 Scalar convert from sign integer to float/double
4132 //===----------------------------------------------------------------------===//
4134 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4135 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4136 PatFrag ld_frag, string asm> {
4137 let hasSideEffects = 0 in {
4138 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
4139 (ins DstVT.FRC:$src1, SrcRC:$src),
4140 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4143 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
4144 (ins DstVT.FRC:$src1, x86memop:$src),
4145 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
4147 } // hasSideEffects = 0
4148 let isCodeGenOnly = 1 in {
4149 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4150 (ins DstVT.RC:$src1, SrcRC:$src2),
4151 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4152 [(set DstVT.RC:$dst,
4153 (OpNode (DstVT.VT DstVT.RC:$src1),
4155 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4157 def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst),
4158 (ins DstVT.RC:$src1, x86memop:$src2),
4159 !strconcat(asm,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4160 [(set DstVT.RC:$dst,
4161 (OpNode (DstVT.VT DstVT.RC:$src1),
4162 (ld_frag addr:$src2),
4163 (i32 FROUND_CURRENT)))]>, EVEX_4V;
4164 }//isCodeGenOnly = 1
4167 multiclass avx512_vcvtsi_round<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4168 X86VectorVTInfo DstVT, string asm> {
4169 def rrb_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
4170 (ins DstVT.RC:$src1, SrcRC:$src2, AVX512RC:$rc),
4172 "\t{$src2, $rc, $src1, $dst|$dst, $src1, $rc, $src2}"),
4173 [(set DstVT.RC:$dst,
4174 (OpNode (DstVT.VT DstVT.RC:$src1),
4176 (i32 imm:$rc)))]>, EVEX_4V, EVEX_B, EVEX_RC;
4179 multiclass avx512_vcvtsi_common<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
4180 X86VectorVTInfo DstVT, X86MemOperand x86memop,
4181 PatFrag ld_frag, string asm> {
4182 defm NAME : avx512_vcvtsi_round<opc, OpNode, SrcRC, DstVT, asm>,
4183 avx512_vcvtsi<opc, OpNode, SrcRC, DstVT, x86memop, ld_frag, asm>,
4187 let Predicates = [HasAVX512] in {
4188 defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4189 v4f32x_info, i32mem, loadi32, "cvtsi2ss{l}">,
4190 XS, EVEX_CD8<32, CD8VT1>;
4191 defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4192 v4f32x_info, i64mem, loadi64, "cvtsi2ss{q}">,
4193 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4194 defm VCVTSI2SDZ : avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR32,
4195 v2f64x_info, i32mem, loadi32, "cvtsi2sd{l}">,
4196 XD, EVEX_CD8<32, CD8VT1>;
4197 defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFpRnd, GR64,
4198 v2f64x_info, i64mem, loadi64, "cvtsi2sd{q}">,
4199 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4201 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
4202 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4203 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
4204 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4205 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
4206 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4207 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
4208 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4210 def : Pat<(f32 (sint_to_fp GR32:$src)),
4211 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4212 def : Pat<(f32 (sint_to_fp GR64:$src)),
4213 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4214 def : Pat<(f64 (sint_to_fp GR32:$src)),
4215 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4216 def : Pat<(f64 (sint_to_fp GR64:$src)),
4217 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4219 defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86SuintToFpRnd, GR32,
4220 v4f32x_info, i32mem, loadi32,
4221 "cvtusi2ss{l}">, XS, EVEX_CD8<32, CD8VT1>;
4222 defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86SuintToFpRnd, GR64,
4223 v4f32x_info, i64mem, loadi64, "cvtusi2ss{q}">,
4224 XS, VEX_W, EVEX_CD8<64, CD8VT1>;
4225 defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, X86SuintToFpRnd, GR32, v2f64x_info,
4226 i32mem, loadi32, "cvtusi2sd{l}">,
4227 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
4228 defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86SuintToFpRnd, GR64,
4229 v2f64x_info, i64mem, loadi64, "cvtusi2sd{q}">,
4230 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4232 def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
4233 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4234 def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
4235 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
4236 def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
4237 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4238 def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
4239 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
4241 def : Pat<(f32 (uint_to_fp GR32:$src)),
4242 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
4243 def : Pat<(f32 (uint_to_fp GR64:$src)),
4244 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
4245 def : Pat<(f64 (uint_to_fp GR32:$src)),
4246 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
4247 def : Pat<(f64 (uint_to_fp GR64:$src)),
4248 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
4251 //===----------------------------------------------------------------------===//
4252 // AVX-512 Scalar convert from float/double to integer
4253 //===----------------------------------------------------------------------===//
4254 multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4255 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
4257 let hasSideEffects = 0 in {
4258 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4259 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4260 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
4261 Requires<[HasAVX512]>;
4263 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
4264 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
4265 Requires<[HasAVX512]>;
4266 } // hasSideEffects = 0
4268 let Predicates = [HasAVX512] in {
4269 // Convert float/double to signed/unsigned int 32/64
4270 defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
4271 ssmem, sse_load_f32, "cvtss2si">,
4272 XS, EVEX_CD8<32, CD8VT1>;
4273 defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
4274 ssmem, sse_load_f32, "cvtss2si">,
4275 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
4276 defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
4277 ssmem, sse_load_f32, "cvtss2usi">,
4278 XS, EVEX_CD8<32, CD8VT1>;
4279 defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
4280 int_x86_avx512_cvtss2usi64, ssmem,
4281 sse_load_f32, "cvtss2usi">, XS, VEX_W,
4282 EVEX_CD8<32, CD8VT1>;
4283 defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
4284 sdmem, sse_load_f64, "cvtsd2si">,
4285 XD, EVEX_CD8<64, CD8VT1>;
4286 defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
4287 sdmem, sse_load_f64, "cvtsd2si">,
4288 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
4289 defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
4290 sdmem, sse_load_f64, "cvtsd2usi">,
4291 XD, EVEX_CD8<64, CD8VT1>;
4292 defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
4293 int_x86_avx512_cvtsd2usi64, sdmem,
4294 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
4295 EVEX_CD8<64, CD8VT1>;
4297 let isCodeGenOnly = 1 in {
4298 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4299 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
4300 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
4301 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4302 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
4303 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
4304 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4305 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
4306 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4307 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
4308 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
4309 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
4311 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
4312 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
4313 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
4314 } // isCodeGenOnly = 1
4316 // Convert float/double to signed/unsigned int 32/64 with truncation
4317 let isCodeGenOnly = 1 in {
4318 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
4319 ssmem, sse_load_f32, "cvttss2si">,
4320 XS, EVEX_CD8<32, CD8VT1>;
4321 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
4322 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
4323 "cvttss2si">, XS, VEX_W,
4324 EVEX_CD8<32, CD8VT1>;
4325 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
4326 sdmem, sse_load_f64, "cvttsd2si">, XD,
4327 EVEX_CD8<64, CD8VT1>;
4328 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
4329 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
4330 "cvttsd2si">, XD, VEX_W,
4331 EVEX_CD8<64, CD8VT1>;
4332 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
4333 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
4334 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
4335 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
4336 int_x86_avx512_cvttss2usi64, ssmem,
4337 sse_load_f32, "cvttss2usi">, XS, VEX_W,
4338 EVEX_CD8<32, CD8VT1>;
4339 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
4340 int_x86_avx512_cvttsd2usi,
4341 sdmem, sse_load_f64, "cvttsd2usi">, XD,
4342 EVEX_CD8<64, CD8VT1>;
4343 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
4344 int_x86_avx512_cvttsd2usi64, sdmem,
4345 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
4346 EVEX_CD8<64, CD8VT1>;
4347 } // isCodeGenOnly = 1
4349 multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
4350 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
4352 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4353 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4354 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
4355 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4356 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4357 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
4360 defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
4361 loadf32, "cvttss2si">, XS,
4362 EVEX_CD8<32, CD8VT1>;
4363 defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
4364 loadf32, "cvttss2usi">, XS,
4365 EVEX_CD8<32, CD8VT1>;
4366 defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
4367 loadf32, "cvttss2si">, XS, VEX_W,
4368 EVEX_CD8<32, CD8VT1>;
4369 defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
4370 loadf32, "cvttss2usi">, XS, VEX_W,
4371 EVEX_CD8<32, CD8VT1>;
4372 defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
4373 loadf64, "cvttsd2si">, XD,
4374 EVEX_CD8<64, CD8VT1>;
4375 defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
4376 loadf64, "cvttsd2usi">, XD,
4377 EVEX_CD8<64, CD8VT1>;
4378 defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
4379 loadf64, "cvttsd2si">, XD, VEX_W,
4380 EVEX_CD8<64, CD8VT1>;
4381 defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
4382 loadf64, "cvttsd2usi">, XD, VEX_W,
4383 EVEX_CD8<64, CD8VT1>;
4385 //===----------------------------------------------------------------------===//
4386 // AVX-512 Convert form float to double and back
4387 //===----------------------------------------------------------------------===//
4388 let hasSideEffects = 0 in {
4389 def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
4390 (ins FR32X:$src1, FR32X:$src2),
4391 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4392 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
4394 def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
4395 (ins FR32X:$src1, f32mem:$src2),
4396 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4397 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
4398 EVEX_CD8<32, CD8VT1>;
4400 // Convert scalar double to scalar single
4401 def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
4402 (ins FR64X:$src1, FR64X:$src2),
4403 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4404 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
4406 def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
4407 (ins FR64X:$src1, f64mem:$src2),
4408 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4409 []>, EVEX_4V, VEX_LIG, VEX_W,
4410 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
4413 def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
4414 Requires<[HasAVX512]>;
4415 def : Pat<(fextend (loadf32 addr:$src)),
4416 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
4418 def : Pat<(extloadf32 addr:$src),
4419 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
4420 Requires<[HasAVX512, OptForSize]>;
4422 def : Pat<(extloadf32 addr:$src),
4423 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
4424 Requires<[HasAVX512, OptForSpeed]>;
4426 def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
4427 Requires<[HasAVX512]>;
4429 multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
4430 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4431 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4433 let hasSideEffects = 0 in {
4434 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4435 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4437 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4438 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4439 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4440 [], d>, EVEX, EVEX_B, EVEX_RC;
4442 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4443 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4445 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4446 } // hasSideEffects = 0
4449 multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
4450 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
4451 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
4453 let hasSideEffects = 0 in {
4454 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4455 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4457 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
4459 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4460 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4462 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
4463 } // hasSideEffects = 0
4466 defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
4467 loadv8f64, f512mem, v8f32, v8f64,
4468 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
4469 EVEX_CD8<64, CD8VF>;
4471 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
4472 loadv4f64, f256mem, v8f64, v8f32,
4473 SSEPackedDouble>, EVEX_V512, PS,
4474 EVEX_CD8<32, CD8VH>;
4475 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4476 (VCVTPS2PDZrm addr:$src)>;
4478 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4479 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
4480 (VCVTPD2PSZrr VR512:$src)>;
4482 def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
4483 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
4484 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
4486 //===----------------------------------------------------------------------===//
4487 // AVX-512 Vector convert from sign integer to float/double
4488 //===----------------------------------------------------------------------===//
4490 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
4491 loadv8i64, i512mem, v16f32, v16i32,
4492 SSEPackedSingle>, EVEX_V512, PS,
4493 EVEX_CD8<32, CD8VF>;
4495 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
4496 loadv4i64, i256mem, v8f64, v8i32,
4497 SSEPackedDouble>, EVEX_V512, XS,
4498 EVEX_CD8<32, CD8VH>;
4500 defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
4501 loadv16f32, f512mem, v16i32, v16f32,
4502 SSEPackedSingle>, EVEX_V512, XS,
4503 EVEX_CD8<32, CD8VF>;
4505 defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
4506 loadv8f64, f512mem, v8i32, v8f64,
4507 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
4508 EVEX_CD8<64, CD8VF>;
4510 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
4511 loadv16f32, f512mem, v16i32, v16f32,
4512 SSEPackedSingle>, EVEX_V512, PS,
4513 EVEX_CD8<32, CD8VF>;
4515 // cvttps2udq (src, 0, mask-all-ones, sae-current)
4516 def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
4517 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
4518 (VCVTTPS2UDQZrr VR512:$src)>;
4520 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
4521 loadv8f64, f512mem, v8i32, v8f64,
4522 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
4523 EVEX_CD8<64, CD8VF>;
4525 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
4526 def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
4527 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
4528 (VCVTTPD2UDQZrr VR512:$src)>;
4530 defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
4531 loadv4i64, f256mem, v8f64, v8i32,
4532 SSEPackedDouble>, EVEX_V512, XS,
4533 EVEX_CD8<32, CD8VH>;
4535 defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
4536 loadv16i32, f512mem, v16f32, v16i32,
4537 SSEPackedSingle>, EVEX_V512, XD,
4538 EVEX_CD8<32, CD8VF>;
4540 def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
4541 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4542 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4544 def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
4545 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
4546 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4548 def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
4549 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4550 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
4552 def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
4553 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
4554 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
4556 def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
4557 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
4558 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
4560 def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
4561 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4562 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
4563 def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
4564 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4565 (VCVTDQ2PDZrr VR256X:$src)>;
4566 def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
4567 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
4568 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
4569 def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
4570 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4571 (VCVTUDQ2PDZrr VR256X:$src)>;
4573 multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
4574 RegisterClass DstRC, PatFrag mem_frag,
4575 X86MemOperand x86memop, Domain d> {
4576 let hasSideEffects = 0 in {
4577 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
4578 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4580 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
4581 !strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
4582 [], d>, EVEX, EVEX_B, EVEX_RC;
4584 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
4585 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
4587 } // hasSideEffects = 0
4590 defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
4591 loadv16f32, f512mem, SSEPackedSingle>, PD,
4592 EVEX_V512, EVEX_CD8<32, CD8VF>;
4593 defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
4594 loadv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
4595 EVEX_V512, EVEX_CD8<64, CD8VF>;
4597 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
4598 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4599 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
4601 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
4602 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4603 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
4605 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
4606 loadv16f32, f512mem, SSEPackedSingle>,
4607 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
4608 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
4609 loadv8f64, f512mem, SSEPackedDouble>, VEX_W,
4610 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
4612 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
4613 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
4614 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
4616 def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
4617 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
4618 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
4620 let Predicates = [HasAVX512] in {
4621 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
4622 (VCVTPD2PSZrm addr:$src)>;
4623 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
4624 (VCVTPS2PDZrm addr:$src)>;
4627 //===----------------------------------------------------------------------===//
4628 // Half precision conversion instructions
4629 //===----------------------------------------------------------------------===//
4630 multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4631 X86MemOperand x86memop> {
4632 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4633 "vcvtph2ps\t{$src, $dst|$dst, $src}",
4635 let hasSideEffects = 0, mayLoad = 1 in
4636 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4637 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4640 multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4641 X86MemOperand x86memop> {
4642 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4643 (ins srcRC:$src1, i32u8imm:$src2),
4644 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4646 let hasSideEffects = 0, mayStore = 1 in
4647 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4648 (ins x86memop:$dst, srcRC:$src1, i32u8imm:$src2),
4649 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
4652 defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
4653 EVEX_CD8<32, CD8VH>;
4654 defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
4655 EVEX_CD8<32, CD8VH>;
4657 def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4658 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4659 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4661 def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4662 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4663 (VCVTPH2PSZrr VR256X:$src)>;
4665 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4666 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
4667 "ucomiss">, PS, EVEX, VEX_LIG,
4668 EVEX_CD8<32, CD8VT1>;
4669 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
4670 "ucomisd">, PD, EVEX,
4671 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4672 let Pattern = []<dag> in {
4673 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
4674 "comiss">, PS, EVEX, VEX_LIG,
4675 EVEX_CD8<32, CD8VT1>;
4676 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
4677 "comisd">, PD, EVEX,
4678 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4680 let isCodeGenOnly = 1 in {
4681 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
4682 load, "ucomiss">, PS, EVEX, VEX_LIG,
4683 EVEX_CD8<32, CD8VT1>;
4684 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
4685 load, "ucomisd">, PD, EVEX,
4686 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4688 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
4689 load, "comiss">, PS, EVEX, VEX_LIG,
4690 EVEX_CD8<32, CD8VT1>;
4691 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
4692 load, "comisd">, PD, EVEX,
4693 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4697 /// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4698 multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4699 X86MemOperand x86memop> {
4700 let hasSideEffects = 0 in {
4701 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4702 (ins RC:$src1, RC:$src2),
4703 !strconcat(OpcodeStr,
4704 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4705 let mayLoad = 1 in {
4706 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4707 (ins RC:$src1, x86memop:$src2),
4708 !strconcat(OpcodeStr,
4709 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
4714 defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4715 EVEX_CD8<32, CD8VT1>;
4716 defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4717 VEX_W, EVEX_CD8<64, CD8VT1>;
4718 defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4719 EVEX_CD8<32, CD8VT1>;
4720 defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4721 VEX_W, EVEX_CD8<64, CD8VT1>;
4723 def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4724 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4725 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4726 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4728 def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4729 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4730 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4731 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4733 def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4734 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4735 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4736 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4738 def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4739 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4740 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4741 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4743 /// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4744 multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4745 X86VectorVTInfo _> {
4746 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4747 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4748 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4749 let mayLoad = 1 in {
4750 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4751 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4753 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4754 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4755 (ins _.ScalarMemOp:$src), OpcodeStr,
4756 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4758 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4763 multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4764 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4765 EVEX_V512, EVEX_CD8<32, CD8VF>;
4766 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4767 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4769 // Define only if AVX512VL feature is present.
4770 let Predicates = [HasVLX] in {
4771 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4772 OpNode, v4f32x_info>,
4773 EVEX_V128, EVEX_CD8<32, CD8VF>;
4774 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4775 OpNode, v8f32x_info>,
4776 EVEX_V256, EVEX_CD8<32, CD8VF>;
4777 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4778 OpNode, v2f64x_info>,
4779 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4780 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4781 OpNode, v4f64x_info>,
4782 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4786 defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4787 defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
4789 def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4790 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4791 (VRSQRT14PSZr VR512:$src)>;
4792 def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4793 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4794 (VRSQRT14PDZr VR512:$src)>;
4796 def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4797 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4798 (VRCP14PSZr VR512:$src)>;
4799 def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4800 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4801 (VRCP14PDZr VR512:$src)>;
4803 /// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4804 multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
4807 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4808 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4809 "$src2, $src1", "$src1, $src2",
4810 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4811 (i32 FROUND_CURRENT))>;
4813 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
4814 (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
4815 "{sae}, $src2, $src1", "$src1, $src2, {sae}",
4816 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
4817 (i32 FROUND_NO_EXC))>, EVEX_B;
4819 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
4820 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
4821 "$src2, $src1", "$src1, $src2",
4822 (OpNode (_.VT _.RC:$src1),
4823 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
4824 (i32 FROUND_CURRENT))>;
4827 multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4828 defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
4829 EVEX_CD8<32, CD8VT1>;
4830 defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
4831 EVEX_CD8<64, CD8VT1>, VEX_W;
4834 let hasSideEffects = 0, Predicates = [HasERI] in {
4835 defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
4836 defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
4838 /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4840 multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4843 defm r : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4844 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4845 (OpNode (_.VT _.RC:$src), (i32 FROUND_CURRENT))>;
4847 defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4848 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4850 (bitconvert (_.LdFrag addr:$src))),
4851 (i32 FROUND_CURRENT))>;
4853 defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4854 (ins _.MemOp:$src), OpcodeStr,
4855 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4857 (X86VBroadcast (_.ScalarLdFrag addr:$src))),
4858 (i32 FROUND_CURRENT))>, EVEX_B;
4860 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
4862 defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4863 (ins _.RC:$src), OpcodeStr,
4864 "{sae}, $src", "$src, {sae}",
4865 (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
4868 multiclass avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4869 defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4870 avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
4871 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
4872 defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4873 avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
4874 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4877 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
4879 // Define only if AVX512VL feature is present.
4880 let Predicates = [HasVLX] in {
4881 defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
4882 EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;
4883 defm PSZ256 : avx512_fp28_p<opc, OpcodeStr#"ps", v8f32x_info, OpNode>,
4884 EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>;
4885 defm PDZ128 : avx512_fp28_p<opc, OpcodeStr#"pd", v2f64x_info, OpNode>,
4886 EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
4887 defm PDZ256 : avx512_fp28_p<opc, OpcodeStr#"pd", v4f64x_info, OpNode>,
4888 EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>;
4891 let Predicates = [HasERI], hasSideEffects = 0 in {
4893 defm VRSQRT28 : avx512_eri<0xCC, "vrsqrt28", X86rsqrt28>, EVEX;
4894 defm VRCP28 : avx512_eri<0xCA, "vrcp28", X86rcp28>, EVEX;
4895 defm VEXP2 : avx512_eri<0xC8, "vexp2", X86exp2>, EVEX;
4897 defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
4898 avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
4900 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
4901 SDNode OpNodeRnd, X86VectorVTInfo _>{
4902 defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4903 (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
4904 (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
4905 EVEX, EVEX_B, EVEX_RC;
4908 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4909 SDNode OpNode, X86VectorVTInfo _>{
4910 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4911 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4912 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4913 let mayLoad = 1 in {
4914 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4915 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4917 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
4919 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4920 (ins _.ScalarMemOp:$src), OpcodeStr,
4921 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4923 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4928 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4929 Intrinsic F32Int, Intrinsic F64Int,
4930 OpndItins itins_s, OpndItins itins_d> {
4931 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4932 (ins FR32X:$src1, FR32X:$src2),
4933 !strconcat(OpcodeStr,
4934 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4935 [], itins_s.rr>, XS, EVEX_4V;
4936 let isCodeGenOnly = 1 in
4937 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4938 (ins VR128X:$src1, VR128X:$src2),
4939 !strconcat(OpcodeStr,
4940 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4942 (F32Int VR128X:$src1, VR128X:$src2))],
4943 itins_s.rr>, XS, EVEX_4V;
4944 let mayLoad = 1 in {
4945 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4946 (ins FR32X:$src1, f32mem:$src2),
4947 !strconcat(OpcodeStr,
4948 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4949 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4950 let isCodeGenOnly = 1 in
4951 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4952 (ins VR128X:$src1, ssmem:$src2),
4953 !strconcat(OpcodeStr,
4954 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4956 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4957 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4959 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4960 (ins FR64X:$src1, FR64X:$src2),
4961 !strconcat(OpcodeStr,
4962 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4964 let isCodeGenOnly = 1 in
4965 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4966 (ins VR128X:$src1, VR128X:$src2),
4967 !strconcat(OpcodeStr,
4968 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4970 (F64Int VR128X:$src1, VR128X:$src2))],
4971 itins_s.rr>, XD, EVEX_4V, VEX_W;
4972 let mayLoad = 1 in {
4973 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4974 (ins FR64X:$src1, f64mem:$src2),
4975 !strconcat(OpcodeStr,
4976 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
4977 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4978 let isCodeGenOnly = 1 in
4979 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4980 (ins VR128X:$src1, sdmem:$src2),
4981 !strconcat(OpcodeStr,
4982 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4984 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4985 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4989 multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4991 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4993 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4994 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4996 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4997 // Define only if AVX512VL feature is present.
4998 let Predicates = [HasVLX] in {
4999 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5000 OpNode, v4f32x_info>,
5001 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
5002 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
5003 OpNode, v8f32x_info>,
5004 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
5005 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5006 OpNode, v2f64x_info>,
5007 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5008 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
5009 OpNode, v4f64x_info>,
5010 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5014 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
5016 defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
5017 v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
5018 defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
5019 v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
5022 defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>,
5023 avx512_sqrt_packed_all_round<0x51, "vsqrt", X86fsqrtRnd>;
5025 defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
5026 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
5027 SSE_SQRTSS, SSE_SQRTSD>;
5029 let Predicates = [HasAVX512] in {
5030 def : Pat<(f32 (fsqrt FR32X:$src)),
5031 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5032 def : Pat<(f32 (fsqrt (load addr:$src))),
5033 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
5034 Requires<[OptForSize]>;
5035 def : Pat<(f64 (fsqrt FR64X:$src)),
5036 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
5037 def : Pat<(f64 (fsqrt (load addr:$src))),
5038 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
5039 Requires<[OptForSize]>;
5041 def : Pat<(f32 (X86frsqrt FR32X:$src)),
5042 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5043 def : Pat<(f32 (X86frsqrt (load addr:$src))),
5044 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
5045 Requires<[OptForSize]>;
5047 def : Pat<(f32 (X86frcp FR32X:$src)),
5048 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
5049 def : Pat<(f32 (X86frcp (load addr:$src))),
5050 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
5051 Requires<[OptForSize]>;
5053 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
5054 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
5055 (COPY_TO_REGCLASS VR128X:$src, FR32)),
5057 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
5058 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
5060 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
5061 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
5062 (COPY_TO_REGCLASS VR128X:$src, FR64)),
5064 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
5065 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
5069 multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
5070 X86MemOperand x86memop, RegisterClass RC,
5071 PatFrag mem_frag, Domain d> {
5072 let ExeDomain = d in {
5073 // Intrinsic operation, reg.
5074 // Vector intrinsic operation, reg
5075 def r : AVX512AIi8<opc, MRMSrcReg,
5076 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
5077 !strconcat(OpcodeStr,
5078 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5081 // Vector intrinsic operation, mem
5082 def m : AVX512AIi8<opc, MRMSrcMem,
5083 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
5084 !strconcat(OpcodeStr,
5085 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5090 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
5091 loadv16f32, SSEPackedSingle>, EVEX_V512,
5092 EVEX_CD8<32, CD8VF>;
5094 def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
5095 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
5097 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
5100 defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
5101 loadv8f64, SSEPackedDouble>, EVEX_V512,
5102 VEX_W, EVEX_CD8<64, CD8VF>;
5104 def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
5105 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
5107 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
5110 avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
5112 let ExeDomain = _.ExeDomain in {
5113 defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5114 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5115 "$src3, $src2, $src1", "$src1, $src2, $src3",
5116 (_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5117 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5119 defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
5120 (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
5121 "{sae}, $src3, $src2, $src1", "$src1, $src2, $src3, {sae}",
5122 (_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),
5123 (i32 imm:$src3), (i32 FROUND_NO_EXC)))>, EVEX_B;
5126 defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
5127 (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,
5128 "$src3, $src2, $src1", "$src1, $src2, $src3",
5129 (_.VT (X86RndScale (_.VT _.RC:$src1),
5130 (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
5131 (i32 imm:$src3), (i32 FROUND_CURRENT)))>;
5133 let Predicates = [HasAVX512] in {
5134 def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
5135 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5136 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
5137 def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
5138 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5139 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
5140 def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
5141 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5142 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
5143 def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
5144 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5145 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
5146 def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS
5147 (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
5148 (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;
5150 def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5151 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5152 addr:$src, (i32 0x1))), _.FRC)>;
5153 def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5154 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5155 addr:$src, (i32 0x2))), _.FRC)>;
5156 def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5157 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5158 addr:$src, (i32 0x3))), _.FRC)>;
5159 def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5160 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5161 addr:$src, (i32 0x4))), _.FRC)>;
5162 def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
5163 (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
5164 addr:$src, (i32 0xc))), _.FRC)>;
5168 defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,
5169 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;
5171 defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,
5172 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;
5174 let Predicates = [HasAVX512] in {
5175 def : Pat<(v16f32 (ffloor VR512:$src)),
5176 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
5177 def : Pat<(v16f32 (fnearbyint VR512:$src)),
5178 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
5179 def : Pat<(v16f32 (fceil VR512:$src)),
5180 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
5181 def : Pat<(v16f32 (frint VR512:$src)),
5182 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
5183 def : Pat<(v16f32 (ftrunc VR512:$src)),
5184 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
5186 def : Pat<(v8f64 (ffloor VR512:$src)),
5187 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
5188 def : Pat<(v8f64 (fnearbyint VR512:$src)),
5189 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
5190 def : Pat<(v8f64 (fceil VR512:$src)),
5191 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
5192 def : Pat<(v8f64 (frint VR512:$src)),
5193 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
5194 def : Pat<(v8f64 (ftrunc VR512:$src)),
5195 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
5197 //-------------------------------------------------
5198 // Integer truncate and extend operations
5199 //-------------------------------------------------
5201 multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
5202 RegisterClass dstRC, RegisterClass srcRC,
5203 RegisterClass KRC, X86MemOperand x86memop> {
5204 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
5206 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
5209 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
5210 (ins KRC:$mask, srcRC:$src),
5211 !strconcat(OpcodeStr,
5212 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
5215 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
5216 (ins KRC:$mask, srcRC:$src),
5217 !strconcat(OpcodeStr,
5218 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5221 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
5222 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5225 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
5226 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
5227 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
5231 defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
5232 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
5233 defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
5234 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
5235 defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
5236 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
5237 defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
5238 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
5239 defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
5240 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
5241 defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
5242 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
5243 defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
5244 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
5245 defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
5246 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
5247 defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
5248 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
5249 defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
5250 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
5251 defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
5252 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
5253 defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
5254 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
5255 defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
5256 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
5257 defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
5258 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
5259 defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
5260 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
5262 def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
5263 def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
5264 def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
5265 def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
5266 def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
5268 def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
5269 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
5270 def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
5271 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
5272 def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
5273 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
5274 def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
5275 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
5278 multiclass avx512_extend_common<bits<8> opc, string OpcodeStr,
5279 X86VectorVTInfo DestInfo, X86VectorVTInfo SrcInfo,
5280 X86MemOperand x86memop, PatFrag LdFrag, SDNode OpNode>{
5282 defm rr : AVX512_maskable<opc, MRMSrcReg, DestInfo, (outs DestInfo.RC:$dst),
5283 (ins SrcInfo.RC:$src), OpcodeStr ,"$src", "$src",
5284 (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src)))>,
5287 let mayLoad = 1 in {
5288 defm rm : AVX512_maskable<opc, MRMSrcMem, DestInfo, (outs DestInfo.RC:$dst),
5289 (ins x86memop:$src), OpcodeStr ,"$src", "$src",
5290 (DestInfo.VT (LdFrag addr:$src))>,
5295 multiclass avx512_extend_BW<bits<8> opc, string OpcodeStr, SDNode OpNode,
5296 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
5297 let Predicates = [HasVLX, HasBWI] in {
5298 defm Z128: avx512_extend_common<opc, OpcodeStr, v8i16x_info,
5299 v16i8x_info, i64mem, LdFrag, OpNode>,
5300 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V128;
5302 defm Z256: avx512_extend_common<opc, OpcodeStr, v16i16x_info,
5303 v16i8x_info, i128mem, LdFrag, OpNode>,
5304 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V256;
5306 let Predicates = [HasBWI] in {
5307 defm Z : avx512_extend_common<opc, OpcodeStr, v32i16_info,
5308 v32i8x_info, i256mem, LdFrag, OpNode>,
5309 EVEX_CD8<8, CD8VH>, T8PD, EVEX_V512;
5313 multiclass avx512_extend_BD<bits<8> opc, string OpcodeStr, SDNode OpNode,
5314 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
5315 let Predicates = [HasVLX, HasAVX512] in {
5316 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
5317 v16i8x_info, i32mem, LdFrag, OpNode>,
5318 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V128;
5320 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
5321 v16i8x_info, i64mem, LdFrag, OpNode>,
5322 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V256;
5324 let Predicates = [HasAVX512] in {
5325 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
5326 v16i8x_info, i128mem, LdFrag, OpNode>,
5327 EVEX_CD8<8, CD8VQ>, T8PD, EVEX_V512;
5331 multiclass avx512_extend_BQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
5332 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi8")> {
5333 let Predicates = [HasVLX, HasAVX512] in {
5334 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
5335 v16i8x_info, i16mem, LdFrag, OpNode>,
5336 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V128;
5338 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
5339 v16i8x_info, i32mem, LdFrag, OpNode>,
5340 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V256;
5342 let Predicates = [HasAVX512] in {
5343 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
5344 v16i8x_info, i64mem, LdFrag, OpNode>,
5345 EVEX_CD8<8, CD8VO>, T8PD, EVEX_V512;
5349 multiclass avx512_extend_WD<bits<8> opc, string OpcodeStr, SDNode OpNode,
5350 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
5351 let Predicates = [HasVLX, HasAVX512] in {
5352 defm Z128: avx512_extend_common<opc, OpcodeStr, v4i32x_info,
5353 v8i16x_info, i64mem, LdFrag, OpNode>,
5354 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V128;
5356 defm Z256: avx512_extend_common<opc, OpcodeStr, v8i32x_info,
5357 v8i16x_info, i128mem, LdFrag, OpNode>,
5358 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V256;
5360 let Predicates = [HasAVX512] in {
5361 defm Z : avx512_extend_common<opc, OpcodeStr, v16i32_info,
5362 v16i16x_info, i256mem, LdFrag, OpNode>,
5363 EVEX_CD8<16, CD8VH>, T8PD, EVEX_V512;
5367 multiclass avx512_extend_WQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
5368 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi16")> {
5369 let Predicates = [HasVLX, HasAVX512] in {
5370 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
5371 v8i16x_info, i32mem, LdFrag, OpNode>,
5372 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V128;
5374 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
5375 v8i16x_info, i64mem, LdFrag, OpNode>,
5376 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V256;
5378 let Predicates = [HasAVX512] in {
5379 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
5380 v8i16x_info, i128mem, LdFrag, OpNode>,
5381 EVEX_CD8<16, CD8VQ>, T8PD, EVEX_V512;
5385 multiclass avx512_extend_DQ<bits<8> opc, string OpcodeStr, SDNode OpNode,
5386 string ExtTy,PatFrag LdFrag = !cast<PatFrag>(ExtTy#"extloadvi32")> {
5388 let Predicates = [HasVLX, HasAVX512] in {
5389 defm Z128: avx512_extend_common<opc, OpcodeStr, v2i64x_info,
5390 v4i32x_info, i64mem, LdFrag, OpNode>,
5391 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V128;
5393 defm Z256: avx512_extend_common<opc, OpcodeStr, v4i64x_info,
5394 v4i32x_info, i128mem, LdFrag, OpNode>,
5395 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V256;
5397 let Predicates = [HasAVX512] in {
5398 defm Z : avx512_extend_common<opc, OpcodeStr, v8i64_info,
5399 v8i32x_info, i256mem, LdFrag, OpNode>,
5400 EVEX_CD8<32, CD8VH>, T8PD, EVEX_V512;
5404 defm VPMOVZXBW : avx512_extend_BW<0x30, "vpmovzxbw", X86vzext, "z">;
5405 defm VPMOVZXBD : avx512_extend_BD<0x31, "vpmovzxbd", X86vzext, "z">;
5406 defm VPMOVZXBQ : avx512_extend_BQ<0x32, "vpmovzxbq", X86vzext, "z">;
5407 defm VPMOVZXWD : avx512_extend_WD<0x33, "vpmovzxwd", X86vzext, "z">;
5408 defm VPMOVZXWQ : avx512_extend_WQ<0x34, "vpmovzxwq", X86vzext, "z">;
5409 defm VPMOVZXDQ : avx512_extend_DQ<0x35, "vpmovzxdq", X86vzext, "z">;
5412 defm VPMOVSXBW: avx512_extend_BW<0x20, "vpmovsxbw", X86vsext, "s">;
5413 defm VPMOVSXBD: avx512_extend_BD<0x21, "vpmovsxbd", X86vsext, "s">;
5414 defm VPMOVSXBQ: avx512_extend_BQ<0x22, "vpmovsxbq", X86vsext, "s">;
5415 defm VPMOVSXWD: avx512_extend_WD<0x23, "vpmovsxwd", X86vsext, "s">;
5416 defm VPMOVSXWQ: avx512_extend_WQ<0x24, "vpmovsxwq", X86vsext, "s">;
5417 defm VPMOVSXDQ: avx512_extend_DQ<0x25, "vpmovsxdq", X86vsext, "s">;
5419 //===----------------------------------------------------------------------===//
5420 // GATHER - SCATTER Operations
5422 multiclass avx512_gather<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5423 X86MemOperand memop, PatFrag GatherNode> {
5424 let Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
5425 def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst, _.KRCWM:$mask_wb),
5426 (ins _.RC:$src1, _.KRCWM:$mask, memop:$src2),
5427 !strconcat(OpcodeStr,
5428 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5429 [(set _.RC:$dst, _.KRCWM:$mask_wb,
5430 (GatherNode (_.VT _.RC:$src1), _.KRCWM:$mask,
5431 vectoraddr:$src2))]>, EVEX, EVEX_K,
5432 EVEX_CD8<_.EltSize, CD8VT1>;
5435 let ExeDomain = SSEPackedDouble in {
5436 defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", v8f64_info, vy64xmem,
5437 mgatherv8i32>, EVEX_V512, VEX_W;
5438 defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", v8f64_info, vz64mem,
5439 mgatherv8i64>, EVEX_V512, VEX_W;
5442 let ExeDomain = SSEPackedSingle in {
5443 defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", v16f32_info, vz32mem,
5444 mgatherv16i32>, EVEX_V512;
5445 defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", v8f32x_info, vz64mem,
5446 mgatherv8i64>, EVEX_V512;
5449 defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", v8i64_info, vy64xmem,
5450 mgatherv8i32>, EVEX_V512, VEX_W;
5451 defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", v16i32_info, vz32mem,
5452 mgatherv16i32>, EVEX_V512;
5454 defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", v8i64_info, vz64mem,
5455 mgatherv8i64>, EVEX_V512, VEX_W;
5456 defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", v8i32x_info, vz64mem,
5457 mgatherv8i64>, EVEX_V512;
5459 multiclass avx512_scatter<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
5460 X86MemOperand memop, PatFrag ScatterNode> {
5462 let mayStore = 1, Constraints = "$mask = $mask_wb" in
5464 def mr : AVX5128I<opc, MRMDestMem, (outs _.KRCWM:$mask_wb),
5465 (ins memop:$dst, _.KRCWM:$mask, _.RC:$src),
5466 !strconcat(OpcodeStr,
5467 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
5468 [(set _.KRCWM:$mask_wb, (ScatterNode (_.VT _.RC:$src),
5469 _.KRCWM:$mask, vectoraddr:$dst))]>,
5470 EVEX, EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5473 let ExeDomain = SSEPackedDouble in {
5474 defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", v8f64_info, vy64xmem,
5475 mscatterv8i32>, EVEX_V512, VEX_W;
5476 defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", v8f64_info, vz64mem,
5477 mscatterv8i64>, EVEX_V512, VEX_W;
5480 let ExeDomain = SSEPackedSingle in {
5481 defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", v16f32_info, vz32mem,
5482 mscatterv16i32>, EVEX_V512;
5483 defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", v8f32x_info, vz64mem,
5484 mscatterv8i64>, EVEX_V512;
5487 defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", v8i64_info, vy64xmem,
5488 mscatterv8i32>, EVEX_V512, VEX_W;
5489 defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", v16i32_info, vz32mem,
5490 mscatterv16i32>, EVEX_V512;
5492 defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", v8i64_info, vz64mem,
5493 mscatterv8i64>, EVEX_V512, VEX_W;
5494 defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", v8i32x_info, vz64mem,
5495 mscatterv8i64>, EVEX_V512;
5498 multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
5499 RegisterClass KRC, X86MemOperand memop> {
5500 let Predicates = [HasPFI], hasSideEffects = 1 in
5501 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
5502 !strconcat(OpcodeStr, "\t{$src {${mask}}|{${mask}}, $src}"),
5506 defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
5507 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5509 defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
5510 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5512 defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
5513 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5515 defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
5516 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5518 defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
5519 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5521 defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
5522 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5524 defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
5525 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5527 defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
5528 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5530 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
5531 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5533 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
5534 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5536 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
5537 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5539 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
5540 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5542 defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
5543 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
5545 defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
5546 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
5548 defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
5549 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
5551 defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
5552 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
5553 //===----------------------------------------------------------------------===//
5554 // VSHUFPS - VSHUFPD Operations
5556 multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
5557 ValueType vt, string OpcodeStr, PatFrag mem_frag,
5559 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
5560 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
5561 !strconcat(OpcodeStr,
5562 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5563 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
5564 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5565 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
5566 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
5567 (ins RC:$src1, RC:$src2, u8imm:$src3),
5568 !strconcat(OpcodeStr,
5569 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5570 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
5571 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
5572 EVEX_4V, Sched<[WriteShuffle]>;
5575 defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", loadv16f32,
5576 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
5577 defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", loadv8f64,
5578 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
5580 def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5581 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5582 def : Pat<(v16i32 (X86Shufp VR512:$src1,
5583 (loadv16i32 addr:$src2), (i8 imm:$imm))),
5584 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5586 def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
5587 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
5588 def : Pat<(v8i64 (X86Shufp VR512:$src1,
5589 (loadv8i64 addr:$src2), (i8 imm:$imm))),
5590 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
5592 // Helper fragments to match sext vXi1 to vXiY.
5593 def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
5594 def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
5596 multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
5597 RegisterClass KRC, RegisterClass RC,
5598 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
5600 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5601 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5603 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5604 !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5606 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
5607 !strconcat(OpcodeStr,
5608 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5610 let mayLoad = 1 in {
5611 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5612 (ins x86memop:$src),
5613 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5615 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5616 (ins KRC:$mask, x86memop:$src),
5617 !strconcat(OpcodeStr,
5618 "\t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
5620 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5621 (ins KRC:$mask, x86memop:$src),
5622 !strconcat(OpcodeStr,
5623 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
5625 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5626 (ins x86scalar_mop:$src),
5627 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5628 ", $dst|$dst, ${src}", BrdcstStr, "}"),
5630 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5631 (ins KRC:$mask, x86scalar_mop:$src),
5632 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5633 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
5634 []>, EVEX, EVEX_B, EVEX_K;
5635 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
5636 (ins KRC:$mask, x86scalar_mop:$src),
5637 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5638 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
5640 []>, EVEX, EVEX_B, EVEX_KZ;
5644 defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
5645 i512mem, i32mem, "{1to16}">, EVEX_V512,
5646 EVEX_CD8<32, CD8VF>;
5647 defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5648 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5649 EVEX_CD8<64, CD8VF>;
5652 (bc_v16i32 (v16i1sextv16i32)),
5653 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5654 (VPABSDZrr VR512:$src)>;
5656 (bc_v8i64 (v8i1sextv8i64)),
5657 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5658 (VPABSQZrr VR512:$src)>;
5660 def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5661 (v16i32 immAllZerosV), (i16 -1))),
5662 (VPABSDZrr VR512:$src)>;
5663 def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5664 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
5665 (VPABSQZrr VR512:$src)>;
5667 multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
5668 RegisterClass RC, RegisterClass KRC,
5669 X86MemOperand x86memop,
5670 X86MemOperand x86scalar_mop, string BrdcstStr> {
5671 let hasSideEffects = 0 in {
5672 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5674 !strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
5677 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5678 (ins x86memop:$src),
5679 !strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
5682 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5683 (ins x86scalar_mop:$src),
5684 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5685 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5687 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5688 (ins KRC:$mask, RC:$src),
5689 !strconcat(OpcodeStr,
5690 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5693 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5694 (ins KRC:$mask, x86memop:$src),
5695 !strconcat(OpcodeStr,
5696 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
5699 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5700 (ins KRC:$mask, x86scalar_mop:$src),
5701 !strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
5702 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5704 []>, EVEX, EVEX_KZ, EVEX_B;
5706 let Constraints = "$src1 = $dst" in {
5707 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5708 (ins RC:$src1, KRC:$mask, RC:$src2),
5709 !strconcat(OpcodeStr,
5710 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5713 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5714 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5715 !strconcat(OpcodeStr,
5716 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
5719 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5720 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
5721 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
5722 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5723 []>, EVEX, EVEX_K, EVEX_B;
5728 let Predicates = [HasCDI] in {
5729 defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
5730 i512mem, i32mem, "{1to16}">,
5731 EVEX_V512, EVEX_CD8<32, CD8VF>;
5734 defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
5735 i512mem, i64mem, "{1to8}">,
5736 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5740 def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5742 (VPCONFLICTDrrk VR512:$src1,
5743 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5745 def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5747 (VPCONFLICTQrrk VR512:$src1,
5748 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5750 let Predicates = [HasCDI] in {
5751 defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5752 i512mem, i32mem, "{1to16}">,
5753 EVEX_V512, EVEX_CD8<32, CD8VF>;
5756 defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5757 i512mem, i64mem, "{1to8}">,
5758 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5762 def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5764 (VPLZCNTDrrk VR512:$src1,
5765 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5767 def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5769 (VPLZCNTQrrk VR512:$src1,
5770 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5772 def : Pat<(v16i32 (ctlz (loadv16i32 addr:$src))),
5773 (VPLZCNTDrm addr:$src)>;
5774 def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5775 (VPLZCNTDrr VR512:$src)>;
5776 def : Pat<(v8i64 (ctlz (loadv8i64 addr:$src))),
5777 (VPLZCNTQrm addr:$src)>;
5778 def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5779 (VPLZCNTQrr VR512:$src)>;
5781 def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5782 def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5783 def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
5785 def : Pat<(store VK1:$src, addr:$dst),
5787 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
5788 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5790 def : Pat<(store VK8:$src, addr:$dst),
5792 (EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
5793 sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
5795 def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5796 (truncstore node:$val, node:$ptr), [{
5797 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5800 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5801 (MOV8mr addr:$dst, GR8:$src)>;
5803 multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5804 def rr : AVX512XS8I<opc, MRMSrcReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5805 !strconcat(OpcodeStr##Vec.Suffix, "\t{$src, $dst|$dst, $src}"),
5806 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5809 multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5810 string OpcodeStr, Predicate prd> {
5811 let Predicates = [prd] in
5812 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5814 let Predicates = [prd, HasVLX] in {
5815 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5816 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5820 multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5821 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5823 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5825 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5827 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5831 defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;
5833 multiclass convert_vector_to_mask_common<bits<8> opc, X86VectorVTInfo _, string OpcodeStr > {
5834 def rr : AVX512XS8I<opc, MRMSrcReg, (outs _.KRC:$dst), (ins _.RC:$src),
5835 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5836 [(set _.KRC:$dst, (trunc (_.VT _.RC:$src)))]>, EVEX;
5839 multiclass avx512_convert_vector_to_mask<bits<8> opc, string OpcodeStr,
5840 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
5841 let Predicates = [prd] in
5842 defm Z : convert_vector_to_mask_common <opc, VTInfo.info512, OpcodeStr>,
5845 let Predicates = [prd, HasVLX] in {
5846 defm Z256 : convert_vector_to_mask_common<opc, VTInfo.info256, OpcodeStr>,
5848 defm Z128 : convert_vector_to_mask_common<opc, VTInfo.info128, OpcodeStr>,
5853 defm VPMOVB2M : avx512_convert_vector_to_mask<0x29, "vpmovb2m",
5854 avx512vl_i8_info, HasBWI>;
5855 defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m",
5856 avx512vl_i16_info, HasBWI>, VEX_W;
5857 defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m",
5858 avx512vl_i32_info, HasDQI>;
5859 defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m",
5860 avx512vl_i64_info, HasDQI>, VEX_W;
5862 //===----------------------------------------------------------------------===//
5863 // AVX-512 - COMPRESS and EXPAND
5865 multiclass compress_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5867 def rrkz : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5868 (ins _.KRCWM:$mask, _.RC:$src),
5869 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5870 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5871 _.ImmAllZerosV)))]>, EVEX_KZ;
5873 let Constraints = "$src0 = $dst" in
5874 def rrk : AVX5128I<opc, MRMDestReg, (outs _.RC:$dst),
5875 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5876 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5877 [(set _.RC:$dst, (_.VT (X86compress _.KRCWM:$mask, _.RC:$src,
5878 _.RC:$src0)))]>, EVEX_K;
5880 let mayStore = 1 in {
5881 def mrk : AVX5128I<opc, MRMDestMem, (outs),
5882 (ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
5883 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5884 [(store (_.VT (X86compress _.KRCWM:$mask, _.RC:$src, undef)),
5886 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5890 multiclass compress_by_elt_width<bits<8> opc, string OpcodeStr,
5891 AVX512VLVectorVTInfo VTInfo> {
5892 defm Z : compress_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5894 let Predicates = [HasVLX] in {
5895 defm Z256 : compress_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5896 defm Z128 : compress_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5900 defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", avx512vl_i32_info>,
5902 defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", avx512vl_i64_info>,
5904 defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", avx512vl_f32_info>,
5906 defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", avx512vl_f64_info>,
5910 multiclass expand_by_vec_width<bits<8> opc, X86VectorVTInfo _,
5912 def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5913 (ins _.KRCWM:$mask, _.RC:$src),
5914 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5915 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask, (_.VT _.RC:$src),
5916 _.ImmAllZerosV)))]>, EVEX_KZ;
5918 let Constraints = "$src0 = $dst" in
5919 def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
5920 (ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src),
5921 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5922 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5923 (_.VT _.RC:$src), _.RC:$src0)))]>, EVEX_K;
5925 let mayLoad = 1, Constraints = "$src0 = $dst" in
5926 def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5927 (ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src),
5928 OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",
5929 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5931 (_.LdFrag addr:$src))),
5933 EVEX_K, EVEX_CD8<_.EltSize, CD8VT1>;
5936 def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
5937 (ins _.KRCWM:$mask, _.MemOp:$src),
5938 OpcodeStr # "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}",
5939 [(set _.RC:$dst, (_.VT (X86expand _.KRCWM:$mask,
5940 (_.VT (bitconvert (_.LdFrag addr:$src))),
5941 _.ImmAllZerosV)))]>,
5942 EVEX_KZ, EVEX_CD8<_.EltSize, CD8VT1>;
5945 multiclass expand_by_elt_width<bits<8> opc, string OpcodeStr,
5946 AVX512VLVectorVTInfo VTInfo> {
5947 defm Z : expand_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5949 let Predicates = [HasVLX] in {
5950 defm Z256 : expand_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5951 defm Z128 : expand_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5955 defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", avx512vl_i32_info>,
5957 defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", avx512vl_i64_info>,
5959 defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", avx512vl_f32_info>,
5961 defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", avx512vl_f64_info>,
5964 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
5965 // op(reg_vec2,mem_vec,imm)
5966 // op(reg_vec2,broadcast(eltVt),imm)
5967 //all instruction created with FROUND_CURRENT
5968 multiclass avx512_fp_packed_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5970 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
5971 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
5972 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
5973 (OpNode (_.VT _.RC:$src1),
5976 (i32 FROUND_CURRENT))>;
5977 let mayLoad = 1 in {
5978 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5979 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
5980 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
5981 (OpNode (_.VT _.RC:$src1),
5982 (_.VT (bitconvert (_.LdFrag addr:$src2))),
5984 (i32 FROUND_CURRENT))>;
5985 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
5986 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
5987 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
5988 "$src1, ${src2}"##_.BroadcastStr##", $src3",
5989 (OpNode (_.VT _.RC:$src1),
5990 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
5992 (i32 FROUND_CURRENT))>, EVEX_B;
5996 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
5997 // op(reg_vec2,mem_vec,imm)
5998 // op(reg_vec2,broadcast(eltVt),imm)
5999 multiclass avx512_3Op_imm8<bits<8> opc, string OpcodeStr, SDNode OpNode,
6001 defm rri : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6002 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
6003 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6004 (OpNode (_.VT _.RC:$src1),
6007 let mayLoad = 1 in {
6008 defm rmi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6009 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
6010 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6011 (OpNode (_.VT _.RC:$src1),
6012 (_.VT (bitconvert (_.LdFrag addr:$src2))),
6014 defm rmbi : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
6015 (ins _.RC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6016 OpcodeStr, "$src3, ${src2}"##_.BroadcastStr##", $src1",
6017 "$src1, ${src2}"##_.BroadcastStr##", $src3",
6018 (OpNode (_.VT _.RC:$src1),
6019 (_.VT (X86VBroadcast(_.ScalarLdFrag addr:$src2))),
6020 (i8 imm:$src3))>, EVEX_B;
6024 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm)
6025 // op(reg_vec2,mem_scalar,imm)
6026 //all instruction created with FROUND_CURRENT
6027 multiclass avx512_fp_scalar_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6028 X86VectorVTInfo _> {
6030 defm rri : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
6031 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
6032 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6033 (OpNode (_.VT _.RC:$src1),
6036 (i32 FROUND_CURRENT))>;
6037 let mayLoad = 1 in {
6038 defm rmi : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
6039 (ins _.RC:$src1, _.MemOp:$src2, u8imm:$src3),
6040 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6041 (OpNode (_.VT _.RC:$src1),
6042 (_.VT (scalar_to_vector
6043 (_.ScalarLdFrag addr:$src2))),
6045 (i32 FROUND_CURRENT))>;
6047 let isAsmParserOnly = 1 in {
6048 defm rmi_alt :AVX512_maskable_in_asm<opc, MRMSrcMem, _, (outs _.FRC:$dst),
6049 (ins _.FRC:$src1, _.ScalarMemOp:$src2, u8imm:$src3),
6050 OpcodeStr, "$src3, $src2, $src1", "$src1, $src2, $src3",
6056 //handle instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6057 multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
6058 SDNode OpNode, X86VectorVTInfo _>{
6059 defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
6060 (ins _.RC:$src1, _.RC:$src2, u8imm:$src3),
6061 OpcodeStr, "$src3,{sae}, $src2, $src1",
6062 "$src1, $src2,{sae}, $src3",
6063 (OpNode (_.VT _.RC:$src1),
6066 (i32 FROUND_NO_EXC))>, EVEX_B;
6068 //handle scalar instruction reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
6069 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
6070 SDNode OpNode, X86VectorVTInfo _> {
6071 defm NAME: avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _>;
6074 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
6075 AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6076 let Predicates = [prd] in {
6077 defm Z : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6078 avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
6082 let Predicates = [prd, HasVLX] in {
6083 defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
6085 defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
6090 multiclass avx512_common_3Op_imm8<string OpcodeStr, AVX512VLVectorVTInfo _,
6091 bits<8> opc, SDNode OpNode>{
6092 let Predicates = [HasAVX512] in {
6093 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6095 let Predicates = [HasAVX512, HasVLX] in {
6096 defm Z128 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info128>, EVEX_V128;
6097 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6101 multiclass avx512_common_fp_sae_scalar_imm<string OpcodeStr,
6102 X86VectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
6103 let Predicates = [prd] in {
6104 defm Z128 : avx512_fp_scalar_imm<opc, OpcodeStr, OpNode, _>,
6105 avx512_fp_sae_scalar_imm<opc, OpcodeStr, OpNode, _>;
6109 defm VFIXUPIMMPD : avx512_common_fp_sae_packed_imm<"vfixupimmpd",
6110 avx512vl_f64_info, 0x54, X86VFixupimm, HasAVX512>,
6111 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6112 defm VFIXUPIMMPS : avx512_common_fp_sae_packed_imm<"vfixupimmps",
6113 avx512vl_f32_info, 0x54, X86VFixupimm, HasAVX512>,
6114 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6116 defm VFIXUPIMMSD: avx512_common_fp_sae_scalar_imm<"vfixupimmsd", f64x_info,
6117 0x55, X86VFixupimm, HasAVX512>,
6118 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6119 defm VFIXUPIMMSS: avx512_common_fp_sae_scalar_imm<"vfixupimmss", f32x_info,
6120 0x55, X86VFixupimm, HasAVX512>,
6121 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6123 defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info,
6124 0x50, X86VRange, HasDQI>,
6125 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6126 defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info,
6127 0x50, X86VRange, HasDQI>,
6128 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6130 defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info,
6131 0x51, X86VRange, HasDQI>,
6132 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
6133 defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info,
6134 0x51, X86VRange, HasDQI>,
6135 AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>;
6138 multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
6139 bits<8> opc, SDNode OpNode = X86Shuf128>{
6140 let Predicates = [HasAVX512] in {
6141 defm Z : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info512>, EVEX_V512;
6144 let Predicates = [HasAVX512, HasVLX] in {
6145 defm Z256 : avx512_3Op_imm8<opc, OpcodeStr, OpNode, _.info256>, EVEX_V256;
6149 defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
6150 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6151 defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2",avx512vl_f64_info, 0x23>,
6152 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6153 defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4",avx512vl_i32_info, 0x43>,
6154 AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>;
6155 defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2",avx512vl_i64_info, 0x43>,
6156 AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W;
6158 multiclass avx512_valign<string OpcodeStr, AVX512VLVectorVTInfo VTInfo_I,
6159 AVX512VLVectorVTInfo VTInfo_FP>{
6160 defm NAME: avx512_common_3Op_imm8<OpcodeStr, VTInfo_I, 0x03, X86VAlign>,
6161 AVX512AIi8Base, EVEX_4V;
6162 let isCodeGenOnly = 1 in {
6163 defm NAME#_FP: avx512_common_3Op_imm8<OpcodeStr, VTInfo_FP, 0x03, X86VAlign>,
6164 AVX512AIi8Base, EVEX_4V;
6168 defm VALIGND: avx512_valign<"valignd", avx512vl_i32_info, avx512vl_f32_info>,
6169 EVEX_CD8<32, CD8VF>;
6170 defm VALIGNQ: avx512_valign<"valignq", avx512vl_i64_info, avx512vl_f64_info>,
6171 EVEX_CD8<64, CD8VF>, VEX_W;